[all-commits] [llvm/llvm-project] 9c6579: [ReachingDefAnalysis] Detect entry block correclty...
Aiden Grossman via All-commits
all-commits at lists.llvm.org
Thu Jan 22 18:31:56 PST 2026
Branch: refs/heads/users/boomanaiden154/dse-make-dse-eliminate-stores-to-objects-with-a-sized-dead_on_return
Home: https://github.com/llvm/llvm-project
Commit: 9c657954f3c35a1d25c98a668a5c2fb15e12224a
https://github.com/llvm/llvm-project/commit/9c657954f3c35a1d25c98a668a5c2fb15e12224a
Author: Mikhail Gudim <mgudim at qti.qualcomm.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
Log Message:
-----------
[ReachingDefAnalysis] Detect entry block correclty. (#176803)
Before a block was deemed an entry block if it did not have any
predecessors, which is wrong: entry block can be a loop header.
Commit: d836261ca3c9ceffd550cc40c22bab5afa69e612
https://github.com/llvm/llvm-project/commit/d836261ca3c9ceffd550cc40c22bab5afa69e612
Author: Julian Pokrovsky <raventid at users.noreply.github.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/BuiltinsX86_64.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/crc32intrin.h
M clang/test/CodeGen/X86/sse42-builtins.c
Log Message:
-----------
[X86][Clang] allow CRC32 intrinsics to be used in constexp (#173908)
Mostly inspired by https://github.com/llvm/llvm-project/pull/152971
CRC32 implementation using reversed polynomial that does not match an
Intel manual, can be changed to canonical implementation if required (if
there is a canonical implementation we should use, please attach a link)
Closes #168881
Part of #30794
Commit: f41767db9db41ba3d31b02bb2d116113a27d9009
https://github.com/llvm/llvm-project/commit/f41767db9db41ba3d31b02bb2d116113a27d9009
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
Log Message:
-----------
[LV] Add replicating load/store cost tests for Apple CPUs.
Add dedicated tests to check replicating load/store costs on Apple CPUs.
Commit: 26f962465ecac878fa27970a3991906bce34020b
https://github.com/llvm/llvm-project/commit/26f962465ecac878fa27970a3991906bce34020b
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/include/llvm/Analysis/CallGraphSCCPass.h
M llvm/include/llvm/CodeGen/BasicBlockSectionsProfileReader.h
M llvm/include/llvm/CodeGen/CFIFixup.h
M llvm/include/llvm/CodeGen/GlobalISel/GISelValueTracking.h
M llvm/include/llvm/CodeGen/LiveStacks.h
M llvm/include/llvm/CodeGen/LiveVariables.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/RegisterUsageInfo.h
M llvm/include/llvm/CodeGen/ReplaceWithVeclib.h
M llvm/include/llvm/InitializePasses.h
M llvm/lib/Analysis/CallGraphSCCPass.cpp
M llvm/lib/Analysis/LazyBranchProbabilityInfo.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/BasicBlockMatchingAndInference.cpp
M llvm/lib/CodeGen/BasicBlockPathCloning.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/BreakFalseDeps.cpp
M llvm/lib/CodeGen/CFGuardLongjmp.cpp
M llvm/lib/CodeGen/CFIInstrInserter.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
M llvm/lib/CodeGen/EHContGuardTargets.cpp
M llvm/lib/CodeGen/ExpandIRInsts.cpp
M llvm/lib/CodeGen/ExpandMemCmp.cpp
M llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
M llvm/lib/CodeGen/ExpandReductions.cpp
M llvm/lib/CodeGen/FEntryInserter.cpp
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
M llvm/lib/CodeGen/FuncletLayout.cpp
M llvm/lib/CodeGen/GCEmptyBasicBlocks.cpp
M llvm/lib/CodeGen/GCMetadata.cpp
M llvm/lib/CodeGen/GCRootLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/CodeGen/HardwareLoops.cpp
M llvm/lib/CodeGen/IfConversion.cpp
M llvm/lib/CodeGen/ImplicitNullChecks.cpp
M llvm/lib/CodeGen/IndirectBrExpandPass.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
M llvm/lib/CodeGen/JMCInstrumenter.cpp
M llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp
M llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
M llvm/lib/CodeGen/LiveDebugVariables.cpp
M llvm/lib/CodeGen/LiveIntervals.cpp
M llvm/lib/CodeGen/LiveRangeShrink.cpp
M llvm/lib/CodeGen/LiveVariables.cpp
M llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
M llvm/lib/CodeGen/LowerEmuTLS.cpp
M llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
M llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
M llvm/lib/CodeGen/MachineBlockHashInfo.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineBranchProbabilityInfo.cpp
M llvm/lib/CodeGen/MachineCFGPrinter.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineCombiner.cpp
M llvm/lib/CodeGen/MachineCycleAnalysis.cpp
M llvm/lib/CodeGen/MachineDominanceFrontier.cpp
M llvm/lib/CodeGen/MachineDominators.cpp
M llvm/lib/CodeGen/MachineFunctionSplitter.cpp
M llvm/lib/CodeGen/MachineInstrBundle.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
M llvm/lib/CodeGen/MachineLoopInfo.cpp
M llvm/lib/CodeGen/MachineModuleInfo.cpp
M llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachinePostDominators.cpp
M llvm/lib/CodeGen/MachineRegionInfo.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/ModuloSchedule.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/PHIElimination.cpp
M llvm/lib/CodeGen/PatchableFunction.cpp
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/CodeGen/ProcessImplicitDefs.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/PseudoProbeInserter.cpp
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocPBQP.cpp
M llvm/lib/CodeGen/RegUsageInfoCollector.cpp
M llvm/lib/CodeGen/RegUsageInfoPropagate.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/RegisterUsageInfo.cpp
M llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
M llvm/lib/CodeGen/RemoveRedundantDebugValues.cpp
M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
M llvm/lib/CodeGen/SafeStack.cpp
M llvm/lib/CodeGen/SanitizerBinaryMetadata.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/ShadowStackGCLowering.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/CodeGen/SlotIndexes.cpp
M llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp
M llvm/lib/CodeGen/StackProtector.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/StaticDataAnnotator.cpp
M llvm/lib/CodeGen/StaticDataSplitter.cpp
M llvm/lib/CodeGen/TailDuplication.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/CodeGen/UnreachableBlockElim.cpp
M llvm/lib/CodeGen/WindowsSecureHotPatching.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
M llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
M llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
M llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
M llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
M llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/tools/llc/llc.cpp
Log Message:
-----------
[LLVM][CodeGen] Remove pass initialization calls from pass constructors (#173061)
- Remove pass initialization calls from pass constructors.
- For some passes, add the initialization to `initializeCodeGen` or
`initializeGlobalISel`.
- Remove redundant initializations from llc and X86 target for some
passes.
Commit: 7e01b33a426f23ac4d6902be88d2027536e708c4
https://github.com/llvm/llvm-project/commit/7e01b33a426f23ac4d6902be88d2027536e708c4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
M llvm/test/CodeGen/PowerPC/vavg.ll
Log Message:
-----------
[PPC] Fix suspicious AltiVec VAVG patterns (#176891)
The existing ((X+Y+1)>>1) patterns didn't correct handle overflow, like
the VAVG instructions would
Remove the old patterns and correctly mark the altivec VAVGS/VAVGU
patterns as matching the ISD::AVGCEIL opcodes - the generic DAG folds
will handle everything else
I've updated the vavg.ll tests to correct match ISD::AVGCEILS/U patterns
and added the old tests as negative "overflow" patterns that shouldn't
fold to VAVG instructions
Fixes #174718
Commit: e02a55ca9094264f179ee99d41caaa769bfe2c06
https://github.com/llvm/llvm-project/commit/e02a55ca9094264f179ee99d41caaa769bfe2c06
Author: Paulo Matos <pmatos at igalia.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/lib/Basic/Targets/WebAssembly.h
M clang/test/CodeGenCXX/wasm-reftypes-mangle.cpp
Log Message:
-----------
[Clang][WebAssembly] Fix crash when using __funcref in C++ code (#176237)
Enable address space map mangling for the WebAssembly target. This fixes
a crash in the Itanium name mangler when trying to mangle types with the
wasm_funcref address space qualifier in C++ mode.
Fixes #176154
Commit: ced1c00c91a2316fff71493f1180e410962c9e62
https://github.com/llvm/llvm-project/commit/ced1c00c91a2316fff71493f1180e410962c9e62
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
Log Message:
-----------
[AMDGPU][NPM] Enable "AMDGPURewriteAGPRCopyMFMAPass" (#173487)
Commit: a304968d5e2e7a6895ce9cc53cc4d254199ecf9a
https://github.com/llvm/llvm-project/commit/a304968d5e2e7a6895ce9cc53cc4d254199ecf9a
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Add RegBankLegalize rules for SMED3 and CVT_PK_I16_I32 (#176596)
These opcodes are created together for the i64->i16 signed clamp
pattern.
Commit: 75167f140baa003b01c2676ef5813cc64a600021
https://github.com/llvm/llvm-project/commit/75167f140baa003b01c2676ef5813cc64a600021
Author: Andrew Haberlandt <ahaberlandt at apple.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/tools/lto/CMakeLists.txt
Log Message:
-----------
[Darwin] CMake warning when building sanitized libLTO on Darwin with system sanitizer library (#176976)
Due to a system security policy, libLTO built with `LLVM_USE_SANITIZER`
and a toolchain (i.e. Xcode) sanitizer library cannot be loaded into the
toolchain `ld`. This only affects Darwin.
This adds a warning when users try to do this, and suggests a workaround
(use just-built sanitizer libraries).
This affected the lldb-cmake-sanitized job:
https://github.com/llvm/llvm-zorg/commits/main/zorg/jenkins/jobs/jobs/lldb-cmake-sanitized
rdar://168502870
Commit: bf9b8dea31a037ccfd848d94d03824b7923d2226
https://github.com/llvm/llvm-project/commit/bf9b8dea31a037ccfd848d94d03824b7923d2226
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
A llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_S_MUL_* (#176842)
Commit: 50c01fa130cc104aa7635be6b73f6df9833a8ebc
https://github.com/llvm/llvm-project/commit/50c01fa130cc104aa7635be6b73f6df9833a8ebc
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/LiveIntervals.cpp
Log Message:
-----------
[CodeGen][NPM] dump slot index info with -debug while running LiveIntervals (#173488)
matches legacy. tests such as "CodeGen/AMDGPU/liveness.mir" and
"CodeGen/AMDGPU/phys-partial-liveness.mir" use this.
Commit: d8c66f1ef34bd87a79837eddfb9b515a199298a6
https://github.com/llvm/llvm-project/commit/d8c66f1ef34bd87a79837eddfb9b515a199298a6
Author: Nico Weber <thakis at chromium.org>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/test/BUILD.gn
Log Message:
-----------
[gn] port 437f39103833
Commit: db713325d530e88d0229643c6002950ddfc16d6e
https://github.com/llvm/llvm-project/commit/db713325d530e88d0229643c6002950ddfc16d6e
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M libc/fuzzing/__support/CMakeLists.txt
A libc/fuzzing/__support/weak_avl_fuzz.cpp
M libc/src/__support/CMakeLists.txt
A libc/src/__support/weak_avl.h
M libc/test/src/__support/CMakeLists.txt
A libc/test/src/__support/weak_avl_test.cpp
Log Message:
-----------
[libc][tsearch] add weak AVL tree for tsearch implementation (#172411)
Related to #114695.
This PR adds a Weak AVL Tree for tsearch APIs. The symbol
implementations are coming in a
following up PR to avoid creating a huge patch. The work is based on
@MaskRay's recent post (see below).
A general self-balancing binary search tree where the node pointer can
be used as stable handles to the stored values.
The self-balancing strategy is the Weak AVL (WAVL) tree, based on the
following foundational references:
1. https://maskray.me/blog/2025-12-14-weak-avl-tree
2. https://reviews.freebsd.org/D25480
3. https://ics.uci.edu/~goodrich/teach/cs165/notes/WeakAVLTrees.pdf
4. https://dl.acm.org/doi/10.1145/2689412 (Rank-Balanced Trees)
WAVL trees belong to the rank-balanced binary search tree framework
(reference 4), alongside AVL and Red-Black trees.
Key Properties of WAVL Trees:
1. Relationship to Red-Black Trees: A WAVL tree can always be colored as
a
Red-Black tree.
2. Relationship to AVL Trees: An AVL tree meets all the requirements of
a
WAVL tree. Insertion-only WAVL trees maintain the same structure as AVL
trees.
Rank-Based Balancing:
In rank-balanced trees, each node is assigned a rank (conceptually
similar
to height). In AVL/WAVL, the rank difference between a parent and its
child is
strictly enforced to be either **1** or **2**.
- **AVL Trees:** Rank is equivalent to height. The strict condition is
that
there are no 2-2 nodes (a parent with rank difference 2 to both
children).
- **WAVL Trees:** The no 2-2 node rule is relaxed for internal nodes
during
the deletion fixup process, making WAVL trees less strictly balanced
than
AVL trees but easier to maintain than Red-Black trees.
Balancing Mechanics (Promotion/Demotion):
- **Null nodes** are considered to have rank -1.
- **External/leaf nodes** have rank 0.
- **Insertion:** Inserting a node may create a situation where a parent
and
child
have the same rank (difference 0). This is fixed by **promoting** the
rank
of the parent and propagating the fix upwards using at most two
rotations
(trinode fixup).
- **Deletion:** Deleting a node may result in a parent being 3 ranks
higher
than a child (difference 3). This is fixed by **demoting** the parent's
rank and propagating the fix upwards.
Implementation Detail:
The rank is **implicitly** maintained. We never store the full rank.
Instead,
a 2-bit tag is used on each node to record the rank difference to each
child:
- Bit cleared (0) -> Rank difference is **1**.
- Bit set (1) -> Rank difference is **2**.
---------
Co-authored-by: Michael Jones <michaelrj at google.com>
Commit: ac5e1b7a965bec85979acf6fb7bd51a042954743
https://github.com/llvm/llvm-project/commit/ac5e1b7a965bec85979acf6fb7bd51a042954743
Author: Augusto Noronha <anoronha at apple.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io.py
Log Message:
-----------
[lldb] Skip TestDAP_launch_io.py tests on asan builds (#177198)
Two out of three TestDAP_launch_io.py's test's classes have been failing
on ASAN builds ever since it was added into the repo. The ASAN failure
is not easy to debug, so skip these tests until we fix it.
Commit: f534711729b7feb0efc443a5f2139a906a60cf8f
https://github.com/llvm/llvm-project/commit/f534711729b7feb0efc443a5f2139a906a60cf8f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M openmp/device/include/Synchronization.h
M openmp/device/src/Synchronization.cpp
Log Message:
-----------
[OpenMP][NFC] Use `uinc` atomic builtins for this operation (#177207)
Summary:
We support this now, this is 1-to-1 equivalent and simply prevents us
from needing to do it ourselves.
Commit: 8f1427d26929bdec364f46a9043303e6b1ed4200
https://github.com/llvm/llvm-project/commit/8f1427d26929bdec364f46a9043303e6b1ed4200
Author: Prerona Chaudhuri <43287592+pchaudhuri-nv at users.noreply.github.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
A llvm/test/TableGen/invalid_typecast_assert.td
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
Log Message:
-----------
[TableGen] Gracefully error out in ParseTreePattern when DAG has zero operands so that llvm-tblgen doesn't crash (#161417)
Also handle the case when Pat->Child(i) is null in
CodeGenDAGPatterns::FindPatternInputsAndOutputs().
Fixes issue #157619 : TableGen asserts on invalid cast
Commit: 9c2124e0f6bb94a9ce4eafe99f62ed0bf61833fe
https://github.com/llvm/llvm-project/commit/9c2124e0f6bb94a9ce4eafe99f62ed0bf61833fe
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[NFC][SLP] Fix typo in assertion (#177079)
Commit: 792e3398f107b8b2a05d2494aa0a9491db86d722
https://github.com/llvm/llvm-project/commit/792e3398f107b8b2a05d2494aa0a9491db86d722
Author: Thurston Dang <thurston at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/neon-dot-product.ll
Log Message:
-----------
[msan] Handle NEON dot product intrinsics (#176084)
Propagate shadow by reusing existing `handleVectorPmaddIntrinsic()`
(used for analogous x86 instructions; renamed to
`handleVectorDotProductIntrinsic()`), instead of strictly handling.
Commit: 86a2486bff5b9633c59f0b7e5f4486edcc3a736a
https://github.com/llvm/llvm-project/commit/86a2486bff5b9633c59f0b7e5f4486edcc3a736a
Author: Nico Weber <thakis at chromium.org>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M libc/shared/math.h
A libc/shared/math/log10.h
A libc/shared/math/log1p.h
A libc/shared/math/log2.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/log10.h
A libc/src/__support/math/log1p.h
A libc/src/__support/math/log2.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/log10.cpp
M libc/src/math/generic/log1p.cpp
M libc/src/math/generic/log2.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_math_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][math] Refactor log10, log1p, log2 implementation to header-only in src/__support/math folder. (#176089)
Part of #147386
in preparation for:
https://discourse.llvm.org/t/rfc-make-clang-builtin-math-functions-constexpr-with-llvm-libc-to-support-c-23-constexpr-math-functions/86450
Commit: 004e2106a8fd6ff31c03c9978ae0ab9794b704ed
https://github.com/llvm/llvm-project/commit/004e2106a8fd6ff31c03c9978ae0ab9794b704ed
Author: Finn Plummer <mail at inbelic.dev>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/ObjCopy/DXContainer/DXContainerObjcopy.cpp
R llvm/test/tools/llvm-objcopy/DXContainer/copy-basic.test
A llvm/test/tools/llvm-objcopy/DXContainer/copy-basic.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/extract-section-basic.test
A llvm/test/tools/llvm-objcopy/DXContainer/extract-section-basic.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/extract-section-errs.test
A llvm/test/tools/llvm-objcopy/DXContainer/extract-section-errs.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/extract-section-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/extract-section-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/only-section-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/only-section-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/reading-errs.test
A llvm/test/tools/llvm-objcopy/DXContainer/reading-errs.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/remove-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/remove-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/remove-root-signature.test
A llvm/test/tools/llvm-objcopy/DXContainer/remove-root-signature.yaml
Log Message:
-----------
[NFC][DirectX] Clean-up `llvm-objcopy` to be consistent across implementation details (#177006)
This change is to ensure the implementation of the various
`llvm-objcopy` args are implemented with consistent patterns.
This is intended to help have a clear and consistent point of reference
for new contributors to extend `llvm-objcopy`.
These changes are largely to propagate the review comments of
https://github.com/llvm/llvm-project/pull/159999 back onto the changes
introduced before it.
Commit: 058a223388576cc7f037f8155967a73d5400b053
https://github.com/llvm/llvm-project/commit/058a223388576cc7f037f8155967a73d5400b053
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
Log Message:
-----------
[HLSL] Add wave active ballot to set of wave ops that set waveops shader flag (#177043)
This PR simply adds wave active ballot to the set of wave ops that
switch on the waveops shader flag.
Commit: e47e51a30a0362686c5f92a36c99476f1d7ac561
https://github.com/llvm/llvm-project/commit/e47e51a30a0362686c5f92a36c99476f1d7ac561
Author: Alan Zhao <ayzhao at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/not.ll
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[profcheck][InstCombine] Fix missing profile data identified by not.ll test (#176497)
Tracking issue: #147390
Commit: 35e9540ba8bd54d31a8b805d70c5c8607cf73cf1
https://github.com/llvm/llvm-project/commit/35e9540ba8bd54d31a8b805d70c5c8607cf73cf1
Author: Matthias Springer <me at m-sp.org>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/test/Analysis/DataFlow/test-dead-code-analysis.mlir
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
Log Message:
-----------
[mlir][SCF] Improve `ForOp::getSuccessorRegions` (#177116)
- Loops with 0 iterations always branch back to the parent.
- Loops with 1 iteration always branch into the loop, then immediately
back to the parent.
This change improves the quality of data flow analyses (e.g., dead code
analysis). It is also in preparation of adding a generic region inlining
canonicalization pattern for `RegionBranchOpInterface` ops (#176641).
---------
Co-authored-by: Jakub Kuderski <jakub at nod-labs.com>
Commit: 6a9699f194fd146262b25a4bb4a5189db1d7f259
https://github.com/llvm/llvm-project/commit/6a9699f194fd146262b25a4bb4a5189db1d7f259
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[ProfCheck] Exclude Transforms/InstCombine/load-addrspacecast-select.ll
This was added recently and needs to be fixed, but for now exclude it so
that the bot can return to green and we can better catch future
regressions.
Commit: 170de19a5b2dc2b9855d73794f139d1ff84bce47
https://github.com/llvm/llvm-project/commit/170de19a5b2dc2b9855d73794f139d1ff84bce47
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
A llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
Log Message:
-----------
[AMDGPU] Latency calculation must be independent of meta insts (#177052)
Debug and other meta instructions in bundles must not affect latency
calculation.
Ensure that code compiled with and without debug instructions is
identical.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 8f58cfecae947da3ec7a3a08a1678bacc76e04ca
https://github.com/llvm/llvm-project/commit/8f58cfecae947da3ec7a3a08a1678bacc76e04ca
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/test/CIR/CodeGenBuiltins/builtin_bit.cpp
Log Message:
-----------
[CIR][NFC] Update out-of-sync OGCG checks in test CIRGen/builtin_bit (#177189)
This patch updates various out-of-sync OGCG checks in the test file
`clang/test/CIR/CIRGen/builtin_bit.cpp`.
These checks are all related to the original clang CodeGen for the
bitwise rotate builtins. The OGCG patch #160259 inserts a new `urem`
instruction before calling the `llvm.fshr.*` intrinsic, which truncates
the rotate amount against the input's bit width. This breaks our OGCG
checks.
I have not yet dug deep enough into the rationale behind the OGCG patch.
The LLVM intrinsic `llvm.fshr.*` should already handle the truncation,
and the new `urem` instruction seems redundant in terms of semantic
correctness. Thus I choose not to hurry to also update relevant CIRGen
code to match OGCG behavior in this patch.
Commit: 7645bd38a7361f166c86600c4a71db405643198d
https://github.com/llvm/llvm-project/commit/7645bd38a7361f166c86600c4a71db405643198d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/performance/BUILD.gn
Log Message:
-----------
[gn build] Port 771517e9bfae
Commit: c3b4d94cd0eb08f818bf438b2dfbac38fe69e3ad
https://github.com/llvm/llvm-project/commit/c3b4d94cd0eb08f818bf438b2dfbac38fe69e3ad
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/tools/llvm-dwarfdump/BUILD.gn
Log Message:
-----------
[gn build] Port df063cbf1122
Commit: 5439df1e1c7d830ddf14986a24273ee71658c2fc
https://github.com/llvm/llvm-project/commit/5439df1e1c7d830ddf14986a24273ee71658c2fc
Author: Steven Perron <stevenperron at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
Log Message:
-----------
[HLSL] Improve HLSL resource method generation (#176806)
Refactor how HLSL resource methods are constructed in
HLSLBuiltinTypeDeclBuilder to be more robust and semantically correct.
- Switch to using Sema::BuildCallExpr and Sema::BuildCStyleCastExpr for
building builtin calls, ensuring proper type checking and AST
structure. This fixes issues with non-template resources like
SamplerState where AST errors aren't automatically resolved during
instantiation.
- Treat parameter placeholders as LValues in convertPlaceholder. This is
required for builtins with 'out' parameters (e.g., GetDimensions) now
that proper type checking via BuildCallExpr is performed.
- Fix a bug in CreateFromBinding methods where the counter handle was
assigned an incorrect handle type.
- Add assertions to ensure the correct field is accessed for handles,
preventing errors when implementing methods like Texture2D.Sample.
- Update AST tests to reflect changes in expression value categories
(VK_LValue) and the introduction of CStyleCastExpr.
Commit: 864c6cc9a62a4106fd09346385a43ead81a64a2f
https://github.com/llvm/llvm-project/commit/864c6cc9a62a4106fd09346385a43ead81a64a2f
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/CUDA/cuda-allocate.fir
M flang/test/Fir/CUDA/cuda-data-transfer.fir
Log Message:
-----------
[flang][cuda] Remove option allocationConversion from pass (#177037)
The pass option was meant to be used during migration. This is not
needed anymore.
Commit: d96cbf4a0224798dd514f03fa4f2301c4f879920
https://github.com/llvm/llvm-project/commit/d96cbf4a0224798dd514f03fa4f2301c4f879920
Author: Syadus Sefat <42645939+mssefat at users.noreply.github.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
Log Message:
-----------
[AMDGPU] Improve codegen for uniform f16<-->i32 conversions (#176833)
This patch improves codegen by chaining scalar operations for uniform
f16<-->i32 conversions where hardware supports the specific SALU
operations.
Added patterns in SOPInstructions.td to synthesize f16<-->i32
conversions via
intermediate f32 (f16-->f32-->i32 and i32-->f32-->f16).
Commit: 1d5e0408c9484cbd8b968a71bde12391ab83926c
https://github.com/llvm/llvm-project/commit/1d5e0408c9484cbd8b968a71bde12391ab83926c
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
M flang/test/Fir/CUDA/cuda-global-addr.mlir
M flang/test/Fir/CUDA/cuda-launch.fir
Log Message:
-----------
[flang][cuda] Remove CUFDeviceAddressOpConversion from CUFOpConversion (#177213)
The pattern has been moved to CUFOpConversionLate
Commit: 567fe2bbca27a934afd4a020f0d56e85edc7bfb2
https://github.com/llvm/llvm-project/commit/567fe2bbca27a934afd4a020f0d56e85edc7bfb2
Author: Daniel Thornburgh <mysterymath at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M lld/COFF/InputFiles.cpp
M llvm/include/llvm/LTO/LTO.h
M llvm/lib/LTO/LTO.cpp
M llvm/lib/LTO/ThinLTOCodeGenerator.cpp
M llvm/lib/Object/IRSymtab.cpp
Log Message:
-----------
[NFC][LTO] Move isPreservedName out of IRSymtab into LTO's Symbol as isLibcall (#177046)
This resolves the FIXME in IRSymtab and cleans up the semantics of the
IRSymtab. The list of preserved symbols really shouldn't be seen as a
property of the IR symbol table, since it's an LTO-specific concern, and
it's very tenuous to claim that this information is actually present in
the bitcode file to be exposed through its symbol table.
Instead, this PR moves this logic into LTO's view of the symbol, which
allows consumers to determine preserved-ness themselves. This was broken
out of #164916; this prevents that PR from introducing a circular
dependency, but it still seems like an independently good idea by virtue
of the above.
Commit: b30971c4bb3f0654fa4fbb242126376169ae66d0
https://github.com/llvm/llvm-project/commit/b30971c4bb3f0654fa4fbb242126376169ae66d0
Author: Teresa Johnson <tejohnson at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/test/Assembler/thinlto-summary.ll
A llvm/test/Bitcode/Inputs/thinlto-function-summary-callgraph-relbf.bc
M llvm/test/Bitcode/thinlto-function-summary-callgraph-relbf.ll
Log Message:
-----------
[ThinLTO] Remove unused relative block frequency support (#177215)
This removes most of the handling of the relative block frequency
support added in 2018 in c73cec84c99e5a63dca961fef67998a677c53a3c, which
was disabled by default and never utilized in the thin link as expected.
Support for reading old Bitcode containing the record is maintained as
required for backwards compatibility requirements, as is the support for
parsing old LLVM assembly containing that information. Tests ensure that
this backwards compatibility is maintained.
This came up in the context of redundant BFI/DT computations which
existed largely for the purpose of computing this information
and are being addressed in PR176646.
Commit: 9e4590f77244bb4ac35f38ab8beff6824428a019
https://github.com/llvm/llvm-project/commit/9e4590f77244bb4ac35f38ab8beff6824428a019
Author: cmtice <cmtice at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[LLVM] Fix Bazel build for llvm-dwarfdump. (#177229)
Fix is needed for https://github.com/llvm/llvm-project/pull/176725,
Commit: c6afb03658c9d62a156bfb7d809067020784e5ce
https://github.com/llvm/llvm-project/commit/c6afb03658c9d62a156bfb7d809067020784e5ce
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/utils/TableGen/DAGISelMatcher.cpp
Log Message:
-----------
[TableGen] Add MatchNumber to CheckChildSameMatcher::printImpl. NFC
Make the formatting more consistent with other child matchers.
This function is only used for debugging so it doesn't change
the output.
Commit: 49903c4e6445cba36f1a0231cc0ece4e4b96c91a
https://github.com/llvm/llvm-project/commit/49903c4e6445cba36f1a0231cc0ece4e4b96c91a
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCIfClauseLowering.cpp
M mlir/test/Dialect/OpenACC/acc-if-clause-lowering.mlir
Log Message:
-----------
[OpenACC][MLIR] clone reduction operands during ACCIfClauseLowering (#177196)
Clone the reduction operands into the compute region side. This also
fixes an issue where references to acc.reduction remain on the host
side.
Commit: 2ee329fc5188ce783a69aa87f1796ecc24bb8927
https://github.com/llvm/llvm-project/commit/2ee329fc5188ce783a69aa87f1796ecc24bb8927
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
Log Message:
-----------
[AMDGPU] Remove intrinsic declarations in a couple tests, NFC (#177218)
There is no need to explicitly declare intrinsic now. In this PR, we
only
remove intrinsic declarations in the two tests recently touched.
Commit: e779482ef5bc1439e1916af67b5e99327fbe2115
https://github.com/llvm/llvm-project/commit/e779482ef5bc1439e1916af67b5e99327fbe2115
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel][IR2Vec] Exclude ir2vec python bindings from main tool (#177230)
#176571 adds python bindings (using nanobind) in a subdirectory of the
ir2vec tool dir, but the bazel target just globs everything. Exclude the
bindings directory, which needs to be built in a special way.
Commit: 5f3643f9843ccfe377b929edcb6c238dda8492ca
https://github.com/llvm/llvm-project/commit/5f3643f9843ccfe377b929edcb6c238dda8492ca
Author: Kirill Vedernikov <kvedernikov at nvidia.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
Log Message:
-----------
[NFC][NVVM][NVPTX] Moved common code for tcgen05.mma to the base class (#176327)
This change moves common code parts for `tcgen05.mma` intrinsics to a
separate base class. It removes code duplication and increases
readability. There are no functional changes.
Commit: f3aa84c81039c4a501afe6a607c7dad387a8ab6f
https://github.com/llvm/llvm-project/commit/f3aa84c81039c4a501afe6a607c7dad387a8ab6f
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86AsmPrinter.h
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86WinEHUnwindV2.cpp
M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
M llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-epilogs.mir
M llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-instr.mir
Log Message:
-----------
[win][x64] Unwind v2: Avoid non-terminator instructions after terminator by using different psuedo for splitting frame infos (#177007)
After merging #159206 the new tests added would fail when verifying
machine code instructions with:
```
*** Bad machine code: Non-terminator instruction after the first terminator ***
- function: has_funclet
- basic block: %bb.4 call.block.4 (0x8000f837e8)
- instruction: SEH_SplitChained
First terminator was: RET64 $eax
*** Bad machine code: Non-terminator instruction after the first terminator ***
- function: has_funclet
- basic block: %bb.4 call.block.4 (0x8000f837e8)
- instruction: SEH_EndPrologue
First terminator was: RET64 $eax
```
This change removes `SEH_SplitChained` and replaces it with
`SEH_SplitChainedAtEndOfBlock` which acts as a marker to `X86AsmPrinter`
to emit the `.seh_splitchained` directive (and `.seh_endprolog`) when
the current block has finished.
Commit: 1843a7fe9f2d89cac9b4994adacf4edef5c36a4d
https://github.com/llvm/llvm-project/commit/1843a7fe9f2d89cac9b4994adacf4edef5c36a4d
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[NFCI][AMDGPU] Use X-macro to reduce boilerplate in `GCNSubtarget.h` (#176844)
`GCNSubtarget.h` contained a large amount of repetitive code following
the pattern `bool HasXXX = false;` for member declarations and `bool
hasXXX() const { return HasXXX; }` for getters. This boilerplate made
the file unnecessarily long and harder to maintain.
This patch introduces an X-macro pattern `GCN_SUBTARGET_HAS_FEATURE`
that consolidates 135 simple subtarget features into a single list. The
macro is expanded twice: once in the protected section to generate
member variable declarations, and once in the public section to generate
the corresponding getter methods. This reduces the file by approximately
600 lines while preserving the exact same API and functionality.
Features with complex getter logic or inconsistent naming conventions
are left as manual implementations for future improvement.
Ideally, these could be generated by TableGen using
`GET_SUBTARGETINFO_MACRO`, similar to the X86 backend. However,
`AMDGPU.td` has several issues that prevent direct adoption: duplicate
field names (e.g., `DumpCode` is set by both `FeatureDumpCode` and
`FeatureDumpCodeLower`), and inconsistent naming conventions where many
features don't have the `Has` prefix (e.g., `FlatAddressSpace`,
`GFX10Insts`, `FP64`). Fixing these issues would require renaming fields
in `AMDGPU.td` and updating all references, which is left for future
work.
Commit: 0e5ab0f4f412a30751bea9d83cb97e0d754bc032
https://github.com/llvm/llvm-project/commit/0e5ab0f4f412a30751bea9d83cb97e0d754bc032
Author: Jonathan Wakely <jwakely at redhat.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M compiler-rt/lib/asan/asan_fake_stack.cpp
Log Message:
-----------
[asan] Fix -Wformat warning for %zx with pointer argument (#177219)
Fixes #175045
Commit: b1907c109c95431ebf0bb6f128c3bbf3fb89b6de
https://github.com/llvm/llvm-project/commit/b1907c109c95431ebf0bb6f128c3bbf3fb89b6de
Author: Ravil Dorozhinskii <ravil.aviva.com at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma.mlir
M mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[ROCDL] Refactored MFMA ops in ODS; added constraints (#175775)
This PR improves the ROCDL MFMA intrinsics by making their operand and
result types explicit in the IR and by modeling immediate arguments
(immargs) as attributes rather than opaque operands.
This brings MFMA intrinsics in line with recent changes made to ROCDL
WMMA operations, where intrinsic signatures were clarified to avoid
treating them as an unstructured “blob of arguments”.
Commit: ee0fb4c395e18fbf70f663acc536050505a13661
https://github.com/llvm/llvm-project/commit/ee0fb4c395e18fbf70f663acc536050505a13661
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/test/MC/AMDGPU/gfx1250_asm_load_tr.s
Log Message:
-----------
[AMDGPU] Auto-generate checks for gfx1250_asm_load_tr.s, NFC (#177220)
Commit: 795d940254aa357cb5095ad776c04e72ced08b9d
https://github.com/llvm/llvm-project/commit/795d940254aa357cb5095ad776c04e72ced08b9d
Author: Augusto Noronha <anoronha at apple.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M lldb/source/API/CMakeLists.txt
Log Message:
-----------
[lldb][cmake] Fix standalone Xcode build header staging (#177033)
The LLDB standalone build using Xcode fails because the staging
directory custom command output is attached to multiple
liblldb-stage-header-* targets, but none of these targets depend on each
other. Xcode's new build system doesn't allow this.
This creates a new target `liblldb-header-staging-dir` that depends on
the staging directory creation, and makes all header staging targets
depend on it instead of directly depending on the directory in their
custom commands. This ensures all targets share a common dependency,
satisfying Xcode's build system requirements.
Commit: d64d3735ab06cd1304fb383543312c355c45eeb8
https://github.com/llvm/llvm-project/commit/d64d3735ab06cd1304fb383543312c355c45eeb8
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/phi-multi-same-nodes.ll
Log Message:
-----------
[SLP]Correctly handle vector nodes, coming from same incoming blocks in PHI nodes
If multiple nodes are generated from same PHI node for the same block,
still need to vectorize vector nodes, even if the value for the incoming block was already emitted.
Fixes #177124
Commit: fa4f7657a24baf21a2127652ae4f1c3ba800c24d
https://github.com/llvm/llvm-project/commit/fa4f7657a24baf21a2127652ae4f1c3ba800c24d
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
[AMDGPU] Further improve `AMDGPUSubtargetFeature` multiclass (#177077)
This PR extends the multiclass to support two additional parameters: one
for specifying whether an `AssemblerPredicate` should be generated, and
another for dependent `SubtargetFeatures`. This allows 15 more
definitions to be converted to use the multiclass.
Commit: 14fe4a89e4db1ed0119c855a49cbfe7531d60b4f
https://github.com/llvm/llvm-project/commit/14fe4a89e4db1ed0119c855a49cbfe7531d60b4f
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M lldb/include/lldb/Utility/UserID.h
Log Message:
-----------
[lldb] Remove unused nested class UserID::IDMatches (NFC) (#177211)
Commit: b5077a7712342eaf6d3d7aa14829040c1252965f
https://github.com/llvm/llvm-project/commit/b5077a7712342eaf6d3d7aa14829040c1252965f
Author: David Green <david.green at arm.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/sink-and-fold-illegal-shift.ll
M llvm/test/CodeGen/AArch64/aarch64-mops.ll
M llvm/test/CodeGen/AArch64/cpa-globalisel.ll
M llvm/test/CodeGen/AArch64/load-store-forwarding.ll
Log Message:
-----------
[AArch64][GlobalISel] Extend smaller than i32 gpr loads/stores in RegBankSelect. (#175810)
A i8 / i16 load and store is only legal for FPR registers. This patch extends
the types on i8/i16 G_LOADS and G_STORES to i32 using anyext / trunc, so that
selection can be simpler and does not need to handle illegal operations.
This can leave some anyext(trunc) operations that could be removed yet but
should be possible to optimize away.
Commit: 6788e8c7d5556590e1fa99ffe51af4754bc99add
https://github.com/llvm/llvm-project/commit/6788e8c7d5556590e1fa99ffe51af4754bc99add
Author: David Green <david.green at arm.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
A llvm/test/CodeGen/AArch64/aarch64-condopt-nzcvdef.mir
Log Message:
-----------
[AArch64] Handle all NZCV clobbers in AArch64ConditionOptimizer (#177034)
This pass was special casing some instructions that could clobber NZCV between
a CMP and a Bcc. This patch alters that to all instructions that might modify
NZCV, making sure we handle all cases.
Commit: 6ec2f97c7c589113027bf95b65159ea43c1716d5
https://github.com/llvm/llvm-project/commit/6ec2f97c7c589113027bf95b65159ea43c1716d5
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M utils/bazel/.bazelrc
Log Message:
-----------
[bazel] Suppress `-Wunused-command-line-argument` for header parsing (#177246)
Running bazel CI is full of warnings like this:
```
INFO: From Compiling libc/hdr/types/clock_t.h:
clang-21: warning: argument unused during compilation: '-c' [-Wunused-command-line-argument]
```
https://github.com/bazelbuild/rules_cc/pull/573 is a possible fix in
bazel itself. Until then, just use a copt to ignore it.
Commit: dd363d06290d6fce22bde191f75d8b126d2c751b
https://github.com/llvm/llvm-project/commit/dd363d06290d6fce22bde191f75d8b126d2c751b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[VPlan] Replace UnrollPart for VPScalarIVSteps with start index op (NFC) (#170906)
Replace the unroll part operand for VPScalarIVStepsRecipe with the start
index. This simplifies https://github.com/llvm/llvm-project/pull/170053
and is also a first step to break down the recipe into its components.
PR: https://github.com/llvm/llvm-project/pull/170906
Commit: 6367c4bae0071e016ce7e5fa4b444b63040c9f97
https://github.com/llvm/llvm-project/commit/6367c4bae0071e016ce7e5fa4b444b63040c9f97
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M cmake/Modules/HandleDoxygen.cmake
Log Message:
-----------
[cmake][NFC] CRLF -> LF
Commit: 83b13e6de9f5c944d823da1a61aa971d9ffb0e93
https://github.com/llvm/llvm-project/commit/83b13e6de9f5c944d823da1a61aa971d9ffb0e93
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
Log Message:
-----------
[VPLan] Update formatting in getSCEVExprForVPValue (NFC).
Reformat TypeSwitch in getSCEVExprForVPValue, to reduce diff in
follow-up changes.
Commit: 3beb520ce1b409fe9dcd50d0e7c73cf2efe54252
https://github.com/llvm/llvm-project/commit/3beb520ce1b409fe9dcd50d0e7c73cf2efe54252
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
Log Message:
-----------
[VPlan] Support VPWidenPointerInduction in getSCEVExprForVPValue (NFCI)
Support VPWidenPointerInductionRecipe in getSCEVExprForVPValue.
This is used in code paths when computing SCEV expressions in the
VPlan-based cost model, which should produce costs matching the legacy
cost model.
Commit: 5c29b64fda6a5a66e09378eec9f28a42066a7c6a
https://github.com/llvm/llvm-project/commit/5c29b64fda6a5a66e09378eec9f28a42066a7c6a
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/lib/CodeGen/CGObjC.cpp
M clang/test/CodeGenObjC/arc-arm.m
M clang/test/CodeGenObjC/arc-foreach.m
M clang/test/CodeGenObjC/arc-property.m
M clang/test/CodeGenObjC/arc-related-result-type.m
M clang/test/CodeGenObjC/arc-unopt.m
M clang/test/CodeGenObjC/arc-unsafeclaim.m
M clang/test/CodeGenObjC/arc-with-atthrow.m
M clang/test/CodeGenObjC/ns_consume_null_check.m
M clang/test/CodeGenObjC/objc-arc-container-subscripting.m
M clang/test/CodeGenObjC/os_log.m
M clang/test/CodeGenObjCXX/auto-release-result-assert.mm
M clang/test/CodeGenObjCXX/inheriting-constructor-cleanup.mm
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/test/CodeGen/AArch64/call-rv-marker.ll
Log Message:
-----------
[CGObjC] Allow clang.arc.attachedcall on -O0 (#164875)
It is supported in GlobalISel there. On X86, we always kick to
SelectionDAG anyway, so there is no point in not doing it for X86 too.
I do not have merge permissions.
Commit: b887b523a2fa9b73adf60563843f6ac72caed78c
https://github.com/llvm/llvm-project/commit/b887b523a2fa9b73adf60563843f6ac72caed78c
Author: Thurston Dang <thurston at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt_f32_su32.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt_n.ll
Log Message:
-----------
[msan] Handle aarch64_neon_vcvt* (#177243)
This fills in missing gaps in MSan's AArch64 NEON vector conversion
intrinsic handling (intrinsics named aarch64_neon_vcvt* instead of
aarch64_neon_fcvt*). SVE support sold separately.
It also generalizes handleNEONVectorConvertIntrinsic to handle
conversions to/from fixed-point.
Commit: 8eac375a4bff84f0a10a9c8ee23c4da409a805f9
https://github.com/llvm/llvm-project/commit/8eac375a4bff84f0a10a9c8ee23c4da409a805f9
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/lib/CodeGen/CGObjC.cpp
M clang/test/CodeGenObjC/arc-arm.m
M clang/test/CodeGenObjC/arc-foreach.m
M clang/test/CodeGenObjC/arc-property.m
M clang/test/CodeGenObjC/arc-related-result-type.m
M clang/test/CodeGenObjC/arc-unopt.m
M clang/test/CodeGenObjC/arc-unsafeclaim.m
M clang/test/CodeGenObjC/arc-with-atthrow.m
M clang/test/CodeGenObjC/ns_consume_null_check.m
M clang/test/CodeGenObjC/objc-arc-container-subscripting.m
M clang/test/CodeGenObjC/os_log.m
M clang/test/CodeGenObjCXX/auto-release-result-assert.mm
M clang/test/CodeGenObjCXX/inheriting-constructor-cleanup.mm
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/test/CodeGen/AArch64/call-rv-marker.ll
Log Message:
-----------
Revert "[CGObjC] Allow clang.arc.attachedcall on -O0 (#164875)"
This reverts commit 5c29b64fda6a5a66e09378eec9f28a42066a7c6a.
This was causing failures at HEAD on x86-64 Linux.
Commit: 2692f5ed537ff81f057340aeaba933428ba3bdd8
https://github.com/llvm/llvm-project/commit/2692f5ed537ff81f057340aeaba933428ba3bdd8
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/R600Subtarget.h
Log Message:
-----------
[NFCI][AMDGPU] Convert more `SubtargetFeatures` to use `AMDGPUSubtargetFeature` and X-macros (#177256)
Extend the X-macro pattern to eliminate boilerplate for additional
subtarget features.
This reduces ~50 lines of repetitive member declarations and getter
definitions.
Commit: d80ba5ee496d43d25db04e767eb465c3f4d8f377
https://github.com/llvm/llvm-project/commit/d80ba5ee496d43d25db04e767eb465c3f4d8f377
Author: Amina Chabane <amina.chabane at arm.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-forwarding.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s
Log Message:
-----------
[AArch64] Model Neoverse N2 late forwarding (#176331)
This patch models late forwarding for N2 as per the [N2
SWOG](https://developer.arm.com/documentation/109914/latest/).
Commit: 643b31a65c86647c4c5482f2b8469e30295fe17d
https://github.com/llvm/llvm-project/commit/643b31a65c86647c4c5482f2b8469e30295fe17d
Author: yronglin <yronglin777 at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaStmt.cpp
M clang/test/CXX/special/class.temporary/p6.cpp
Log Message:
-----------
[clang] Fix lifetime extension of temporaries in for-range-initializers in templates (#177191)
Fixes https://github.com/llvm/llvm-project/issues/165182.
This patch fix the lifetime extension of temporaries in
for-range-initializers in templates. Whether this issue was occurred
when the for-range statement in a dependent context, but itself is not
type/value dependent.
---------
Signed-off-by: Wang, Yihan <yronglin777 at gmail.com>
Commit: c3c22c945aacf432ae6d2fe710b636f6c4235c25
https://github.com/llvm/llvm-project/commit/c3c22c945aacf432ae6d2fe710b636f6c4235c25
Author: Augusto Noronha <anoronha at apple.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M lldb/test/API/functionalities/ubsan/basic/TestUbsanBasic.py
Log Message:
-----------
[lldb] Skip TestUbsanBasic (#177263)
The fix for this is being discussed in
https://github.com/llvm/llvm-project/issues/177064. Skip the test for
now to get the bots green.
Commit: 5e4f8d74867ba08d0d8b65307d81ad087441e65c
https://github.com/llvm/llvm-project/commit/5e4f8d74867ba08d0d8b65307d81ad087441e65c
Author: Julian Pokrovsky <raventid at users.noreply.github.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
Log Message:
-----------
[CIR][X86] Add support for shuff32x4/shufi32x4 builtins (#172960)
This implementation is adapted from the existing code for
`X86::BI__builtin_ia32_shuf_i*` and `X86::BI__builtin_ia32_shuf_f*` from
`/llvm-project/clang/lib/CodeGen/TargetBuiltins/X86.cpp`.
It adds support for the following X86 builtins:
- __builtin_ia32_shuf_f32x4
- __builtin_ia32_shuf_f64x2
- __builtin_ia32_shuf_i32x4
- __builtin_ia32_shuf_i64x2
- __builtin_ia32_shuf_f32x4_256
- __builtin_ia32_shuf_f64x2_256
- __builtin_ia32_shuf_i32x4_256
- __builtin_ia32_shuf_i64x2_256
Part of https://github.com/llvm/llvm-project/issues/167765
Commit: 084916a1696a5f279e44b144fc0b40fd92e3167c
https://github.com/llvm/llvm-project/commit/084916a1696a5f279e44b144fc0b40fd92e3167c
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/test/Analysis/LifetimeSafety/benchmark.py
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
M clang/test/Sema/warn-lifetime-safety-dataflow.cpp
M clang/test/Sema/warn-lifetime-safety-missing-origin-stats.cpp
M clang/test/Sema/warn-lifetime-safety-suggestions.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
Log Message:
-----------
[LifetimeSafety] Remove "experimental-" prefix from flags and diagnostics (#176821)
Remove the "experimental-" prefix from lifetime safety diagnostic groups
and command-line options. This enables the analysis in `-Wall`.
We are now in a pretty stable state with no crashes. This change
indicates that lifetime safety analysis is no longer considered
experimental and is now a stable feature. By removing the
"experimental-" prefix, we're signaling to users that this functionality
is ready for use.
- Renamed diagnostic groups from `experimental-lifetime-safety*` to
`lifetime-safety*`
- Updated command-line options from `-fexperimental-lifetime-safety*` to
`-flifetime-safety*` and this is now ON by default.
- Added a check to only enable lifetime safety analysis when relevant
diagnostics are enabled
- Updated test files to use the new flag names
Commit: 688a88408d81bf26fec50b8ae0d61110e7c06542
https://github.com/llvm/llvm-project/commit/688a88408d81bf26fec50b8ae0d61110e7c06542
Author: James Y Knight <jyknight at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp
Log Message:
-----------
[clang][test] Specify value of `-fopenmp=libomp` for tests. (#177239)
`libomp` is the default value when unconfigured in cmake, but llvm can
be configured to have `libgomp` be the default instead. Explicitly
specify this value so the test does not fail when it assumes libomp is
always the default.
Fix for f369d23ceaa49ffa9e6ef9673851749d66b35b3f (#150580)
Commit: 5bcfe6e60696bb3cad5ebb9f3b6b469c24ec0061
https://github.com/llvm/llvm-project/commit/5bcfe6e60696bb3cad5ebb9f3b6b469c24ec0061
Author: Mariusz Borsa <wrotki at msn.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/tests/sanitizer_procmaps_mac_test.cpp
Log Message:
-----------
[Sanitizers] Remove unused variable (#177061)
Must've remained from debugging the test case.
rdar://119958411
Co-authored-by: Mariusz Borsa <m_borsa at apple.com>
Commit: 24b86130ef0def2c3954852e0a8746392a782fa0
https://github.com/llvm/llvm-project/commit/24b86130ef0def2c3954852e0a8746392a782fa0
Author: knickish <knickish at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/M68k/M68kCollapseMOVEMPass.cpp
M llvm/test/CodeGen/M68k/CollapseMOVEM.mir
Log Message:
-----------
[M68k] Fix MOVEM collapse pass for 2 instances of same register (#174349)
Add test case for MOVEM collapse opt pass failure and fix pass handling
of 2 appearances of the same register in a MOVEM block.
Commit: 138910d5d51a58839fe8cf279a45c1a5f6cec3ae
https://github.com/llvm/llvm-project/commit/138910d5d51a58839fe8cf279a45c1a5f6cec3ae
Author: Matthew Maurer <matthew.r.maurer at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/include/llvm/IR/Attributes.h
M llvm/lib/IR/Attributes.cpp
Log Message:
-----------
[IR] Support constructing `dead_on_return` without an argument (#177272)
After #171712, `dead_on_return` takes an optional argument indicating
the number of bytes known dead. The existing clang callsite uses the
attribute builder interface directly which supports the optional
argument through `DeadOnReturnInfo`. However, users constructing the
Attribute directly (e.g. `rustc`) were using `Attribute::get` which will
now default to providing a 0 value to the optional argument.
Add the additional method `Attribute::getWithDeadOnReturnInfo` to allow
users which produce explicit `Attribute` values to continue to indicate
`dead_on_return` without an argument.
Commit: 00fecbcf00f96e816608dcf8e82562e6aa272d21
https://github.com/llvm/llvm-project/commit/00fecbcf00f96e816608dcf8e82562e6aa272d21
Author: Ben Dunbobbin <Ben.Dunbobbin at sony.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M cross-project-tests/dtlto/archive.test
M cross-project-tests/dtlto/archives-mixed-lto-modes-test.test
M cross-project-tests/dtlto/archives-same-module-id.test
M cross-project-tests/dtlto/link-archive-thin.test
M cross-project-tests/dtlto/signal.test
Log Message:
-----------
[DTLTO][NFC] Minor cleanups and improvements to DTLTO tests (#177282)
This change makes small, non-functional improvements to the DTLTO test
suite, including:
- Tightening+Regularizing FileCheck match expressions across tests
- Simplifying `signal.test` using more lit macro features
Commit: 53c237c00667502a69f9e3df4d60d3bd80ae3ba8
https://github.com/llvm/llvm-project/commit/53c237c00667502a69f9e3df4d60d3bd80ae3ba8
Author: Sam Clegg <sbc at chromium.org>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M lld/COFF/Config.h
M lld/COFF/Driver.cpp
M lld/COFF/MinGW.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/Writer.cpp
Log Message:
-----------
[lld][COFF] Use `.contains` rather than `.count` for set membership. NFC (#177067)
Also converted a couple of `std::set` to
`llvm::StringSet`/`llvm::SmallSet`.
This matches the usage in the other linker backends.
See #176610
Commit: b857faeda6eec88e056fb0f95b1d4beed634f29e
https://github.com/llvm/llvm-project/commit/b857faeda6eec88e056fb0f95b1d4beed634f29e
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
Log Message:
-----------
[NFC][AMDGPU] Remove stale/dangling comments
Commit: 11b9e5f5ab6e5088286d856b595d80117e337f6c
https://github.com/llvm/llvm-project/commit/11b9e5f5ab6e5088286d856b595d80117e337f6c
Author: Iñaki V Arrechea <inakiarrechea at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Analysis/FunctionPropertiesAnalysis.cpp
Log Message:
-----------
Remove nomenclature clash in statistic pass with one of the stats (#177267)
Attribute TotalInstructionCount is used, but previously the name of the
stat printed out was "Total"+property, which made it look like
TotalTotalInstruction. Num does not provide such clashes in the
nomenclature.
Commit: 688b01ad529b85a38509d6c27dc0376816e027f2
https://github.com/llvm/llvm-project/commit/688b01ad529b85a38509d6c27dc0376816e027f2
Author: Michael Park <mcypark at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/Modules/pr171769.cpp
M clang/unittests/Serialization/CMakeLists.txt
A clang/unittests/Serialization/NamespaceLookupTest.cpp
Log Message:
-----------
[C++20][Modules] Improve namespace look-up performance for modules. (Attempt #2) (#177255)
Commit: 2688b124b104979bcdf4bfc3e1b1bb6386985bc1
https://github.com/llvm/llvm-project/commit/2688b124b104979bcdf4bfc3e1b1bb6386985bc1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/unittests/Serialization/BUILD.gn
Log Message:
-----------
[gn build] Port 688b01ad529b
Commit: 503db9859e43b775dfbb4d8765e0ce9ad84fae58
https://github.com/llvm/llvm-project/commit/503db9859e43b775dfbb4d8765e0ce9ad84fae58
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M libcxx/include/__iterator/wrap_iter.h
Log Message:
-----------
[libc++][NFC] Reformat `wrap_iter.h` (#177127)
As a pre-requisite to https://github.com/llvm/llvm-project/pull/172200
Commit: 8c8661e170d49afb8cae3914fa28346e5089ecad
https://github.com/llvm/llvm-project/commit/8c8661e170d49afb8cae3914fa28346e5089ecad
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M libcxx/include/__ranges/subrange.h
Log Message:
-----------
[libc++][NFC] Reformat `subrange.h` (#177118)
As a pre-requisite to https://github.com/llvm/llvm-project/pull/176936
Commit: b57dcfff1d74c2d843e7ad7c28adb39799ca4bc8
https://github.com/llvm/llvm-project/commit/b57dcfff1d74c2d843e7ad7c28adb39799ca4bc8
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFFunctionRewrite.cpp
Log Message:
-----------
[flang][cuda][NFC] Fix typo in header (#177299)
Commit: 1869b15a0569e4e0fa0b97ee462db4e826519d4f
https://github.com/llvm/llvm-project/commit/1869b15a0569e4e0fa0b97ee462db4e826519d4f
Author: Fangrui Song <i at maskray.me>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M lld/ELF/MarkLive.cpp
M lld/test/ELF/why-live.test
Log Message:
-----------
[ELF] --why-live: Skip symbol at index 0 and section symbols, handle .eh_frame symbols (#177099)
Symbols of empty names can be matched by `--why-live='*'`, which are
generally not useful.
* The first entry in a symbol table (STB_LOCAL and undefined)
* `STT_SECTION` symbols (emitted by LLVM integrated assembler when
needed by relocations). These input section symbols will be demoted by
`demoteAndCopyLocalSymbols`, so technically not really live.
In addition, such symbols of non-allocable sections currently lead to
crashes: `whyLive` does not record the section, causing the second
iteration of the `while (true)` loop in printWhyLive to call
`std::get<Symbol *>(cur)` when `cur` is an `InputSectionBase *`.
In addition, handle GCC crtendS.o `__FRAME_END__`, which is defined
relative to a `.eh_frame` section created with
`__attribute__((used, section(".eh_frame")))`.
Fix #176890
Commit: 614989535419d5d3bc16703cf38c010659baaa82
https://github.com/llvm/llvm-project/commit/614989535419d5d3bc16703cf38c010659baaa82
Author: Lang Hames <lhames at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M orc-rt/unittests/bit-test.cpp
Log Message:
-----------
[orc-rt] Actually test orc-rt/bit.h functions. (#177300)
The unit test was copied from a similar test in llvm, and was still
qualifying calls with 'llvm::'. This was unintended, but happened to
work because LLVM's bit.h is transitively included through LLVM's gtest
headers. Qualifying with 'orc_rt::' tests the intended functions.
Thanks to @jaredwy for spotting this!
Commit: d7d47864820b3610fdff04ca5380cd5762b609f0
https://github.com/llvm/llvm-project/commit/d7d47864820b3610fdff04ca5380cd5762b609f0
Author: yronglin <yronglin777 at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/www/cxx_status.html
Log Message:
-----------
[NFC][clang] Mark P3034R1 as implemented (#177150)
Mark [P1857R3 Modules Dependency Discovery](https://wg21.link/p1857r3)
as implemented.
This paper was implemented in
https://github.com/llvm/llvm-project/pull/173789.
Signed-off-by: yronglin <yronglin777 at gmail.com>
Commit: e838f27e0f3f417e3963992c9591d412b621cd4c
https://github.com/llvm/llvm-project/commit/e838f27e0f3f417e3963992c9591d412b621cd4c
Author: Lang Hames <lhames at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M orc-rt/unittests/EndianTest.cpp
Log Message:
-----------
[orc-rt] Update another unittest to use orc-rt/bit.h functions. (#177303)
Unit test was mistakenly using an `llvm::` function.
Thanks to @jaredwy for spotting this!
Commit: 2036bc524bc404ed3bb97375ef050a6cb9b4b8c8
https://github.com/llvm/llvm-project/commit/2036bc524bc404ed3bb97375ef050a6cb9b4b8c8
Author: Luke Lau <luke at igalia.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
M llvm/lib/IR/IRBuilder.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
Log Message:
-----------
[IR] Update IRBuilder::createVectorSplice to allow variable offsets (#177178)
Following on from #174693, this updates IRBuilder to allow variable
offsets, and splits the createVectorSplice function into two functions
for left and right splices.
We could preserve the existing createVectorSplice API but given there's
only one LLVM-internal user of it in the loop vectorizer, and the notion
of a negative offset doesn't exist in the intrinsics anymore, I've
removed it. Happy to add it back if reviewers prefer though.
I've also added unit tests since createVectorSpliceLeft has no coverage
otherwise.
Commit: 2b22d76ba773dee4a8d07fc284e1dab2524b6b47
https://github.com/llvm/llvm-project/commit/2b22d76ba773dee4a8d07fc284e1dab2524b6b47
Author: Lang Hames <lhames at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M orc-rt/include/orc-rt/bit.h
M orc-rt/unittests/EndianTest.cpp
M orc-rt/unittests/bit-test.cpp
Log Message:
-----------
[orc-rt] Implement rotl / rotr, fix missing include in unit test. (#177305)
In e838f27e0f3 the EndianTest.cpp unittest was updated to avoid using
`llvm::rotl` function, but the corresponding `orc_rt::rotl` function had
not been implemented yet.
This commit implements orc_rt::rotl, orc_rt::rotr, and
orc_rt::has_single_bit by copying their definitions from the
corresponding LLVM header (llvm-project/llvm/include/llvm/ADT/bit.h).
Unit tests for these functions are also copied from their LLVM
counterparts.
Thanks to @jaredwy for spotting this!
Commit: 73a309e20e92ff8e9af295c81ee74a58b07a93ba
https://github.com/llvm/llvm-project/commit/73a309e20e92ff8e9af295c81ee74a58b07a93ba
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir
M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
A llvm/test/CodeGen/RISCV/rvv/pr171231.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
M llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll
M llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
M llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
M llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
Log Message:
-----------
[RISCV] Add ZZZ_ to some inline assembly vector register classes to sort them after VR/VRNoV0 in regclass enum. (#177087)
This prevents getCommonSubClass from finding them before VR/VRNoV0.
Fixes a crash reported post-commit in #171231. getCommonSubClass
returned one of these classes, but it doesn't have the same VTs as
VR/VRNoV0 leading to an assertion failure.
The subregister-undef-early-clobber.mir still ends up finding these
register classes in the InitUndef pass.
Commit: f2a3079a1b48033a92d0a7d9f03251ebeb4a0c30
https://github.com/llvm/llvm-project/commit/f2a3079a1b48033a92d0a7d9f03251ebeb4a0c30
Author: Volodymyr Sapsai <vsapsai at apple.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/lib/Serialization/ModuleManager.cpp
A clang/test/ClangScanDeps/build-session-validation-outdated-module.c
Log Message:
-----------
[Modules] Fix spurious errors about module input file changing after .pcm file was built. (#176537)
For incremental multi-process/multi-thread compilation utilizing a build
session fix errors like
> fatal error: file '/path/to/Frmwrk.framework/Headers/Header.h' has been modified since the module file '/path/to/ModuleCache.noindex/XXX/Frmwrk-YYY.pcm' was built: mtime changed (was aaa, now bbb)
Another symptom of the bug is when you check Frmwrk.pcm the header's
mtime is correct, so it is confusing where "was aaa" is even coming from.
The main problem is that in case of a signature mismatch
`ModuleManager::addModule` returns `OutOfDate` but keeps .pcm buffer in
`InMemoryModuleCache`. So if later on it tries to use such a module, it
would have an outdated buffer in `InMemoryModuleCache`. If another
process/thread happens to rebuild such module and write a new validation
timestamp, the original process would skip the input file validation and
would keep using the outdated .pcm buffer hitting errors about
unexpected input modifications.
I want to note that in the current implementation the validation
timestamp can be still incorrect. When we are writing AST we don't
account for the case when an input file is modified after its mtime and
size are captured. We are relying on the input files not being modified
while building a module using these files.
rdar://165237499
Commit: c91d5c76db36c0fe7df72c93945a131f08f43030
https://github.com/llvm/llvm-project/commit/c91d5c76db36c0fe7df72c93945a131f08f43030
Author: Rux124 <jhlee755 at andestech.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Utils/InjectTLIMappings.cpp
M llvm/test/Transforms/Util/add-TLI-mappings.ll
Log Message:
-----------
InjectTLIMappings: remove incompatible attributes from vector declarations. (#173206)
Some attributes (e.g., the signext attribute) are not supported on
vector types; adding them would cause the verifier pass to fail.
Commit: 962a9a3be967b4967fe5b73a330f5be73dcf261a
https://github.com/llvm/llvm-project/commit/962a9a3be967b4967fe5b73a330f5be73dcf261a
Author: James Newling <james.newling at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize-conv.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/Vector/canonicalize/vector-from-elements.mlir
A mlir/test/Dialect/Vector/canonicalize/vector-to-shape-cast.mlir
M mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir
M mlir/test/Dialect/Vector/vector-warp-distribute.mlir
Log Message:
-----------
[mlir][vector] Canonicalize vector.extract and vector.broadcast to vector.shape_cast (#174452)
Based on the original PR
https://github.com/llvm/llvm-project/pull/140583, but without
vector.transpose -> vector.shape_cast.
This PR canonicalizes
%0 = vector.broadcast %arg0 : vector<4xi8> to vector<1x1x4xi8>
%2 = vector.extract %arg2[0] : vector<4xi8> from vector<1x4xi8>
to shape_cast. It was decided (see
https://github.com/llvm/llvm-project/pull/140583) that the
vector.transpose -> vector.shape_cast needs further consideration before
being added.
---------
Signed-off-by: James Newling <james.newling at gmail.com>
Commit: 1b37911f1a90edd0bef0090010d0267cd1605255
https://github.com/llvm/llvm-project/commit/1b37911f1a90edd0bef0090010d0267cd1605255
Author: Yaxing Cai <caiyaxing666 at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M compiler-rt/lib/orc/elfnix_platform.cpp
A compiler-rt/test/orc/TestCases/Linux/Generic/ctor-dtor.cpp
M llvm/include/llvm/ExecutionEngine/Orc/ELFNixPlatform.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/ObjectFormats.h
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/ObjectFormats.cpp
Log Message:
-----------
[ORC] Fix missing support of deinitialize on ELF platform and execution order by priority (#175981)
This PR fixes
1. issue #175509 about missing support of deinitialize on ELF platform.
2. missing support of execution order by proirity at both initialize and
deinitialize stage.
cc: @tqchen @joker-eph
Commit: a581ceb3e3953e690af53fa8f64e84edbcde29dd
https://github.com/llvm/llvm-project/commit/a581ceb3e3953e690af53fa8f64e84edbcde29dd
Author: Haowei <haowei at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/CMakeLists.txt
Log Message:
-----------
[clang][cmake] Use llvm-libtool-darwin in clang multi-stage build (#177277)
We are seeing the build system uses the XCode's libtool when building
the 2nd stage of the clang on mac. We should use the llvm-libtool-darwin
from the previous stage clang build instead. This patch makes multi-stage
clang build to use llvm-libtool-darwin from the previous stage when targeting
mac.
Commit: cfc876998e06a0916338c3d286c5b169c9d78274
https://github.com/llvm/llvm-project/commit/cfc876998e06a0916338c3d286c5b169c9d78274
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/utils/TableGen/DAGISelMatcher.cpp
Log Message:
-----------
[TableGen] Make sure ResNo is the same in CheckTypeMatcher::isContradictoryImpl. (#177312)
CheckType can only be contradictory if the same result is being checked.
Noticed while looking at the code. This doesn't affect the output on any
in tree targets.
Commit: 4fe4f23e2f4334b63172b16ae837c34bf4a537d7
https://github.com/llvm/llvm-project/commit/4fe4f23e2f4334b63172b16ae837c34bf4a537d7
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
[TargetParser] Fix fp16 feature name for ARM64 Windows feature detection (#176925)
The feature is called fullfp16, not fp16, see:
https://github.com/llvm/llvm-project/blob/979db00b9a2401b65725f44de8172aba79cacd38/llvm/lib/Target/AArch64/AArch64Features.td#L142
Commit: 15e421dc643ce4d9d79174fec585cf787e56b1a0
https://github.com/llvm/llvm-project/commit/15e421dc643ce4d9d79174fec585cf787e56b1a0
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/MC/MCObjectStreamer.cpp
Log Message:
-----------
[MC] Explicitly use memcpy in emitBytes() (NFC) (#177187)
We've observed a compile-time regression in LLVM 22 when including large
blobs. The root cause was that emitBytes() was copying bytes one-by-one,
which is much slower than using memcpy for large objects.
Optimization of std::copy to memmove is apparently much less reliable
than one might think. In particular, when using a non-bleeding-edge
libstdc++ (anything older than version 15), this does not happen if the
types of the input and output iterators do not match (like here, where
there is a signed/unsigned mismatch).
As this code is performance sensitive, I think it makes sense to
directly use memcpy.
Previously this code used SmallVector::append, which explicitly uses
memcpy.
Commit: fa0071baabe9f8ca4069dbe6222e04740f0a5382
https://github.com/llvm/llvm-project/commit/fa0071baabe9f8ca4069dbe6222e04740f0a5382
Author: nataliakokoromyti <nataliakokoromyti at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
A llvm/test/Transforms/CodeGenPrepare/X86/codegenprepare-hang-bitcast-phi.ll
Log Message:
-----------
[CodeGenPrepare] Fix infinite loop with same-type bitcasts (#176694)
OptimizeNoopCopyExpression was sinking same-type bitcasts (e.g. bitcast
i32 to i32) which would then be reintroduced by optimizePhiType, causing
an infinite loop.
Fix by adding a check (PhiTy == ConvertTy) in optimizePhiType to skip
the conversion when types are already identical.
Fixes #176688.
Commit: efe9b436e07555d0cd54b2e3bfd3f5c6df1f4af4
https://github.com/llvm/llvm-project/commit/efe9b436e07555d0cd54b2e3bfd3f5c6df1f4af4
Author: nataliakokoromyti <nataliakokoromyti at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
A llvm/test/CodeGen/AMDGPU/issue176966-extend-vector-inreg.ll
Log Message:
-----------
Fix EXTEND_VECTOR_INREG widening when input > result size (#177095)
This patch fixes an LLVM crash on AMDGPU that occurred when compiling
valid code involving non-power-of-two vector sizes. During type
legalization, LLVM widened an EXTEND_VECTOR_INREG operation by first
widening the input vector, which could make the input larger than the
result and trigger an assertion failure.
The fix changes the logic to widen the result first and then extract the
needed portion so there's no invalid size mismatch. I've added a test
that previously crashed but now doesn't.
fixes #176966.
---------
Co-authored-by: Natalia Kokoromyti <knatalia at yost-cm-01-imme.stanford.edu>
Commit: 524589119afd59525ab1f124a1538f0311d608de
https://github.com/llvm/llvm-project/commit/524589119afd59525ab1f124a1538f0311d608de
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/TargetLoweringBase.cpp
A llvm/test/CodeGen/fptoi-256.ll
Log Message:
-----------
[LLVM] Update the default value for MaxLargeFPConvertBitWidthSupported to 128 (#176851)
Previously, we can't compile the program which convert 256 bits to
floating points and vice versa(we'll crash). After this, we're able to
compile them.
Commit: 1d2be35b9b475922c45611cba2a26974fd4c1f1c
https://github.com/llvm/llvm-project/commit/1d2be35b9b475922c45611cba2a26974fd4c1f1c
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/test/CodeGen/fptoi-256.ll
Log Message:
-----------
[NFC] Add the require clause to a test
See https://github.com/llvm/llvm-project/pull/176851
Commit: de997639876db38d20c7ed9fb0c683a239d56bf5
https://github.com/llvm/llvm-project/commit/de997639876db38d20c7ed9fb0c683a239d56bf5
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
[AArch64] Fix partial_reduce v16i8 -> v2i32 (#177119)
The lowering doesn't need to check for `ConvertToScalable`, because it
lowers to another `PARTIAL_REDUCE_*MLA` node, which is subsequently
lowered using either fixed-length or scalable types.
This fixes https://github.com/llvm/llvm-project/issues/176954
Commit: 01ccb4055adba8cec038a72aaad7c9bfba5aca27
https://github.com/llvm/llvm-project/commit/01ccb4055adba8cec038a72aaad7c9bfba5aca27
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/fixed-length-bf16-arith.ll
Log Message:
-----------
[AArch64] Use +0.0 for accumulator for FMUL -> BFMLAL lowering in more cases (#174423)
Depending on the users of the FMUL we may not need to preserve the sign
of the multiplication result (when it is zero).
See: 29611f4cbea0e867a3e55516f8dfdeca595be436
Commit: 59db71c7bd6af903865869674d424429d9da4967
https://github.com/llvm/llvm-project/commit/59db71c7bd6af903865869674d424429d9da4967
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M lldb/test/API/functionalities/ubsan/basic/Makefile
M lldb/test/API/functionalities/ubsan/basic/TestUbsanBasic.py
M lldb/test/API/functionalities/ubsan/basic/main.c
Log Message:
-----------
[lldb][test] Re-enable and fix TestUbsanBasic.py
UBSAN stopped reporting the misaligned load since https://github.com/llvm/llvm-project/commit/5569bf26f0097c2d8b088f0a7cf46451da752dea so this test started failing. We skipped it to unblock CI.
There's been discussion on making UBSAN stricter and still trigger on
the one-line version of this. But for now, to get the test running
again, change it to a form which *does* trigger UBSAN.
Fixes https://github.com/llvm/llvm-project/issues/177064
Commit: 68804704550d663d6bcab7c96c7eae531020b60a
https://github.com/llvm/llvm-project/commit/68804704550d663d6bcab7c96c7eae531020b60a
Author: Thibault Monnier <thibaultmonni at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/Lex/Lexer.cpp
M llvm/include/llvm/Support/Compiler.h
Log Message:
-----------
Revert "[Clang][Lexer] Reland "Detect SSE4.2 availability at runtime in fastParseASCIIIdentifier"" (#177322)
Reverts llvm/llvm-project#175452 because of buildbot failures reported.
Commit: a43b55edf42b4e70e3b26e493e5997a2f5682fea
https://github.com/llvm/llvm-project/commit/a43b55edf42b4e70e3b26e493e5997a2f5682fea
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-arch.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store.ll
M llvm/test/CodeGen/RISCV/atomic-load-store.ll
M llvm/test/CodeGen/RISCV/atomic-load-zext.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/rv32zalasr-invalid.s
M llvm/test/MC/RISCV/rv64zalasr-invalid.s
M llvm/test/MC/RISCV/rv64zalasr-valid.s
M llvm/test/MC/RISCV/rvzalasr-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV]Remove experimental from Zalasr (#177120)
Zalasr 1.0 was ratified in October 2025.
Documentation:https://docs.riscv.org/reference/isa/extensions/zalasr/_attachments/riscv-zalasr.pdf
Commit: fa457302cb6ad12d7e75e078da22ace6bb4184e6
https://github.com/llvm/llvm-project/commit/fa457302cb6ad12d7e75e078da22ace6bb4184e6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
A llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fsub.ll
Log Message:
-----------
InstCombine: Add SimplifyDemandedFPClass fsub baseline tests (#175851)
Commit: 4386ba5805be3050c05b20bf0e5691cd7a7fe28c
https://github.com/llvm/llvm-project/commit/4386ba5805be3050c05b20bf0e5691cd7a7fe28c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
A llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll
A llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll
Log Message:
-----------
InstCombine: Add minnum/maxnum SimplifyDemandedFPClass baseline tests (#177325)
This is just the existing minimumnum/maximumnum tests copied with
find and replace.
Commit: f5ef142c60176817d4da5653dcfa7e3e7c6748a0
https://github.com/llvm/llvm-project/commit/f5ef142c60176817d4da5653dcfa7e3e7c6748a0
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCUtils.cpp
M flang/test/Lower/OpenACC/acc-reduction.f90
Log Message:
-----------
[flang][acc] fix allocatable logical reduction (#177177)
The value types were not properly unwrapped from the variable type in
`getReductionInitValue`, which caused issues with logical reductions on
allocatables or pointers.
Commit: 01f5ae2486427e65a14932a5e590bb9c0fa9ddb1
https://github.com/llvm/llvm-project/commit/01f5ae2486427e65a14932a5e590bb9c0fa9ddb1
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp
Log Message:
-----------
[lldb][ClangExpressionDeclMap][NFC] Reword/add FIXMEs
Commit: 3ea0a0b5eca7adc088bc2d324101a68f4e071110
https://github.com/llvm/llvm-project/commit/3ea0a0b5eca7adc088bc2d324101a68f4e071110
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M mlir/include/mlir/Conversion/TosaToLinalg/TosaToLinalg.h
Log Message:
-----------
[mlir][tosa][nfc] Fix comments (#177335)
Commit: 9bc0e62617ab2a36029b67e8e5fa8b0f0a2fbeb1
https://github.com/llvm/llvm-project/commit/9bc0e62617ab2a36029b67e8e5fa8b0f0a2fbeb1
Author: Tony Linthicum <tony.linthicum at outlook.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
A llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
A llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
Log Message:
-----------
[AMDGPU] Add scheduling stage to rewrite MFMA from VGPR to AGPR (#170335)
This pull request is an update of [Jeff Byrne's
PR](https://github.com/llvm/llvm-project/pull/149367). Additionally, all
unresolved comments from the original PR have been addressed.
Changes to make the MachineScheduler dependent upon
MachineBlockFrequencyInfo have been pulled out into a new PR,
[176172](https://github.com/llvm/llvm-project/pull/176172), upon which
this PR now depends.
---------
Co-authored-by: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Commit: 2b522e0b094acbc1e911b1cfb14a47a0ff91931a
https://github.com/llvm/llvm-project/commit/2b522e0b094acbc1e911b1cfb14a47a0ff91931a
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
Reapply "[AMDGPU] Fix excessive stack usage in SIInsertWaitcnts::run (#134835)" (#174215) (#177338)
This reverts commit 0dd03598dca91c93c74b94a714c38a4ffad0ed1c.
Apparently the stack usage on Windows was still large enough to cause
problems for some DirectX games.
Commit: 70998175a4ed4e45344b407f7449cc9208bdf173
https://github.com/llvm/llvm-project/commit/70998175a4ed4e45344b407f7449cc9208bdf173
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
A llvm/test/CodeGen/X86/combine-bzhi.ll
Log Message:
-----------
[X86] Add BZHI zero mask / constant fold test coverage (#177136)
We need known bits support before we can start adding simplify demanded bits handling to address #176974
Pulled from the instcombine equivalent tests
Commit: 9ec0eccf48e931224ab96454be93ba8e3a006cc5
https://github.com/llvm/llvm-project/commit/9ec0eccf48e931224ab96454be93ba8e3a006cc5
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/test/AST/ByteCode/cxx26.cpp
Log Message:
-----------
[clang][bytecode] Fix a crash with explicit this parameters (#177154)
Fixes https://github.com/llvm/llvm-project/issues/177133
Commit: 1e468b2813bd0518369a7025cee143cf0a4e810c
https://github.com/llvm/llvm-project/commit/1e468b2813bd0518369a7025cee143cf0a4e810c
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.td
M mlir/lib/Dialect/GPU/Transforms/NVVMAttachTarget.cpp
M mlir/test/Dialect/GPU/nvvm-attach-target.mlir
Log Message:
-----------
[MLIR][GPU][NVVM] Add verify-target-arch option to nvvm-attach-target pass (#176774)
This change adds the `verify-target-arch` option to the
`nvvm-attach-target` to control the `verifyTarget` parameter in the
attached `NVVMTargetAttr` which is used to enable/disable the
verification of the target architecture with respect to the NVVM Ops.
Commit: ee95ebe396e567fcf9c12e5843c2761fc26893d3
https://github.com/llvm/llvm-project/commit/ee95ebe396e567fcf9c12e5843c2761fc26893d3
Author: Yingying Wang <3171290993 at qq.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
A llvm/test/Transforms/LoopInterchange/reduction2mem-limitation.ll
A llvm/test/Transforms/LoopInterchange/reduction2mem.ll
Log Message:
-----------
[LoopInterchange] Support the inner-loop reduction via Reduction2Mem (#172970)
Following our
[discussion](https://discourse.llvm.org/t/rfc-plan-to-improve-loopinterchange-by-undoing-simple-reductions/89071),
I ported GCC’s undo_simple_reduction into LLVM.
**Key changes**
- Implement an Reduction2Memory step in LoopInterchange to support the
reduction in the inner loop.
- The feature is behind an option `-loop-interchange-reduction-to-mem`
and is OFF by default. With the feature off, the pass behaves as before
(minimal impact).
- Add a regression test.
**Validation & performance**
- No compile or semantic errors observed on SPEC2006 and SPEC2017 with
the new feature enabled for validation.
- With options: `-da-disable-delinearization-checks` and
`-loop-interchange-reduction-to-mem`
- SPEC2006 410.bwaves on x86 (Intel i9-11900K, Rocket Lake): **+6%**
- SPEC2017 603.bwaves_s on x86 (Intel i9-11900K, Rocket Lake): **+6%**
- SPEC2006 410.bwaves on SpacemiT Key Stone K1: **+29%**
- SPEC2006 410.bwaves on KMH RTL: **+56%**
- SPEC2017 603.bwaves_s on KMH RTL: **+24%**
**Note**
- Reduction2Memory only runs when legality and profitability checks
indicate the interchange will actually be performed. If interchange is
illegal or not profitable, no reduction2mem is applied.
---------
Co-authored-by: ict-ql <168183727+ict-ql at users.noreply.github.com>
Co-authored-by: Lin Wang <wanglulin at ict.ac.cn>
Co-authored-by: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Commit: 699792b94bc7d8983b600482841fb7c3869be5b6
https://github.com/llvm/llvm-project/commit/699792b94bc7d8983b600482841fb7c3869be5b6
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/IR/invalid-memcpy.cir
A clang/test/CIR/IR/libc-memcpy.cir
A clang/test/CIR/Lowering/libc.cir
Log Message:
-----------
[CIR] Add cir.libc.memcpy Op (#176781)
The operation is a 1:1 mapping to libc's memcpy.
NOTE: This patch upstreams code from
* https://github.com/llvm/clangir.
This Op was originally implemented by Vinicius Couto Espindola
in https://github.com/llvm/clangir/pull/237. Further
modifications were made by other ClangIR contributors.
Co-authored-by: Vinicius Couto Espindola <vini.couto.e at gmail.com>
Commit: 088f88d6fd4047c52266b92eba5ca60782a69ba1
https://github.com/llvm/llvm-project/commit/088f88d6fd4047c52266b92eba5ca60782a69ba1
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M lldb/source/ValueObject/DILEval.cpp
Log Message:
-----------
[lldb] Fix crash when there is no compile unit. (#177278)
The crash occurred in lldb-dap when we are in a shared library with no
debug information and we are trying to get the expression path for an
address.
Commit: 69fbba1948c97ff349cbd4abf5107f2e8373f883
https://github.com/llvm/llvm-project/commit/69fbba1948c97ff349cbd4abf5107f2e8373f883
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M lldb/test/API/lang/cpp/template-alias/TestTemplateAlias.py
Log Message:
-----------
[lldb][test] TestTemplateAlias.py: skip on older Clang versions
The `-g[no-]template-alias` flag is not available on older versions.
Commit: 2be02dcb49d4d7b8bf717d81bb46efb51690c6d7
https://github.com/llvm/llvm-project/commit/2be02dcb49d4d7b8bf717d81bb46efb51690c6d7
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M lldb/test/API/lang/cpp/template-alias/TestTemplateAlias.py
Log Message:
-----------
[lldb][test] TestTemplateAlias.py: skip on older Clang version
The `-g[no-]template-alias` flag is not available on older versions.
Commit: ec28be3ccac432ea6a45eca67249b209be216c0a
https://github.com/llvm/llvm-project/commit/ec28be3ccac432ea6a45eca67249b209be216c0a
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/optional/TestDataFormatterLibcxxOptionalSimulator.py
Log Message:
-----------
[lldb][test] TestDataFormatterLibcxxOptionalSimulator.py: skip on older Clang versions
Commit: de51bced24842d095a50f5c15d67440e55b8371e
https://github.com/llvm/llvm-project/commit/de51bced24842d095a50f5c15d67440e55b8371e
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Dialect/Transforms/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
R clang/lib/CIR/Dialect/Transforms/LoweringPrepareCXXABI.h
R clang/lib/CIR/Dialect/Transforms/LoweringPrepareItaniumCXXABI.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRCXXABI.h
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerItaniumCXXABI.cpp
M clang/test/CIR/CodeGen/dynamic-cast.cpp
Log Message:
-----------
[CIR][NFC] Move ABI lowering of dynamic_cast to CXXABILowering (#176931)
This patch moves the ABI lowering for `dynamic_cast` from
LoweringPrepare to the new CXXABILowering pass. This effectively removes
ABI lowering code away from LoweringPrepare, thus the patch also removes
the LoweringPrepareCXXABI classes and files.
Related to #175968 .
Commit: 9357c5906cd8b3d5f15fec853f458b1478f03e4a
https://github.com/llvm/llvm-project/commit/9357c5906cd8b3d5f15fec853f458b1478f03e4a
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizeZeroSizeArrays.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareGlobals.cpp
M llvm/test/CodeGen/SPIRV/fembed-bitcode-marker.ll
M llvm/test/CodeGen/SPIRV/hip_dyn_lds.ll
Log Message:
-----------
[SPIRV] Unify unsized array handling for AMGCN flavoured SPIR-V (#175848)
Currently we handle 0-sized arrays in multiple places, non-uniformly,
either via `SPIRVLegalizeZeroSizeArrays` or via `SPIRVPrepareGlobals`.
For AMDGCN flavoured SPIR-V we have a singular, simpler solution: set
all 0-sized arrays to be `UINT64_MAX` sized. This is an unambiguous
token that we can use during reverse translation to restore the intended
0 size.
Commit: 95687721874d2e32296cc377e819eee15dfb8ae7
https://github.com/llvm/llvm-project/commit/95687721874d2e32296cc377e819eee15dfb8ae7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.iterative.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
Log Message:
-----------
AMDGPU: Select VGPR MFMAs by default (#159493)
AGPRs are undesirable since they are only usable by a
handful instructions like loads, stores and mfmas and everything
else requires copies to/from VGPRs. Using the AGPR form should be
a measure of last resort if we must use more than 256 VGPRs.
Commit: 925b033fce5481cc57df4b767318b318af4ebc13
https://github.com/llvm/llvm-project/commit/925b033fce5481cc57df4b767318b318af4ebc13
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
Log Message:
-----------
[CoroFrame][NFC] Create more helper functions for insertSpills (#177149)
This allows us to delete some variables and simplify the core loop of of
insertSpills.
Commit: d5899ccb6f338e254995760bf11c6acddade5391
https://github.com/llvm/llvm-project/commit/d5899ccb6f338e254995760bf11c6acddade5391
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/AST/Expr.cpp
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/CodeGen/atomic-ops.c
M clang/test/CodeGen/scoped-atomic-ops.c
M clang/test/Sema/atomic-ops.c
M clang/test/Sema/scoped-atomic-ops.c
M libclc/clc/lib/generic/atomic/clc_atomic_dec.cl
M libclc/clc/lib/generic/atomic/clc_atomic_inc.cl
M openmp/device/include/Synchronization.h
Log Message:
-----------
[Clang] Rename `uinc_wrap` and add normal atomic builtin (#177253)
Summary:
The `__scoped_atomic` builtins are supposed to match the standard
GNU-flavored `__atomic` builtins. We added a scoped builtin without a
corresponding standard one before the fork so this should be added in
the release candidate. These were originally added in
https://github.com/llvm/llvm-project/pull/168666
Also, the name `uinc_wrap` does not follow the naming convention. The
GNU atomics use `fetch_xyz` to indicate that the builtin returns the
previous location's value as part of the RMW operation, which these do.
This PR renames it and its uses.
Commit: a81d2bf933fb3acc993fa5493ac34ce582352191
https://github.com/llvm/llvm-project/commit/a81d2bf933fb3acc993fa5493ac34ce582352191
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/test/Transforms/InstCombine/load-addrspacecast-select.ll
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[InstCombine] Propagate profiles when folding addrscast through loads (#177214)
#176352 introduced a new fold and a new test for this functionality.
Given the select condition is the same before and after, we can
propagate any profile information that may be attached to the select
instruction. We should not need to explicitly drop any metadata off the
select.
Commit: 02d34a76f70db89fc8cab379208cabacfecefab8
https://github.com/llvm/llvm-project/commit/02d34a76f70db89fc8cab379208cabacfecefab8
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
[NFCI][AMDGPU] Remove more redundant code from `GCNSubtarget.h` (#177297)
We are getting pretty close to use `GET_SUBTARGETINFO_MACRO` in the
header with this cleanup.
Commit: 9f536c771d29a11cc1767e36ae0d56452d1e56fa
https://github.com/llvm/llvm-project/commit/9f536c771d29a11cc1767e36ae0d56452d1e56fa
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
Log Message:
-----------
[NFC][AMDGPU] Remove unused `FeatureDisable` (#177288)
Commit: 735f7b3bd4bcbc16f01d34882365d79d3cf21853
https://github.com/llvm/llvm-project/commit/735f7b3bd4bcbc16f01d34882365d79d3cf21853
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/combine-bzhi.ll
Log Message:
-----------
[X86] computeKnownBitsForTargetNode - add basic X86ISD::BZHI handling (#177347)
Currently limited to constant masks, if the mask (truncated to i8) if
less than the bitwidth then it will zero the upper bits.
So far it mainly just handles BZHI(X,0) -> 0 and BZHI(C1,C2) constant
folding.
All the BMI node combines seem to just call SimplifyDemandedBits - so
I've merged them into a single combineBMI.
Commit: af4f5ee93bf5ac4d8f0056b1a9dbdaa6732a7809
https://github.com/llvm/llvm-project/commit/af4f5ee93bf5ac4d8f0056b1a9dbdaa6732a7809
Author: Aryan Kadole <aryankadole95 at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[DAG] SDPatternMatch - add m_Negative/m_StrictlyPositive/m_NonNegative/m_NonPositive/m_NonZero matchers (#175191)
Resolves #174327
Commit: c63a744f3fbc91f0f544d79a50ae91e860d092b7
https://github.com/llvm/llvm-project/commit/c63a744f3fbc91f0f544d79a50ae91e860d092b7
Author: Dan Blackwell <dan_blackwell at apple.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/test/CodeGen/lifetime-sanitizer.c
M clang/test/CodeGenCXX/lifetime-sanitizer.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll
Log Message:
-----------
[CodeGen][InstCombine][Sanitizers] Emit lifetimes when compiling with memtag-stack (#177130)
Currently we do not emit lifetimes by default when compiling with
memtag-stack - which means we don't catch use-after-scope (when
compiling without optimization).
This patch fixes that by mirroring ASan, HWASan and MSan, and always
emitting lifetime markers. The patch is based on the changes made in
aeca569.
rdar://163713381
Commit: 7a37eacbf56c8022ad716f2e1b17497bd6ae3602
https://github.com/llvm/llvm-project/commit/7a37eacbf56c8022ad716f2e1b17497bd6ae3602
Author: Susan Tan (ス-ザン タン) <zujunt at nvidia.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
A flang/test/Fir/FirToSCF/any.fir
A flang/test/Fir/FirToSCF/do-extra.fir
A flang/test/Fir/FirToSCF/if-extra.fir
A flang/test/Fir/FirToSCF/iterate-while-extra.fir
A flang/test/Fir/FirToSCF/nested-unregistered.fir
A flang/test/Fir/FirToSCF/normalize.fir
A flang/test/Fir/FirToSCF/sum.fir
Log Message:
-----------
[flang] [test] add tests for FIRToSCF (#176026)
Increase the coverage of FIRToSCF testing.
Commit: 580176741d990d14f65db81574aaa8954b76b793
https://github.com/llvm/llvm-project/commit/580176741d990d14f65db81574aaa8954b76b793
Author: Matthias Springer <me at m-sp.org>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
[mlir] Add myself as CODEOWNER for `ControlFlowInterfaces` (#177366)
Set up notifications and automatically add myself as reviewer.
Commit: b4b9ed6ad16f7ecdf947b92b8ee250d6d0cf7636
https://github.com/llvm/llvm-project/commit/b4b9ed6ad16f7ecdf947b92b8ee250d6d0cf7636
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/include/clang/Driver/CommonArgs.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
A flang/test/Driver/global-isel.f90
A flang/test/Driver/lto-global-isel.f90
Log Message:
-----------
[Flang][Driver] Enable the global-isel option (#177188)
Commit: 986be54564add8e8fd0dade557d663a87661deb9
https://github.com/llvm/llvm-project/commit/986be54564add8e8fd0dade557d663a87661deb9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Log Message:
-----------
[RISCV] Use DecoderMethod and a template function to reduce the amount of boilerplate for decodings a register class. NFC (#177296)
The decode functions for GPR/FPR and their compressed register classes
are very similar. We just need the number of registers, the constant for
the first register in the class, and whether or not the register class
is shrunk by RVE.
I've added a template function that takes this information and used the
DecoderMethod in tablegen to provide the values for the the template
parameters.
I kept an alias for DecodeGPRRegisterClass because it has multiple
callers.
---------
Co-authored-by: Sam Elliott <sam at lenary.co.uk>
Commit: d23b3a58dd159612dd7ebb0692771545c277f248
https://github.com/llvm/llvm-project/commit/d23b3a58dd159612dd7ebb0692771545c277f248
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Log Message:
-----------
[RISCV] Add sub_128 SubRegIndex. Use if for FPR256. (#176986)
Instead of branching FPR256 from FPR32, branch it from FPR128. The
hardware that supports FPR256 doesn't have D or Q, but I assume if it
did, the FPR64/FPR128 registers would be subregs of FPR256.
Commit: ada79f4c2691ab6546d379a144377162fd4f5191
https://github.com/llvm/llvm-project/commit/ada79f4c2691ab6546d379a144377162fd4f5191
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/Serialization/ModuleManager.cpp
Log Message:
-----------
[clang][modules] Read PCM validation timestamp earlier (#177062)
When building a module, the PCM file is always written first and then
the validation timestamp gets created. Clang needs to first read the
validation timestamp and only then read the PCM file. Otherwise, it
could read an out-of-date PCM file and then read the validation
timestamp for its new up-to-date version. This would erroneously skip
validation with `-fmodules-validate-once-per-build-session`. I'm not
concerned about multiple Clang instances seeing different filesystem
contents from each other within a single build session, since that would
break the assumption `-fmodules-validate-once-per-build-session` relies
on.
Commit: fe5f6f5be884619318df02523f970dc7d9a7dc9d
https://github.com/llvm/llvm-project/commit/fe5f6f5be884619318df02523f970dc7d9a7dc9d
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M flang/lib/Semantics/check-declarations.cpp
M flang/test/Semantics/cuf03.cuf
Log Message:
-----------
[flang][cuda] Allow pointer object with the managed attribute (#177304)
Commit: 7f7d78d05c3558b6dd201cb735ec0f16e3636ba8
https://github.com/llvm/llvm-project/commit/7f7d78d05c3558b6dd201cb735ec0f16e3636ba8
Author: Hussam A. <60274772+hussam-alhassan at users.noreply.github.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
A llvm/test/CodeGen/AArch64/aarch64-condopt-cross-block-different-regs.mir
M llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
Log Message:
-----------
[AArch64] Add register check to ConditionOptimizer cross-block logic (#176528)
This patch adds a missing guard to the AArch64 ConditionOptimizer pass
Previously, the cross-block optimization would not check for register
equivalence before modifying the two comparison instructions.
This means that two cmp instructions with suitable cond codes and
immediates would be modified, even if their registers were different,
which would not trigger CSE afterwards. This doesn't affect correctness
but is unhelpful.
A negative ll test and mir tests has also been added to confirm this
fix.
Commit: d6e1f70e671032bcbce69f38d57deeed6db801b5
https://github.com/llvm/llvm-project/commit/d6e1f70e671032bcbce69f38d57deeed6db801b5
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M flang/docs/Extensions.md
M flang/include/flang/Evaluate/initial-image.h
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Evaluate/fold.cpp
M flang/lib/Evaluate/initial-image.cpp
M flang/lib/Semantics/data-to-inits.cpp
M flang/lib/Semantics/data-to-inits.h
M flang/lib/Semantics/semantics.cpp
A flang/test/Semantics/bug2098.f90
M flang/test/Semantics/data07.f90
M flang/test/Semantics/data12.f90
M flang/test/Semantics/data23.f90
M flang/test/Semantics/equivalence02.f90
Log Message:
-----------
[flang] Allow multiple identical DATA initializations (#177063)
ISO Fortran disallows DATA statements from affecting the same bit of
memory more than once; however, all (but one) other compilers allow this
usage. They differ, however, in the case of multiple distinct
initializations -- some compilers take the "last" value in source order,
some don't.
This patch accepts multiple identical DATA initializations, which is
portable usage that appears in code, and emits an optional warning. It
continues to detect and report multiple distinct DATA initializations,
since they are not portable.
Commit: c66546bfc8a28322664384f95794f910fc008630
https://github.com/llvm/llvm-project/commit/c66546bfc8a28322664384f95794f910fc008630
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M flang/lib/Semantics/check-declarations.cpp
M flang/test/Semantics/declarations06.f90
Log Message:
-----------
[flang] Improve error message for polymorphic implicit interface (#177225)
PROCEDURE(CLASS(...)) specifies a procedure with an implicit interface
whose result is polymorphic. That turns out to never be a valid
declaration, since a CLASS(...) function result is required to also be
POINTER or ALLOCATABLE, both of which require the presence of an
explicit interface. We caught this error already, but the message should
be improved for procedures.
Fixes https://github.com/llvm/llvm-project/issues/176861.
Commit: 1493ae5da2b8d445fa195142babb000ba99937d8
https://github.com/llvm/llvm-project/commit/1493ae5da2b8d445fa195142babb000ba99937d8
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M flang/lib/Parser/message.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Semantics/check-coarray.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Parser/keyword-optional-spaces.f90
Log Message:
-----------
[flang] Allow missing space in some free-form keywords (#177254)
When asked to emit warnings about missing spaces in free form source
code, flang-new is emitting some warnings in cases when the space is an
optional one between keywords. Use the existing token matching
capability that allows these ("END " with a trailing blank), add a test
for all cases in Table 6.2, and fix a couple other bogus warning exposed
by compiling that test with -pedantic.
Fixes https://github.com/llvm/llvm-project/issues/177098.
Commit: 711e8e56943c0188b037f3a9a42905d071949c90
https://github.com/llvm/llvm-project/commit/711e8e56943c0188b037f3a9a42905d071949c90
Author: Cheng Lingfei <53817093+clingfei at users.noreply.github.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/aarch64-mops.ll
Log Message:
-----------
[AArch64] Optimize memcpy for non-power of two sizes (#168890)
The previous getMemcpyLoadsAndStores implementation would chain
load/store instructions from "NumLdStInMemcpy - GlueIter -
GluedLdStLimit" to "NumLdStInMemcpy - GlueIter". This approach caused
issues when copying non-power-of-two sizes, as it would chain leading
load/stores with subsequent instructions at non-power-of-two aligned
offsets.
This chaining pattern prevented optimal optimizations in
aarch64-ldst-opt pass for these load/store instructions.
This commit modifies the chaining range to be from GlueIter to GlueIter
+ GluedLdStLimit, enabling proper optimization of load/store
instructions in aarch64-ldst-opt.
Closes https://github.com/llvm/llvm-project/issues/165947
Commit: 3954cd2db69dcaa87676752dfc6fec9408cd9540
https://github.com/llvm/llvm-project/commit/3954cd2db69dcaa87676752dfc6fec9408cd9540
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVCallLowering.h
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_no_return.ll
Log Message:
-----------
[SPIRV] Process indirect function calls immediately (#177222)
The SPIR-V backend processes indirect function calls in
`SPIRVCallLowering`, which is a subclass of the generic `CallLowering`.
It intends to process them function by function, by first collecting all
indirect calls in a function, and then processing all of a function's
indirect calls at once when the call lowering for the function is about
to end.
Today, it relies on the `lowerReturn` virtual function to be called by
the generic call lowering infra to know the function processing is about
to end, and at that time it processes all of the collected indirect
calls and clears the vector of indirect calls.
The problem is that not all functions have return instructions. Every
basic block must have a terminator instruction, but it does
[not](https://llvm.org/docs/LangRef.html#terminator-instructions) have
to be a return.
In the failing case here, function `a` has an infinite loop, with every
iteration having an indirect call and a check to see if it should break
out of the infinite loop. There is a return instruction initially, but
it is optimized out in the middle end. There is also an unrelated
function `b` with no indirect calls.
During call lowering, information about the indirect call in `a` is
captured in the vector in SPIRVCallLowering, but since there is no
return instruction, it is never processed.
Then, function `b` is processed. `b` happens to have a return
instruction, so the indirect call from `a` is processed, but the
processing assumes that the indirect call is inside the function being
processed, and it writes to a `{function, register}->SPIRVType` map, but
the function is `b` not `a`.
This ends up causing the map to have an invalid SPIRVType for the
register in function `b`, and `b` happens to have a register of the same
type, causing an invalid result from the map lookup and thus invalid IR
(`G_ADDRSPACE_CAST` from `ptr addrspace(4)` to `i32`).
We can't move the indirect call processing into a seperate pass because
we lose required information after call lowering ends.
Here, we change the indirect call processing to be done immediately when
it is seen.
Comments say the reason the collect all then process style was done was
to get better type information for the caller of the indirect function
if an opaque pointer is an arg to the caller and the indirect function,
but [an existing test
case](https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll)
seems to exercise this, and the test still passes after this change and
actually has the exact same assembly.
The test case added is a minimal example from `llvm-reduce`, so it's
just an infinite loop with no exit condition.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 6de6f7b46bda0fef45b997d05fe57e046f60e4df
https://github.com/llvm/llvm-project/commit/6de6f7b46bda0fef45b997d05fe57e046f60e4df
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/OffloadArch.h
M clang/lib/Basic/OffloadArch.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
M libclc/CMakeLists.txt
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/TargetParser/TargetParser.h
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[AMDGPU] Define gfx1310 target with ELF number 0x50 (#177355)
For now this is identical to gfx1250.
---------
Co-authored-by: Jay Foad <jay.foad at amd.com>
Commit: 65134634f994d3aa44e45338e3fbd65ab9b7f3f4
https://github.com/llvm/llvm-project/commit/65134634f994d3aa44e45338e3fbd65ab9b7f3f4
Author: Endre Fülöp <endre.fulop at sigmatechnology.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/UnsafeFunctionsCheck.cpp
M clang/docs/analyzer/checkers.rst
A clang/include/clang/Analysis/AnnexKDetection.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
A clang/lib/Analysis/AnnexKDetection.cpp
M clang/lib/Analysis/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp
M clang/test/Analysis/Inputs/system-header-simulator.h
M clang/test/Analysis/analyzer-config.c
A clang/test/Analysis/security-deprecated-buffer-handling-report-modes.c
Log Message:
-----------
Reland "[clang][analyzer] Add ReportInC99AndEarlier option to Depreca… (#177379)
…tedOrUnsafeBuf…" (#176603)
The bolt-aarch64-ubuntu-clang failure seems unrelated.
This reverts commit 17ff9b3c67ab62f77b2dd5cba98fa0011f14d9a2.
Commit: 4a3f33d800c760a9fae244dfebacff0e8df4361c
https://github.com/llvm/llvm-project/commit/4a3f33d800c760a9fae244dfebacff0e8df4361c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Log Message:
-----------
GlobalISel: Fix mishandling vector-as-scalar in return values (#175780)
This fixes 2 cases when the AMDGPU ABI is fixed to pass <2 x i16>
values as packed on gfx6/gfx7. The ABI does not pack values
currently; this is a pre-fix for that change.
Insert a bitcast if there is a single part with a different size.
Previously this would miscompile by going through the scalarization
and extend path, dropping the high element.
Also fix assertions in odd cases, like <3 x i16> -> i32. This needs
to unmerge with excess elements from the widened source vector.
All of this code is in need of a cleanup; this should look more
like the DAG version using getVectorTypeBreakdown.
Commit: a97f5ec95f56987de7d4730a85d4507c4071af07
https://github.com/llvm/llvm-project/commit/a97f5ec95f56987de7d4730a85d4507c4071af07
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
M llvm/test/CodeGen/AMDGPU/abs_i16.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/saddsat.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/sibling-call.ll
M llvm/test/CodeGen/AMDGPU/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
M llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/usubsat.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
Log Message:
-----------
AMDGPU: Change ABI of 16-bit element vectors on gfx6/7 (#175781)
Fix ABI on old subtargets so match new subtargets, packing
16-bit element subvectors into 32-bit registers. Previously
this would be scalarized and promoted to i32/float.
Note this only changes the vector cases. Scalar i16/half are
still promoted to i32/float for now. I've unsuccessfully tried
to make that switch in the past, so leave that for later.
This will help with removal of softPromoteHalfType.
Commit: 4016592bf7560f17c9fbab127d50d6ed7713603d
https://github.com/llvm/llvm-project/commit/4016592bf7560f17c9fbab127d50d6ed7713603d
Author: DaKnig <37626476+DaKnig at users.noreply.github.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/neon-abd.ll
Log Message:
-----------
[SDAG] (abd? (?ext x), c) -> (zext (abd? x, c)) (#176366)
just the existing pattern, with constants
Commit: 71a2e8fa1811ecd949a3d3fc649077e3c1c73487
https://github.com/llvm/llvm-project/commit/71a2e8fa1811ecd949a3d3fc649077e3c1c73487
Author: eleviant <56861949+eleviant at users.noreply.github.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/tail-call-stack-args.ll
Log Message:
-----------
[AArch64] Don't skip storing stack arguments in case of size mismatch (#177360)
Wnen argument on stack needs to be zero extended, we can't omit ld/st
pair, because we may get an undefined value in certain conditions. (e.g
the code below will print 0xFFFFFFFF00000042 instead of 0x42)
```
[[gnu::noinline]]
void baz(int, int, int, int, int, int, int, int, long v)
{
printf("Value of v: %#lx\n", v);
}
[[gnu::noinline]]
void bar(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, unsigned v)
{
baz(i1, i2, i3, i4, i5, i6, i7, i8, v);
}
[[gnu::noinline]]
void foo(int=1, int=2, int=3, int=4, int=5, int=6, int=7, int=8, uint64_t dummy=-1ULL)
{
bar(1, 2, 3, 4, 5, 6, 7, 8, 0x42)
}
```
Commit: 5692ae96a8c7637181e461ae27b93a2bd9d72475
https://github.com/llvm/llvm-project/commit/5692ae96a8c7637181e461ae27b93a2bd9d72475
Author: Nico Weber <thakis at chromium.org>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/combine-pclmul.ll
Log Message:
-----------
Revert "[X86] combinePCLMULQDQ - attempt to fold PCLMULQDQ(SHUFFLE(X),SHUFFLE(Y),C) -> PCLMULQDQ(X,Y,C') (#176932)"
This reverts commit c13a730c89da0a28b011a157bdfacd8625201625.
Makes clang assert, standalone repro here:
https://github.com/llvm/llvm-project/pull/176932#issuecomment-3785362760
Commit: 1036d782ae83b37578d6a810544a30f7453b79e9
https://github.com/llvm/llvm-project/commit/1036d782ae83b37578d6a810544a30f7453b79e9
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/assigned-goto.f90
Log Message:
-----------
[flang][lowering] lowering assigned goto of allocatable variable (#175874)
towards [#173594](https://github.com/llvm/llvm-project/issues/173594)
This PR adds a lowering for `AssignedGoto`s that reference an
allocatable variable.
Commit: 39642a4b22a2494a25ee31b06ad5f8e55d11d6d0
https://github.com/llvm/llvm-project/commit/39642a4b22a2494a25ee31b06ad5f8e55d11d6d0
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_MUL (#177314)
Add missing S16, S64, and V2S16 support for G_MUL.
Commit: 8b59338e9b7bbea9357ae40427f796a6e44d44fc
https://github.com/llvm/llvm-project/commit/8b59338e9b7bbea9357ae40427f796a6e44d44fc
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Add ubfe and sbfe intrinsic RegBankLegalize rules (#177276)
Commit: 26eb7382502ef46f3553f9016f6d4677427e1d38
https://github.com/llvm/llvm-project/commit/26eb7382502ef46f3553f9016f6d4677427e1d38
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
Log Message:
-----------
Revert "[AMDGPU][GlobalISel] Add RegBankLegalize support for G_MUL" (#177405)
Reverts llvm/llvm-project#177314
mul.ll test is failing expensive checks.
Commit: f18b4ec54935c1ed0cbb8b4403086be830d9bb48
https://github.com/llvm/llvm-project/commit/f18b4ec54935c1ed0cbb8b4403086be830d9bb48
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Avoid emitting a switch that only contains a default. (#177391)
Addresses post commit feedback from #174471
Commit: 4b1cfc5d7c606ece125d1e0ef6d13e0289553200
https://github.com/llvm/llvm-project/commit/4b1cfc5d7c606ece125d1e0ef6d13e0289553200
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Log Message:
-----------
[NFCI][AMDGPU] Final touch before moving to `GET_SUBTARGETINFO_MACRO` (#177401)
Commit: d7078b67378a344f9effdfa3c0011981a7022eb9
https://github.com/llvm/llvm-project/commit/d7078b67378a344f9effdfa3c0011981a7022eb9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
OMPIRBuilder.cpp - fix gcc Wparentheses warning. NFC. (#177403)
Commit: 2b30325fb34452f04cecc3c466a11b21bc009e3d
https://github.com/llvm/llvm-project/commit/2b30325fb34452f04cecc3c466a11b21bc009e3d
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/.clang-format
Log Message:
-----------
[LLVM] Disable clang-format for TableGen files (#177002)
Clang-format is not very maintained for TableGen, and seems to make odd
choices that differ significantly from how humans write and read the
backend's tablegen.
For the moment, disable clang-format for TableGen files. This should
also apply when using `git clang-format`, which should help with newer
contributors who sometimes end up formatting td files by accident.
Commit: 5c35af8f1e6ebc7c32721723e8afc5015e67f867
https://github.com/llvm/llvm-project/commit/5c35af8f1e6ebc7c32721723e8afc5015e67f867
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
Log Message:
-----------
[RISCV] Replace RISCVISD::CLMUL* with ISD::CLMUL*. (#177386)
This patch does the minimum to remove RISCVISD::CLMUL*. It does not
remove existing intrinsics.
There's some missed optimizations for i32 CLMULH/CLMULR on RV64, but
those may be generic issues.
I've put the test cases in the existing files so it's more obvious what
the missed optimizations are by comparing within the file.
Commit: 3e341320b36cc25379089c8108afd452da3e112c
https://github.com/llvm/llvm-project/commit/3e341320b36cc25379089c8108afd452da3e112c
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Improve building on/for Windows (#171761)
Few things going on here:
- I think we should be able to use the blake3 x86-64 asm on windows with
some slight adjustments (sorry it's still named *_unix.S, renaming
seemed like a bit bigger project)
- `genrule` is really evil because it bakes the path to the host bash
into the command, which fails spectacularly when running on a
non-windows remote executor. Swap to `write_file`/`run_binary` rules to
mitigate it
- The existing windows linkopts do not work correctly for clang in mingw
mode
With this set of changes (as well as another one that rewrites
`bundle_resources.py` into C) I am able to hermetically cross-build
clang/lld/etc from a windows host to a (mingw) windows target on a linux
executor, and use the resulting compilers to compile C binaries/tests
(see
https://github.com/dzbarsky/toolchains_llvm_bootstrapped/actions/runs/20121686105/job/57743214313?pr=1
and https://github.com/dzbarsky/toolchains_llvm_bootstrapped/pull/1)
Commit: 829ebfd5062302d6b1472ca2a4ba6367fff82501
https://github.com/llvm/llvm-project/commit/829ebfd5062302d6b1472ca2a4ba6367fff82501
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] dsymutil should link against CF framework on darwin (#177394)
Matches cmake
https://github.com/llvm/llvm-project/blob/6de6f7b46bda0fef45b997d05fe57e046f60e4df/llvm/tools/dsymutil/CMakeLists.txt#L48
Commit: e1bd0ee125d07b1a745f51e04fb0ed38fe0ff4ac
https://github.com/llvm/llvm-project/commit/e1bd0ee125d07b1a745f51e04fb0ed38fe0ff4ac
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64][NFC] Extract a `LowerNTStore()` method (#176872)
Extracts nontermporal store lowering from `LowerSTORE` into its own
private method `LowerNTStore`. The refactoring improves overall code
structure (and prepares for later scaling of custom STNP lowering
logic).
Commit: c31e506dab719461efbd3dd18dd3cd6841d8d2f8
https://github.com/llvm/llvm-project/commit/c31e506dab719461efbd3dd18dd3cd6841d8d2f8
Author: Egor Zhdan <e_zhdan at apple.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/Sema/SemaAPINotes.cpp
M clang/test/APINotes/Inputs/Headers/Methods.apinotes
M clang/test/APINotes/Inputs/Headers/Methods.h
M clang/test/APINotes/methods.cpp
Log Message:
-----------
[APINotes] Support overloaded operators
This adds support for annotating C++ operators via API Notes. For instance:
```
Tags:
- Name: MyTag
Methods:
- Name: operator+
Availability: none
```
At the moment only operators that are declared as methods of C++ records can be annotated.
rdar://148534260
Commit: 4c5ffe74e849e841ae5bc7ea357d506fae41384d
https://github.com/llvm/llvm-project/commit/4c5ffe74e849e841ae5bc7ea357d506fae41384d
Author: Sam Clegg <sbc at chromium.org>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/ScriptParser.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Writer.cpp
M lld/MachO/InputFiles.cpp
M lld/MachO/ObjC.cpp
M lld/MachO/SymbolTable.cpp
M lld/include/lld/Common/BPSectionOrdererBase.inc
Log Message:
-----------
[lld][ELF/MachO] Use `.contains` rather than `.count` for set membership. NFC (#177404)
This matches the usage in the other linker backends.
See #176610, #177067
Commit: a1062d98bbce2af9f6ef8f85837f40b523ee1f3f
https://github.com/llvm/llvm-project/commit/a1062d98bbce2af9f6ef8f85837f40b523ee1f3f
Author: Alan Zhao <ayzhao at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Utils/ProfileVerify.cpp
M llvm/test/Transforms/PGOProfile/prof-verify-no-entrycount.ll
M llvm/test/Transforms/PGOProfile/prof-verify.ll
M llvm/test/Transforms/PGOProfile/profcheck-llvm.global_ctors.ll
M llvm/test/Transforms/PGOProfile/profcheck-select.ll
Log Message:
-----------
[profcheck] Print the function name in the error (#177264)
This is helpful for tests with a lot of test cases and grepping for
instructions with missing profile data isn't feasible because it doesn't
account for things like vectors which are exempt.
Tracking issue: #147390
Commit: 84db4da288b1b2b69ee7e42e9fbab8edb55fa299
https://github.com/llvm/llvm-project/commit/84db4da288b1b2b69ee7e42e9fbab8edb55fa299
Author: Michael Jones <michaelrj at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M libc/src/__support/wchar/character_converter.h
Log Message:
-----------
[libc] Fix character converter in C++20 (#177421)
Internally character converter uses char8_t to represent a character.
Before C++20 we provide a typedef for it, but since C++20 it's a
keyword. The keyword version isn't listed in our is_integral, causing
countl to reject it as an invalid type. This patch just casts from
char8_t to int8_t to sidestep the issue, but in future we may want to
add char8_t, char16_t, and char32_t to our is_integral.
Commit: 73549e60460abd1b850477d1b4409b833ef04a08
https://github.com/llvm/llvm-project/commit/73549e60460abd1b850477d1b4409b833ef04a08
Author: Nico Weber <thakis at chromium.org>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/utils/reduce-clang-crash.py
Log Message:
-----------
reduce-clang-crash.py: Use creduce if cvise is not found (#177413)
See discussion on #128592.
Commit: 0381093140428b727a1a7af708ec034a8b07d521
https://github.com/llvm/llvm-project/commit/0381093140428b727a1a7af708ec034a8b07d521
Author: Thurston Dang <thurston at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
Log Message:
-----------
[msan] Handle NEON vsli/vsri (vector shift left/right and insert) (#177283)
This does a shift and combine on the two vectors, hence we can precisely
propagate the shadow by applying the intrinsic to the input shadows.
Commit: 2e08bf7c53e142b69b6ad449025565122ff89780
https://github.com/llvm/llvm-project/commit/2e08bf7c53e142b69b6ad449025565122ff89780
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Log Message:
-----------
[TableGen] Prefer base class on tied RC sizes (#177257)
When searching for a matching subclass tablegen behavior is non
deterministic if we have several classes with the same size.
Break the tie by choosing a class with smaller BaseClassOrder.
Commit: 68c67dbd2cdc8db5b8847d8ca56487fe50132ff5
https://github.com/llvm/llvm-project/commit/68c67dbd2cdc8db5b8847d8ca56487fe50132ff5
Author: joaosaffran <joaosaffranllvm at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/test/CodeGenHLSL/builtins/radians-overloads.hlsl
Log Message:
-----------
[HLSL] Make radians overload tests stricter. NFC (#177252)
This patch is updating
`clang/test/CodeGenHLSL/builtins/radians-overloads.hlsl` to use -O1
instead of -disable-llvm-passes, and updating the check to match the
change accordenlly.
This work is part of #138016.
Commit: aca0df927fc3c75842009d983e56483e8993a90c
https://github.com/llvm/llvm-project/commit/aca0df927fc3c75842009d983e56483e8993a90c
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
A clang/test/CIR/CodeGen/builtin-bit-cast.cpp
Log Message:
-----------
[Clang][CIR] Implement CIRGen logic for __builtin_bit_cast (#176782)
NOTE: This PR upstreams code from
* https://github.com/llvm/clangir.
This logic was originally implemented by Sirui Mu in
https://github.com/llvm/clangir/pull/762. Further
modification were made by other ClangIR contributors.
Co-authored-by: Sirui Mu <msrlancern at gmail.com>
Commit: 9fc5fd0ad689eed94f65b1d6d10f9c5642935e68
https://github.com/llvm/llvm-project/commit/9fc5fd0ad689eed94f65b1d6d10f9c5642935e68
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
A llvm/test/CodeGen/NVPTX/default-sm.ll
M llvm/test/CodeGen/NVPTX/i128.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
Log Message:
-----------
[NVPTX] Update the default SM to 7.5 (#176021)
Update NVPTX's default SM to sm_75. This matches the behavior of offline
compilation tools in the CUDA Toolkit (nvcc, ptxas, ...)
Commit: 0e9ded5d91180a5369cc3afac70d940cfa803644
https://github.com/llvm/llvm-project/commit/0e9ded5d91180a5369cc3afac70d940cfa803644
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M flang/lib/Semantics/check-call.cpp
M flang/test/Semantics/cuf23.cuf
Log Message:
-----------
[flang][cuda] Allow device descriptor in show_descriptor (#177424)
Descriptor are always in managed memory so it is safe to call
show_descriptor for them.
Commit: 41c1905b61dc6fd43496a14e8bb48575f84b805a
https://github.com/llvm/llvm-project/commit/41c1905b61dc6fd43496a14e8bb48575f84b805a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
A llvm/test/CodeGen/X86/clmul-vector-256.ll
A llvm/test/CodeGen/X86/clmul-vector-512.ll
Log Message:
-----------
[X86] Add 256-bit and 512-bit vector CLMUL test coverage (#176718)
Commit: 4b939beb79e3390046b760bef71b7d891ba9b4df
https://github.com/llvm/llvm-project/commit/4b939beb79e3390046b760bef71b7d891ba9b4df
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/CodeGen/CGObjC.cpp
M clang/test/CodeGenObjC/arc-arm.m
M clang/test/CodeGenObjC/arc-foreach.m
M clang/test/CodeGenObjC/arc-property.m
M clang/test/CodeGenObjC/arc-related-result-type.m
M clang/test/CodeGenObjC/arc-unopt.m
M clang/test/CodeGenObjC/arc-unsafeclaim.m
M clang/test/CodeGenObjC/arc-with-atthrow.m
M clang/test/CodeGenObjC/ns_consume_null_check.m
M clang/test/CodeGenObjC/objc-arc-container-subscripting.m
M clang/test/CodeGenObjC/os_log.m
M clang/test/CodeGenObjCXX/auto-release-result-assert.mm
M clang/test/CodeGenObjCXX/inheriting-constructor-cleanup.mm
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/test/CodeGen/AArch64/call-rv-marker.ll
Log Message:
-----------
Reapply "[CGObjC] Allow clang.arc.attachedcall on -O0 (#164875)" (#177285)
This reverts commit 8eac375a4bff84f0a10a9c8ee23c4da409a805f9.
A unit test needed to be updated, that was all.
I do not have merge permissions.
Commit: 056e5a32c80d0f494797788ecdaede314eb0f947
https://github.com/llvm/llvm-project/commit/056e5a32c80d0f494797788ecdaede314eb0f947
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/integer-canonicalizing-src-modifiers.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
M llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
Log Message:
-----------
AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)
Keep bf16/f16 values encoded as the low half of a 32-bit register,
instead of promoting to float. This avoids unwanted FP effects
from the fpext/fptrunc which should not be implied by just
passing an argument. This also fixes ABI divergence between
SelectionDAG and GlobalISel.
I've wanted to make this change for ages, and failed the last
few times. The main complication was the hack to return
shader integer types in SGPRs, which now needs to inspect
the underlying IR type.
Commit: ce88e6e363efb91415cc47c8cb353073d1cacc9a
https://github.com/llvm/llvm-project/commit/ce88e6e363efb91415cc47c8cb353073d1cacc9a
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/Maintainers.rst
Log Message:
-----------
Move John McCall to the inactive maintainers list (#177406)
While reaching out to folks for a maintainers list refresh, John asked
to step down due to other commitments. Thank you for all your help!
Commit: b6fd5bb5f3e7c12cce5091e66d05cfcaf0bd8ffb
https://github.com/llvm/llvm-project/commit/b6fd5bb5f3e7c12cce5091e66d05cfcaf0bd8ffb
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[ProfCheck] Add LoopInterchange test to xfail list
LoopInterchange is not currently on in the default pipeline and we have
not done any work around profile propagation within the pass yet, so
disable the test for now to get the profcheck bot back to green.
Commit: d10b2b566ae39e5fd20184d8fff45f3b87933461
https://github.com/llvm/llvm-project/commit/d10b2b566ae39e5fd20184d8fff45f3b87933461
Author: Jameson Nash <vtjnash at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/include/llvm/IR/GlobalVariable.h
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/IR/Globals.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/Linker/LinkModules.cpp
M llvm/lib/Object/IRSymtab.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/TargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/Instrumentation/IndirectCallPromotion.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Scalar/JumpTableToSwitch.cpp
M llvm/lib/Transforms/Utils/RelLookupTableConverter.cpp
Log Message:
-----------
[NFCI] replace getValueType with new getGlobalSize query (#177186)
Returns uint64_t to simplify callers. The goal is eventually replace
getValueType with this query, which should return the known minimum
reference-able size, as provided (instead of a Type) during create.
Additionally the common isSized query would be replaced with an
isExactKnownSize query to test if that size is an exact definition.
Commit: 35563fa37c5abd3fc91fd0ac026f3345a02d37a0
https://github.com/llvm/llvm-project/commit/35563fa37c5abd3fc91fd0ac026f3345a02d37a0
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
Log Message:
-----------
[LifetimeSafety] Add dtor for failing CFG-based tests (#177362)
Commit: d5545db0b08e939c3fad42a1635f8cd5224318d2
https://github.com/llvm/llvm-project/commit/d5545db0b08e939c3fad42a1635f8cd5224318d2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
Log Message:
-----------
AMDGPU: Mark strict_fp16_to_fp as expand (#177417)
This prevents a regression in a future change.
Commit: e936715b8c5e624b5d6cc1e2e50a32c394d03209
https://github.com/llvm/llvm-project/commit/e936715b8c5e624b5d6cc1e2e50a32c394d03209
Author: Akshay Deodhar <adeodhar at nvidia.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.py
Log Message:
-----------
[NVPTX] Weak cmpxchg unittests for NVPTX (#176078)
Commit: e0a132691fe9499857d95dc1d26994f82f7f4a44
https://github.com/llvm/llvm-project/commit/e0a132691fe9499857d95dc1d26994f82f7f4a44
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
Log Message:
-----------
[SystemZ] Precommit for moving some functions around. (#177441)
In preparation for #171066 (FP16 vector support).
Commit: 14a209f8525a07339567863216cef4746485e97d
https://github.com/llvm/llvm-project/commit/14a209f8525a07339567863216cef4746485e97d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
Log Message:
-----------
[VPlan] Replace ComputeFindIVRes with ComputeRdxRes + cmp + sel (NFC) (#176672)
Replace ComputeFindIVResult with ComputeReductionResult + explicit
compare + select, to more explicitly and simpler model computing finding
the first/last induction, which boils down to a min/max reduction +
compare and select of the sentinel value.
PR: https://github.com/llvm/llvm-project/pull/176672
Commit: 869256dbd6772badac6f442dd9679f46d1f7767c
https://github.com/llvm/llvm-project/commit/869256dbd6772badac6f442dd9679f46d1f7767c
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn
Log Message:
-----------
[gn build] Port 65134634f994
Commit: 6934ed51b3345caf9a4005420d1d4078fa3716b9
https://github.com/llvm/llvm-project/commit/6934ed51b3345caf9a4005420d1d4078fa3716b9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/IR/FixedMetadataKinds.def
M llvm/include/llvm/IR/Metadata.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/IR/Attributes.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/test/Transforms/ArgumentPromotion/metadata.ll
M llvm/test/Transforms/Attributor/nofpclass.ll
M llvm/test/Transforms/GVN/PRE/load-metadata.ll
A llvm/test/Transforms/GVN/merge-nofpclass.ll
M llvm/test/Transforms/GVNHoist/hoist-md.ll
M llvm/test/Transforms/InstCombine/fold-phi-load-metadata.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
M llvm/test/Transforms/SROA/preserve-metadata.ll
M llvm/test/Transforms/SimplifyCFG/hoist-with-metadata.ll
A llvm/test/Verifier/nofpclass-metadata.ll
M llvm/test/tools/llvm-reduce/reduce-operands-to-args-metadata-to-attributes.ll
Log Message:
-----------
IR: Add !nofpclass metadata (#177140)
This adds the analogous metadata to the nofpclass attribute
to assert values are not a certain set of floating-point classes.
This allows the same information to be expressed if a function
argument is passed indirectly. This matches the bitmask encoding
of nofpclass.
I also think this should be allowed for stores to symmetrically handle
sret, but leave that for later.
Alternatively we could add a more expressive !fprange metadata,
but that would be much more complex. It's useful to match the attribute,
and more annotations can always be added.
Fixes #133560
Commit: e89a99e26db168f99e928f6a82cab0df13a77c96
https://github.com/llvm/llvm-project/commit/e89a99e26db168f99e928f6a82cab0df13a77c96
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/test/CodeGen/X86/combine-pclmul.ll
Log Message:
-----------
[X86] Add crash regression test reported on #176932 (#177414)
is128BitLaneRepeatedShuffleMask can't handle target shuffle masks containing SM_SentinelZero
Commit: 6d8b25431cc7fe3abb5243701ad7e8d4d19268c9
https://github.com/llvm/llvm-project/commit/6d8b25431cc7fe3abb5243701ad7e8d4d19268c9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
A llvm/test/CodeGen/X86/pclmulqdq.ll
Log Message:
-----------
[X86] Add test coverage for #176879 (#177393)
Commit: 967aeecdaa7db58db4cc896823b0327636c7219c
https://github.com/llvm/llvm-project/commit/967aeecdaa7db58db4cc896823b0327636c7219c
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
R llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
A llvm/test/CodeGen/AMDGPU/waves-per-eu-hints-lower-occupancy-target.ll
Log Message:
-----------
[AMDGPU] Allow amdgpu-waves-per-eu to lower target occupancy range (#168358)
`amdgpu-waves-per-eu` currently does not allow users to lower the target
occupancy range that the backend will try to achieve. For example, for a
kernel targeting gfx942 with default flat workgroup sizes and no LDS
usage, `AMDGPUSubtarget::getWavesPerEU` will by default produce the
range [4,10]. Setting `"amdgpu-waves-per-eu=M,N"` (N being optional)
will only have an effect if 4 <= M <= N <= 10, in which case the [M,N]
range will be produced instead. Advanced developers may in some cases
know that a specifc kernel would not benefit from higher occupancies and
wish to communicate that to the backend. It in turns could make better
codegen decisions if it knows that increasing occupancy is not a
priority.
This modifies the computation of the waves/EU range to enable this
behavior. User-provided minimum/maximum number of waves/EU are now able
to change the default waves/EU range almost arbitrarily, with only
subtarget's specifications and the maximum occupancy induced by
workgroup size and LDS usage limiting the target occupancy range. In the
previous example, the target range will be [M,N] as long as 1 <= M <= N
<= 10.
To allow users to specify only a maximum desired number of waves per EU,
the attribute now accepts a minimum value of 0 and understands it as a
wish to not restrict the minimum number of waves per EU (a minimum value
of 1 indicates instead that the user is ok with an occupancy of 1, so it
cannot be used as the default).
Commit: 265d093d8fa96ef2c7d5c3c49ab68a59f144d790
https://github.com/llvm/llvm-project/commit/265d093d8fa96ef2c7d5c3c49ab68a59f144d790
Author: Kjetil Kjeka <kjetilkjeka at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp
A llvm/test/CodeGen/NVPTX/extern-shared-valid-name.ll
Log Message:
-----------
[NVPTX] fix illegal name for .extern .shared global variables (#173018)
In ptx we can create a GV in AS(3) that will be compiled to a `.extern
.shared` in ptx. Since the `.extern .shared` is not an "extern" in the
traditional sense of the word it will not be linked based on name but
rather refer to the shared memory allocated at kernel launch.
Since we don't care about the name it's tempting to make the GV unnamed.
Then the problem that the `nameUnamedGlobals` will use a name for the
global that is invalid ptx occurs. For non-extern globals, this is later
fixed by running the `NVPTXAssignValidGlobalNames` pass. However, It
makes sure to not touch externs as changing the name of "traditional
externs" will cause linking issues down the road.
This MR treats `.extern .shared` in the same manner as non-extern
globals during `NVPTXAssignValidGlobalNames` to fix the invalid names
given by `nameUnamedGlobals`.
Co-authored-by: Kjetil Kjeka <kjetil at muybridge.com>
Commit: be96289e03af836591bf0fe8dbaafe981d73405b
https://github.com/llvm/llvm-project/commit/be96289e03af836591bf0fe8dbaafe981d73405b
Author: Matthias Springer <me at m-sp.org>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/test/Dialect/Arith/int-range-interface.mlir
M mlir/test/Dialect/SCF/canonicalize.mlir
M mlir/test/Dialect/SCF/one-shot-bufferize.mlir
Log Message:
-----------
[mlir][Interfaces] Add generic pattern for region inlining (#176641)
Add a new canonicalization pattern that inlines the body of acyclic
`RegionBranchOpInterface` ops. This pattern is a generalization and
replacement for the following existing patterns:
* `SingleBlockExecuteInliner`: inlines `scf.execute_region` ops with a
single block.
* `SimplifyTrivialLoops`: inlines / folds away `scf.for` ops with 0 or 1
iterations.
* `RemoveStaticCondition`: inlines `scf.if` ops with a static condition.
* `FoldConstantCase`: inlines `scf.index_switch` ops with a constant
operand.
Additionally, this new pattern is also enabled for `scf.while` ops.
Loops with `scf.condition(%false)` are now also inlined. (New test case
added.)
The new pattern looks for region branch ops with a single acyclic path
through the operation (starting from and ending at "parent"). All
regions on that path can be inlined into the enclosing block.
Depends on #177116.
Commit: 15cd9f736bdd9c4af4cc8f585f4bf035d1983a25
https://github.com/llvm/llvm-project/commit/15cd9f736bdd9c4af4cc8f585f4bf035d1983a25
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[DAG] expandIntMINMAX - use getOppositeSignednessMinMaxOpcode helper to flip min/max signedness. NFC. (#177450)
Commit: 3c40eadfcaa0568b38836cc48491bb785cd338e5
https://github.com/llvm/llvm-project/commit/3c40eadfcaa0568b38836cc48491bb785cd338e5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
AMDGPU: Avoid introducing illegal fminnum_ieee/fmaxnum_ieee (#177418)
Avoid introducing fminnum_ieee/fmaxnum_ieee on f16 if f16
is not legal. This avoids regressing minimum/maximum cases
in a future commit.
Commit: 5f6258b2555ea88fdb0a2a110f8ad66581fff0c3
https://github.com/llvm/llvm-project/commit/5f6258b2555ea88fdb0a2a110f8ad66581fff0c3
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang-tools-extra/Maintainers.rst
Log Message:
-----------
Move Piotr Zegar to the inactive maintainers list (#176967)
While reaching out to folks for a maintainers list refresh, Piotr asked
to step down due to other commitments. Thank you for all your help!
Commit: 3d3dd559a0830ea9048cbbc92b0f7b762c5dd0e3
https://github.com/llvm/llvm-project/commit/3d3dd559a0830ea9048cbbc92b0f7b762c5dd0e3
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M flang-rt/include/flang-rt/runtime/type-info.h
M flang-rt/lib/runtime/assign.cpp
M flang-rt/lib/runtime/copy.cpp
M flang-rt/lib/runtime/derived.cpp
M flang-rt/lib/runtime/type-info.cpp
M flang/lib/Semantics/runtime-type-info.cpp
M flang/module/__fortran_type_info.f90
M flang/test/Lower/CUDA/cuda-allocatable-device.cuf
M flang/test/Lower/volatile-openmp.f90
M flang/test/Semantics/typeinfo01.f90
M flang/test/Semantics/typeinfo08.f90
Log Message:
-----------
[flang][cuda] Add support for derived-type component with managed/unified attributes (#177409)
Derived-type components that have the `ALLOCATABLE` or `POINTER`
attribute as well as the CUDA `MANAGED` or `UNIFIED` attribute need to
have a specific allocator index set in the descriptor so the allocation
is done correctly. Without this, the allocation is done in host memory
and will trigger illegal read or write if the component is used on the
device. The correct allocator index was set some time ago for the
`DEVICE` attribute but the `MANAGED` and `UNIFIED` attribute need the
same mechanism.
Since the `Component::Genre` has quite some room I opted to add specific
genre for allocatable and pointer with both managed or unified
attribute.
@klausler Let me know if you would prefer another solution. I was
thinking about a separate field but I wanted to avoid wasting some
bytes.
Commit: 1286de408cc4a3ba1bd6cb6fed7d9517c0429462
https://github.com/llvm/llvm-project/commit/1286de408cc4a3ba1bd6cb6fed7d9517c0429462
Author: Congzhe <congzhe.cao at huawei.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/test/Transforms/LoopFusion/lcssa.ll
A llvm/test/Transforms/LoopFusion/pr165087.ll
M llvm/test/Transforms/LoopFusion/sunk-phi-nodes.ll
Log Message:
-----------
[LoopFusion] Optimize away Phi nodes that are sunk from the 2nd loop preheader (#176503)
Fixed issue #165087.
When we sink phis from the 2nd loop preheader to the exit block, we
optimize it a bit further, i.e., propagate the uses of each phi node with
its incoming value and optimize away the phis. Deleted `fixPHINodes()`
too because the phis are already optimized away and there is no point
processing `fixPHINodes()`.
Commit: 9269f84d677491f7cbecff0cf2555d90ea713f28
https://github.com/llvm/llvm-project/commit/9269f84d677491f7cbecff0cf2555d90ea713f28
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/Maintainers.rst
Log Message:
-----------
[clang] Add myself as an additional offloading driver maintainer (#177392)
I've worked in the offloading driver a decent amount both directly here
and in Intel's downstream forks and I feel I have the judgement to
consider the needs of the project overall as well as the bandwidth to
properly carry out the role.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 10d6e4e5bd3939daa0d27a81380db16cc0367b09
https://github.com/llvm/llvm-project/commit/10d6e4e5bd3939daa0d27a81380db16cc0367b09
Author: Mingming Liu <mingmingl at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
Log Message:
-----------
[StaticDataLayout] Temporarily undo diagnostic warning when the data access profile payload is not available (#177412)
Added a FIXME to add it back later after figuring out how to make it a
non-error like the PGO profile mismatch one.
Commit: 8735e0c5145d9392b85edd54ca17481eb468d4bf
https://github.com/llvm/llvm-project/commit/8735e0c5145d9392b85edd54ca17481eb468d4bf
Author: Roland McGrath <mcgrathr at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M libc/config/linux/app.h
M libc/src/__support/threads/fork_callbacks.cpp
Log Message:
-----------
[libc] Remove superfluous explicitly defaulted constructors (#177471)
Any user-defined constructor, even an `= default` one, is
incompatible with aggregate initialization in C++20.
The default constructor does not need to be declared at all in
these cases. It's implicit.
Commit: 7ea1fa591abc28df2596781c5d7be67cf92f6ed3
https://github.com/llvm/llvm-project/commit/7ea1fa591abc28df2596781c5d7be67cf92f6ed3
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/find-last.ll
Log Message:
-----------
[LV] Skip FindLast reductions in collectInLoopReductions.
FindLast in-loop reductions are not supported, similarly to FindLastIV
reductions. Skip them in collectInLoopReductions, to avoid a crash for
loops with FindLast reductions and in-loop reductions preferred.
Commit: ce2a5919cd69fe41322064fdec1fe9c1218e2bef
https://github.com/llvm/llvm-project/commit/ce2a5919cd69fe41322064fdec1fe9c1218e2bef
Author: Akimasa Watanuki <mencotton0410 at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/test/Dialect/GPU/invalid.mlir
Log Message:
-----------
[mlir][gpu] Enforce async keyword when parsing gpu.launch with results (#176570)
The `gpu.launch` parser attempts to add a null `asyncTokenType` to the
results list if a result is requested but the `async` keyword is
missing, leading to an assertion failure.
Explicitly verify that `asyncTokenType` is valid when
`parser.getNumResults() > 0`. Emit a diagnostic error if the `async`
keyword is missing instead of crashing.
Add a regression test to `mlir/test/Dialect/GPU/invalid.mlir`.
Fix: https://github.com/llvm/llvm-project/issues/176530
Commit: 8b72266f415a1aa98d2ea686a1059cfd90bced1f
https://github.com/llvm/llvm-project/commit/8b72266f415a1aa98d2ea686a1059cfd90bced1f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/combine-pclmul.ll
M llvm/test/CodeGen/X86/pclmulqdq.ll
Log Message:
-----------
[X86] combinePCLMULQDQ - attempt to fold PCLMULQDQ(SHUFFLE(X),SHUFFLE(Y),C) -> PCLMULQDQ(X,Y,C') (REAPPLIED) (#177454)
Peek through input shuffle operands and see if we can access the shuffle
source directly with an adjusted PCLMULQDQ mask bit
REAPPLIED after #176932 was reverted due to use of
is128BitLaneRepeatedShuffleMask instead of isRepeatedTargetShuffleMask
caused failures with SM_SentinalZero shuffle mask indices - regression
test added by #177414
Fixes #176880
Commit: 5af4c1c65a0a4500a4f9f892c3562f2fab0392b2
https://github.com/llvm/llvm-project/commit/5af4c1c65a0a4500a4f9f892c3562f2fab0392b2
Author: Steven Wu <stevenwu at apple.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
A llvm/include/llvm/CAS/CASNodeSchema.h
A llvm/include/llvm/CAS/NamedValuesSchema.h
A llvm/lib/CAS/CASNodeSchema.cpp
M llvm/lib/CAS/CMakeLists.txt
A llvm/lib/CAS/NamedValuesSchema.cpp
M llvm/unittests/CAS/CMakeLists.txt
A llvm/unittests/CAS/NamedValuesSchemaTest.cpp
Log Message:
-----------
[CAS] Introduce CASNodeSchema and NamedValuesSchema (#177058)
Introduce CASNodeSchema, which is the common base class for
building a schema that can be used to represent an object
inside CAS. The schema describes the ways to encode and decode
between CAS objects and their representative objects.
NamedValuesSchema is a basic schema that describes a sorted
list of named nodes, where each node is an object. The names are
stored in the root object, allowing users to decide whether to
load the objects based on their names.
Commit: f8c4974963302912cd6c5c11d5097de5530c4943
https://github.com/llvm/llvm-project/commit/f8c4974963302912cd6c5c11d5097de5530c4943
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/MemCpyOptimizer.h
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
R llvm/test/Transforms/MemCpyOpt/stack-move-offset.ll
Log Message:
-----------
Revert "[MemCpyOpt] support offset slices for performStackMoveOptzn and processMemCpy (#176436)" (#177482)
This reverts commit 019eb855dd6a18a8f7ae5dd86abf6bc3ad0d9fa4.
Causes miscompiles, see original PR and #177185
Fixes https://github.com/llvm/llvm-project/issues/177185
Commit: f6e050c5f84803c6ca0d1d6d19051d3434e439a4
https://github.com/llvm/llvm-project/commit/f6e050c5f84803c6ca0d1d6d19051d3434e439a4
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CAS/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CAS/BUILD.gn
Log Message:
-----------
[gn build] Port 5af4c1c65a0a
Commit: 3219f1a5ce497125025ad8d27131cdea4b6e8595
https://github.com/llvm/llvm-project/commit/3219f1a5ce497125025ad8d27131cdea4b6e8595
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M openmp/device/src/Configuration.cpp
Log Message:
-----------
[OpenMP] Force initialization of global device environment
Summary:
This causes issues when we omit this, which requires a constructor from
an incompatible address space and bad things happen.
Commit: 1e6e25573f5a9dce9591e6ab429c465a8271ad18
https://github.com/llvm/llvm-project/commit/1e6e25573f5a9dce9591e6ab429c465a8271ad18
Author: Roland McGrath <mcgrathr at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M libc/src/__support/CPP/type_traits/is_unsigned.h
Log Message:
-----------
[libc] Clean up cpp::is_unsigned (#177456)
There are no unsigned floating-point types, so make it a
subset of is_integral instead of is_arithmetic.
Commit: 778ee545b54792d7b43fba201669699ef2d9b033
https://github.com/llvm/llvm-project/commit/778ee545b54792d7b43fba201669699ef2d9b033
Author: Roland McGrath <mcgrathr at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M libc/src/__support/CPP/limits.h
Log Message:
-----------
[libc] Clean up cpp::numeric_limits (#177461)
This adds the missing is_signed member and uses a generic
implementation for all integral types, using the same methods
employed by the libc++ implementation.
Commit: 53b0a64e9826c0696f22b945aa919e8552ed432d
https://github.com/llvm/llvm-project/commit/53b0a64e9826c0696f22b945aa919e8552ed432d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
Log Message:
-----------
[SelectionDAG] Add very basic computeKnownBits support for ISD::CLMUL. (#177445)
This implements leading zero count support so we can remove some
unnecessary ANDs.
Commit: 707ae1df5c266522c38b9af7e9586dd891267c17
https://github.com/llvm/llvm-project/commit/707ae1df5c266522c38b9af7e9586dd891267c17
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
Log Message:
-----------
Reland "[AMDGPU][GlobalISel] Add RegBankLegalize support for G_MUL (#… (#177481)
…177314)"
Original reverted due to v2s16 test failure caused by upstream gfx6/7
16-bit vector behavior change that landed shortly before.
Rebased and regenerated mul.ll test.
Original PR: #177314
Commit: 30fc5c1cdf9b177fabba55f9fc9df0025d54cf18
https://github.com/llvm/llvm-project/commit/30fc5c1cdf9b177fabba55f9fc9df0025d54cf18
Author: Sean Fertile <sd.fertile at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
A llvm/test/CodeGen/PowerPC/ppc64-patchpoint-size-check.ll
Log Message:
-----------
[PPC64] Convert assert in patchpoint emission to usage error. (#177453)
If the patchpoint intrinsic has requested less bytes then it takes to
make the call then report a fatal usage error. Also fixed a bug where we
forgot to count one of the instructions emitted.
Commit: a7b57cf7bba13cd7851bca1f2f3a820c74110c0d
https://github.com/llvm/llvm-project/commit/a7b57cf7bba13cd7851bca1f2f3a820c74110c0d
Author: Abhinav Gaba <abhinav.gaba at intel.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/test/OpenMP/declare_mapper_codegen.cpp
M clang/test/OpenMP/target_map_array_of_structs_with_nested_mapper_codegen.cpp
M clang/test/OpenMP/target_map_array_section_of_structs_with_nested_mapper_codegen.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/test/Target/LLVMIR/omptarget-llvm.mlir
M offload/libomptarget/omptarget.cpp
A offload/test/mapping/declare_mapper_target_checks.cpp
Log Message:
-----------
[OpenMP][Mappers] Fix ref-count tracking for maps inserted by mappers. (#177059)
This is a fix for https://github.com/llvm/llvm-project/issues/61636.
Ravi had this implemented downstream before he retired. This PR is a
chery-pick of that.
The test is taken from @jdoerfert's WIP change in
https://github.com/jdoerfert/llvm-project/commit/527bf4b1293f452aac1f872c4f771c7950b911f9.
The change partially undoes the changes done in
0caf736d7e1d16d1059553fc28dbac31f0b9f788, so @alexey-bataev might need
to take a look.
---------
Co-authored-by: Ravi Narayanaswamy <ravi.narayanaswamy at intel.com>
Co-authored-by: Johannes Doerfert <johannes at jdoerfert.de>
Commit: 98b42e384a957d418b48ee7351ebcbb6eccd5a8b
https://github.com/llvm/llvm-project/commit/98b42e384a957d418b48ee7351ebcbb6eccd5a8b
Author: joaosaffran <joaosaffranllvm at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/test/CodeGenHLSL/builtins/atan2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/ceil-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/cos-overloads.hlsl
Log Message:
-----------
[HLSL] Make atan2, cos, ceil overload tests stricter NFC (#177431)
This patch updates atan2, cos and ceil overload tests to use -O1 instead
of -disable-llvm-passes; also, the checks are updated to match the
change accordingly.
This work is part of https://github.com/llvm/llvm-project/issues/138016.
Commit: 58f3159a00a84b5a8a2f933a47e8ed92c6cca614
https://github.com/llvm/llvm-project/commit/58f3159a00a84b5a8a2f933a47e8ed92c6cca614
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M flang/include/flang/Evaluate/real.h
Log Message:
-----------
[flang][AIX] Suppress AIX compat error (NFC) (#177174)
Commit: 8a954feb3ed879794a82ff4313d22dcf5c4f32f8
https://github.com/llvm/llvm-project/commit/8a954feb3ed879794a82ff4313d22dcf5c4f32f8
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Replace legacy FindLast check with VPlan-based one (NFCI).
Checking directly in VPlan is more accurate, as the reductions could
have been transformed. This does not happen yet, so currently NFC.
Commit: 476a194935fa55f9e18f9193d25d86170f2219ab
https://github.com/llvm/llvm-project/commit/476a194935fa55f9e18f9193d25d86170f2219ab
Author: Roland McGrath <mcgrathr at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M libc/src/__support/CPP/type_traits/is_integral.h
M libc/src/__support/wchar/character_converter.h
Log Message:
-----------
[libc] Handle charNN_t in cpp::is_integral (#177463)
In C++20, char8_t is a distinct type from unsigned char, but is
still an integral type. char16_t and char32_t are integral types
in both C++17 and C++20.
This also reverts the change in PR #177421, which is not needed
when cpp::is_integral_v<char8_t> works correctly in all modes.
Commit: 7d5622f7917815d224b780309432ffe4729e4852
https://github.com/llvm/llvm-project/commit/7d5622f7917815d224b780309432ffe4729e4852
Author: Abhinav Gaba <abhinav.gaba at intel.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M offload/test/mapping/declare_mapper_target_checks.cpp
Log Message:
-----------
[NFC][OpenMP] Mark new mapper test as XFAIL on intelgpu. (#177491)
Other tests in the directory already do this. The new test was added in
#177059.
Commit: bc4b2765eb60a28913af1a2c5e92e4e806144f73
https://github.com/llvm/llvm-project/commit/bc4b2765eb60a28913af1a2c5e92e4e806144f73
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
Log Message:
-----------
[NFCI][AMDGPU] Refine `AMDGPUSubtarget.h` (#177473)
This PR is to move code around to pave the path for using
`GET_SUBTARGETINFO_MACRO` in `GCNSubtarget.h`.
Commit: 12b3a9f52e76611b3d3ceb746559d2c384b2565e
https://github.com/llvm/llvm-project/commit/12b3a9f52e76611b3d3ceb746559d2c384b2565e
Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/test/tools/llvm-exegesis/AArch64/debug-gen-asm.s
Log Message:
-----------
[llvm-exegesis] Add -mtriple to AArch64 test (#177485)
Similar to https://github.com/llvm/llvm-project/pull/148968
Commit: 626e3423f8bde1e0e79055c4675ed7ca944579c9
https://github.com/llvm/llvm-project/commit/626e3423f8bde1e0e79055c4675ed7ca944579c9
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/test/CIR/CodeGen/coro-task.cpp
Log Message:
-----------
[CIR] Upstream coroutine builtin coro_end (#176598)
This PR adds support for emitting the `__builtin_coro_end` builtin in
CIR.
Commit: 07ffea4d8c4f6da0ad6cfb83411c3f934c1821c1
https://github.com/llvm/llvm-project/commit/07ffea4d8c4f6da0ad6cfb83411c3f934c1821c1
Author: cmtice <cmtice at google.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
A llvm/test/CodeGen/AArch64/fptoi-256.ll
R llvm/test/CodeGen/fptoi-256.ll
Log Message:
-----------
[LLVM] Move CodeGen test to proper subdirectory. (#177493)
PR #176851 put an AArch64 test directly in the llvm/test/CodeGen
directory. This moves the test to the proper subdirectory.
Commit: 6fbd16115049f784dfb8aae525d6dcf6c7a1756e
https://github.com/llvm/llvm-project/commit/6fbd16115049f784dfb8aae525d6dcf6c7a1756e
Author: Nico Weber <thakis at chromium.org>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/test/AST/ast-dump-decl-stmts.cpp
Log Message:
-----------
[clang] Set end loc on declspec() (#177001)
Follow-up to #176296 where the root problem was declspec() not having a
valid range.
I don't if this is the right fix! It _is_ a progression on the included
test file though, and it's similar to what
Parser::ParsePackIndexingType() in the same file does.
Commit: 6f4661ce8f65dbc17797d7b55a3020f8b744b1c6
https://github.com/llvm/llvm-project/commit/6f4661ce8f65dbc17797d7b55a3020f8b744b1c6
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M SECURITY.md
Log Message:
-----------
[SECURITY.md] add pointers to "what is a security issue" (#177372)
Over the years, the security group has received a decent number of
reports of malicious input causing e.g., Clang to crash.
While these reports are valuable, it seems useful to clarify that many
of them are considered bugs, rather than security issues.
Commit: a24f6ce743cc2dd311e35894f386c05d0ead089c
https://github.com/llvm/llvm-project/commit/a24f6ce743cc2dd311e35894f386c05d0ead089c
Author: Adrian Prantl <aprantl at apple.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/ModuleList.h
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/ModuleList.cpp
M lldb/source/Symbol/Variable.cpp
M lldb/test/API/commands/expression/diagnostics/TestExprDiagnostics.py
Log Message:
-----------
[LLDB] Add a setting to simulate variables with missing locations (#177279)
Writing testcases for error handling that depends on specific DWARF is
very difficult and the resulting tests tend not to be very portable.
This patch adds a new setting to inject an error into variable
materialization, thus making it possible to write very simple source
code based tests for error handling instead.
This is primarily motivated by the Swift language plugin, but
functionality is generic and should be useful for other languages as
well.
Commit: 599c2731b3bbe9add135558377dbee2e1fa24358
https://github.com/llvm/llvm-project/commit/599c2731b3bbe9add135558377dbee2e1fa24358
Author: Alireza Torabian <alireza.torabian at huawei.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
A llvm/test/Transforms/LoopFusion/pr115279.ll
Log Message:
-----------
[LoopFusion] Forget cached SCEV values after the fusion (#177455)
This patch fixes the issue #115279. After the fusion, some of the cached
SCEV values such as the induction variable may not be valid anymore and
need to be forgotten.
Commit: f53fe860385c706903f74ac45404e95a841c113f
https://github.com/llvm/llvm-project/commit/f53fe860385c706903f74ac45404e95a841c113f
Author: Jie Fu <jiefu at tencent.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
Log Message:
-----------
[Vectorize] Silence a warning (NFC)
/llvm-project/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp:1533:11:
error: unused variable 'FindIVSelect' [-Werror,-Wunused-variable]
auto *FindIVSelect = findUserOf<Instruction::Select>(FindIVCmp);
^
1 error generated.
Commit: 33c301e84137af8a6b8701657b3023355f4f22b2
https://github.com/llvm/llvm-project/commit/33c301e84137af8a6b8701657b3023355f4f22b2
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang-tools-extra/clang-tidy/llvm/UseRangesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/llvm/use-ranges.rst
M clang-tools-extra/test/clang-tidy/checkers/llvm/use-ranges.cpp
Log Message:
-----------
[clang-tidy] Add replace_ to llvm-use-ranges (#177457)
Also sort the list of known algorithm wrappers.
Commit: 8a94708d8f64f0286401f8eb36f90111e245edb4
https://github.com/llvm/llvm-project/commit/8a94708d8f64f0286401f8eb36f90111e245edb4
Author: Akira Hatanaka <ahatanak at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/Sema/SemaDeclAttr.cpp
A clang/test/PlatformSpecific/xrOS/Sema/Inputs/XROS.sdk/SDKSettings.json
A clang/test/PlatformSpecific/xrOS/Sema/infer-ios-availability.c
A clang/test/PlatformSpecific/xrOS/Sema/infer-unavailable-from-missing-ios-availability-mapping.c
Log Message:
-----------
Infer visionOS availability from iOS availability (#176990)
Automatically infer and apply availability or unavailable attributes for
visionOS based on the corresponding iOS availability of the same
declaration using the version mapping information provided in
SDKSettings.json.
rdar://162148639
Commit: 11f64e92c627154a1caeb6d68c9999cca20f0dae
https://github.com/llvm/llvm-project/commit/11f64e92c627154a1caeb6d68c9999cca20f0dae
Author: Jie Fu <jiefu at tencent.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
Log Message:
-----------
[AMDGPU] Silence a warning (NFC)
llvm-project/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp:686:7:
error: unused variable 'DstTy' [-Werror,-Wunused-variable]
LLT DstTy = MRI.getType(Dst);
^
1 error generated.
Commit: 1ec48db07915e477f4f0dc0c3427191957f45fce
https://github.com/llvm/llvm-project/commit/1ec48db07915e477f4f0dc0c3427191957f45fce
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M .github/CODEOWNERS
M SECURITY.md
M clang-tools-extra/Maintainers.rst
M clang-tools-extra/clang-tidy/bugprone/UnsafeFunctionsCheck.cpp
M clang-tools-extra/clang-tidy/llvm/UseRangesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/llvm/use-ranges.rst
M clang-tools-extra/test/clang-tidy/checkers/llvm/use-ranges.cpp
M clang/CMakeLists.txt
M clang/Maintainers.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/checkers.rst
A clang/include/clang/Analysis/AnnexKDetection.h
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/BuiltinsX86_64.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Basic/OffloadArch.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/CommonArgs.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Serialization/ASTWriter.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ExprConstant.cpp
A clang/lib/Analysis/AnnexKDetection.cpp
M clang/lib/Analysis/CMakeLists.txt
M clang/lib/Basic/OffloadArch.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/Dialect/Transforms/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
R clang/lib/CIR/Dialect/Transforms/LoweringPrepareCXXABI.h
R clang/lib/CIR/Dialect/Transforms/LoweringPrepareItaniumCXXABI.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRCXXABI.h
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerItaniumCXXABI.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGObjC.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Headers/crc32intrin.h
M clang/lib/Lex/Lexer.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/SemaAPINotes.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ModuleManager.cpp
M clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp
M clang/test/APINotes/Inputs/Headers/Methods.apinotes
M clang/test/APINotes/Inputs/Headers/Methods.h
M clang/test/APINotes/methods.cpp
M clang/test/AST/ByteCode/cxx26.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/AST/ast-dump-decl-stmts.cpp
M clang/test/Analysis/Inputs/system-header-simulator.h
M clang/test/Analysis/LifetimeSafety/benchmark.py
M clang/test/Analysis/analyzer-config.c
A clang/test/Analysis/security-deprecated-buffer-handling-report-modes.c
A clang/test/CIR/CodeGen/builtin-bit-cast.cpp
M clang/test/CIR/CodeGen/coro-task.cpp
M clang/test/CIR/CodeGen/dynamic-cast.cpp
M clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
M clang/test/CIR/CodeGenBuiltins/builtin_bit.cpp
A clang/test/CIR/IR/invalid-memcpy.cir
A clang/test/CIR/IR/libc-memcpy.cir
A clang/test/CIR/Lowering/libc.cir
M clang/test/CXX/special/class.temporary/p6.cpp
A clang/test/ClangScanDeps/build-session-validation-outdated-module.c
M clang/test/CodeGen/X86/sse42-builtins.c
M clang/test/CodeGen/atomic-ops.c
M clang/test/CodeGen/lifetime-sanitizer.c
M clang/test/CodeGen/scoped-atomic-ops.c
M clang/test/CodeGenCXX/lifetime-sanitizer.cpp
M clang/test/CodeGenCXX/wasm-reftypes-mangle.cpp
M clang/test/CodeGenHLSL/builtins/atan2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/ceil-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/cos-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/radians-overloads.hlsl
M clang/test/CodeGenObjC/arc-arm.m
M clang/test/CodeGenObjC/arc-foreach.m
M clang/test/CodeGenObjC/arc-property.m
M clang/test/CodeGenObjC/arc-related-result-type.m
M clang/test/CodeGenObjC/arc-unopt.m
M clang/test/CodeGenObjC/arc-unsafeclaim.m
M clang/test/CodeGenObjC/arc-with-atthrow.m
M clang/test/CodeGenObjC/ns_consume_null_check.m
M clang/test/CodeGenObjC/objc-arc-container-subscripting.m
M clang/test/CodeGenObjC/os_log.m
M clang/test/CodeGenObjCXX/auto-release-result-assert.mm
M clang/test/CodeGenObjCXX/inheriting-constructor-cleanup.mm
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-arch.c
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
A clang/test/Modules/pr171769.cpp
M clang/test/OpenMP/declare_mapper_codegen.cpp
M clang/test/OpenMP/target_map_array_of_structs_with_nested_mapper_codegen.cpp
M clang/test/OpenMP/target_map_array_section_of_structs_with_nested_mapper_codegen.cpp
A clang/test/PlatformSpecific/xrOS/Sema/Inputs/XROS.sdk/SDKSettings.json
A clang/test/PlatformSpecific/xrOS/Sema/infer-ios-availability.c
A clang/test/PlatformSpecific/xrOS/Sema/infer-unavailable-from-missing-ios-availability-mapping.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Sema/atomic-ops.c
M clang/test/Sema/scoped-atomic-ops.c
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
M clang/test/Sema/warn-lifetime-safety-dataflow.cpp
M clang/test/Sema/warn-lifetime-safety-missing-origin-stats.cpp
M clang/test/Sema/warn-lifetime-safety-suggestions.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp
M clang/unittests/Serialization/CMakeLists.txt
A clang/unittests/Serialization/NamespaceLookupTest.cpp
M clang/utils/reduce-clang-crash.py
M clang/www/cxx_status.html
M cmake/Modules/HandleDoxygen.cmake
M compiler-rt/lib/asan/asan_fake_stack.cpp
M compiler-rt/lib/orc/elfnix_platform.cpp
M compiler-rt/lib/sanitizer_common/tests/sanitizer_procmaps_mac_test.cpp
A compiler-rt/test/orc/TestCases/Linux/Generic/ctor-dtor.cpp
M cross-project-tests/dtlto/archive.test
M cross-project-tests/dtlto/archives-mixed-lto-modes-test.test
M cross-project-tests/dtlto/archives-same-module-id.test
M cross-project-tests/dtlto/link-archive-thin.test
M cross-project-tests/dtlto/signal.test
M flang-rt/include/flang-rt/runtime/type-info.h
M flang-rt/lib/runtime/assign.cpp
M flang-rt/lib/runtime/copy.cpp
M flang-rt/lib/runtime/derived.cpp
M flang-rt/lib/runtime/type-info.cpp
M flang/docs/Extensions.md
M flang/include/flang/Evaluate/initial-image.h
M flang/include/flang/Evaluate/real.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Evaluate/fold.cpp
M flang/lib/Evaluate/initial-image.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCUtils.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFFunctionRewrite.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/lib/Parser/message.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-coarray.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/data-to-inits.cpp
M flang/lib/Semantics/data-to-inits.h
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Semantics/runtime-type-info.cpp
M flang/lib/Semantics/semantics.cpp
M flang/module/__fortran_type_info.f90
A flang/test/Driver/global-isel.f90
A flang/test/Driver/lto-global-isel.f90
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/CUDA/cuda-allocate.fir
M flang/test/Fir/CUDA/cuda-data-transfer.fir
M flang/test/Fir/CUDA/cuda-global-addr.mlir
M flang/test/Fir/CUDA/cuda-launch.fir
A flang/test/Fir/FirToSCF/any.fir
A flang/test/Fir/FirToSCF/do-extra.fir
A flang/test/Fir/FirToSCF/if-extra.fir
A flang/test/Fir/FirToSCF/iterate-while-extra.fir
A flang/test/Fir/FirToSCF/nested-unregistered.fir
A flang/test/Fir/FirToSCF/normalize.fir
A flang/test/Fir/FirToSCF/sum.fir
M flang/test/Lower/CUDA/cuda-allocatable-device.cuf
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/assigned-goto.f90
M flang/test/Lower/volatile-openmp.f90
A flang/test/Parser/keyword-optional-spaces.f90
A flang/test/Semantics/bug2098.f90
M flang/test/Semantics/cuf03.cuf
M flang/test/Semantics/cuf23.cuf
M flang/test/Semantics/data07.f90
M flang/test/Semantics/data12.f90
M flang/test/Semantics/data23.f90
M flang/test/Semantics/declarations06.f90
M flang/test/Semantics/equivalence02.f90
M flang/test/Semantics/typeinfo01.f90
M flang/test/Semantics/typeinfo08.f90
M libc/config/linux/app.h
M libc/fuzzing/__support/CMakeLists.txt
A libc/fuzzing/__support/weak_avl_fuzz.cpp
M libc/shared/math.h
A libc/shared/math/log10.h
A libc/shared/math/log1p.h
A libc/shared/math/log2.h
M libc/src/__support/CMakeLists.txt
M libc/src/__support/CPP/limits.h
M libc/src/__support/CPP/type_traits/is_integral.h
M libc/src/__support/CPP/type_traits/is_unsigned.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/log10.h
A libc/src/__support/math/log1p.h
A libc/src/__support/math/log2.h
M libc/src/__support/threads/fork_callbacks.cpp
A libc/src/__support/weak_avl.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/log10.cpp
M libc/src/math/generic/log1p.cpp
M libc/src/math/generic/log2.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_math_test.cpp
M libc/test/src/__support/CMakeLists.txt
A libc/test/src/__support/weak_avl_test.cpp
M libclc/CMakeLists.txt
M libclc/clc/lib/generic/atomic/clc_atomic_dec.cl
M libclc/clc/lib/generic/atomic/clc_atomic_inc.cl
M libcxx/include/__iterator/wrap_iter.h
M libcxx/include/__ranges/subrange.h
M lld/COFF/Config.h
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/MinGW.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/Writer.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/ScriptParser.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Writer.cpp
M lld/MachO/InputFiles.cpp
M lld/MachO/ObjC.cpp
M lld/MachO/SymbolTable.cpp
M lld/include/lld/Common/BPSectionOrdererBase.inc
M lld/test/ELF/why-live.test
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/ModuleList.h
M lldb/include/lldb/Utility/UserID.h
M lldb/source/API/CMakeLists.txt
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/ModuleList.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp
M lldb/source/Symbol/Variable.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/test/API/commands/expression/diagnostics/TestExprDiagnostics.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/optional/TestDataFormatterLibcxxOptionalSimulator.py
M lldb/test/API/functionalities/ubsan/basic/Makefile
M lldb/test/API/functionalities/ubsan/basic/main.c
M lldb/test/API/lang/cpp/template-alias/TestTemplateAlias.py
M lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io.py
M llvm/.clang-format
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/LangRef.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/Analysis/CallGraphSCCPass.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
A llvm/include/llvm/CAS/CASNodeSchema.h
A llvm/include/llvm/CAS/NamedValuesSchema.h
M llvm/include/llvm/CodeGen/BasicBlockSectionsProfileReader.h
M llvm/include/llvm/CodeGen/CFIFixup.h
M llvm/include/llvm/CodeGen/GlobalISel/GISelValueTracking.h
M llvm/include/llvm/CodeGen/LiveStacks.h
M llvm/include/llvm/CodeGen/LiveVariables.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/RegisterUsageInfo.h
M llvm/include/llvm/CodeGen/ReplaceWithVeclib.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/ExecutionEngine/Orc/ELFNixPlatform.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/ObjectFormats.h
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/FixedMetadataKinds.def
M llvm/include/llvm/IR/GlobalVariable.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/Metadata.h
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LTO/LTO.h
M llvm/include/llvm/Support/Compiler.h
M llvm/include/llvm/TargetParser/TargetParser.h
M llvm/include/llvm/Transforms/Scalar/MemCpyOptimizer.h
M llvm/lib/Analysis/CallGraphSCCPass.cpp
M llvm/lib/Analysis/FunctionPropertiesAnalysis.cpp
M llvm/lib/Analysis/LazyBranchProbabilityInfo.cpp
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
A llvm/lib/CAS/CASNodeSchema.cpp
M llvm/lib/CAS/CMakeLists.txt
A llvm/lib/CAS/NamedValuesSchema.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/BasicBlockMatchingAndInference.cpp
M llvm/lib/CodeGen/BasicBlockPathCloning.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/BreakFalseDeps.cpp
M llvm/lib/CodeGen/CFGuardLongjmp.cpp
M llvm/lib/CodeGen/CFIInstrInserter.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
M llvm/lib/CodeGen/EHContGuardTargets.cpp
M llvm/lib/CodeGen/ExpandIRInsts.cpp
M llvm/lib/CodeGen/ExpandMemCmp.cpp
M llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
M llvm/lib/CodeGen/ExpandReductions.cpp
M llvm/lib/CodeGen/FEntryInserter.cpp
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
M llvm/lib/CodeGen/FuncletLayout.cpp
M llvm/lib/CodeGen/GCEmptyBasicBlocks.cpp
M llvm/lib/CodeGen/GCMetadata.cpp
M llvm/lib/CodeGen/GCRootLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/CodeGen/HardwareLoops.cpp
M llvm/lib/CodeGen/IfConversion.cpp
M llvm/lib/CodeGen/ImplicitNullChecks.cpp
M llvm/lib/CodeGen/IndirectBrExpandPass.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
M llvm/lib/CodeGen/JMCInstrumenter.cpp
M llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp
M llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
M llvm/lib/CodeGen/LiveDebugVariables.cpp
M llvm/lib/CodeGen/LiveIntervals.cpp
M llvm/lib/CodeGen/LiveRangeShrink.cpp
M llvm/lib/CodeGen/LiveVariables.cpp
M llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
M llvm/lib/CodeGen/LowerEmuTLS.cpp
M llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
M llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
M llvm/lib/CodeGen/MachineBlockHashInfo.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineBranchProbabilityInfo.cpp
M llvm/lib/CodeGen/MachineCFGPrinter.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineCombiner.cpp
M llvm/lib/CodeGen/MachineCycleAnalysis.cpp
M llvm/lib/CodeGen/MachineDominanceFrontier.cpp
M llvm/lib/CodeGen/MachineDominators.cpp
M llvm/lib/CodeGen/MachineFunctionSplitter.cpp
M llvm/lib/CodeGen/MachineInstrBundle.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
M llvm/lib/CodeGen/MachineLoopInfo.cpp
M llvm/lib/CodeGen/MachineModuleInfo.cpp
M llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachinePostDominators.cpp
M llvm/lib/CodeGen/MachineRegionInfo.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/ModuloSchedule.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/PHIElimination.cpp
M llvm/lib/CodeGen/PatchableFunction.cpp
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/CodeGen/ProcessImplicitDefs.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/PseudoProbeInserter.cpp
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocPBQP.cpp
M llvm/lib/CodeGen/RegUsageInfoCollector.cpp
M llvm/lib/CodeGen/RegUsageInfoPropagate.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/RegisterUsageInfo.cpp
M llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
M llvm/lib/CodeGen/RemoveRedundantDebugValues.cpp
M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
M llvm/lib/CodeGen/SafeStack.cpp
M llvm/lib/CodeGen/SanitizerBinaryMetadata.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/ShadowStackGCLowering.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/CodeGen/SlotIndexes.cpp
M llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp
M llvm/lib/CodeGen/StackProtector.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/StaticDataAnnotator.cpp
M llvm/lib/CodeGen/StaticDataSplitter.cpp
M llvm/lib/CodeGen/TailDuplication.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/CodeGen/UnreachableBlockElim.cpp
M llvm/lib/CodeGen/WindowsSecureHotPatching.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/ObjectFormats.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Attributes.cpp
M llvm/lib/IR/Globals.cpp
M llvm/lib/IR/IRBuilder.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/LTO/ThinLTOCodeGenerator.cpp
M llvm/lib/Linker/LinkModules.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/ObjCopy/DXContainer/DXContainerObjcopy.cpp
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/Object/IRSymtab.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
M llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/R600Subtarget.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/M68k/M68kCollapseMOVEMPass.cpp
M llvm/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
M llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
M llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
M llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
M llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVCallLowering.h
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizeZeroSizeArrays.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareGlobals.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/TargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86AsmPrinter.h
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86WinEHUnwindV2.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/IndirectCallPromotion.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/JumpTableToSwitch.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/InjectTLIMappings.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/ProfileVerify.cpp
M llvm/lib/Transforms/Utils/RelLookupTableConverter.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/Assembler/thinlto-summary.ll
A llvm/test/Bitcode/Inputs/thinlto-function-summary-callgraph-relbf.bc
M llvm/test/Bitcode/thinlto-function-summary-callgraph-relbf.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/sink-and-fold-illegal-shift.ll
A llvm/test/CodeGen/AArch64/aarch64-condopt-cross-block-different-regs.mir
A llvm/test/CodeGen/AArch64/aarch64-condopt-nzcvdef.mir
M llvm/test/CodeGen/AArch64/aarch64-mops.ll
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/call-rv-marker.ll
M llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
M llvm/test/CodeGen/AArch64/cpa-globalisel.ll
M llvm/test/CodeGen/AArch64/fixed-length-bf16-arith.ll
A llvm/test/CodeGen/AArch64/fptoi-256.ll
M llvm/test/CodeGen/AArch64/load-store-forwarding.ll
M llvm/test/CodeGen/AArch64/neon-abd.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/tail-call-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
M llvm/test/CodeGen/AMDGPU/abs_i16.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
A llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
R llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/integer-canonicalizing-src-modifiers.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
A llvm/test/CodeGen/AMDGPU/issue176966-extend-vector-inreg.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.iterative.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/saddsat.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
A llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
A llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/sibling-call.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
M llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/usubsat.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
A llvm/test/CodeGen/AMDGPU/waves-per-eu-hints-lower-occupancy-target.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
M llvm/test/CodeGen/M68k/CollapseMOVEM.mir
M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.py
A llvm/test/CodeGen/NVPTX/default-sm.ll
A llvm/test/CodeGen/NVPTX/extern-shared-valid-name.ll
M llvm/test/CodeGen/NVPTX/i128.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
A llvm/test/CodeGen/PowerPC/ppc64-patchpoint-size-check.ll
M llvm/test/CodeGen/PowerPC/vavg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir
M llvm/test/CodeGen/RISCV/atomic-load-store.ll
M llvm/test/CodeGen/RISCV/atomic-load-zext.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
A llvm/test/CodeGen/RISCV/rvv/pr171231.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
M llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll
M llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
M llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
M llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_no_return.ll
M llvm/test/CodeGen/SPIRV/fembed-bitcode-marker.ll
M llvm/test/CodeGen/SPIRV/hip_dyn_lds.ll
A llvm/test/CodeGen/X86/clmul-vector-256.ll
A llvm/test/CodeGen/X86/clmul-vector-512.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
A llvm/test/CodeGen/X86/combine-bzhi.ll
M llvm/test/CodeGen/X86/combine-pclmul.ll
A llvm/test/CodeGen/X86/pclmulqdq.ll
M llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-epilogs.mir
M llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-instr.mir
M llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt_f32_su32.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt_n.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/neon-dot-product.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_load_tr.s
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/rv32zalasr-invalid.s
M llvm/test/MC/RISCV/rv64zalasr-invalid.s
M llvm/test/MC/RISCV/rv64zalasr-valid.s
M llvm/test/MC/RISCV/rvzalasr-valid.s
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
A llvm/test/TableGen/invalid_typecast_assert.td
M llvm/test/Transforms/ArgumentPromotion/metadata.ll
M llvm/test/Transforms/Attributor/nofpclass.ll
A llvm/test/Transforms/CodeGenPrepare/X86/codegenprepare-hang-bitcast-phi.ll
M llvm/test/Transforms/GVN/PRE/load-metadata.ll
A llvm/test/Transforms/GVN/merge-nofpclass.ll
M llvm/test/Transforms/GVNHoist/hoist-md.ll
M llvm/test/Transforms/InstCombine/fold-phi-load-metadata.ll
M llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll
M llvm/test/Transforms/InstCombine/load-addrspacecast-select.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
M llvm/test/Transforms/InstCombine/not.ll
A llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fsub.ll
A llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll
A llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll
M llvm/test/Transforms/LoopFusion/lcssa.ll
A llvm/test/Transforms/LoopFusion/pr115279.ll
A llvm/test/Transforms/LoopFusion/pr165087.ll
M llvm/test/Transforms/LoopFusion/sunk-phi-nodes.ll
A llvm/test/Transforms/LoopInterchange/reduction2mem-limitation.ll
A llvm/test/Transforms/LoopInterchange/reduction2mem.ll
A llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
M llvm/test/Transforms/LoopVectorize/find-last.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
R llvm/test/Transforms/MemCpyOpt/stack-move-offset.ll
M llvm/test/Transforms/PGOProfile/prof-verify-no-entrycount.ll
M llvm/test/Transforms/PGOProfile/prof-verify.ll
M llvm/test/Transforms/PGOProfile/profcheck-llvm.global_ctors.ll
M llvm/test/Transforms/PGOProfile/profcheck-select.ll
A llvm/test/Transforms/SLPVectorizer/X86/phi-multi-same-nodes.ll
M llvm/test/Transforms/SROA/preserve-metadata.ll
M llvm/test/Transforms/SimplifyCFG/hoist-with-metadata.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
A llvm/test/Verifier/nofpclass-metadata.ll
M llvm/test/tools/llvm-exegesis/AArch64/debug-gen-asm.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-forwarding.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s
R llvm/test/tools/llvm-objcopy/DXContainer/copy-basic.test
A llvm/test/tools/llvm-objcopy/DXContainer/copy-basic.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/extract-section-basic.test
A llvm/test/tools/llvm-objcopy/DXContainer/extract-section-basic.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/extract-section-errs.test
A llvm/test/tools/llvm-objcopy/DXContainer/extract-section-errs.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/extract-section-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/extract-section-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/only-section-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/only-section-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/reading-errs.test
A llvm/test/tools/llvm-objcopy/DXContainer/reading-errs.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/remove-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/remove-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/remove-root-signature.test
A llvm/test/tools/llvm-objcopy/DXContainer/remove-root-signature.yaml
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/test/tools/llvm-reduce/reduce-operands-to-args-metadata-to-attributes.ll
M llvm/tools/llc/llc.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/lto/CMakeLists.txt
M llvm/unittests/CAS/CMakeLists.txt
A llvm/unittests/CAS/NamedValuesSchemaTest.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/DAGISelMatcher.cpp
M llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/performance/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Serialization/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/CAS/BUILD.gn
M llvm/utils/gn/secondary/llvm/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-dwarfdump/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CAS/BUILD.gn
M llvm/utils/profcheck-xfail.txt
M mlir/include/mlir/Conversion/TosaToLinalg/TosaToLinalg.h
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/Transforms/NVVMAttachTarget.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCIfClauseLowering.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/test/Analysis/DataFlow/test-dead-code-analysis.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma.mlir
M mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma.mlir
M mlir/test/Dialect/Arith/int-range-interface.mlir
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/GPU/nvvm-attach-target.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize-conv.mlir
M mlir/test/Dialect/OpenACC/acc-if-clause-lowering.mlir
M mlir/test/Dialect/SCF/canonicalize.mlir
M mlir/test/Dialect/SCF/one-shot-bufferize.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/Vector/canonicalize/vector-from-elements.mlir
A mlir/test/Dialect/Vector/canonicalize/vector-to-shape-cast.mlir
M mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir
M mlir/test/Dialect/Vector/vector-warp-distribute.mlir
M mlir/test/Target/LLVMIR/omptarget-llvm.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M offload/libomptarget/omptarget.cpp
A offload/test/mapping/declare_mapper_target_checks.cpp
M openmp/device/include/Synchronization.h
M openmp/device/src/Configuration.cpp
M openmp/device/src/Synchronization.cpp
M orc-rt/include/orc-rt/bit.h
M orc-rt/unittests/EndianTest.cpp
M orc-rt/unittests/bit-test.cpp
M utils/bazel/.bazelrc
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
rebase
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/b1bef31b4c48...1ec48db07915
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