[all-commits] [llvm/llvm-project] 81ec09: AMDGPU: Change ABI of 16-bit scalar values for gfx...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/amdgpu/change-abi-16-bit-gfx6-gfx7
  Home:   https://github.com/llvm/llvm-project
  Commit: 81ec09c747eb7fb0f9769f1ef5026a77c05fe049
      https://github.com/llvm/llvm-project/commit/81ec09c747eb7fb0f9769f1ef5026a77c05fe049
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-01-22 (Thu, 22 Jan 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/clamp.ll
    M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
    M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
    M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
    M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.ll
    M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
    M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
    M llvm/test/CodeGen/AMDGPU/fneg.ll
    M llvm/test/CodeGen/AMDGPU/fpow.ll
    M llvm/test/CodeGen/AMDGPU/fract-match.ll
    M llvm/test/CodeGen/AMDGPU/function-args.ll
    M llvm/test/CodeGen/AMDGPU/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
    M llvm/test/CodeGen/AMDGPU/integer-canonicalizing-src-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.ll
    M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/minimumnum.ll
    M llvm/test/CodeGen/AMDGPU/omod.ll
    M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
    M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
    M llvm/test/CodeGen/AMDGPU/roundeven.ll
    M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
    M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
    M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
    M llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
    M llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll

  Log Message:
  -----------
  AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7

Keep bf16/f16 values encoded as the low half of a 32-bit register,
instead of promoting to float. This avoids unwanted FP effects
from the fpext/fptrunc which should not be implied by just
passing an argument. This also fixes ABI divergence between
SelectionDAG and GlobalISel.

I've wanted to make this change for ages, and failed the last
few times. The main complication was the hack to return
shader integer types in SGPRs, which now needs to inspect
the underlying IR type.



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