[all-commits] [llvm/llvm-project] 73a309: [RISCV] Add ZZZ_ to some inline assembly vector re...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 73a309e20e92ff8e9af295c81ee74a58b07a93ba
      https://github.com/llvm/llvm-project/commit/73a309e20e92ff8e9af295c81ee74a58b07a93ba
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-01-21 (Wed, 21 Jan 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir
    M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
    A llvm/test/CodeGen/RISCV/rvv/pr171231.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll
    M llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
    M llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
    M llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

  Log Message:
  -----------
  [RISCV] Add ZZZ_ to some inline assembly vector register classes to sort them after VR/VRNoV0 in regclass enum. (#177087)

This prevents getCommonSubClass from finding them before VR/VRNoV0.

Fixes a crash reported post-commit in #171231. getCommonSubClass
returned one of these classes, but it doesn't have the same VTs as
VR/VRNoV0 leading to an assertion failure.

The subregister-undef-early-clobber.mir still ends up finding these
register classes in the InitUndef pass.



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