[all-commits] [llvm/llvm-project] f53471: [OpenMP][NFC] Use `uinc` atomic builtins for this ...
Steven Wu via All-commits
all-commits at lists.llvm.org
Wed Jan 21 13:44:47 PST 2026
Branch: refs/heads/users/cachemeifyoucan/spr/cas-introduce-casnodeschema-and-namedvaluesschema
Home: https://github.com/llvm/llvm-project
Commit: f534711729b7feb0efc443a5f2139a906a60cf8f
https://github.com/llvm/llvm-project/commit/f534711729b7feb0efc443a5f2139a906a60cf8f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M openmp/device/include/Synchronization.h
M openmp/device/src/Synchronization.cpp
Log Message:
-----------
[OpenMP][NFC] Use `uinc` atomic builtins for this operation (#177207)
Summary:
We support this now, this is 1-to-1 equivalent and simply prevents us
from needing to do it ourselves.
Commit: 8f1427d26929bdec364f46a9043303e6b1ed4200
https://github.com/llvm/llvm-project/commit/8f1427d26929bdec364f46a9043303e6b1ed4200
Author: Prerona Chaudhuri <43287592+pchaudhuri-nv at users.noreply.github.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
A llvm/test/TableGen/invalid_typecast_assert.td
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
Log Message:
-----------
[TableGen] Gracefully error out in ParseTreePattern when DAG has zero operands so that llvm-tblgen doesn't crash (#161417)
Also handle the case when Pat->Child(i) is null in
CodeGenDAGPatterns::FindPatternInputsAndOutputs().
Fixes issue #157619 : TableGen asserts on invalid cast
Commit: 9c2124e0f6bb94a9ce4eafe99f62ed0bf61833fe
https://github.com/llvm/llvm-project/commit/9c2124e0f6bb94a9ce4eafe99f62ed0bf61833fe
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[NFC][SLP] Fix typo in assertion (#177079)
Commit: 792e3398f107b8b2a05d2494aa0a9491db86d722
https://github.com/llvm/llvm-project/commit/792e3398f107b8b2a05d2494aa0a9491db86d722
Author: Thurston Dang <thurston at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/neon-dot-product.ll
Log Message:
-----------
[msan] Handle NEON dot product intrinsics (#176084)
Propagate shadow by reusing existing `handleVectorPmaddIntrinsic()`
(used for analogous x86 instructions; renamed to
`handleVectorDotProductIntrinsic()`), instead of strictly handling.
Commit: 86a2486bff5b9633c59f0b7e5f4486edcc3a736a
https://github.com/llvm/llvm-project/commit/86a2486bff5b9633c59f0b7e5f4486edcc3a736a
Author: Nico Weber <thakis at chromium.org>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M libc/shared/math.h
A libc/shared/math/log10.h
A libc/shared/math/log1p.h
A libc/shared/math/log2.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/log10.h
A libc/src/__support/math/log1p.h
A libc/src/__support/math/log2.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/log10.cpp
M libc/src/math/generic/log1p.cpp
M libc/src/math/generic/log2.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_math_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][math] Refactor log10, log1p, log2 implementation to header-only in src/__support/math folder. (#176089)
Part of #147386
in preparation for:
https://discourse.llvm.org/t/rfc-make-clang-builtin-math-functions-constexpr-with-llvm-libc-to-support-c-23-constexpr-math-functions/86450
Commit: 004e2106a8fd6ff31c03c9978ae0ab9794b704ed
https://github.com/llvm/llvm-project/commit/004e2106a8fd6ff31c03c9978ae0ab9794b704ed
Author: Finn Plummer <mail at inbelic.dev>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/ObjCopy/DXContainer/DXContainerObjcopy.cpp
R llvm/test/tools/llvm-objcopy/DXContainer/copy-basic.test
A llvm/test/tools/llvm-objcopy/DXContainer/copy-basic.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/extract-section-basic.test
A llvm/test/tools/llvm-objcopy/DXContainer/extract-section-basic.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/extract-section-errs.test
A llvm/test/tools/llvm-objcopy/DXContainer/extract-section-errs.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/extract-section-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/extract-section-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/only-section-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/only-section-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/reading-errs.test
A llvm/test/tools/llvm-objcopy/DXContainer/reading-errs.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/remove-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/remove-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/remove-root-signature.test
A llvm/test/tools/llvm-objcopy/DXContainer/remove-root-signature.yaml
Log Message:
-----------
[NFC][DirectX] Clean-up `llvm-objcopy` to be consistent across implementation details (#177006)
This change is to ensure the implementation of the various
`llvm-objcopy` args are implemented with consistent patterns.
This is intended to help have a clear and consistent point of reference
for new contributors to extend `llvm-objcopy`.
These changes are largely to propagate the review comments of
https://github.com/llvm/llvm-project/pull/159999 back onto the changes
introduced before it.
Commit: 058a223388576cc7f037f8155967a73d5400b053
https://github.com/llvm/llvm-project/commit/058a223388576cc7f037f8155967a73d5400b053
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
Log Message:
-----------
[HLSL] Add wave active ballot to set of wave ops that set waveops shader flag (#177043)
This PR simply adds wave active ballot to the set of wave ops that
switch on the waveops shader flag.
Commit: e47e51a30a0362686c5f92a36c99476f1d7ac561
https://github.com/llvm/llvm-project/commit/e47e51a30a0362686c5f92a36c99476f1d7ac561
Author: Alan Zhao <ayzhao at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/not.ll
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[profcheck][InstCombine] Fix missing profile data identified by not.ll test (#176497)
Tracking issue: #147390
Commit: 35e9540ba8bd54d31a8b805d70c5c8607cf73cf1
https://github.com/llvm/llvm-project/commit/35e9540ba8bd54d31a8b805d70c5c8607cf73cf1
Author: Matthias Springer <me at m-sp.org>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/test/Analysis/DataFlow/test-dead-code-analysis.mlir
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
Log Message:
-----------
[mlir][SCF] Improve `ForOp::getSuccessorRegions` (#177116)
- Loops with 0 iterations always branch back to the parent.
- Loops with 1 iteration always branch into the loop, then immediately
back to the parent.
This change improves the quality of data flow analyses (e.g., dead code
analysis). It is also in preparation of adding a generic region inlining
canonicalization pattern for `RegionBranchOpInterface` ops (#176641).
---------
Co-authored-by: Jakub Kuderski <jakub at nod-labs.com>
Commit: 6a9699f194fd146262b25a4bb4a5189db1d7f259
https://github.com/llvm/llvm-project/commit/6a9699f194fd146262b25a4bb4a5189db1d7f259
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[ProfCheck] Exclude Transforms/InstCombine/load-addrspacecast-select.ll
This was added recently and needs to be fixed, but for now exclude it so
that the bot can return to green and we can better catch future
regressions.
Commit: 170de19a5b2dc2b9855d73794f139d1ff84bce47
https://github.com/llvm/llvm-project/commit/170de19a5b2dc2b9855d73794f139d1ff84bce47
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
A llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
Log Message:
-----------
[AMDGPU] Latency calculation must be independent of meta insts (#177052)
Debug and other meta instructions in bundles must not affect latency
calculation.
Ensure that code compiled with and without debug instructions is
identical.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 8f58cfecae947da3ec7a3a08a1678bacc76e04ca
https://github.com/llvm/llvm-project/commit/8f58cfecae947da3ec7a3a08a1678bacc76e04ca
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/test/CIR/CodeGenBuiltins/builtin_bit.cpp
Log Message:
-----------
[CIR][NFC] Update out-of-sync OGCG checks in test CIRGen/builtin_bit (#177189)
This patch updates various out-of-sync OGCG checks in the test file
`clang/test/CIR/CIRGen/builtin_bit.cpp`.
These checks are all related to the original clang CodeGen for the
bitwise rotate builtins. The OGCG patch #160259 inserts a new `urem`
instruction before calling the `llvm.fshr.*` intrinsic, which truncates
the rotate amount against the input's bit width. This breaks our OGCG
checks.
I have not yet dug deep enough into the rationale behind the OGCG patch.
The LLVM intrinsic `llvm.fshr.*` should already handle the truncation,
and the new `urem` instruction seems redundant in terms of semantic
correctness. Thus I choose not to hurry to also update relevant CIRGen
code to match OGCG behavior in this patch.
Commit: 7645bd38a7361f166c86600c4a71db405643198d
https://github.com/llvm/llvm-project/commit/7645bd38a7361f166c86600c4a71db405643198d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/performance/BUILD.gn
Log Message:
-----------
[gn build] Port 771517e9bfae
Commit: c3b4d94cd0eb08f818bf438b2dfbac38fe69e3ad
https://github.com/llvm/llvm-project/commit/c3b4d94cd0eb08f818bf438b2dfbac38fe69e3ad
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/tools/llvm-dwarfdump/BUILD.gn
Log Message:
-----------
[gn build] Port df063cbf1122
Commit: 5439df1e1c7d830ddf14986a24273ee71658c2fc
https://github.com/llvm/llvm-project/commit/5439df1e1c7d830ddf14986a24273ee71658c2fc
Author: Steven Perron <stevenperron at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
Log Message:
-----------
[HLSL] Improve HLSL resource method generation (#176806)
Refactor how HLSL resource methods are constructed in
HLSLBuiltinTypeDeclBuilder to be more robust and semantically correct.
- Switch to using Sema::BuildCallExpr and Sema::BuildCStyleCastExpr for
building builtin calls, ensuring proper type checking and AST
structure. This fixes issues with non-template resources like
SamplerState where AST errors aren't automatically resolved during
instantiation.
- Treat parameter placeholders as LValues in convertPlaceholder. This is
required for builtins with 'out' parameters (e.g., GetDimensions) now
that proper type checking via BuildCallExpr is performed.
- Fix a bug in CreateFromBinding methods where the counter handle was
assigned an incorrect handle type.
- Add assertions to ensure the correct field is accessed for handles,
preventing errors when implementing methods like Texture2D.Sample.
- Update AST tests to reflect changes in expression value categories
(VK_LValue) and the introduction of CStyleCastExpr.
Commit: 864c6cc9a62a4106fd09346385a43ead81a64a2f
https://github.com/llvm/llvm-project/commit/864c6cc9a62a4106fd09346385a43ead81a64a2f
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/CUDA/cuda-allocate.fir
M flang/test/Fir/CUDA/cuda-data-transfer.fir
Log Message:
-----------
[flang][cuda] Remove option allocationConversion from pass (#177037)
The pass option was meant to be used during migration. This is not
needed anymore.
Commit: d96cbf4a0224798dd514f03fa4f2301c4f879920
https://github.com/llvm/llvm-project/commit/d96cbf4a0224798dd514f03fa4f2301c4f879920
Author: Syadus Sefat <42645939+mssefat at users.noreply.github.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
Log Message:
-----------
[AMDGPU] Improve codegen for uniform f16<-->i32 conversions (#176833)
This patch improves codegen by chaining scalar operations for uniform
f16<-->i32 conversions where hardware supports the specific SALU
operations.
Added patterns in SOPInstructions.td to synthesize f16<-->i32
conversions via
intermediate f32 (f16-->f32-->i32 and i32-->f32-->f16).
Commit: 1d5e0408c9484cbd8b968a71bde12391ab83926c
https://github.com/llvm/llvm-project/commit/1d5e0408c9484cbd8b968a71bde12391ab83926c
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
M flang/test/Fir/CUDA/cuda-global-addr.mlir
M flang/test/Fir/CUDA/cuda-launch.fir
Log Message:
-----------
[flang][cuda] Remove CUFDeviceAddressOpConversion from CUFOpConversion (#177213)
The pattern has been moved to CUFOpConversionLate
Commit: 567fe2bbca27a934afd4a020f0d56e85edc7bfb2
https://github.com/llvm/llvm-project/commit/567fe2bbca27a934afd4a020f0d56e85edc7bfb2
Author: Daniel Thornburgh <mysterymath at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M lld/COFF/InputFiles.cpp
M llvm/include/llvm/LTO/LTO.h
M llvm/lib/LTO/LTO.cpp
M llvm/lib/LTO/ThinLTOCodeGenerator.cpp
M llvm/lib/Object/IRSymtab.cpp
Log Message:
-----------
[NFC][LTO] Move isPreservedName out of IRSymtab into LTO's Symbol as isLibcall (#177046)
This resolves the FIXME in IRSymtab and cleans up the semantics of the
IRSymtab. The list of preserved symbols really shouldn't be seen as a
property of the IR symbol table, since it's an LTO-specific concern, and
it's very tenuous to claim that this information is actually present in
the bitcode file to be exposed through its symbol table.
Instead, this PR moves this logic into LTO's view of the symbol, which
allows consumers to determine preserved-ness themselves. This was broken
out of #164916; this prevents that PR from introducing a circular
dependency, but it still seems like an independently good idea by virtue
of the above.
Commit: b30971c4bb3f0654fa4fbb242126376169ae66d0
https://github.com/llvm/llvm-project/commit/b30971c4bb3f0654fa4fbb242126376169ae66d0
Author: Teresa Johnson <tejohnson at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/test/Assembler/thinlto-summary.ll
A llvm/test/Bitcode/Inputs/thinlto-function-summary-callgraph-relbf.bc
M llvm/test/Bitcode/thinlto-function-summary-callgraph-relbf.ll
Log Message:
-----------
[ThinLTO] Remove unused relative block frequency support (#177215)
This removes most of the handling of the relative block frequency
support added in 2018 in c73cec84c99e5a63dca961fef67998a677c53a3c, which
was disabled by default and never utilized in the thin link as expected.
Support for reading old Bitcode containing the record is maintained as
required for backwards compatibility requirements, as is the support for
parsing old LLVM assembly containing that information. Tests ensure that
this backwards compatibility is maintained.
This came up in the context of redundant BFI/DT computations which
existed largely for the purpose of computing this information
and are being addressed in PR176646.
Commit: 9e4590f77244bb4ac35f38ab8beff6824428a019
https://github.com/llvm/llvm-project/commit/9e4590f77244bb4ac35f38ab8beff6824428a019
Author: cmtice <cmtice at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[LLVM] Fix Bazel build for llvm-dwarfdump. (#177229)
Fix is needed for https://github.com/llvm/llvm-project/pull/176725,
Commit: c6afb03658c9d62a156bfb7d809067020784e5ce
https://github.com/llvm/llvm-project/commit/c6afb03658c9d62a156bfb7d809067020784e5ce
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/utils/TableGen/DAGISelMatcher.cpp
Log Message:
-----------
[TableGen] Add MatchNumber to CheckChildSameMatcher::printImpl. NFC
Make the formatting more consistent with other child matchers.
This function is only used for debugging so it doesn't change
the output.
Commit: 49903c4e6445cba36f1a0231cc0ece4e4b96c91a
https://github.com/llvm/llvm-project/commit/49903c4e6445cba36f1a0231cc0ece4e4b96c91a
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCIfClauseLowering.cpp
M mlir/test/Dialect/OpenACC/acc-if-clause-lowering.mlir
Log Message:
-----------
[OpenACC][MLIR] clone reduction operands during ACCIfClauseLowering (#177196)
Clone the reduction operands into the compute region side. This also
fixes an issue where references to acc.reduction remain on the host
side.
Commit: 2ee329fc5188ce783a69aa87f1796ecc24bb8927
https://github.com/llvm/llvm-project/commit/2ee329fc5188ce783a69aa87f1796ecc24bb8927
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
Log Message:
-----------
[AMDGPU] Remove intrinsic declarations in a couple tests, NFC (#177218)
There is no need to explicitly declare intrinsic now. In this PR, we
only
remove intrinsic declarations in the two tests recently touched.
Commit: e779482ef5bc1439e1916af67b5e99327fbe2115
https://github.com/llvm/llvm-project/commit/e779482ef5bc1439e1916af67b5e99327fbe2115
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel][IR2Vec] Exclude ir2vec python bindings from main tool (#177230)
#176571 adds python bindings (using nanobind) in a subdirectory of the
ir2vec tool dir, but the bazel target just globs everything. Exclude the
bindings directory, which needs to be built in a special way.
Commit: 5f3643f9843ccfe377b929edcb6c238dda8492ca
https://github.com/llvm/llvm-project/commit/5f3643f9843ccfe377b929edcb6c238dda8492ca
Author: Kirill Vedernikov <kvedernikov at nvidia.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
Log Message:
-----------
[NFC][NVVM][NVPTX] Moved common code for tcgen05.mma to the base class (#176327)
This change moves common code parts for `tcgen05.mma` intrinsics to a
separate base class. It removes code duplication and increases
readability. There are no functional changes.
Commit: f3aa84c81039c4a501afe6a607c7dad387a8ab6f
https://github.com/llvm/llvm-project/commit/f3aa84c81039c4a501afe6a607c7dad387a8ab6f
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86AsmPrinter.h
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86WinEHUnwindV2.cpp
M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
M llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-epilogs.mir
M llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-instr.mir
Log Message:
-----------
[win][x64] Unwind v2: Avoid non-terminator instructions after terminator by using different psuedo for splitting frame infos (#177007)
After merging #159206 the new tests added would fail when verifying
machine code instructions with:
```
*** Bad machine code: Non-terminator instruction after the first terminator ***
- function: has_funclet
- basic block: %bb.4 call.block.4 (0x8000f837e8)
- instruction: SEH_SplitChained
First terminator was: RET64 $eax
*** Bad machine code: Non-terminator instruction after the first terminator ***
- function: has_funclet
- basic block: %bb.4 call.block.4 (0x8000f837e8)
- instruction: SEH_EndPrologue
First terminator was: RET64 $eax
```
This change removes `SEH_SplitChained` and replaces it with
`SEH_SplitChainedAtEndOfBlock` which acts as a marker to `X86AsmPrinter`
to emit the `.seh_splitchained` directive (and `.seh_endprolog`) when
the current block has finished.
Commit: 1843a7fe9f2d89cac9b4994adacf4edef5c36a4d
https://github.com/llvm/llvm-project/commit/1843a7fe9f2d89cac9b4994adacf4edef5c36a4d
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[NFCI][AMDGPU] Use X-macro to reduce boilerplate in `GCNSubtarget.h` (#176844)
`GCNSubtarget.h` contained a large amount of repetitive code following
the pattern `bool HasXXX = false;` for member declarations and `bool
hasXXX() const { return HasXXX; }` for getters. This boilerplate made
the file unnecessarily long and harder to maintain.
This patch introduces an X-macro pattern `GCN_SUBTARGET_HAS_FEATURE`
that consolidates 135 simple subtarget features into a single list. The
macro is expanded twice: once in the protected section to generate
member variable declarations, and once in the public section to generate
the corresponding getter methods. This reduces the file by approximately
600 lines while preserving the exact same API and functionality.
Features with complex getter logic or inconsistent naming conventions
are left as manual implementations for future improvement.
Ideally, these could be generated by TableGen using
`GET_SUBTARGETINFO_MACRO`, similar to the X86 backend. However,
`AMDGPU.td` has several issues that prevent direct adoption: duplicate
field names (e.g., `DumpCode` is set by both `FeatureDumpCode` and
`FeatureDumpCodeLower`), and inconsistent naming conventions where many
features don't have the `Has` prefix (e.g., `FlatAddressSpace`,
`GFX10Insts`, `FP64`). Fixing these issues would require renaming fields
in `AMDGPU.td` and updating all references, which is left for future
work.
Commit: 0e5ab0f4f412a30751bea9d83cb97e0d754bc032
https://github.com/llvm/llvm-project/commit/0e5ab0f4f412a30751bea9d83cb97e0d754bc032
Author: Jonathan Wakely <jwakely at redhat.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M compiler-rt/lib/asan/asan_fake_stack.cpp
Log Message:
-----------
[asan] Fix -Wformat warning for %zx with pointer argument (#177219)
Fixes #175045
Commit: b1907c109c95431ebf0bb6f128c3bbf3fb89b6de
https://github.com/llvm/llvm-project/commit/b1907c109c95431ebf0bb6f128c3bbf3fb89b6de
Author: Ravil Dorozhinskii <ravil.aviva.com at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma.mlir
M mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[ROCDL] Refactored MFMA ops in ODS; added constraints (#175775)
This PR improves the ROCDL MFMA intrinsics by making their operand and
result types explicit in the IR and by modeling immediate arguments
(immargs) as attributes rather than opaque operands.
This brings MFMA intrinsics in line with recent changes made to ROCDL
WMMA operations, where intrinsic signatures were clarified to avoid
treating them as an unstructured “blob of arguments”.
Commit: ee0fb4c395e18fbf70f663acc536050505a13661
https://github.com/llvm/llvm-project/commit/ee0fb4c395e18fbf70f663acc536050505a13661
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/test/MC/AMDGPU/gfx1250_asm_load_tr.s
Log Message:
-----------
[AMDGPU] Auto-generate checks for gfx1250_asm_load_tr.s, NFC (#177220)
Commit: 795d940254aa357cb5095ad776c04e72ced08b9d
https://github.com/llvm/llvm-project/commit/795d940254aa357cb5095ad776c04e72ced08b9d
Author: Augusto Noronha <anoronha at apple.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M lldb/source/API/CMakeLists.txt
Log Message:
-----------
[lldb][cmake] Fix standalone Xcode build header staging (#177033)
The LLDB standalone build using Xcode fails because the staging
directory custom command output is attached to multiple
liblldb-stage-header-* targets, but none of these targets depend on each
other. Xcode's new build system doesn't allow this.
This creates a new target `liblldb-header-staging-dir` that depends on
the staging directory creation, and makes all header staging targets
depend on it instead of directly depending on the directory in their
custom commands. This ensures all targets share a common dependency,
satisfying Xcode's build system requirements.
Commit: d64d3735ab06cd1304fb383543312c355c45eeb8
https://github.com/llvm/llvm-project/commit/d64d3735ab06cd1304fb383543312c355c45eeb8
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/phi-multi-same-nodes.ll
Log Message:
-----------
[SLP]Correctly handle vector nodes, coming from same incoming blocks in PHI nodes
If multiple nodes are generated from same PHI node for the same block,
still need to vectorize vector nodes, even if the value for the incoming block was already emitted.
Fixes #177124
Commit: fa4f7657a24baf21a2127652ae4f1c3ba800c24d
https://github.com/llvm/llvm-project/commit/fa4f7657a24baf21a2127652ae4f1c3ba800c24d
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
[AMDGPU] Further improve `AMDGPUSubtargetFeature` multiclass (#177077)
This PR extends the multiclass to support two additional parameters: one
for specifying whether an `AssemblerPredicate` should be generated, and
another for dependent `SubtargetFeatures`. This allows 15 more
definitions to be converted to use the multiclass.
Commit: 14fe4a89e4db1ed0119c855a49cbfe7531d60b4f
https://github.com/llvm/llvm-project/commit/14fe4a89e4db1ed0119c855a49cbfe7531d60b4f
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M lldb/include/lldb/Utility/UserID.h
Log Message:
-----------
[lldb] Remove unused nested class UserID::IDMatches (NFC) (#177211)
Commit: b5077a7712342eaf6d3d7aa14829040c1252965f
https://github.com/llvm/llvm-project/commit/b5077a7712342eaf6d3d7aa14829040c1252965f
Author: David Green <david.green at arm.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/sink-and-fold-illegal-shift.ll
M llvm/test/CodeGen/AArch64/aarch64-mops.ll
M llvm/test/CodeGen/AArch64/cpa-globalisel.ll
M llvm/test/CodeGen/AArch64/load-store-forwarding.ll
Log Message:
-----------
[AArch64][GlobalISel] Extend smaller than i32 gpr loads/stores in RegBankSelect. (#175810)
A i8 / i16 load and store is only legal for FPR registers. This patch extends
the types on i8/i16 G_LOADS and G_STORES to i32 using anyext / trunc, so that
selection can be simpler and does not need to handle illegal operations.
This can leave some anyext(trunc) operations that could be removed yet but
should be possible to optimize away.
Commit: 489e4ef760ac9b926a783a64afaaa90ba322b055
https://github.com/llvm/llvm-project/commit/489e4ef760ac9b926a783a64afaaa90ba322b055
Author: Steven Wu <stevenwu at apple.com>
Date: 2026-01-21 (Wed, 21 Jan 2026)
Changed paths:
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/CIR/CodeGenBuiltins/builtin_bit.cpp
M compiler-rt/lib/asan/asan_fake_stack.cpp
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/CUDA/cuda-allocate.fir
M flang/test/Fir/CUDA/cuda-data-transfer.fir
M flang/test/Fir/CUDA/cuda-global-addr.mlir
M flang/test/Fir/CUDA/cuda-launch.fir
M libc/shared/math.h
A libc/shared/math/log10.h
A libc/shared/math/log1p.h
A libc/shared/math/log2.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/log10.h
A libc/src/__support/math/log1p.h
A libc/src/__support/math/log2.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/log10.cpp
M libc/src/math/generic/log1p.cpp
M libc/src/math/generic/log2.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_math_test.cpp
M lld/COFF/InputFiles.cpp
M lldb/include/lldb/Utility/UserID.h
M lldb/source/API/CMakeLists.txt
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/include/llvm/LTO/LTO.h
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CAS/NamedValuesSchema.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/LTO/ThinLTOCodeGenerator.cpp
M llvm/lib/ObjCopy/DXContainer/DXContainerObjcopy.cpp
M llvm/lib/Object/IRSymtab.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86AsmPrinter.h
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86WinEHUnwindV2.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/Assembler/thinlto-summary.ll
A llvm/test/Bitcode/Inputs/thinlto-function-summary-callgraph-relbf.bc
M llvm/test/Bitcode/thinlto-function-summary-callgraph-relbf.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/sink-and-fold-illegal-shift.ll
M llvm/test/CodeGen/AArch64/aarch64-mops.ll
M llvm/test/CodeGen/AArch64/cpa-globalisel.ll
M llvm/test/CodeGen/AArch64/load-store-forwarding.ll
A llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
M llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-epilogs.mir
M llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-instr.mir
M llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/neon-dot-product.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_load_tr.s
A llvm/test/TableGen/invalid_typecast_assert.td
M llvm/test/Transforms/InstCombine/not.ll
A llvm/test/Transforms/SLPVectorizer/X86/phi-multi-same-nodes.ll
R llvm/test/tools/llvm-objcopy/DXContainer/copy-basic.test
A llvm/test/tools/llvm-objcopy/DXContainer/copy-basic.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/extract-section-basic.test
A llvm/test/tools/llvm-objcopy/DXContainer/extract-section-basic.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/extract-section-errs.test
A llvm/test/tools/llvm-objcopy/DXContainer/extract-section-errs.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/extract-section-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/extract-section-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/only-section-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/only-section-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/reading-errs.test
A llvm/test/tools/llvm-objcopy/DXContainer/reading-errs.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/remove-headers.test
A llvm/test/tools/llvm-objcopy/DXContainer/remove-headers.yaml
R llvm/test/tools/llvm-objcopy/DXContainer/remove-root-signature.test
A llvm/test/tools/llvm-objcopy/DXContainer/remove-root-signature.yaml
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/DAGISelMatcher.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/performance/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-dwarfdump/BUILD.gn
M llvm/utils/profcheck-xfail.txt
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCIfClauseLowering.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/test/Analysis/DataFlow/test-dead-code-analysis.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma.mlir
M mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma.mlir
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Dialect/OpenACC/acc-if-clause-lowering.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M openmp/device/include/Synchronization.h
M openmp/device/src/Synchronization.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
address review feedback
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/14fb596753fc...489e4ef760ac
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