[all-commits] [llvm/llvm-project] 5fec9f: [AMDGPU] Enable ISD::{FSIN, FCOS} custom lowering t...

[Frederik Harwath via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5fec9fb3cf76d23c065f157a0eff824fb09e543f
      https://github.com/llvm/llvm-project/commit/5fec9fb3cf76d23c065f157a0eff824fb09e543f
  Author: Frederik Harwath <frederik.harwath at amd.com>
  Date:   2026-01-20 (Tue, 20 Jan 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll

  Log Message:
  -----------
  [AMDGPU] Enable ISD::{FSIN,FCOS} custom lowering to work on v2f16 (#176382)

Currently ISD::FSIN and ISD::FCOS of type MVT::v2f16 are legalized by
first expanding and then using a custom lowering on the resulting f16
instructions. This ordering prevents using packed math variants of the
instructions introduced by the legalization (e.g. the multiplication) and
makes it difficult to deal with the resulting IR in peephole
optimizations (e.g. si-peephole-sdwa).

Change the legalization action for ISD::FSIN and ISD::FCOS of type
MTF::v2f16 to Custom and change the custom trig lowering to deal
with vectors.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications