[all-commits] [llvm/llvm-project] 0cdc1b: [SelectionDAG] Support integer types with multiple...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0cdc1b6dd4a870fc41d4b15ad97e0001882aba58
      https://github.com/llvm/llvm-project/commit/0cdc1b6dd4a870fc41d4b15ad97e0001882aba58
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-12-13 (Sat, 13 Dec 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/ARM/cttz.ll
    M llvm/test/CodeGen/NVPTX/i128.ll
    M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/idiv_large.ll
    M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
    M llvm/test/CodeGen/X86/bsf.ll
    M llvm/test/CodeGen/X86/bsr.ll
    M llvm/test/CodeGen/X86/ctlo.ll
    M llvm/test/CodeGen/X86/ctlz.ll
    M llvm/test/CodeGen/X86/cttz.ll
    M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
    M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
    M llvm/test/CodeGen/X86/scheduler-backtracking.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll

  Log Message:
  -----------
  [SelectionDAG] Support integer types with multiple registers in ComputePHILiveOutRegInfo. (#172081)

PHIs that are larger than a legal integer type are split into multiple
virtual registers that are numbered sequentially. We can propagate the
known bits for each of these registers individually.

Big endian is not supported yet because the register order needs to be
reversed.

Fixes #171671



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