[all-commits] [llvm/llvm-project] 02b4dd: [AArch64] Restrict TBI to ignore top 4 bits for Da...

[Alexander Richardson via All-commits]

  Branch: refs/heads/users/arichardson/spr/tablegen-improve-generated-comments-for-regclassbyhwmode-tables
  Home:   https://github.com/llvm/llvm-project
  Commit: 02b4dd04626c31f225db2bb8e9e0b82cddd28c25
      https://github.com/llvm/llvm-project/commit/02b4dd04626c31f225db2bb8e9e0b82cddd28c25
  Author: Amara Emerson <amara at apple.com>
  Date:   2025-12-10 (Wed, 10 Dec 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/tbi.ll

  Log Message:
  -----------
  [AArch64] Restrict TBI to ignore top 4 bits for Darwin targets.

In order to allow arm64 code to run on MTE environments, we need to make the
compiler only assume the top 4 bits can be ignored as MTE occupies the lower 4.

rdar://164645323


  Commit: 6dafa096f417378e7e7b5540fca14d8a0b4b4e59
      https://github.com/llvm/llvm-project/commit/6dafa096f417378e7e7b5540fca14d8a0b4b4e59
  Author: jimingham <jingham at apple.com>
  Date:   2025-12-10 (Wed, 10 Dec 2025)

  Changed paths:
    M lldb/source/Interpreter/CommandInterpreter.cpp
    M lldb/test/API/functionalities/breakpoint/breakpoint_command/TestRegexpBreakCommand.py
    M lldb/test/API/terminal/TestEditlineCompletions.py

  Log Message:
  -----------
  Add a _regexp-break-add and some more tests for the b alias. (#171236)

This commit leaves "b" aliased to the old _regexp-break for now. The two
variants are identical except that `_regexp-break` allows you to say:

`(lldb) b <unrecognized_input> 
`
which gets translated to:

`break set <unrecognized_input>
`

So switching people to `_regexp-break-add` would be a surprising
behavior change. It would be wrong for `_regexp_break-add` have one
branch that call `break set`, so to avoid surprise, I'll add the command
and let people who are playing with `break add` instead of `break set`
can set the alias to the new one by hand for now.


  Commit: 3abaed8086fae30726b1ffb6fbbad69b1d42a7d0
      https://github.com/llvm/llvm-project/commit/3abaed8086fae30726b1ffb6fbbad69b1d42a7d0
  Author: Alexander Richardson <alexrichardson at google.com>
  Date:   2025-12-10 (Wed, 10 Dec 2025)

  Changed paths:
    M llvm/test/TableGen/RegClassByHwModeErrors.td
    M llvm/utils/TableGen/Common/InfoByHwMode.cpp

  Log Message:
  -----------
  [TableGen] Replace reachable assertion with error in *ByHwMode

Having duplicate mode entries previously asserted (or silently replaced
the last value with a new one in release builds). Report an error with
a helpful message instead.

Pull Request: https://github.com/llvm/llvm-project/pull/171715


  Commit: c5470e0f1f51291ac2b59c27a8278494e9f67ebd
      https://github.com/llvm/llvm-project/commit/c5470e0f1f51291ac2b59c27a8278494e9f67ebd
  Author: Alexander Richardson <alexrichardson at google.com>
  Date:   2025-12-10 (Wed, 10 Dec 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td

  Log Message:
  -----------
  [RISC-V][MC] Fix tied operand register class mismatch in P-extension

I have a change to validate the operand classes emitted in the AsmParser
and that caused llvm/test/MC/RISCV/rv32p-valid.s to fail due to the rd_wb
register using a different register class from rd:
`PWADDA_H operand 1 register X6 is not a member of register class GPRPair`
This happens because tablegen's AsmMatcherEmitter emits code to literally
copy over the tied registers and does not feed them through the equivalent
of RISCVAsmParser::validateTargetOperandClass() which would allow adjusting
these operand classes.

Ideally we would handle this in tablegen (or at least add an error), but
the tied operand handling logic is rather complex and I don't understand
it yet. For now just update the rd register class to match rd_wb.

Pull Request: https://github.com/llvm/llvm-project/pull/171738


  Commit: 055bfc48edeeb451070f816f1a7bc154b1d49a41
      https://github.com/llvm/llvm-project/commit/055bfc48edeeb451070f816f1a7bc154b1d49a41
  Author: Alex Richardson <alexrichardson at google.com>
  Date:   2025-12-10 (Wed, 10 Dec 2025)

  Changed paths:
    M lldb/source/Interpreter/CommandInterpreter.cpp
    M lldb/test/API/functionalities/breakpoint/breakpoint_command/TestRegexpBreakCommand.py
    M lldb/test/API/terminal/TestEditlineCompletions.py
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
    M llvm/test/CodeGen/AArch64/tbi.ll
    M llvm/test/TableGen/RegClassByHwModeErrors.td
    M llvm/utils/TableGen/Common/InfoByHwMode.cpp

  Log Message:
  -----------
  clang-format

Created using spr 1.3.8-beta.1


Compare: https://github.com/llvm/llvm-project/compare/42e332e04c5a...055bfc48edee

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