[all-commits] [llvm/llvm-project] 7464b8: [AArch64][SVE] Add SubtargetFeature to disable low...

[Kinoshita Kotaro via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7464b860e240d76c45cdf0a648f68dbb73b27ea7
      https://github.com/llvm/llvm-project/commit/7464b860e240d76c45cdf0a648f68dbb73b27ea7
  Author: Kinoshita Kotaro <k.kotaro at fujitsu.com>
  Date:   2025-12-10 (Wed, 10 Dec 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Features.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64Processors.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll

  Log Message:
  -----------
  [AArch64][SVE] Add SubtargetFeature to disable lowering unpredicated loads/stores as LDR/STR (#170256)

PR #127837 changed the lowering for unpredicated loads/stores to use LDR/STR instead of LD1/ST1.
However, on some CPUs, such as A64FX, there is a performance difference between LD1/ST1 and LDR/STR.
As a result, the lowering introduced in #127837 can cause a performance regression on these targets.
This patch adds a SubtargetFeature `disable-unpredicated-ld-st-lower` to disable this lowering.
It is enabled for the A64FX target.



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