[all-commits] [llvm/llvm-project] 898963: [AArch64] Fix missing register definitions in homo...

Mon Dec 8 21:54:58 PST 2025

  Branch: refs/heads/users/arichardson/spr/main.tablegen-improve-error-message-for-bad-vtbyhwmode-in-registerbyhwmode
  Home:   https://github.com/llvm/llvm-project
  Commit: 898963b029619ee399393e49b547f3e80386d746
      https://github.com/llvm/llvm-project/commit/898963b029619ee399393e49b547f3e80386d746
  Author: Zhaoxuan Jiang <jiangzhaoxuan94 at gmail.com>
  Date:   2025-12-08 (Mon, 08 Dec 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
    A llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-tail-call.mir

  Log Message:
  -----------
  [AArch64] Fix missing register definitions in homogeneous epilog lowering (#171118)

The lowering for HOM_Epilog did not transfer explicit register defs from
the pseudo-instruction to the generated helper calls. MachineVerifier
would complain if a following tail call uses one of the restored CSRs.
This scenario occurs in code generated by the Swift compiler, where X20
is used to pass swiftself.

This patch fixes the issue by adding the missing defs back to the helper
call as implicit defs.

  Commit: f2ddc7b0be83b1c9b247f0c3d5dcce189568e5e9
      https://github.com/llvm/llvm-project/commit/f2ddc7b0be83b1c9b247f0c3d5dcce189568e5e9
  Author: Mircea Trofin <mtrofin at google.com>
  Date:   2025-12-08 (Mon, 08 Dec 2025)

  Changed paths:
    M llvm/test/Transforms/LowerTypeTests/import.ll

  Log Message:
  -----------
  [NFC] Run UTC --check-globals on LowerTypeTests/import.ll (#170755)

  Commit: 893479adcc03e8ce0ed5e0b550cae7d32724cd9a
      https://github.com/llvm/llvm-project/commit/893479adcc03e8ce0ed5e0b550cae7d32724cd9a
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2025-12-09 (Tue, 09 Dec 2025)

  Changed paths:
    M llvm/test/Transforms/LoopUnroll/RISCV/vector.ll

  Log Message:
  -----------
  [RISCV] Precommit test for unrolling loops with vector operands

  Commit: e5a1821f5b345d278a3fadee0a975dbd228f9a65
      https://github.com/llvm/llvm-project/commit/e5a1821f5b345d278a3fadee0a975dbd228f9a65
  Author: Wenju He <wenju.he at intel.com>
  Date:   2025-12-09 (Tue, 09 Dec 2025)

  Changed paths:
    M clang/include/clang/Basic/OpenCLExtensions.def
    M clang/test/SemaOpenCL/extension-version.cl

  Log Message:
  -----------
  [OpenCL] Add missing Intel extensions to OpenCLExtensions.def (#169875)

Add following extensions:
cl_intel_bfloat16_conversion
cl_intel_subgroup_buffer_prefetch
cl_intel_subgroup_local_block_io
cl_intel_subgroups_char
cl_intel_subgroups_long

This allows targets to expose these extensions via
getSupportedOpenCLOpts and ensures macros are defined when enabled.

  Commit: a0b6638c85065b6a098a9a4b1bc468652e8cddc5
      https://github.com/llvm/llvm-project/commit/a0b6638c85065b6a098a9a4b1bc468652e8cddc5
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2025-12-09 (Tue, 09 Dec 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/Transforms/LoopUnroll/RISCV/vector.ll

  Log Message:
  -----------
  [RISCV] Don't unroll vectorized loops with vector operands (#171089)

We have disabled unrolling for vectorized loops in #151525 but this
PR only checked the instruction type.

For some loops, there is no instruction with vector type but they
are still vector operations (just like the memset zero test in the
precommit test).

Here we check the operands as well to cover these cases.

  Commit: ba3208e19f7dcaf8c8a95f47f03c46a5b3acf57d
      https://github.com/llvm/llvm-project/commit/ba3208e19f7dcaf8c8a95f47f03c46a5b3acf57d
  Author: Owen Anderson <resistor at mac.com>
  Date:   2025-12-08 (Mon, 08 Dec 2025)

  Changed paths:
    M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

  Log Message:
  -----------
  [LLVM/CodeGen] Use the correct address space when building structor tables. (#171247)

No in-tree target exercises this, but it's needed for CHERI, and I
believe its correctness is verifiable by inspection.

Co-authored-by: Alex Richardson <alexrichardson at google.com>

  Commit: ce76c393ce749f854e51e1d32a1bb2e5e092e106
      https://github.com/llvm/llvm-project/commit/ce76c393ce749f854e51e1d32a1bb2e5e092e106
  Author: Mircea Trofin <mtrofin at google.com>
  Date:   2025-12-08 (Mon, 08 Dec 2025)

  Changed paths:
    M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-tail-call.mir

  Log Message:
  -----------
  Fix test outputting to test dir (#171255)

The test introduced in #171118 has `llc` inadvertently producing an
output into the same dir as the test file itself. Most build bots don't
clean up the local git repo, which is assumed to not be written by build
+ test, and patch on top (for build performance reasons), which means
the produced output from the aforementioned PR is treated as a test from
here onwards, by all bots. Since it's missing `RUN` lines, we get
errors, for example
 https://lab.llvm.org/buildbot/#/builders/108/builds/20674

This patch fixes the `llc` line and also removes the `.s`. This avoids
all bot maintainers go restart their bots. Then, the cleanup is removed
in #171256.

  Commit: 93c7ad188042bfade0af38754ab87426a17e059c
      https://github.com/llvm/llvm-project/commit/93c7ad188042bfade0af38754ab87426a17e059c
  Author: Mircea Trofin <mtrofin at google.com>
  Date:   2025-12-08 (Mon, 08 Dec 2025)

  Changed paths:
    M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
    M llvm/test/Transforms/LowerTypeTests/import.ll
    M llvm/utils/profcheck-xfail.txt

  Log Message:
  -----------
  [LTT] Bias branch weights as "expected" when lowering type tests with conditional (#170752)

We expect the type test to succeed.

  Commit: 0df8306479aba5a51971e9d358508ad8b65393ca
      https://github.com/llvm/llvm-project/commit/0df8306479aba5a51971e9d358508ad8b65393ca
  Author: Rajat Bajpai <rbajpai at nvidia.com>
  Date:   2025-12-09 (Tue, 09 Dec 2025)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsNVPTX.td
    M clang/include/clang/Basic/Cuda.h
    M clang/include/clang/Basic/OffloadArch.h
    M clang/lib/Basic/Cuda.cpp
    M clang/lib/Basic/OffloadArch.cpp
    M clang/lib/Basic/Targets/NVPTX.cpp
    M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
    M clang/test/Misc/target-invalid-cpu-note/nvptx.c

  Log Message:
  -----------
  [Clang][CUDA] Add support for SM_88, SM_110, and SM_110a architectures (#170258)

This patch adds support for new GPU architectures introduced in CUDA
13.0 in Clang:
- SM_88: Ampere architecture variant
- SM_110/SM_110a: Blackwell architecture variants

Additionally, this patch deprecates SM_101/SM_101a support for CUDA 13.0
and later versions. The SM_101 architecture is superseded by SM_110 and
is no longer supported by CUDA 13.0+ toolchain components.

  Commit: 773a6a9cc8b659c3790d430699e8a8b93ec27317
      https://github.com/llvm/llvm-project/commit/773a6a9cc8b659c3790d430699e8a8b93ec27317
  Author: Timm Bäder <tbaeder at redhat.com>
  Date:   2025-12-09 (Tue, 09 Dec 2025)

  Changed paths:
    M clang/lib/AST/ByteCode/Descriptor.cpp
    M clang/lib/AST/ByteCode/Descriptor.h
    M clang/lib/AST/ByteCode/Disasm.cpp
    M clang/lib/AST/ByteCode/EvaluationResult.cpp
    M clang/lib/AST/ByteCode/Interp.cpp
    M clang/lib/AST/ByteCode/Interp.h
    M clang/lib/AST/ByteCode/InterpBuiltin.cpp
    M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
    M clang/lib/AST/ByteCode/InterpBuiltinBitCast.h
    M clang/lib/AST/ByteCode/Pointer.cpp
    M clang/lib/AST/ByteCode/Pointer.h
    M clang/test/AST/ByteCode/const-eval.c

  Log Message:
  -----------
  Revert "[clang][bytecode] Allocate InitMaps via Program/InterpState allocators (#170272)"

This reverts commit 8fe38c4c9c71c7a86ecdba476ee5bae4c02c0dfe.

This breaks the clang-armv7-2stage build bot:
https://lab.llvm.org/buildbot/#/builders/79/builds/2531

  Commit: 9baf76a9f8603e8f5c40aec6a1b755c46d279e00
      https://github.com/llvm/llvm-project/commit/9baf76a9f8603e8f5c40aec6a1b755c46d279e00
  Author: Alexander Richardson <alexrichardson at google.com>
  Date:   2025-12-08 (Mon, 08 Dec 2025)

  Changed paths:
    M llvm/lib/MC/MCAsmStreamer.cpp
    M llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
    M llvm/test/CodeGen/Mips/llvm-ir/load.ll
    M llvm/test/CodeGen/Mips/llvm-ir/store.ll
    M llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
    M llvm/test/CodeGen/Mips/setcc-se.ll
    M llvm/test/MC/AMDGPU/buffer-op-swz-operand.s
    M llvm/test/MC/Disassembler/ARM/sub-sp-imm-thumb2.txt
    M llvm/test/MC/Lanai/conditional_inst.s
    M llvm/test/MC/Lanai/memory.s
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/asm-show-inst.ll.expected

  Log Message:
  -----------
  [MCAsmStreamer] Print register names in --show-inst mode

Passing the context to `Inst.dump_pretty()` allows printing symbolic
register names instead of `<MCOperand Reg:1234>` in the output.
I plan to use this in a future RVY test cases where we have register
class with the same name in assembly syntax, but different underlying
register enum values. Printing the name of the enum value makes it
easier to test that we selected the correct register.

Reviewed By: lenary

Pull Request: https://github.com/llvm/llvm-project/pull/171252

  Commit: 5079260ec73506e57f8cd8baf903595efca34c73
      https://github.com/llvm/llvm-project/commit/5079260ec73506e57f8cd8baf903595efca34c73
  Author: Alexander Richardson <alexrichardson at google.com>
  Date:   2025-12-08 (Mon, 08 Dec 2025)

  Changed paths:
    A llvm/test/TableGen/Common/RegClassByHwModeCommon.td
    M llvm/test/TableGen/RegClassByHwMode.td
    A llvm/test/TableGen/RegClassByHwModeErrors.td
    M llvm/utils/TableGen/Common/CodeGenInstAlias.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.h
    M llvm/utils/TableGen/Common/CodeGenTarget.cpp
    M llvm/utils/TableGen/Common/CodeGenTarget.h
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [TableGen] Slightly improve error location for a fatal error

I was hitting this error and the error location was pointing to the
register class definition instead of the incorrect InstAlias. Pass in
the InstAlias location to make it easier to debug.

Happens with `def : InstAlias<"foo", (Inst X0)>`, where `Inst` takes
a RegClassByHwMode operand that is not necessarily satisfied by
register X0. Similar problem with the CompressPat backend.

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/170790

  Commit: 0893fdbe5be8dada944444459578fea29d7f811f
      https://github.com/llvm/llvm-project/commit/0893fdbe5be8dada944444459578fea29d7f811f
  Author: Alexander Richardson <alexrichardson at google.com>
  Date:   2025-12-08 (Mon, 08 Dec 2025)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsNVPTX.td
    M clang/include/clang/Basic/Cuda.h
    M clang/include/clang/Basic/OffloadArch.h
    M clang/include/clang/Basic/OpenCLExtensions.def
    M clang/lib/AST/ByteCode/Descriptor.cpp
    M clang/lib/AST/ByteCode/Descriptor.h
    M clang/lib/AST/ByteCode/Disasm.cpp
    M clang/lib/AST/ByteCode/EvaluationResult.cpp
    M clang/lib/AST/ByteCode/Interp.cpp
    M clang/lib/AST/ByteCode/Interp.h
    M clang/lib/AST/ByteCode/InterpBuiltin.cpp
    M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
    M clang/lib/AST/ByteCode/InterpBuiltinBitCast.h
    M clang/lib/AST/ByteCode/Pointer.cpp
    M clang/lib/AST/ByteCode/Pointer.h
    M clang/lib/Basic/Cuda.cpp
    M clang/lib/Basic/OffloadArch.cpp
    M clang/lib/Basic/Targets/NVPTX.cpp
    M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
    M clang/test/AST/ByteCode/const-eval.c
    M clang/test/Misc/target-invalid-cpu-note/nvptx.c
    M clang/test/SemaOpenCL/extension-version.cl
    M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
    A llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-tail-call.mir
    M llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
    M llvm/test/Transforms/LowerTypeTests/import.ll
    M llvm/utils/profcheck-xfail.txt

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]

Compare: https://github.com/llvm/llvm-project/compare/0835d709475d...0893fdbe5be8

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