[all-commits] [llvm/llvm-project] 21559f: Constant pool load

[Guy David via All-commits]

  Branch: refs/heads/users/guy-david/aarch64-reduce-spilling
  Home:   https://github.com/llvm/llvm-project
  Commit: 21559f9ff47a788e21bae54bf37b09ce93771b60
      https://github.com/llvm/llvm-project/commit/21559f9ff47a788e21bae54bf37b09ce93771b60
  Author: Guy David <guyda96 at gmail.com>
  Date:   2025-12-07 (Sun, 07 Dec 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
    M llvm/test/CodeGen/AArch64/aarch64-avoid-illegal-extract-subvector.ll
    M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
    M llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll
    M llvm/test/CodeGen/AArch64/add-negative.ll
    M llvm/test/CodeGen/AArch64/addsub-constant-folding.ll
    M llvm/test/CodeGen/AArch64/alias_mask.ll
    M llvm/test/CodeGen/AArch64/alias_mask_nosve.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
    M llvm/test/CodeGen/AArch64/arm64-setcc-int-to-fp-combine.ll
    M llvm/test/CodeGen/AArch64/arm64-tbl.ll
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll
    M llvm/test/CodeGen/AArch64/bf16-shuffle.ll
    M llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
    M llvm/test/CodeGen/AArch64/cmp-select-sign.ll
    M llvm/test/CodeGen/AArch64/code-model-large.ll
    M llvm/test/CodeGen/AArch64/combine-sdiv.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat.ll
    M llvm/test/CodeGen/AArch64/concat-vector.ll
    M llvm/test/CodeGen/AArch64/dag-combine-mul-shl.ll
    M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
    M llvm/test/CodeGen/AArch64/extract-vector-elt.ll
    M llvm/test/CodeGen/AArch64/fdiv-const.ll
    M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
    M llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
    M llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll
    M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
    M llvm/test/CodeGen/AArch64/fptoi.ll
    M llvm/test/CodeGen/AArch64/fsh.ll
    M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
    M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
    M llvm/test/CodeGen/AArch64/insert-subvector.ll
    M llvm/test/CodeGen/AArch64/movi64_sve.ll
    M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
    M llvm/test/CodeGen/AArch64/neon-extracttruncate.ll
    M llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
    M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
    M llvm/test/CodeGen/AArch64/setcc-type-mismatch.ll
    M llvm/test/CodeGen/AArch64/shuffle-extend.ll
    M llvm/test/CodeGen/AArch64/shuffle-select.ll
    M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
    M llvm/test/CodeGen/AArch64/shuffles.ll
    M llvm/test/CodeGen/AArch64/shufflevector.ll
    M llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
    M llvm/test/CodeGen/AArch64/sitofp-to-tbl.ll
    M llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
    M llvm/test/CodeGen/AArch64/sve-index-const-step-vector.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
    M llvm/test/CodeGen/AArch64/tbl-loops.ll
    M llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
    M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
    M llvm/test/CodeGen/AArch64/vec-combine-compare-truncate-store.ll
    M llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
    M llvm/test/CodeGen/AArch64/vector-compress.ll
    M llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
    M llvm/test/CodeGen/AArch64/vector-gep.ll
    M llvm/test/CodeGen/AArch64/vselect-constants.ll
    M llvm/test/CodeGen/AArch64/vselect-ext.ll
    M llvm/test/CodeGen/AArch64/zext-shuffle.ll
    M llvm/test/CodeGen/AArch64/zext-to-tbl.ll

  Log Message:
  -----------
  Constant pool load


  Commit: 0258b45ac07a0b294995afb5f9a8395a8feaae43
      https://github.com/llvm/llvm-project/commit/0258b45ac07a0b294995afb5f9a8395a8feaae43
  Author: Guy David <guyda96 at gmail.com>
  Date:   2025-12-07 (Sun, 07 Dec 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td

  Log Message:
  -----------
  MVNI + FNEG


Compare: https://github.com/llvm/llvm-project/compare/21559f9ff47a%5E...0258b45ac07a

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