[all-commits] [llvm/llvm-project] df5a39: [AArch64][GlobalISel] Removed sqshl fallback occur...

[Joshua Rodriguez via All-commits]

  Branch: refs/heads/users/JoshdRod/shift-fallbacks/01-qshl-fallbacks
  Home:   https://github.com/llvm/llvm-project
  Commit: df5a3947dfe05400c5e5b640dda048af4eb85a7e
      https://github.com/llvm/llvm-project/commit/df5a3947dfe05400c5e5b640dda048af4eb85a7e
  Author: Josh Rodriguez <josh.rodriguez at arm.com>
  Date:   2025-12-04 (Thu, 04 Dec 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Removed sqshl fallback occurring for <1 x i64> operands

GISel now places sqshl operands on floating point registers. Generated code is slightly less efficient compared to SDAG.


  Commit: 71e4e0d66ec1eeb5c767188aa447c52247207029
      https://github.com/llvm/llvm-project/commit/71e4e0d66ec1eeb5c767188aa447c52247207029
  Author: Josh Rodriguez <josh.rodriguez at arm.com>
  Date:   2025-12-04 (Thu, 04 Dec 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Removed fallback for uqsh, uqrsh, and sqrsh with <1 x i64> operands

GISel now places operands for these intrinsics on floating point registers. Generated code is slightly less efficient compared to SDAG.


  Commit: 53c3c4bdf4c704a1d09915e643e30231a7211bc2
      https://github.com/llvm/llvm-project/commit/53c3c4bdf4c704a1d09915e643e30231a7211bc2
  Author: Josh Rodriguez <josh.rodriguez at arm.com>
  Date:   2025-12-04 (Thu, 04 Dec 2025)

  Changed paths:
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Updated arm64-vshift.ll to have correct fallback lines

Check lines were previously expecting some fallbacks which no longer happen. This update fixes that.


  Commit: 80ef01ce6cdb45ca3a5c9187758a752536e806f3
      https://github.com/llvm/llvm-project/commit/80ef01ce6cdb45ca3a5c9187758a752536e806f3
  Author: Josh Rodriguez <josh.rodriguez at arm.com>
  Date:   2025-12-04 (Thu, 04 Dec 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll
    M llvm/test/CodeGen/AArch64/neon-addlv.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Removed fallback for urshl/srshl intrinsics with <1 x i64> operands

GISel now places urshl/srshl operands on floating point registers. Generated code is slightly less efficient compare to SDAG.


  Commit: 7060138135143170161a24f9d3ef7ccbfc0ba393
      https://github.com/llvm/llvm-project/commit/7060138135143170161a24f9d3ef7ccbfc0ba393
  Author: Josh Rodriguez <josh.rodriguez at arm.com>
  Date:   2025-12-04 (Thu, 04 Dec 2025)

  Changed paths:
    M llvm/test/CodeGen/AArch64/arm64-int-neon.ll
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Updated test checks


Compare: https://github.com/llvm/llvm-project/compare/2d4d7e369c3a...706013813514

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