[all-commits] [llvm/llvm-project] 00c8e6: [AArch64] Add bitcasts for lowering saturating add...

[Lukacma via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 00c8e615e30a6f38698b7bb7e426f83abb8b5798
      https://github.com/llvm/llvm-project/commit/00c8e615e30a6f38698b7bb7e426f83abb8b5798
  Author: Lukacma <Marian.Lukac at arm.com>
  Date:   2025-12-03 (Wed, 03 Dec 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    A llvm/test/CodeGen/AArch64/arm64-int-neon.ll
    M llvm/test/CodeGen/AArch64/arm64-vmul.ll
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll

  Log Message:
  -----------
  [AArch64] Add bitcasts for lowering saturating add/sub and shift intrinsics.  (#161840)

This is followup patch to #157680 . In this patch, we are adding
explicit bitcasts to floating-point type when lowering saturating
add/sub and shift NEON scalar intrinsics using SelectionDAG, so they can
be picked up by patterns added in first part of this series. To do that,
we have to create new nodes for these intrinsics, which operate on
floating-point types and wrap them in bitcast nodes.



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