[all-commits] [llvm/llvm-project] 7cdb27: [NFC][AMDGPU] Refactor wave reduce test files (#17...
Fabian Ritter via All-commits
all-commits at lists.llvm.org
Wed Dec 3 02:38:47 PST 2025
Branch: refs/heads/users/felipepiovezan/spr/main.lldb-handle-backwards-branches-in-unwindassemblyinstemulation
Home: https://github.com/llvm/llvm-project
Commit: 7cdb27a4b3757879446596d6f042f87b5119c638
https://github.com/llvm/llvm-project/commit/7cdb27a4b3757879446596d6f042f87b5119c638
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2025-12-03 (Wed, 03 Dec 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
Log Message:
-----------
[NFC][AMDGPU] Refactor wave reduce test files (#170440)
Separate out float wave-reduce intrinsic tests from the overloaded call.
Moved float add/sub/min/max ops from:
`llvm.amdgcn.reduce.add/sub/min/max` to
`llvm.amdgcn.reduce.fadd/fsub/fmin/fmax`.
Commit: 2b725ab8bf08b0bde29910ec4fa1c610eaaffa63
https://github.com/llvm/llvm-project/commit/2b725ab8bf08b0bde29910ec4fa1c610eaaffa63
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-12-03 (Wed, 03 Dec 2025)
Changed paths:
M lldb/include/lldb/Core/Disassembler.h
M lldb/source/Core/Disassembler.cpp
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
Log Message:
-----------
[lldb] Add DisassemblerLLVMC::IsBarrier API (#169632)
This will allow the instruction emulation unwinder to reason about
instructions that prevent the subsequent instruction from executing.
Part of a sequence of PRs:
[lldb][NFCI] Rewrite UnwindAssemblyInstEmulation in terms of a CFG visit
#169630
[lldb][NFC] Rename forward_branch_offset to branch_offset in
UnwindAssemblyInstEmulation #169631
[lldb] Add DisassemblerLLVMC::IsBarrier API #169632
[lldb] Handle backwards branches in UnwindAssemblyInstEmulation #169633
commit-id:bb5df4aa
Commit: 9296223b28029095c1e734ba9373b9bcfc853d7b
https://github.com/llvm/llvm-project/commit/9296223b28029095c1e734ba9373b9bcfc853d7b
Author: mitchell <mitchell.xu2 at gmail.com>
Date: 2025-12-03 (Wed, 03 Dec 2025)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeMemberInitCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-member-init.ignorearrays.cpp
Log Message:
-----------
[clang-tidy] Fix `cppcoreguidelines-pro-type-member-init` check (#169832)
Closes [#169677](https://github.com/llvm/llvm-project/issues/169677)
---------
Co-authored-by: EugeneZelenko <eugene.zelenko at gmail.com>
Commit: 114ca6522e4ea425115adb778c39fd89745a6853
https://github.com/llvm/llvm-project/commit/114ca6522e4ea425115adb778c39fd89745a6853
Author: Shih-Po Hung <shihpo.hung at sifive.com>
Date: 2025-12-03 (Wed, 03 Dec 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Log Message:
-----------
[TTI] Use MemIntrinsicCostAttributes for getStridedOpCost (#170436)
- Following #168029. This is a step toward a unified interface for
masked/gather-scatter/strided/expand-compress cost modeling.
- Replace the ad-hoc parameter list with a single attributes object.
API change:
```
- InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr,
bool VariableMask, Align Alignment,
TTI::TargetCostKind CostKind,
const Instruction *I = nullptr);
+ InstructionCost getStridedMemoryOpCost(MemIntrinsicCostAttributes,
+ CostKind);
```
Notes:
- NFCI intended: callers populate MemIntrinsicCostAttributes with same
information as before.
Commit: 5ccf8c90d1e4020d5f9bc255fe521aa0763f2b2b
https://github.com/llvm/llvm-project/commit/5ccf8c90d1e4020d5f9bc255fe521aa0763f2b2b
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-12-03 (Wed, 03 Dec 2025)
Changed paths:
M flang/docs/Directives.md
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Parser/Fortran-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/canonicalize-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Lower/vectorlength.f90
M flang/test/Parser/compiler-directives.f90
Log Message:
-----------
[flang] implement VECTOR VECTORLENGTH directive (#170114)
This should match exactly the llvm attributes generated by classic
flang.
Commit: 8feb6762ba9fb83f8e13ef9486c3b743e1b5cfa7
https://github.com/llvm/llvm-project/commit/8feb6762ba9fb83f8e13ef9486c3b743e1b5cfa7
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-12-03 (Wed, 03 Dec 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
Log Message:
-----------
[AMDGPU] Take BUF instructions into account in mayAccessScratchThroughFlat (#170274)
BUF instructions can access the scratch address space, so
SIInsertWaitCnt needs to be able
to track the SCRATCH_WRITE_ACCESS event for such BUF instructions.
The release-vgprs.mir test had to be updated because BUF instructions
w/o a MMO are now
tracked as a SCRATCH_WRITE_ACCESS. I added a MMO that touches global to
keep the test result unchanged. I also added a couple of testcases with no MMO to test the corrected behavior.
Commit: 2697c8cb459c1705f6c3a60c908462ca099e657f
https://github.com/llvm/llvm-project/commit/2697c8cb459c1705f6c3a60c908462ca099e657f
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-12-03 (Wed, 03 Dec 2025)
Changed paths:
M llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
M llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
M llvm/unittests/Transforms/Utils/MemTransferLowering.cpp
Log Message:
-----------
[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowering (#169039)
So far, memcpy with known size, memcpy with unknown size, memmove with known
size, and memmove with unknown size have individual optimized loop lowering
implementations, while memset and memset.pattern use an unoptimized loop
lowering. This patch extracts the parts of the memcpy lowerings (for known and
unknown sizes) that generate the control flow for the loop expansion into an
`insertLoopExpansion` function. The `createMemCpyLoop(Unk|K)nownSize` functions
then only collect the necessary arguments for `insertLoopExpansion`, call it,
and fill the generated loop basic blocks.
The immediate benefit of this is that logic from the two memcpy lowerings is
deduplicated. Moreover, it enables follow-up patches that will use
`insertLoopExpansion` to optimize the memset and memset.pattern implementations
similarly to memcpy, since they can use the exact same control flow patterns.
The test changes are due to more consistent and useful basic block names in the
loop expansion and an improvement in basic block ordering: previously, the
basic block that determines if the residual loop is executed would be put at
the end of the function, now it is put before the residual loop body.
Otherwise, the generated code should be equivalent.
This patch doesn't affect memmove; deduplicating its logic would also be nice,
but to extract all CF generation from the memmove lowering,
`insertLoopExpansion` would need to be able to also create code that iterates
backwards over the argument buffers. That would make `insertLoopExpansion` a
lot more complex for a code path that's only used for memmove, so it's probably
not worth refactoring.
For SWDEV-543208.
Commit: e2d3e410e63b979624336a880adf3338cbadc145
https://github.com/llvm/llvm-project/commit/e2d3e410e63b979624336a880adf3338cbadc145
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-12-03 (Wed, 03 Dec 2025)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeMemberInitCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-member-init.ignorearrays.cpp
M flang/docs/Directives.md
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Parser/Fortran-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/canonicalize-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Lower/vectorlength.f90
M flang/test/Parser/compiler-directives.f90
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
M llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
M llvm/unittests/Transforms/Utils/MemTransferLowering.cpp
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/8e48ac826366...e2d3e410e63b
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