[all-commits] [llvm/llvm-project] cd86b2: [CodeGen] Add MO_LaneMask type and a new COPY_LANE...

Felipe de Azevedo Piovezan via All-commits all-commits at lists.llvm.org
Wed Dec 3 00:56:44 PST 2025 

  Branch: refs/heads/users/felipepiovezan/spr/lldb-handle-backwards-branches-in-unwindassemblyinstemulation
  Home:   https://github.com/llvm/llvm-project
  Commit: cd86b2ab32bb2c444fb48e41a40f43c80a7eaeae
      https://github.com/llvm/llvm-project/commit/cd86b2ab32bb2c444fb48e41a40f43c80a7eaeae
  Author: Vikash Gupta <Vikash.Gupta at amd.com>
  Date:   2025-12-03 (Wed, 03 Dec 2025)

  Changed paths:
    M llvm/docs/MIRLangRef.rst
    M llvm/include/llvm/CodeGen/MIR2Vec.h
    M llvm/include/llvm/CodeGen/MachineInstr.h
    M llvm/include/llvm/CodeGen/MachineInstrBuilder.h
    M llvm/include/llvm/CodeGen/MachineOperand.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/CodeGen/MIRParser/MILexer.cpp
    M llvm/lib/CodeGen/MIRParser/MILexer.h
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/lib/CodeGen/MIRPrinter.cpp
    M llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
    M llvm/lib/CodeGen/MachineOperand.cpp
    M llvm/lib/CodeGen/MachineStableHash.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-empty-lanemask.mir
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-lanemask.mir
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-lparen.mir
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-rparen.mir
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
    M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
    M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
    A llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask-invalid-lanemask.mir
    A llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask-missing-lanemask.mir
    M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
    M llvm/unittests/CodeGen/MachineOperandTest.cpp

  Log Message:
  -----------
  [CodeGen] Add MO_LaneMask type and a new COPY_LANEMASK instruction (#151944)

Introduce MO_LaneMask as new machine operand type. This can be used to
hold liveness infomation at sub-register granularity for register-type
operands. We also introduce a new COPY_LANEMASK instruction that uses
MO_lanemask operand to perform partial copy from source register
opernad.

One such use case of MO_LaneMask can be seen in #151123, where it can be
used to store live regUnits information corresponding to the source
register of the COPY instructions, later can be used during CopyPhysReg
expansion.


  Commit: c5ecdec9fb84e6865fe44f69e380afa1291c2adf
      https://github.com/llvm/llvm-project/commit/c5ecdec9fb84e6865fe44f69e380afa1291c2adf
  Author: Ebuka Ezike <yerimyah1 at gmail.com>
  Date:   2025-12-03 (Wed, 03 Dec 2025)

  Changed paths:
    M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
    M lldb/tools/lldb-dap/DAP.cpp
    M lldb/tools/lldb-dap/Protocol/ProtocolBase.h

  Log Message:
  -----------
  [lldb-dap] start all sent protocol message from number one. (#170378)

This aligns with the DAP
[specification](https://microsoft.github.io/debug-adapter-protocol//specification.html#Base_Protocol_ProtocolMessage)

Force it to be an error in test cases.


  Commit: 6638d59c972512d45da474c214abc67ec3cfe333
      https://github.com/llvm/llvm-project/commit/6638d59c972512d45da474c214abc67ec3cfe333
  Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
  Date:   2025-12-03 (Wed, 03 Dec 2025)

  Changed paths:
    M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
    M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.h

  Log Message:
  -----------
  [lldb][NFC] Rename forward_branch_offset to branch_offset in UnwindAssemblyInstEmulation (#169631)

This will reduce the diff in subsequent patches

Part of a sequence of PRs:
[lldb][NFCI] Rewrite UnwindAssemblyInstEmulation in terms of a CFG visit
#169630
[lldb][NFC] Rename forward_branch_offset to branch_offset in
UnwindAssemblyInstEmulation #169631
[lldb] Add DisassemblerLLVMC::IsBarrier API #169632
[lldb] Handle backwards branches in UnwindAssemblyInstEmulation #169633
commit-id:5e758a22


  Commit: 4b0a9759395f3e9cbefa9c194ca331f4d88003bf
      https://github.com/llvm/llvm-project/commit/4b0a9759395f3e9cbefa9c194ca331f4d88003bf
  Author: Hongyu Chen <xxs_chy at outlook.com>
  Date:   2025-12-03 (Wed, 03 Dec 2025)

  Changed paths:
    M clang/lib/CodeGen/Targets/AMDGPU.cpp
    M clang/lib/CodeGen/Targets/NVPTX.cpp
    M clang/lib/CodeGen/Targets/SPIR.cpp
    M clang/lib/Sema/SemaType.cpp
    M clang/test/CodeGenOpenCL/ptx-calls.cl
    M clang/test/CodeGenOpenCL/reflect.cl

  Log Message:
  -----------
  [OpenCL][NVPTX] Don't set calling convention for OpenCL kernel (#170170)

Fixes #154772
We previously set `ptx_kernel` for all kernels. But it's incorrect to
add `ptx_kernel` to the stub version of kernel introduced in #115821.
This patch copies the workaround of AMDGPU.


  Commit: 8b7a07a5f7e7b2a96417665f807cbf79a3161a76
      https://github.com/llvm/llvm-project/commit/8b7a07a5f7e7b2a96417665f807cbf79a3161a76
  Author: Ebuka Ezike <yerimyah1 at gmail.com>
  Date:   2025-12-03 (Wed, 03 Dec 2025)

  Changed paths:
    M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusNameParser.cpp
    M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp

  Log Message:
  -----------
  [lldb]  Fix abi_tag parsing for operator<< and operator-named tags (#170224)

The parser now correctly handles:
- abi_tags attached to operator<<: `operator<<[abi:SOMETAG]`
- abi_tags with "operator" as the tag name: `func[abi:operator]`


  Commit: 8e48ac826366f47684fc07cf829ba5be2a0b0c78
      https://github.com/llvm/llvm-project/commit/8e48ac826366f47684fc07cf829ba5be2a0b0c78
  Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
  Date:   2025-12-03 (Wed, 03 Dec 2025)

  Changed paths:
    M clang/lib/CodeGen/Targets/AMDGPU.cpp
    M clang/lib/CodeGen/Targets/NVPTX.cpp
    M clang/lib/CodeGen/Targets/SPIR.cpp
    M clang/lib/Sema/SemaType.cpp
    M clang/test/CodeGenOpenCL/ptx-calls.cl
    M clang/test/CodeGenOpenCL/reflect.cl
    M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
    M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusNameParser.cpp
    M lldb/tools/lldb-dap/DAP.cpp
    M lldb/tools/lldb-dap/Protocol/ProtocolBase.h
    M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
    M llvm/docs/MIRLangRef.rst
    M llvm/include/llvm/CodeGen/MIR2Vec.h
    M llvm/include/llvm/CodeGen/MachineInstr.h
    M llvm/include/llvm/CodeGen/MachineInstrBuilder.h
    M llvm/include/llvm/CodeGen/MachineOperand.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/CodeGen/MIRParser/MILexer.cpp
    M llvm/lib/CodeGen/MIRParser/MILexer.h
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/lib/CodeGen/MIRPrinter.cpp
    M llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
    M llvm/lib/CodeGen/MachineOperand.cpp
    M llvm/lib/CodeGen/MachineStableHash.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-empty-lanemask.mir
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-lanemask.mir
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-lparen.mir
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-rparen.mir
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
    M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
    M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
    A llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask-invalid-lanemask.mir
    A llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask-missing-lanemask.mir
    M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
    M llvm/unittests/CodeGen/MachineOperandTest.cpp

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]


  Commit: 8e2f8722457516ef45ff34bd1c6a2d77bbc74e07
      https://github.com/llvm/llvm-project/commit/8e2f8722457516ef45ff34bd1c6a2d77bbc74e07
  Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
  Date:   2025-12-03 (Wed, 03 Dec 2025)

  Changed paths:
    M clang/lib/CodeGen/Targets/AMDGPU.cpp
    M clang/lib/CodeGen/Targets/NVPTX.cpp
    M clang/lib/CodeGen/Targets/SPIR.cpp
    M clang/lib/Sema/SemaType.cpp
    M clang/test/CodeGenOpenCL/ptx-calls.cl
    M clang/test/CodeGenOpenCL/reflect.cl
    M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
    M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusNameParser.cpp
    M lldb/tools/lldb-dap/DAP.cpp
    M lldb/tools/lldb-dap/Protocol/ProtocolBase.h
    M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
    M llvm/docs/MIRLangRef.rst
    M llvm/include/llvm/CodeGen/MIR2Vec.h
    M llvm/include/llvm/CodeGen/MachineInstr.h
    M llvm/include/llvm/CodeGen/MachineInstrBuilder.h
    M llvm/include/llvm/CodeGen/MachineOperand.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/CodeGen/MIRParser/MILexer.cpp
    M llvm/lib/CodeGen/MIRParser/MILexer.h
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/lib/CodeGen/MIRPrinter.cpp
    M llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
    M llvm/lib/CodeGen/MachineOperand.cpp
    M llvm/lib/CodeGen/MachineStableHash.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-empty-lanemask.mir
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-lanemask.mir
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-lparen.mir
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-rparen.mir
    A llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
    M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
    M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
    A llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask-invalid-lanemask.mir
    A llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask-missing-lanemask.mir
    M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
    M llvm/unittests/CodeGen/MachineOperandTest.cpp

  Log Message:
  -----------
  rebased

Created using spr 1.3.7


Compare: https://github.com/llvm/llvm-project/compare/d5ef331e8eac...8e2f87224575

To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications

More information about the All-commits mailing list