[all-commits] [llvm/llvm-project] 76cb98: [RISCV] Sources of vmerge shouldn't overlap V0 (#1...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 76cb98442b280bf9b5862f0bec3a56c2cc37d70f
      https://github.com/llvm/llvm-project/commit/76cb98442b280bf9b5862f0bec3a56c2cc37d70f
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2025-12-03 (Wed, 03 Dec 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir
    M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
    M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
    M llvm/test/CodeGen/RISCV/rvv/pr88576.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
    M llvm/test/CodeGen/RISCV/rvv/vl-optimizer-subreg-assert.mir
    M llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir

  Log Message:
  -----------
  [RISCV] Sources of vmerge shouldn't overlap V0 (#170070)

According to the spec:

> A vector register cannot be used to provide source operands with more
> than one EEW for a single instruction. A mask register source is
> considered to have EEW=1 for this constraint.

There must be a mask `V0` in `vmerge` variants so the sources should
use register classes without `V0`.

This fixes #169905.

Co-authored-by: Luke Lau <luke at igalia.com>



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