[all-commits] [llvm/llvm-project] 5dad4b: Pre commit test: Add <6 x 32-bit> test cases for i...

[Juan Manuel Martinez Caamaño via All-commits]

  Branch: refs/heads/users/jmmartinez/fix/extract_insert_vector_dynelt_with_O0
  Home:   https://github.com/llvm/llvm-project
  Commit: 5dad4b1b9fd03ee2daa7beea78c68d5829e804d8
      https://github.com/llvm/llvm-project/commit/5dad4b1b9fd03ee2daa7beea78c68d5829e804d8
  Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
  Date:   2025-12-02 (Tue, 02 Dec 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll

  Log Message:
  -----------
  Pre commit test: Add <6 x 32-bit> test cases for insert/extract element with a dynamic index


  Commit: 4d04e2e012d61f596cd4dc510aca9401bf4ee8a8
      https://github.com/llvm/llvm-project/commit/4d04e2e012d61f596cd4dc510aca9401bf4ee8a8
  Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
  Date:   2025-12-02 (Tue, 02 Dec 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll

  Log Message:
  -----------
  Add llc -O0 line that triggers instruction selection failure


  Commit: 93d6942afefbe4a6443460c10d666dab0af0b18e
      https://github.com/llvm/llvm-project/commit/93d6942afefbe4a6443460c10d666dab0af0b18e
  Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
  Date:   2025-12-02 (Tue, 02 Dec 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.h
    M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll

  Log Message:
  -----------
  [AMDGCN][SDAG] Expand (INSERT|EXTRACT)_VECTOR_ELT for dynamic indices even with -O0

Before this patch, insertelement/extractelement with dynamic indices would
fail to select with -O0 for vector types that do not map to a
SI_INDIRECT_SRC/DST pattern.

To solve this issue, we allow this expansion with -O0 by hoisting the
code that does the expansion outside of the second `switch` statement in
`SITargetLowering::PerformDAGCombine` and into the first `switch`.


Compare: https://github.com/llvm/llvm-project/compare/5dad4b1b9fd0%5E...93d6942afefb

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