[all-commits] [llvm/llvm-project] 75aa01: Revert "LangRef: Clarify llvm.minnum and llvm.maxn...
Steven Wu via All-commits
all-commits at lists.llvm.org
Sun Nov 30 20:24:31 PST 2025
Branch: refs/heads/users/cachemeifyoucan/sprcas-temporarily-skip-tests-on-old-windows-version
Home: https://github.com/llvm/llvm-project
Commit: 75aa01b89553bf4213a3b0e83829b6d0689941b9
https://github.com/llvm/llvm-project/commit/75aa01b89553bf4213a3b0e83829b6d0689941b9
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-12-01 (Mon, 01 Dec 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/ISDOpcodes.h
Log Message:
-----------
Revert "LangRef: Clarify llvm.minnum and llvm.maxnum about sNaN and signed zero (#112852)" (#168838)
This reverts commit 363b05944f9212511ee6811d0eb1af841c177226.
This is a follow up of #166912. Sorry for not noticing the change at the
beginning, but I disagree with both sNaN and signed zero semantics
change.
I have 3 justifications:
- llvm.minnum and llvm.maxnum are common intrinsics, we cannot change
the definition just because "some architectures" support the changed
semantic. For example, X86 min/max instructions neither distinguish sNaN
nor signed zero. We have to add couples of extra instructions to match
with the new definition, which makes the intrinsics less efficient. But
efficient is not the reason for the objection. I object because such
cost is unnecessary;
- As the example ``minnum(fadd(sNaN, -0.0), 1.0)`` shows, minnum/maxnum
themself cannot guarantee consistent result if multiple FP arithmetic
operations involved. It makes the sacrifice of performance totally
unnecessary. `Behavior of Floating-Point NaN values` notes all NaNs can
be treated as quiet NaNs unless using Constrained Floating-Point
Intrinsics. So the cost is only worth for constrained minnum/maxnum ones
if we want to define them;
- Signed zero handling is unnecessary either, because even the C
functions don't require it. If any other front ends require, they can
use the existing fminnum_ieee/fmaxnum_ieee or define new intrinsics;
Fixes: https://github.com/llvm/llvm-project/issues/138303 and
https://github.com/llvm/llvm-project/issues/169122
Commit: e110abc3c65bb33f738738a9fa6e0f5b602ed97f
https://github.com/llvm/llvm-project/commit/e110abc3c65bb33f738738a9fa6e0f5b602ed97f
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-12-01 (Mon, 01 Dec 2025)
Changed paths:
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/test/Dialect/Affine/loop-coalescing.mlir
Log Message:
-----------
[mlir][affine] Use iter argument replace init when delete loop in the coalesceLoops function (#169514)
Fix https://github.com/llvm/llvm-project/issues/169483 by using iter
argument replace init when delete loop in the coalesceLoops function.
Commit: 2e21bb815d527ebbe4d53f0396d1e40aae9e2146
https://github.com/llvm/llvm-project/commit/2e21bb815d527ebbe4d53f0396d1e40aae9e2146
Author: fennecJ <hwahwa649 at gmail.com>
Date: 2025-12-01 (Mon, 01 Dec 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll
Log Message:
-----------
[RISCV][ISelLowering] Use Zicond for FP selects on Zfinx/Zdinx (#169299)
### Summary
This patch let RISCVTargetLowering::lowerSELECT to lower some
floating-point select operations through an integer zicond select when:
* Zicond is available, and
* FP values live in GPRs (Zfinx/Zdinx), and
* Select condition is an integer type.
In that scenario there is no extra cost for GPR <-> "FP GPR" moves, so
we can implement FP selects with a CZERO-based sequence instead of a
branch.
For example, for
```c
float foo(int cond, float x) {
return (cond != 0) ? x : 0.0f;
}
```
the current lowering produces:
```asm
foo:
mv a2, a0
li a0, 0
beqz a2, .LBB0_2
.LBB0_1:
mv a0, a1
.LBB0_2:
ret
```
With this patch, when targeting rv64ima_zicond_zfinx we instead get:
```asm
foo:
czero.nez a2, zero, a0
czero.eqz a0, a1, a0
or a0, a2, a0
ret
```
The existing branch-based lowering is preserved for:
* targets without Zicond
* targets where FP registers are separate (+f, +d without zfinx/zdinx)
### Testing
Adds llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll to cover:
* RV64 Zfinx/Zicond vs Zfinx without Zicond
* RV64 Zdinx/Zicond vs Zdinx without Zicond
* RV32 Zfinx/Zicond vs Zfinx without Zicond
Also adds baseline RV32F/RV64F/RV64D cases to ensure we still use
branches when FP registers are separate.
The tests check that:
* With Zicond + Zfinx/Zdinx, FP select lowers to a CZERO+OR sequence
with no conditional branches.
* Without Zicond (or without Zfinx/Zdinx), we still get branch-based
code and no czero.* instructions.
Commit: 7494f3df14e5d401b73f2f8ccbd811f3556c5be5
https://github.com/llvm/llvm-project/commit/7494f3df14e5d401b73f2f8ccbd811f3556c5be5
Author: Aadesh Premkumar <aadesh.premkumar at multicorewareinc.com>
Date: 2025-11-30 (Sun, 30 Nov 2025)
Changed paths:
M llvm/docs/SPIRVUsage.rst
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
A llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_integers.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_int4/negative.ll
M llvm/test/CodeGen/SPIRV/extensions/both-allowed-disallowed-extension-error.ll
M llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
M llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll
M llvm/test/CodeGen/SPIRV/extensions/unused-but-allowed-SPV_INTEL_arbitrary_precision_integers.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/bitreverse_small_type.ll
M llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
Log Message:
-----------
[SPIRV] Added support for extension SPV_ALTERA_arbitrary_precision_fixed_point and name change of SPV_INTEL_arbitrary_precision_integers to SPV_ALTERA_arbitrary_precision_integers (#136085)
--Added support for extension SPV_ALTERA_arbitrary_precision_fixed_point
--Added test files for extension
SPV_ALTERA_arbitrary_precision_fixed_point
Commit: 6369279a0c4ca1a008241f171657c1db83cfe026
https://github.com/llvm/llvm-project/commit/6369279a0c4ca1a008241f171657c1db83cfe026
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-12-01 (Mon, 01 Dec 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/ISDOpcodes.h
Log Message:
-----------
Revert "Revert "LangRef: Clarify llvm.minnum and llvm.maxnum about sNaN and signed zero (#112852)"" (#170067)
Reverts llvm/llvm-project#168838
Justification is confused and this did not receive adequate discussion,
particularly during a holiday week
Commit: e2181400d70857bc5a212a4053d5d7940c84acaf
https://github.com/llvm/llvm-project/commit/e2181400d70857bc5a212a4053d5d7940c84acaf
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2025-12-01 (Mon, 01 Dec 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
Log Message:
-----------
[RISCV][llvm] Correct shamt in P extension EXTRACT_VECTOR_ELT lowering (#169823)
During operation legalization, element type should have been turn into
XLenVT which makes the SHL a no-op. We need to use exact vector element
type instead.
Commit: 095badfe264aaf96dce6cb303e436c7448bdeaac
https://github.com/llvm/llvm-project/commit/095badfe264aaf96dce6cb303e436c7448bdeaac
Author: Steven Wu <stevenwu at apple.com>
Date: 2025-12-01 (Mon, 01 Dec 2025)
Changed paths:
M llvm/docs/SPIRVUsage.rst
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
A llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_integers.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_int4/negative.ll
M llvm/test/CodeGen/SPIRV/extensions/both-allowed-disallowed-extension-error.ll
M llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
M llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll
M llvm/test/CodeGen/SPIRV/extensions/unused-but-allowed-SPV_INTEL_arbitrary_precision_integers.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/bitreverse_small_type.ll
M llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
M llvm/unittests/CAS/CASTestConfig.h
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/test/Dialect/Affine/loop-coalescing.mlir
Log Message:
-----------
actually fix windows build
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/602639c56fcd...095badfe264a
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