[all-commits] [llvm/llvm-project] 9bae84: [RegAlloc] Relax the split constrain on MBB prolog...

Luo Yuanke via All-commits all-commits at lists.llvm.org
Fri Nov 28 15:27:41 PST 2025


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9bae84b01718e53495abf50958abc86ea45f16bb
      https://github.com/llvm/llvm-project/commit/9bae84b01718e53495abf50958abc86ea45f16bb
  Author: Luo Yuanke <lyk_03 at hotmail.com>
  Date:   2025-11-29 (Sat, 29 Nov 2025)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/lib/CodeGen/SplitKit.cpp
    M llvm/lib/CodeGen/SplitKit.h
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
    M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
    M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
    A llvm/test/CodeGen/AMDGPU/spill-before-exec2.mir
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll

  Log Message:
  -----------
  [RegAlloc] Relax the split constrain on MBB prolog (#168259)

https://reviews.llvm.org/D52052 is to prevent register split on the MBB
which have prolog instructions defining the exec register (or mask register
that activate the threads of a warp in GPU). The constrain seems too
strict, because 1) If the split is allowed, it may fit the free live range
of a physical register, and no spill will happen; 2) The register class of
register that is under splitting may not be the same to the register that
is defined in prolog, so there is no interference with the register being
defined in prolog. 
The current code has another small issue. The MBB->getFirstNonDebugInstr()
just skip debug instructions, but SA->getFirstSplitPoint(Number) would skip
label and phi instructions. This cause some MBB with label instruction
being taken as prolog.
This patch is to relax the split constrain on MMB with prolog by checking
if the register defined in prolog has the common register class with the
register being split. It allow the split if the register defined in prolog
is physical register or there is no common register class.

---------

Co-authored-by: Yuanke Luo <ykluo at birentech.com>



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