[all-commits] [llvm/llvm-project] 7b94dd: [VPLan] Reduce duplication in VPHeaderPHIRecipe::c...
Sergei Barannikov via All-commits
all-commits at lists.llvm.org
Thu Nov 27 21:38:59 PST 2025
Branch: refs/heads/users/s.barannikov/decoder-operands-7-arm
Home: https://github.com/llvm/llvm-project
Commit: 7b94dd336e25b18e05b3b1f20360df81e4900ffb
https://github.com/llvm/llvm-project/commit/7b94dd336e25b18e05b3b1f20360df81e4900ffb
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPLan] Reduce duplication in VPHeaderPHIRecipe::classof. (NFCI)
Implement VPHeaderPHIRecipe::classof(const VPValue *V) in terms of the
variant taking VPRecipeBase.
Reduces some duplication, split off from
https://github.com/llvm/llvm-project/pull/141431.
Commit: c32c1d0d21cedb8017914eb6951bea4cf1fb10f9
https://github.com/llvm/llvm-project/commit/c32c1d0d21cedb8017914eb6951bea4cf1fb10f9
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/lib/sanitizer_common/symbolizer/CMakeLists.txt
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
M offload/test/lit.site.cfg.in
M openmp/CMakeLists.txt
M openmp/cmake/OpenMPTesting.cmake
M runtimes/CMakeLists.txt
Log Message:
-----------
[Runtimes] Default build must use its own output dirs (#168266)
Post-commit fix of #164794 reported at
https://github.com/llvm/llvm-project/pull/164794#issuecomment-3536253493
`LLVM_LIBRARY_OUTPUT_INTDIR` and `LLVM_RUNTIME_OUTPUT_INTDIR` is used by
`AddLLVM.cmake` as output directories. Unless we are in a
bootstrapping-build, It must not point to directories found by
`find_package(LLVM)` which may be read-only directories. MLIR for
instance sets thesese variables to its own build output
directory, so should the runtimes.
Commit: bdcaa0001a5081737b12b9ec0c284fe06002a97c
https://github.com/llvm/llvm-project/commit/bdcaa0001a5081737b12b9ec0c284fe06002a97c
Author: Philip Ginsbach-Chen <ginsbach at github.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64PerfectShuffle.h
M llvm/test/CodeGen/AArch64/arm64-trn.ll
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
M llvm/test/CodeGen/AArch64/vldn_shuffle.ll
Log Message:
-----------
[AArch64] match TRN starting from undef elements (#167955)
When the first element of a trn mask is undef, the `isTRNMask` function
assumes `WhichResult = 1`. That has a 50% chance of being wrong, so we
fail to match some valid trn1/trn2.
This patch introduces a more precise test to determine the correct value
of `WhichResult`, based on corresponding code in the `isZIPMask` and
`isUZPMask` functions.
- This change is based on #89578. I'd like to follow it up with a
further change along the lines of #167235.
Commit: dce60025c1ae5c6c00885b49e496b29dffc03c8b
https://github.com/llvm/llvm-project/commit/dce60025c1ae5c6c00885b49e496b29dffc03c8b
Author: Hendrik Hübner <117831077+HendrikHuebner at users.noreply.github.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/include/clang/Basic/Builtins.h
M clang/lib/Basic/Builtins.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
Log Message:
-----------
[Clang][Codegen] Move floating point math intrinsic check to separate function [NFC] (#168198)
This PR moves the code that checks whether an LLVM intrinsic should be
generated instead of a call to floating point math functions to a
separate function. This simplifies `EmitBuiltinExpr` in `CGBuiltin.cpp`
and will allow us to reuse the logic in ClangIR.
Commit: 655662e94e969ee1bb3c17ea036335d7865f0462
https://github.com/llvm/llvm-project/commit/655662e94e969ee1bb3c17ea036335d7865f0462
Author: BogdanDragosV <dragos-valentin.bogdan at intel.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M mlir/include/mlir/IR/Properties.td
Log Message:
-----------
[MLIR][ODS] Fully qualify namespace for mlir::Attribute in ODS generated code (#168536)
ODS generate code can be included and used outside of the `mlir`
namespace and so references to symbols in the mlir namespace
must be fully qualified.
Commit: 6fc48de4ffe23508b3936c5480e46a5c0af02fec
https://github.com/llvm/llvm-project/commit/6fc48de4ffe23508b3936c5480e46a5c0af02fec
Author: Simon Wallis <simon.wallis2 at arm.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
M llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-writeback.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-zero-dependency.s
Log Message:
-----------
[AArch64] Update zero latency instructions in Neoverse scheduling tables (#165690)
NeoverseZeroMove was introduced for Neoverse-V2 and was added to V3 and
V3AE.
Use NeoverseZeroMove for Neoverse-V1, N2, N3 in the same way, including
these instructions:
MOV Xd|Wd, #0|XZR|WZR
For all the above Neoverse targets, the following instructions are also
decoded as not utilizing the scheduling and execution resources of the
machine:
MOV Wd,Wn
MOV Xd,Xn
For Neoverse-N3 only, these instructions also have zero latency
FMOV Dd, Dn
FMOV Sd, Sn
MOV Vd, Vn (vector)
MOV Zd.D, Zn.D
PTRUE
PFALSE
Commit: 68d2ce8e74cb2428d5c6299176f471753151d356
https://github.com/llvm/llvm-project/commit/68d2ce8e74cb2428d5c6299176f471753151d356
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/Banerjee.ll
M llvm/test/Analysis/DependenceAnalysis/Coupled.ll
M llvm/test/Analysis/DependenceAnalysis/DifferentOffsets.ll
M llvm/test/Analysis/DependenceAnalysis/Invariant.ll
M llvm/test/Analysis/DependenceAnalysis/NonCanonicalizedSubscript.ll
M llvm/test/Analysis/DependenceAnalysis/PR51512.ll
M llvm/test/Analysis/DependenceAnalysis/Propagating.ll
M llvm/test/Analysis/DependenceAnalysis/SameSDLoops.ll
M llvm/test/Analysis/DependenceAnalysis/Separability.ll
M llvm/test/Analysis/DependenceAnalysis/StrongSIV.ll
M llvm/test/Transforms/LoopFusion/pr164082.ll
M llvm/test/Transforms/LoopInterchange/legality-check.ll
M llvm/test/Transforms/LoopInterchange/outer-dependency-lte.ll
M llvm/test/Transforms/LoopUnrollAndJam/dependencies_multidims.ll
Log Message:
-----------
[DA] Replace delinearization for fixed size array (#161822)
This patch replaces the delinearization function used in DA, switching
from one that depends on type information in GEPs to one that does not.
There are three types of changes in regression tests: improvements,
degradations, and degradations but the related features will be
removed. Since there were very few cases that are classified into the
second category, I believe the impact of this change should be
practically insignificant.
Commit: a2ddb020d76cdb1c5708cf3dadd2c46866202707
https://github.com/llvm/llvm-project/commit/a2ddb020d76cdb1c5708cf3dadd2c46866202707
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
A llvm/test/Transforms/LoopInterchange/loopnest-with-outer-btc0.ll
M llvm/test/Transforms/LoopInterchange/pr43326.ll
M llvm/test/Transforms/LoopInterchange/pr57148.ll
A llvm/test/Transforms/LoopInterchange/zero-btc.ll
Log Message:
-----------
[LoopInterchange] Don't consider loops with BTC=0 (#167113)
Do not consider loops with a zero backedge taken count as candidates for
interchange. This seems like a sensible thing because it suggests the loop
doesn't execute and there is no point in interchanging. As a bonus, this
seems to avoid triggering an assert about phis and their uses from source
code, so this is a partial fix for #163954 but it needs more work to properly
fix that.
Commit: 7fe35641672b6431134e99af658bd79fd438da54
https://github.com/llvm/llvm-project/commit/7fe35641672b6431134e99af658bd79fd438da54
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/Headers/llvm_libc_wrappers/assert.h
M clang/lib/Headers/llvm_libc_wrappers/ctype.h
M clang/lib/Headers/llvm_libc_wrappers/inttypes.h
R clang/lib/Headers/llvm_libc_wrappers/llvm-libc-decls/README.txt
M clang/lib/Headers/llvm_libc_wrappers/stdio.h
M clang/lib/Headers/llvm_libc_wrappers/stdlib.h
M clang/lib/Headers/llvm_libc_wrappers/string.h
M clang/lib/Headers/llvm_libc_wrappers/time.h
M libc/cmake/modules/LLVMLibCHeaderRules.cmake
M libc/docs/dev/header_generation.rst
R libc/utils/hdrgen/hdrgen/gpu_headers.py
M libc/utils/hdrgen/hdrgen/yaml_to_classes.py
Log Message:
-----------
[Clang] Gut the libc wrapper headers and simplify (#168438)
Summary:
These were originally intended to represent the functions that are
present on the GPU as to be provided by the LLVM libc implementation.
The original plan was that LLVM libc would report which functions were
supported and then the offload interface would mark those as supported.
The problem is that these wrapper headers are very difficult to make
work given the various libc extensions everyone does so they were
extremely fragile.
OpenMP already declares all functions used inside of a target region as
implicitly host / device, while these headers weren't even used for CUDA
/ HIP yet anyway. The only things we need to define right now are the
stdio FILE types. If we want to make this work for CUDA we'd need to
define these manually, but we're a ways off and that's way easier
because they do proper overloading.
Commit: 9eee396c58d2e24beb93c460141170def328776d
https://github.com/llvm/llvm-project/commit/9eee396c58d2e24beb93c460141170def328776d
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M flang/lib/Optimizer/Builder/Runtime/Character.cpp
Log Message:
-----------
[flang] "Almost NFC" changes to fir::runtime::genCharCompare() (#168563)
As part of investigating a related issue, I made the following changes
to fir::runtime::genCharCompare():
- Renamed a variable
- Added an error check for the same kind of input args
- Updated another error check to use the same error found elsewhere in
this source file
Commit: 5da0445420015d859f71431a2c76f5b0cf78cbad
https://github.com/llvm/llvm-project/commit/5da0445420015d859f71431a2c76f5b0cf78cbad
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Consolidate shouldOptimizeForSize and remove unused BFI/PSI. NFC (#168697)
#158690 plans on passing BFI as a lazy lambda to avoid computing
BlockFrequencyInfo when not needed.
In preparation for that, this PR removes BFI and PSI from some
constructors that aren't used. It also consolidates the two calls to
llvm::shouldOptimizeForSize so that the result is computed once and
passed where needed.
This also renames OptForSize in LoopVectorizationLegality to clarify
that it's to prevent runtime SCEV checks, see
https://reviews.llvm.org/D68082
Commit: 7b8eee6b2b10ce88a24521aa0e91193cf7203c95
https://github.com/llvm/llvm-project/commit/7b8eee6b2b10ce88a24521aa0e91193cf7203c95
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
A llvm/test/CodeGen/RISCV/sincos-expansion.ll
Log Message:
-----------
[RISCV][test] Add sincos-expansion.ll test case
Commit: 2fc42c7163142d74e2e8ce5549f5d0142fccd89f
https://github.com/llvm/llvm-project/commit/2fc42c7163142d74e2e8ce5549f5d0142fccd89f
Author: Nathan Gauër <brioche at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CodeGenHLSL/semantics/SV_Position.ps.hlsl
A clang/test/CodeGenHLSL/semantics/semantic-struct-2-output.hlsl
A clang/test/CodeGenHLSL/semantics/semantic.array.output.hlsl
A clang/test/CodeGenHLSL/semantics/semantic.struct.output.hlsl
M clang/test/CodeGenHLSL/sret_output.hlsl
M clang/test/SemaHLSL/Availability/attr-availability-compute.hlsl
M clang/test/SemaHLSL/Availability/attr-availability-mesh.hlsl
M clang/test/SemaHLSL/Availability/attr-availability-pixel.hlsl
M clang/test/SemaHLSL/Availability/avail-diag-default-compute.hlsl
M clang/test/SemaHLSL/Availability/avail-diag-default-lib.hlsl
M clang/test/SemaHLSL/Availability/avail-diag-relaxed-compute.hlsl
M clang/test/SemaHLSL/Availability/avail-diag-relaxed-lib.hlsl
M clang/test/SemaHLSL/Availability/avail-diag-strict-compute.hlsl
M clang/test/SemaHLSL/Availability/avail-diag-strict-lib.hlsl
A clang/test/SemaHLSL/Semantics/missing-vs.hlsl
M clang/test/SemaHLSL/Semantics/position.ps.hlsl
M clang/test/SemaHLSL/Semantics/position.ps.struct.hlsl
M clang/test/SemaHLSL/Semantics/position.ps.struct.reuse.hlsl
M clang/test/SemaHLSL/Semantics/position.vs.hlsl
M clang/test/SemaHLSL/WaveBuiltinAvailability.hlsl
M clang/test/SemaHLSL/num_threads.hlsl
M clang/test/SemaHLSL/shader_type_attr.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
Log Message:
-----------
[HLSL] Add initial support for output semantics (#168095)
This commits adds the first part of the output semantics. It only
considers return values (and sret), but does not handle `inout` or `out`
parameters yet.
Those missing bits will reuse the same code, but will require additional
testing & some fixups, so planning on adding them separately.
Commit: 48dca1e929f5ef4ffbd4d291ce8bd9ab03c23fed
https://github.com/llvm/llvm-project/commit/48dca1e929f5ef4ffbd4d291ce8bd9ab03c23fed
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/include/clang/AST/StmtOpenACC.h
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
A clang/test/CIR/CodeGenOpenACC/atomic-capture.cpp
M clang/test/CIR/CodeGenOpenACC/openacc-not-implemented.cpp
Log Message:
-----------
[OpenACC][CIR] Implement 'atomic capture' lowering (#168422)
The 'atomic capture' variant of the `atomic` construct accepts either a
single statement, or a compound statement containing two statements.
Each of the statements it accepts meet a form of the previous
read/write/update forms, or is a combination of two.
The IR node for atomic capture takes two separate other acc.atomics,
plus a terminator.
This patch implements all of the lowering for these.
Note: This gets the postfix-increment/decrement wrong, but the effort
to do so is enough that I believe we can do that in a followup patch, so
I'll be doing so in the next patch.
Commit: ad31e11ab6d719d803708169a981a49b347c4d82
https://github.com/llvm/llvm-project/commit/ad31e11ab6d719d803708169a981a49b347c4d82
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/include/__ranges/iota_view.h
M libcxx/test/std/ranges/range.factories/range.iota.view/indices.pass.cpp
M libcxx/test/std/ranges/range.factories/range.iota.view/iterator/member_typedefs.compile.pass.cpp
Log Message:
-----------
[libc++] Make views::iota aware of __int128 (#167869)
Fixes #167991
Commit: a7ba8dcad76476478100c228a31d9c48391b1e03
https://github.com/llvm/llvm-project/commit/a7ba8dcad76476478100c228a31d9c48391b1e03
Author: mitchell <mitchell.xu2 at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/mpi/buffer-deref.rst
M clang-tools-extra/docs/clang-tidy/checks/mpi/type-mismatch.rst
M clang-tools-extra/docs/clang-tidy/checks/objc/forbidden-subclassing.rst
M clang-tools-extra/docs/clang-tidy/checks/objc/nsdate-formatter.rst
M clang-tools-extra/docs/clang-tidy/checks/objc/property-declaration.rst
M clang-tools-extra/docs/clang-tidy/checks/performance/no-int-to-ptr.rst
M clang-tools-extra/docs/clang-tidy/checks/performance/noexcept-swap.rst
M clang-tools-extra/docs/clang-tidy/checks/performance/unnecessary-copy-initialization.rst
M clang-tools-extra/docs/clang-tidy/checks/portability/simd-intrinsics.rst
M clang-tools-extra/docs/clang-tidy/checks/portability/std-allocator-const.rst
M clang-tools-extra/docs/clang-tidy/checks/portability/template-virtual-member-function.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/container-contains.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/container-data-pointer.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/convert-member-functions-to-static.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/delete-null-pointer.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/else-after-return.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/function-cognitive-complexity.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/make-member-function-const.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/math-missing-parentheses.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/named-parameter.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/operators-representation.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/redundant-casting.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/redundant-control-flow.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/redundant-string-cstr.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/reference-to-constructed-temporary.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/simplify-boolean-expr.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/string-compare.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/suspicious-call-argument.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/uppercase-literal-suffix.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/use-anyofallof.rst
Log Message:
-----------
[clang-tidy][docs][NFC] Enforce 80 characters limit (4/4) (#168049)
Fix documentation in `mpi`, `objc`, `openmp`, `performance`,
`portability`, `readability` and `zircon`.
This is part of the codebase cleanup described in
https://github.com/llvm/llvm-project/issues/167098
Commit: 93a1327deaef7abd5c2bf5caf4c4ef40d34460f6
https://github.com/llvm/llvm-project/commit/93a1327deaef7abd5c2bf5caf4c4ef40d34460f6
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M lldb/test/API/lang/cpp/libcxx-internals-recognizer/TestLibcxxInternalsRecognizer.py
Log Message:
-----------
[lldb] Skip TestLibcxxInternalsRecognizer on asan + MacOS
Unfortunately, in this configuration, the bots are forced to use the
system libcxx, which is too old for what this test is verifying.
In the future, we should re-enable building libcxx with asan on MacOS.
Commit: 1723a5137cba77cc1aace84d392b2ecd501e1069
https://github.com/llvm/llvm-project/commit/1723a5137cba77cc1aace84d392b2ecd501e1069
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
Log Message:
-----------
[mlir][tensor] Drop unused AffineExpr variable (NFC) (#168651)
Commit: c62fc065b4c10370c1aa68cad6f5fa980b640136
https://github.com/llvm/llvm-project/commit/c62fc065b4c10370c1aa68cad6f5fa980b640136
Author: Jake Egan <Jake.egan at ibm.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M compiler-rt/lib/asan/CMakeLists.txt
A compiler-rt/lib/asan/asan_aix.cpp
M compiler-rt/lib/asan/asan_posix.cpp
M compiler-rt/lib/asan/scripts/asan_symbolize.py
Log Message:
-----------
[asan] Implement address sanitizer on AIX: platform support (#139587)
Adds some general changes for supporting asan on AIX.
Issue: #138916
Commit: 71e3de8a7f1c0fc71302ac84c826f34fa324ee1c
https://github.com/llvm/llvm-project/commit/71e3de8a7f1c0fc71302ac84c826f34fa324ee1c
Author: Simone Pellegrini <simone.pellegrini at arm.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorization/linalg-ops-with-patterns.mlir
Log Message:
-----------
[mlir][vector] Missing indices on vectorization of 1-d reduction to 1-ranked memref (#166959)
Vectorization of a 1-d reduction where the output variable is a 1-ranked
memref can generate an invalid `vector.transfer_write` with no indices
for the memref, e.g.:
vector.transfer_write"(%vec, %buff) <{...}> : (vector<f32>,
memref<1xf32>) -> ()
This patch solves the problem by providing the expected amount of
indices (i.e. matching the rank of the memref).
Commit: b11b7b333ddb90db42dfd2d5003e3a51c3a7c38a
https://github.com/llvm/llvm-project/commit/b11b7b333ddb90db42dfd2d5003e3a51c3a7c38a
Author: Endre Fülöp <endre.fulop at sigmatechnology.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/BlockInCriticalSectionChecker.cpp
M clang/test/Analysis/block-in-critical-section.cpp
Log Message:
-----------
[clang][analyzer] Add defer_lock_t modelling to BlockInCriticalSectionChecker (#168338)
Fixes #166573
---------
Co-authored-by: Donát Nagy <donat.nagy at ericsson.com>
Co-authored-by: Alan Li <me at alanli.org>
Commit: b79a665f7170fbb631b13175ec747ccfd779bf9e
https://github.com/llvm/llvm-project/commit/b79a665f7170fbb631b13175ec747ccfd779bf9e
Author: LU-JOHN <John.Lu at amd.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
Log Message:
-----------
[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE. (#168546)
Remove leftover implicit operands from SI_SPILL/SI_RESTORE.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 86a82f27ee8cb7477c25561bc5697a6a6a8ff21d
https://github.com/llvm/llvm-project/commit/86a82f27ee8cb7477c25561bc5697a6a6a8ff21d
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M mlir/CMakeLists.txt
M mlir/examples/standalone/python/CMakeLists.txt
M mlir/python/CMakeLists.txt
Log Message:
-----------
[MLIR][Python] make sure stubs get installed with LLVM_DISTRIBUTION_COMPONENTS (#168407)
Fixes https://github.com/llvm/llvm-project/issues/168393. Also adds
top-level `MLIR_PYTHON_STUBGEN_ENABLED` CMake option.
Commit: 9cd40da328ca4ee4018dae42f071e5a1540e359f
https://github.com/llvm/llvm-project/commit/9cd40da328ca4ee4018dae42f071e5a1540e359f
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M flang/test/Lower/assignment.f90
M flang/test/Lower/assumed-shape-callee.f90
M flang/test/Lower/assumed-shape-caller.f90
M flang/test/Lower/big-integer-parameter.f90
M flang/test/Lower/c-interoperability.f90
M flang/test/Lower/call-copy-in-out.f90
M flang/test/Lower/charconvert.f90
M flang/test/Lower/control-flow.f90
M flang/test/Lower/default-initialization.f90
M flang/test/Lower/derived-allocatable-components.f90
M flang/test/Lower/derived-type-descriptor.f90
M flang/test/Lower/derived-types.f90
M flang/test/Lower/dispatch.f90
M flang/test/Lower/do_concurrent_delayed_locality.f90
M flang/test/Lower/do_concurrent_reduce.f90
M flang/test/Lower/do_loop.f90
M flang/test/Lower/dummy-argument-contiguous.f90
M flang/test/Lower/dummy-procedure-character.f90
M flang/test/Lower/dummy-procedure.f90
M flang/test/Lower/equivalence-1.f90
M flang/test/Lower/equivalence-2.f90
M flang/test/Lower/explicit-interface-results.f90
M flang/test/Lower/host-associated.f90
Log Message:
-----------
[flang][NFC] Strip trailing whitespace from tests (7 of N)
Only some fortran source files in flang/test/Lower have been modified.
The other files in the directory will be cleaned up in subsequent
commits
Commit: 7a3923676fecb0dc8d2d728310e84949dabb511a
https://github.com/llvm/llvm-project/commit/7a3923676fecb0dc8d2d728310e84949dabb511a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/Darwin/interface_symbols_darwin.cpp
Log Message:
-----------
[ASan] Fix interface_symbols_darwin.cpp on internal shell
This test turned out to not actually be that interested. There was just a
subshell usage that needed replacing with readfile, and then the test just
works.
Reviewers: fmayer, DanBlackwell, ndrewh
Reviewed By: ndrewh
Pull Request: https://github.com/llvm/llvm-project/pull/168654
Commit: c2b4e481a0504cbb50e83098d2634b063be6b5c9
https://github.com/llvm/llvm-project/commit/c2b4e481a0504cbb50e83098d2634b063be6b5c9
Author: Wael Yehia <wmyehia2001 at yahoo.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/tools/lto/lto.cpp
Log Message:
-----------
[libLTO] add thinlto caching flags to libLTO (#168567)
On AIX, the linker's release cadence is once per year and it doesn't
backport non-critical fixes to previous releases.
We would like to get thinLTO caching accessible for current customers,
so this PR adds the cache flags as cl::opt options.
Commit: 30e5f76d73fda77becb2010012b5cb090cc78c65
https://github.com/llvm/llvm-project/commit/30e5f76d73fda77becb2010012b5cb090cc78c65
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/include/llvm/DebugInfo/DWARF/DWARFContext.h
M llvm/include/llvm/Object/OffloadBinary.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/SeedCollector.h
M llvm/lib/Object/RecordStreamer.cpp
Log Message:
-----------
[llvm] Construct iterator_range with the conversion constructor (NFC) (#168674)
This patch simplifies iterator_range construction with the conversion
constructor.
Commit: 19129ea34388a923fcc9f5e7222ee238adfca0c6
https://github.com/llvm/llvm-project/commit/19129ea34388a923fcc9f5e7222ee238adfca0c6
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/include/llvm/Bitcode/BitcodeConvenience.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/PrintInstructionCount.h
M llvm/lib/CAS/OnDiskCAS.cpp
M llvm/lib/CAS/OnDiskGraphDB.cpp
M llvm/lib/ObjectYAML/MinidumpEmitter.cpp
M llvm/lib/Support/BalancedPartitioning.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
M llvm/tools/llvm-xray/xray-extract.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
[llvm] Use llvm::size (NFC) (#168675)
Note that llvm::size only works on types that allow std::distance in
O(1).
Commit: 139f726c84bc2c5144d10a79dd8f31e17ce7e03b
https://github.com/llvm/llvm-project/commit/139f726c84bc2c5144d10a79dd8f31e17ce7e03b
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/include/llvm/TableGen/CodeGenHelpers.h
M llvm/utils/TableGen/InstrInfoEmitter.cpp
Log Message:
-----------
[NFC][TableGen] Add IfGuardEmitter and adopt it in InstrInfoEmitter (#168616)
Add a RAII `IfGuardEmitter` to insert simple #if guards and adopt it in
InstrInfoEmitter.
Commit: 4703195c8de047f102214495e39ae80aad152e15
https://github.com/llvm/llvm-project/commit/4703195c8de047f102214495e39ae80aad152e15
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
Log Message:
-----------
[NFC][LLVM] Namespace cleanup in SLPVectorizer (#168623)
- Remove file local functions out of `llvm` or anonymous namespace and
make them static.
- Use namespace qualifier to define `BoUpSLP` class and several template
specializations.
Commit: 4f3d68a16e7ed8838b18b527192f515971209548
https://github.com/llvm/llvm-project/commit/4f3d68a16e7ed8838b18b527192f515971209548
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCParser/MCAsmParserExtension.h
M llvm/include/llvm/MC/MCWin64EH.h
M llvm/include/llvm/MC/MCWinEH.h
M llvm/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp
M llvm/lib/MC/MCNullStreamer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/COFFAsmParser.cpp
M llvm/lib/MC/MCParser/COFFMasmParser.cpp
M llvm/lib/MC/MCParser/DarwinAsmParser.cpp
M llvm/lib/MC/MCParser/ELFAsmParser.cpp
M llvm/lib/MC/MCParser/GOFFAsmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCParser/WasmAsmParser.cpp
M llvm/lib/MC/MCParser/XCOFFAsmParser.cpp
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/MC/MCWinEH.cpp
Log Message:
-----------
[NFC][MC] Namespace cleanup in MC (#168627)
- Add declarations of various `MCAsmParserExtension` creation functions
to MCAsmParserExtension.h and use namespace qualifiers to define these
and some other functions.
- Add end of namespace comments.
- Fix indentation of `MCNullStreamer` class.
- Remove namespace surrounding code in MCWinEH.cpp and use "using
namespace" instead.
Commit: 93d759ce5a63cf74882087bad020825764043381
https://github.com/llvm/llvm-project/commit/93d759ce5a63cf74882087bad020825764043381
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/test/SemaCXX/wmissing-noreturn-suggestion.cpp
Log Message:
-----------
[Clang] suppress -Wmissing-noreturn for virtual methods with throw-only bodies (#167523)
Fixes #167247
---
This PR addresses a case where Clang emitted `-Wmissing-noreturn` for
virtual methods whose body consists of a `throw` expression
```cpp
struct Base {
virtual void foo() {
throw std::runtime_error("error");
}
};
```
Commit: 435384583830ded8c3c9bc332a7f361de2d29346
https://github.com/llvm/llvm-project/commit/435384583830ded8c3c9bc332a7f361de2d29346
Author: Joshua Rodriguez <josh.rodriguez at arm.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/docs/GlobalISel/GenericOpcode.rst
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
M llvm/test/CodeGen/AArch64/arm64-vhadd.ll
M llvm/test/CodeGen/AArch64/freeze.ll
M llvm/test/CodeGen/AArch64/trunc-avg-fold.ll
M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
M llvm/test/TableGen/get-named-operand-idx.td
M llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
M llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
Log Message:
-----------
[AArch64][GlobalISel] Added support for hadd family of intrinsics (#163985)
GlobalISel now selects hadd family of intrinsics, without falling back
to SDAG.
Commit: 80d327e84606a99fd2c0b3f6ddb37f32ed89b997
https://github.com/llvm/llvm-project/commit/80d327e84606a99fd2c0b3f6ddb37f32ed89b997
Author: Fateme Hosseini <quic_fhossein at quicinc.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/Hexagon.h
M llvm/lib/Target/Hexagon/HexagonCallingConv.td
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
M llvm/lib/Target/Hexagon/HexagonSubtarget.h
A llvm/test/CodeGen/Hexagon/bfloat.ll
A llvm/test/CodeGen/Hexagon/bfloat_vec.ll
Log Message:
-----------
[Hexagon] Enable soft bf16 in hexagon (#167924)
This patch adds:
1. Support to recognize bf16 type in the frontend and isel/abi support
for scalar bf16 programs
Limitations: fp_to_bf16 is being generated with a tablegen pattern
instead of lowering via expansion. This is because we do not have
support for fcanonincalize instruction which should prevent an SNaN
being converted to an infinity due to truncation.
2. Vector codegen support for bf16
Patch By: Fateme Hosseini
Co-authored-by: Muntasir Mallick <quic_mallick at quicinc.com>
Co-authored-by: Muntasir Mallick <mallick at qti.qualcomm.com>
Co-authored-by: Kaushik Kulkarni <quic_kauskulk at quicinc.com>
Commit: f3d8a5cf5bc058328004bd0905ab4974f09fc131
https://github.com/llvm/llvm-project/commit/f3d8a5cf5bc058328004bd0905ab4974f09fc131
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Analysis/InstructionPrecedenceTracking.cpp
Log Message:
-----------
[IPT] Remove ipt.NumInstScanned statistic (#168515)
The NumInstScanned statistic is non-determinstic across multiple
identical invocations of LLVM, and leads to noise when trying to diff
LLVM statistics with e.g. ./utils/tdiff.py in llvm-test-suite.
My understanding is that it's non-deterministic because the users of
IPT's hasSpecialInstructions/isPreceededBySpecialInstruction API aren't
deterministic themselves.
This PR removes it and fixes #157598. This is just a small
quality-of-life improvement for the ./utils/tdiff.py workflow, but happy
to leave the statistic in if others are using it.
Commit: 9c2bbfe4a46e2d58294b6bb3e3a3584ade6a3304
https://github.com/llvm/llvm-project/commit/9c2bbfe4a46e2d58294b6bb3e3a3584ade6a3304
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
A llvm/test/CodeGen/X86/pr168594.ll
Log Message:
-----------
[X86] X86ISelDAGToDAG - don't let ADD/SUB(X,1) -> SUB/ADD(X,-1) constant fold (#168726)
This late into lowering we don't have a good way to handle constant build_vector lowering
Fixes #168594
Commit: c9e22d3751299fe31eeefbfb646bef7a78bcde8a
https://github.com/llvm/llvm-project/commit/c9e22d3751299fe31eeefbfb646bef7a78bcde8a
Author: Charles Zablit <c_zablit at apple.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M lldb/tools/driver/Driver.cpp
Log Message:
-----------
[lldb][windows] add color to the Python.dll not found error (#168718)
Make the `Python.dll not found` error message stand out more by using
the `llvm::WithColor::error()` method.
---
### Example
#### Before
<img width="782" height="431" alt="Screenshot 2025-11-19 at 15 50 22"
src="https://github.com/user-attachments/assets/93960c50-cbf2-41f7-aba3-2f2a8af916cc"
/>
#### After
<img width="780" height="430" alt="Screenshot 2025-11-19 at 15 54 28"
src="https://github.com/user-attachments/assets/f7f4954b-0ce3-4a4b-b9af-5af876032573"
/>
rdar://165047059
Commit: c6775e2eb6b94fd60453d207902cf961195bf780
https://github.com/llvm/llvm-project/commit/c6775e2eb6b94fd60453d207902cf961195bf780
Author: Andrew Haberlandt <ndrewh at users.noreply.github.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M compiler-rt/test/fuzzer/merge-posix.test
Log Message:
-----------
[compiler-rt] [libFuzzer] Fix merge-posix test (again) (#168639)
Commit: 5c73feddd1654624703102fdfd341df5046ba793
https://github.com/llvm/llvm-project/commit/5c73feddd1654624703102fdfd341df5046ba793
Author: nerix <nerixdev at outlook.de>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp
A llvm/test/tools/llvm-pdbutil/inline-annotations.test
Log Message:
-----------
[ObjectYAML][CodeView] Include inline annotation data (#168211)
The annotation data for `S_INLINESITE` symbols was missing in YAML. This
caused PDBs with inline sites to have incorrect symbol offsets, because
`S_INLINESITE` wouldn't have the same size after creating a PDB from
YAML.
I kept the annotations as binary, because that's how they're represented
in LLVM.
Commit: 1d474e4b97208a5cdda76e4f18dddd16e62f8f6e
https://github.com/llvm/llvm-project/commit/1d474e4b97208a5cdda76e4f18dddd16e62f8f6e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp
Log Message:
-----------
[llvm-cov] Use a range-based for loop (NFC) (#168671)
Identified with modernize-loop-convert.
Commit: b78824acef43066694978a701517d9f2d280a117
https://github.com/llvm/llvm-project/commit/b78824acef43066694978a701517d9f2d280a117
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/tools/llvm-profdata/llvm-profdata.cpp
Log Message:
-----------
[llvm-profdata] Use a range-based for loop (NFC) (#168672)
Identified with modernize-loop-convert.
Commit: c2445d9c26c10eebfd6df603f2a9a0aa774e8d84
https://github.com/llvm/llvm-project/commit/c2445d9c26c10eebfd6df603f2a9a0aa774e8d84
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Support/SpecialCaseList.cpp
Log Message:
-----------
[Support] Use StringMap::contains (NFC) (#168673)
Identified with readability-container-contains.
Commit: d988991f9f6b50941ecbffc316890342147a9f75
https://github.com/llvm/llvm-project/commit/d988991f9f6b50941ecbffc316890342147a9f75
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M flang/include/flang/Parser/characters.h
M flang/include/flang/Parser/preprocessor.h
M flang/lib/Parser/preprocessor.cpp
A flang/test/Preprocessing/bug168077.F90
Log Message:
-----------
[flang] Tokenize all -D macro bodies, and do it better (#168116)
The compiler presently tokenizes the bodies of only function-like macro
definitions from the command line, and does so crudely. Tokenize
keyword-like macros too, get character literals right, and handle
numeric constants correctly. (Also delete two needless functions noticed
in characters.h.)
Fixes https://github.com/llvm/llvm-project/issues/168077.
Commit: f5f6ca659992ae6d26b2a96304ceb65a1fd63ad6
https://github.com/llvm/llvm-project/commit/f5f6ca659992ae6d26b2a96304ceb65a1fd63ad6
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/bug168099.f90
Log Message:
-----------
[flang] Fix crash in UseErrorDetails construction case (#168126)
When a derived type has the same name as a generic function, and is
use-associated into a scope along with other distinct derived types of
the same name, we crash. Don't crash.
Fixes https://github.com/llvm/llvm-project/issues/168099.
Commit: a55e30b12cf90ba2e9c674c94ea3f2b5fa8f2c3b
https://github.com/llvm/llvm-project/commit/a55e30b12cf90ba2e9c674c94ea3f2b5fa8f2c3b
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M flang-rt/include/flang-rt/runtime/environment.h
M flang-rt/lib/runtime/environment.cpp
M flang-rt/lib/runtime/unit.cpp
M flang/docs/Extensions.md
M flang/docs/RuntimeEnvironment.md
Log Message:
-----------
[flang][runtime] Control stream truncation via runtime environment (#168415)
The ISO Fortran standards don't say whether a WRITE to a formatted
stream unit should truncate the unit if there has been any repositioning
(via POS= control list specifiers) to an earlier point in the stream.
But units with sequential records do truncate on writes after BACKSPACE
and REWIND statements, and many compilers (including this one) truncate
stream units too. Since some compilers don't truncate streams, this
patch adds an environment variable FORT_TRUNCATE_STREAM that can be set
to 0 to disable truncation and ease porting to flang-new of codes that
depend on that behavior.
Fixes https://github.com/llvm/llvm-project/issues/167569.
Commit: 2f6f045ea8d9342a2c57ea93f6343622499dd87a
https://github.com/llvm/llvm-project/commit/2f6f045ea8d9342a2c57ea93f6343622499dd87a
Author: darkbuck <michael.hliao at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/call.c
M flang/lib/Optimizer/Transforms/SetRuntimeCallAttributes.cpp
M flang/test/Transforms/set-runtime-call-attributes.fir
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
M mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Conversion/FuncToLLVM/convert-funcs.mlir
M mlir/test/Conversion/XeVMToLLVM/xevm-to-llvm.mlir
M mlir/test/Dialect/LLVMIR/func.mlir
M mlir/test/Dialect/LLVMIR/inlining.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/Import/instructions.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][LLVM] Resync memory effect attribute with LLVM IR (#168568)
- Add missing locations, namely 'ErrnoMem', 'TargetMem0', and
'TargetMem1'.
Commit: eb65517c76c131de7a3f772beea02347279ab6a3
https://github.com/llvm/llvm-project/commit/eb65517c76c131de7a3f772beea02347279ab6a3
Author: Aleksandr Nogikh <wp32pw at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
A clang/test/Sema/attr-malloc_span.c
A clang/test/SemaCXX/attr-malloc_span.cpp
Log Message:
-----------
[Clang] Introduce malloc_span attribute (#167010)
The "malloc" attribute restricts the possible function signatures to the
ones returning a pointer, which is not the case for some non-standard
allocation function variants. For example, P0901R11 proposed ::operator
new overloads that return a return_size_t result - a struct that
contains a pointer to the allocated memory as well as the actual size of
the allocated memory. Another example is __size_returning_new.
Introduce a new "malloc_span" attribute that exhibits similar semantics,
but applies to functions returning records where one member is a pointer
(assumed to point to the allocated memory) and another is an integer
(assumed to be the size of the allocated memory). This is the case for
return_size_t as well as std::span, should it be returned from such an
annotated function.
An alternative approach would be to relax the restrictions of the
existing "malloc" attribute to be applied to both functions returning
pointers and functions returning span-like structs. However, it would
complicate the user-space code by requiring specific Clang version
checks. In contrast, the presence of a new attribute can be
straightforwardly verified via the __has_attribute macro. Introducing a
new attribute also avoids concerns about the potential incompatibility
with GCC's "malloc" semantics.
In future commits, codegen can be improved to recognize the noalias-ness
of the pointer returned inside a span-like struct.
This change helps unlock the alloc token instrumentation for such
non-standard allocation functions:
https://clang.llvm.org/docs/AllocToken.html#instrumenting-non-standard-allocation-functions
Commit: c41f64239954b55468e44e6a6c92c1b4d2a1d8fe
https://github.com/llvm/llvm-project/commit/c41f64239954b55468e44e6a6c92c1b4d2a1d8fe
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/Darwin/dyld_insert_libraries_reexec.cpp
M compiler-rt/test/asan/TestCases/Darwin/lit.local.cfg.py
Log Message:
-----------
[ASan] Make dyld_insert_libraries_reexec work with internal shell
This test was doing some feature checks within the test itself. This patch
rewrites the feature checks to be done in a fashion more idiomatic to lit,
as the internal shell does not support the features needed for the previous
feature checks.
Reviewers: ndrewh, DanBlackwell, fmayer
Reviewed By: ndrewh
Pull Request: https://github.com/llvm/llvm-project/pull/168655
Commit: e6fc654bfd632a23574e18b43631470285a2cdf8
https://github.com/llvm/llvm-project/commit/e6fc654bfd632a23574e18b43631470285a2cdf8
Author: Nathan Gauër <brioche at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
Log Message:
-----------
[HLSL] replace std::unordered_map with DenseMap (#168739)
Broke some builds because of a missing include. Changing to a DenseMap
and adding the missing include.
Commit: 8f91d9f0ace77a5856219190b5e51105c5133af9
https://github.com/llvm/llvm-project/commit/8f91d9f0ace77a5856219190b5e51105c5133af9
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
A cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/Inputs/simplified_template_names.cpp
A cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/simplified_template_names-debug-types.test
R cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/simplified_template_names.cpp
A cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/simplified_template_names.test
Log Message:
-----------
[cross-project-tests][DebugInfo] Make simplified-template-names test runnable on Darwin (#168725)
The test was failing on Darwin for two reasons:
1. `-fdebug-type-sections` is not a recognized flag on Darwin
2. We fail to reconstitute a name if the template parameter has a type
that has a preferred_name. With LLDB tuning the type of such a parameter
is a typedef, i.e., the preferred name. Without tuning it would be the
canonical type that the typedef (possibly through a chain of typedefs)
points to.
This patch addresses (1) by splitting the `-fdebug-type-sections` tests
into a separate file (and only mark that one `UNSUPPORTED`). Which means
we can at least XFAIL the non-type-sections tests on Darwin.
To fix (2) we might need to make the `DWARFTypePrinter` aware of
non-canonical `DW_AT_type`s of template parameters.
Commit: e9b11ae83731bbca6adf9f9b39b6d3aa1869e445
https://github.com/llvm/llvm-project/commit/e9b11ae83731bbca6adf9f9b39b6d3aa1869e445
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
A compiler-rt/test/asan/TestCases/Darwin/Inputs/check-syslog.sh
M compiler-rt/test/asan/TestCases/Darwin/duplicate_os_log_reports.cpp
Log Message:
-----------
[ASan] Make duplicate_os_log_reports.cpp work with the internal shell
This test used a for loop to implement retries and also did some trickery with PIDs.
For this test, just invoke bash for actually running the test given we need the PID,
and move the for loop into a separate shell script file that we can then invoke from
within the test. Normally it would make sense to rewrite such a script in Python, but
given this test does not have portability concerns only running on Darwin, it is fine
to use a shell script here given there is no other convenient alternative.
Reviewers: ndrewh, DanBlackwell, fmayer
Reviewed By: ndrewh
Pull Request: https://github.com/llvm/llvm-project/pull/168656
Commit: 0b921f52cc9313b89ca8fe2707d90cb1c2809387
https://github.com/llvm/llvm-project/commit/0b921f52cc9313b89ca8fe2707d90cb1c2809387
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Log Message:
-----------
DAG: Use poison when splitting vector_shuffle results (#168176)
Commit: 1782e501f57ee5d3a1d2548f87ed4b82e7568b1d
https://github.com/llvm/llvm-project/commit/1782e501f57ee5d3a1d2548f87ed4b82e7568b1d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
Log Message:
-----------
DAG: Reorder SDPatternMatch combinators earlier (#168625)
Split out from #168288
Commit: ed0c36ca2885f4b0d6b36d7645248e24c2e8573c
https://github.com/llvm/llvm-project/commit/ed0c36ca2885f4b0d6b36d7645248e24c2e8573c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M compiler-rt/test/fuzzer/big-file-copy.test
Log Message:
-----------
[Fuzzer] make big-file-copy.test work with the internal shell (#168658)
This patch uses several shell features not supported by the internal
shell, such as $? to get the exit code of a command, and exit. This
patch adjusts the test to work with the internal shell by using bash to
run the actual command with a zero exit code to ensure the file is
deleted, and python to propagate the exit code up to lit.
Commit: 36cbceca40b7e6a8b5809718bf1afdb2af8b039a
https://github.com/llvm/llvm-project/commit/36cbceca40b7e6a8b5809718bf1afdb2af8b039a
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/test/CIR/CodeGen/ternary-throw.cpp
Log Message:
-----------
[CIR] Ternary with const cond and throw in the live part (#168432)
Ternary with a constant condition and throw in the live part
Commit: 009ec6fc64e23ee853485f2b97027a2dc1f040ab
https://github.com/llvm/llvm-project/commit/009ec6fc64e23ee853485f2b97027a2dc1f040ab
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/IR/eh-inflight.cir
A clang/test/CIR/Lowering/eh-inflight.cir
Log Message:
-----------
[CIR] Upstream Exception EhInflight op (#165621)
Upstream Exception EhInflight op as a prerequisite for full catch
handlers implementation
Issue https://github.com/llvm/llvm-project/issues/154992
Commit: f65294ed52cc8682924c5af17c262be267349f7d
https://github.com/llvm/llvm-project/commit/f65294ed52cc8682924c5af17c262be267349f7d
Author: Sterling-Augustine <saugustine at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
A libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/xsgetn.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/xsgetn.test.dat
Log Message:
-----------
Add test case for xsgetn in basic_filebuf (#167937)
This is the promised follow-up to #167779. It simply adds a test case
provided by philnik777
Commit: 87a1fd17e9be508e17fdeb37ad284b44c71795d5
https://github.com/llvm/llvm-project/commit/87a1fd17e9be508e17fdeb37ad284b44c71795d5
Author: Nico Weber <thakis at chromium.org>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
Log Message:
-----------
[gn] "port" 5efce7392f3f (arm 32-bit asm compiler-rt)
Commit: 6ad162393cf8ab2989e158576877e4570e091bbf
https://github.com/llvm/llvm-project/commit/6ad162393cf8ab2989e158576877e4570e091bbf
Author: Sayan Saha <sayans at mathworks.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Utils/ConversionUtils.cpp
Log Message:
-----------
[tosa] : Enhance EqualizeRanks to handle dynamic dimensions. (#168564)
Legalizing following IR to `tosa` using `tf-tosa-opt` from `tensorflow`
repo:
```
func.func @main(%arg0: tensor<?x?x?x?xf32>) -> tensor<?x?x?x5xf32> {
%0 = "tfl.pseudo_const"() <{value = dense<0.000000e+00> : tensor<5xf32>}> : () -> tensor<5xf32>
%1 = tfl.add(%arg0, %0) <{fused_activation_function = "NONE"}> : (tensor<?x?x?x?xf32>, tensor<5xf32>) -> tensor<?x?x?x5xf32>
return %1 : tensor<?x?x?x5xf32>
}
```
fails with
```
error: 'tosa.add' op operands don't have matching ranks
%1 = tfl.add(%arg0, %0) <{fused_activation_function = "NONE"}> : (tensor<?x?x?x?xf32>, tensor<5xf32>) -> tensor<?x?x?x5xf32>
^
tfl.mlir:3:10: note: see current operation: %1 = "tosa.add"(%arg0, %0) : (tensor<?x?x?x?xf32>, tensor<5xf32>) -> tensor<?x?x?x5xf32>
// -----// IR Dump After TosaLegalizeTFLPass Failed (tosa-legalize-tfl) //----- //
"func.func"() <{function_type = (tensor<?x?x?x?xf32>) -> tensor<?x?x?x5xf32>, sym_name = "main"}> ({
^bb0(%arg0: tensor<?x?x?x?xf32>):
%0 = "tosa.const"() <{values = dense<0.000000e+00> : tensor<5xf32>}> : () -> tensor<5xf32>
%1 = "tosa.add"(%arg0, %0) : (tensor<?x?x?x?xf32>, tensor<5xf32>) -> tensor<?x?x?x5xf32>
"func.return"(%1) : (tensor<?x?x?x5xf32>) -> ()
}) : () -> ()
```
This is because of the following check in `computeReshapeOutput` called
from `EqualizeRanks` function:
```
if (lowerRankDim != 1 && higherRankDim != 1 &&
lowerRankDim != higherRankDim)
return failure();
```
Based on the broadcast semantics defined in
https://mlir.llvm.org/docs/Traits/Broadcastable/#dimension-inference I
think it's legal to allow `lowerRankDim != higherRankDim` if one of them
is dynamic. At runtime verifier should enforce that
1. if lowerRankDim is dynamic and higherRankDim is static then the
dynamic dim matches the static dim and vice-versa
2. if both are dynamic, they should match
It's not necessary to error out during the op construction time.
Commit: 8bfd29486e042af5b4e4a6e9ef5e6d04ce618651
https://github.com/llvm/llvm-project/commit/8bfd29486e042af5b4e4a6e9ef5e6d04ce618651
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M libcxx/include/__charconv/from_chars_integral.h
M libcxx/include/__charconv/to_chars_integral.h
M libcxx/include/__locale_dir/num.h
M libcxx/include/__mdspan/extents.h
M libcxx/include/limits
M libcxx/test/libcxx/numerics/clamp_to_integral.pass.cpp
M libcxx/test/std/numerics/c.math/isnormal.pass.cpp
M libcxx/test/std/time/time.clock/time.clock.gps/types.compile.pass.cpp
M libcxx/test/std/time/time.clock/time.clock.tai/types.compile.pass.cpp
M libcxx/test/std/time/time.clock/time.clock.utc/types.compile.pass.cpp
M libcxx/test/std/utilities/utility/utility.intcmp/intcmp.cmp_greater/cmp_greater.pass.cpp
M libcxx/test/std/utilities/utility/utility.intcmp/intcmp.cmp_less/cmp_less.pass.cpp
M libcxx/test/std/utilities/utility/utility.intcmp/intcmp.cmp_less_equal/cmp_less_equal.pass.cpp
Log Message:
-----------
[libc++] Remove is_signed<T> use from <limits> (#168334)
`numeric_limits` already has an `is_signed` member. We can use that
instead of using `std::is_signed`.
Commit: 449807a39867d98bbd0abbd597ff3388a4f86a2a
https://github.com/llvm/llvm-project/commit/449807a39867d98bbd0abbd597ff3388a4f86a2a
Author: Nico Weber <thakis at chromium.org>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/lib/asan/BUILD.gn
Log Message:
-----------
[gn] port c62fc065b4c1
Commit: 0c7d826129209972741dda3bd8bc40e500d5cda8
https://github.com/llvm/llvm-project/commit/0c7d826129209972741dda3bd8bc40e500d5cda8
Author: Charles Zablit <c_zablit at apple.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M lldb/include/lldb/Expression/DiagnosticManager.h
A lldb/include/lldb/Host/common/DiagnosticsRendering.h
M lldb/include/lldb/Interpreter/CommandReturnObject.h
R lldb/include/lldb/Utility/DiagnosticsRendering.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/source/Commands/CommandObjectExpression.cpp
M lldb/source/Host/CMakeLists.txt
A lldb/source/Host/common/DiagnosticsRendering.cpp
M lldb/source/Interpreter/CommandReturnObject.cpp
M lldb/source/Interpreter/Options.cpp
M lldb/source/Utility/CMakeLists.txt
R lldb/source/Utility/DiagnosticsRendering.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/unittests/Host/common/CMakeLists.txt
A lldb/unittests/Host/common/DiagnosticsRenderingTest.cpp
M lldb/unittests/Utility/CMakeLists.txt
R lldb/unittests/Utility/DiagnosticsRenderingTest.cpp
M llvm/utils/gn/secondary/lldb/source/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Utility/BUILD.gn
Log Message:
-----------
[NFC][lldb] move DiagnosticsRendering to Host (#168696)
NFC patch which moves `DiagnosticsRendering` from `Utility` to `Host`.
This refactoring is needed for
https://github.com/llvm/llvm-project/pull/168603. It adds a method to
check whether the current terminal supports Unicode or not. This will be
OS dependent and a better fit for `Host`. Since `Utility` cannot depend
on `Host`, `DiagnosticsRendering` must live in `Host` instead.
Commit: 3890a4a9e5a8c128cf9b193c57841efbbaf36866
https://github.com/llvm/llvm-project/commit/3890a4a9e5a8c128cf9b193c57841efbbaf36866
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-comparison.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-minmax.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mul-div.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
Log Message:
-----------
[RISCV] Update X60 ReleaseAtCycles for Vector Integer Arithmetic Instructions (#152557)
This PR updates the ReleaseAtCycles for all instructions described in
Section 11 of the RVV Spec: Vector Integer Arithmetic Instructions. The
data used comes from camel-cdr.
Commit: 8ab7b60c27c3c61558b6e94f2b010a41842a7592
https://github.com/llvm/llvm-project/commit/8ab7b60c27c3c61558b6e94f2b010a41842a7592
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Bump Runner Version in CI Containers
To ensure we stay ahead of the ~6 month time horizon. This new version
seems to be mostly small version bumps and minor fixes that probably are
not too relevant to us.
Commit: 0f615dc6a6bc8b96fe85f23adef740a313537a0e
https://github.com/llvm/llvm-project/commit/0f615dc6a6bc8b96fe85f23adef740a313537a0e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M .github/workflows/build-metrics-container.yml
Log Message:
-----------
[Github] Make metrics container build use common actions (#168667)
This patch makes the metrics container build/push job use the common
container build/push actions to simplify the workflow by quite a bit.
Commit: 6f8e87b9d097c5ef631f24d2eb2f34eb31b54d3b
https://github.com/llvm/llvm-project/commit/6f8e87b9d097c5ef631f24d2eb2f34eb31b54d3b
Author: Nico Weber <thakis at chromium.org>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/include/clang/Sema/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
Log Message:
-----------
[gn] port 22a2cae5d6735 (AttrIsTypeDependent.inc)
Commit: a4456a5ce3fd4a57343c0cc6dd46b2d024985bc4
https://github.com/llvm/llvm-project/commit/a4456a5ce3fd4a57343c0cc6dd46b2d024985bc4
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M utils/bazel/.bazelrc
M utils/bazel/MODULE.bazel.lock
Log Message:
-----------
[bazel] Flip --enable_bzlmod to true (#168555)
Switches to the config added in #164891
Fixes #55924
Commit: ddbdc9a86ec6aa2b449f94003bdaa1bf9e16b3b0
https://github.com/llvm/llvm-project/commit/ddbdc9a86ec6aa2b449f94003bdaa1bf9e16b3b0
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
Log Message:
-----------
[AMDGPU] Add baseline test to show spilling of wmma scale. NFC (#168163)
This is to show the spilling of WMMA scale values which are limited
to low 256 VGPRs. We have free registers, just RA allocates low 256
first.
Commit: 98b170893e955659b9c678c4b8ede08bb11163b2
https://github.com/llvm/llvm-project/commit/98b170893e955659b9c678c4b8ede08bb11163b2
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M mlir/docs/Dialects/NVVMDialect.md
M mlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt
Log Message:
-----------
[MLIR][NVVM] Doc fixes (#168716)
Commit: 1f3455093c0e0849f52016fccc91b413f85a609a
https://github.com/llvm/llvm-project/commit/1f3455093c0e0849f52016fccc91b413f85a609a
Author: Nico Weber <thakis at chromium.org>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/tools/lldb-server/BUILD.gn
Log Message:
-----------
[gn] port 2675dcd72d02ee1ac (lldb-server PlatformOptions.inc)
Commit: bc5f3d2063e740262a873f223b86ffda39dfa7a6
https://github.com/llvm/llvm-project/commit/bc5f3d2063e740262a873f223b86ffda39dfa7a6
Author: Nico Weber <thakis at chromium.org>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/ARM/BUILD.gn
Log Message:
-----------
[gn] port 0ae2bccde45 (arm SDNodeInfo)
Commit: 3adcfd22ecc2f2a8fbd32e0d1533fc22111ed7cb
https://github.com/llvm/llvm-project/commit/3adcfd22ecc2f2a8fbd32e0d1533fc22111ed7cb
Author: Nico Weber <thakis at chromium.org>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/NVPTX/BUILD.gn
Log Message:
-----------
[gn] port e47e9f3b7b136 (nvptx SDNodeInfo)
Commit: d2c7c6064259320def7a74e111079725958697d4
https://github.com/llvm/llvm-project/commit/d2c7c6064259320def7a74e111079725958697d4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/test/Transforms/InstSimplify/ConstProp/vector-calls.ll
Log Message:
-----------
[InstSimplify] Add whitespace to struct declarations in vector-calls.ll. NFC
This matches how IR is printed.
Commit: 1233c4bf230bcc40f86b8684e4cc1e4d368a8b79
https://github.com/llvm/llvm-project/commit/1233c4bf230bcc40f86b8684e4cc1e4d368a8b79
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/test/Driver/crash-ir-repro.cpp
Log Message:
-----------
Minor fix of reproducer in #165572 (#168751)
Commit: a757c4e74e6a3130c708b26903d5117a9279bef8
https://github.com/llvm/llvm-project/commit/a757c4e74e6a3130c708b26903d5117a9279bef8
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/BPF/BPFISelLowering.cpp
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.h
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/XCore/XCoreISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/unittests/CodeGen/MFCommon.inc
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
Log Message:
-----------
CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)
Currently LibcallLoweringInfo is defined inside of TargetLowering,
which is owned by the subtarget. Pass in the subtarget so we can
construct LibcallLoweringInfo with the subtarget. This is a temporary
step that should be revertable in the future, after LibcallLoweringInfo
is moved out of TargetLowering.
Commit: 36f9d5a41f0eff44e65f09240c7ca454c47b35cd
https://github.com/llvm/llvm-project/commit/36f9d5a41f0eff44e65f09240c7ca454c47b35cd
Author: Paddy McDonald <padriff at hotmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/docs/AddressSanitizer.rst
M compiler-rt/include/sanitizer/common_interface_defs.h
M compiler-rt/lib/asan/asan_errors.cpp
A compiler-rt/test/asan/TestCases/disable_container_overflow_checks.cpp
A compiler-rt/test/asan/TestCases/stack_container_dynamic_lib.cpp
Log Message:
-----------
[ASan] Document define to disable container overflow checks at compile time. (#163468)
Document a define to allow library developers to support disabling
AddressSanitizer's container overflow detection in template code at
compile time.
The primary motivation is to reduce false positives in environments
where
libraries and frameworks that cannot be recompiled with sanitizers
enabled
are called from application code. This supports disabling checks when
the
runtime environment cannot be reliably controlled to use ASAN_OPTIONS.
Key changes:
- Use the define `__SANITIZER_DISABLE_CONTAINER_OVERFLOW__` to disable
instrumentation at compile time
- Implemented redefining the container overflow APIs in
common_interface_defs.h
to use define to provide null implementation when define is present
- Update documentation in AddressSanitizer.rst to suggest and illustrate
use of the define
- Add details of the define in PrintContainerOverflowHint()
- Add test disable_container_overflow_checks to verify new hints on the
error and fill the testing gap that
ASAN_OPTIONS=detect_container_overflow=0
works
- Add tests demonstrating the issue around closed source libraries and
instrumented apps that both modify containers
This requires no compiler changes and should be supportable cross
compiler toolchains.
An RFC has been opened to discuss:
https://discourse.llvm.org/t/rfc-add-fsanitize-address-disable-container-overflow-flag-to-addresssanitizer/88349
Commit: fc95558f628de4243dc85e31eaaac795435ca031
https://github.com/llvm/llvm-project/commit/fc95558f628de4243dc85e31eaaac795435ca031
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
[TableGen] Use size_t for SubRegIndicesSize (NFC) (#168728)
This patch changes the type of SubRegIndicesSize to size_t. The
original type deduced for "auto" is a signed type, but size_t, an
unsigned type, is safe here according to the usage.
Commit: 06f0d30e2887b98841a4d5d0915aebbc1ef7480e
https://github.com/llvm/llvm-project/commit/06f0d30e2887b98841a4d5d0915aebbc1ef7480e
Author: Nico Weber <thakis at chromium.org>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/ARM/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/ARM/BUILD.gn
Log Message:
-----------
[gn] port 0ae2bccde45 more
Commit: fb8155c2b87f265c56a1668b3640a52afaaa55d2
https://github.com/llvm/llvm-project/commit/fb8155c2b87f265c56a1668b3640a52afaaa55d2
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
Log Message:
-----------
[gn build] Port 8fce476c8122
Commit: 60a27953eabe3a0ded7c9b7b7786dfd1fe5d8c5f
https://github.com/llvm/llvm-project/commit/60a27953eabe3a0ded7c9b7b7786dfd1fe5d8c5f
Author: Benjamin Stott <Benjamin.Stott at sony.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/CodeGen/CGExprComplex.cpp
A clang/test/CodeGen/complex-compound-assign-bitfield.c
Log Message:
-----------
[Clang][CodeGen] Use EmitLoadOfLValue instead of EmitLoadOfScalar to get LHS for complex compound assignment (#166798)
- Fixes https://github.com/llvm/llvm-project/issues/166512
- `ComplexExprEmitter::EmitCompoundAssignLValue` is calling
`EmitLoadOfScalar(LValue, SourceLocation)` to load the LHS value in the
case that it's non-complex, however this function requires that the
value is a simple LValue - issue occurred because the LValue in question
was a bitfield LValue. I changed it to use this function which seems to
handle all of the different cases (deferring to the original
`EmitLoadOfScalar` if it's a simple LValue)
Commit: 13e09ebe2dc7699598ac6eeb5fcb8738db27743b
https://github.com/llvm/llvm-project/commit/13e09ebe2dc7699598ac6eeb5fcb8738db27743b
Author: Peter Collingbourne <pcc at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/Target.h
A lld/test/ELF/aarch64-funcinit64-invalid.s
A lld/test/ELF/aarch64-funcinit64.s
Log Message:
-----------
ELF: Add support for relocating R_AARCH64_FUNCINIT64.
R_AARCH64_FUNCINIT64 is a dynamic relocation type for relocating
word-sized data in the output file using the return value of
a function. An R_AARCH64_FUNCINIT64 shall be relocated as an
R_AARCH64_IRELATIVE with the target symbol address if the target
symbol is non-preemptible, and it shall be a usage error to relocate an
R_AARCH64_FUNCINIT64 with a preemptible or STT_GNU_IFUNC target symbol.
The initial use case for this relocation type shall be for emitting
global variable field initializers for structure protection. With
structure protection, the relocation value computation is tied to the
compiler implementation in such a way that it would not be reasonable to
define a relocation type for it (for example, it may involve computing
a hash using a compiler-determined algorithm), hence the need for the
computation to be implemented as code in the binary.
Part of the AArch64 psABI extension:
https://github.com/ARM-software/abi-aa/issues/340
Reviewers: smithp35, fmayer, MaskRay
Reviewed By: fmayer
Pull Request: https://github.com/llvm/llvm-project/pull/156564
Commit: 56112685f7a25078868b8f09c72feaf4ceae50f9
https://github.com/llvm/llvm-project/commit/56112685f7a25078868b8f09c72feaf4ceae50f9
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/test/CIR/CodeGen/defaultarg.cpp
Log Message:
-----------
[CIR] Handle default arguments in ctors (#168649)
This adds the scalar expression visitor needed to handle default
arguments being passed to constructors.
Commit: afcb9537bb40143d45dd5aeb06009b6aaee1f6f6
https://github.com/llvm/llvm-project/commit/afcb9537bb40143d45dd5aeb06009b6aaee1f6f6
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/extensions.bzl
Log Message:
-----------
[bazel] Fix bzlmod reference to @vulkan_sdk (#168767)
vulkan_sdk_setup is the name of the method that configures it, but the
repo itself has the name vulkan_sdk
This was caught by enabling the bzlmod flag for CI. The GH action runs
`blaze test @llvm-project/...` but the target is tagged manual, so it's
excluded. The buildkite CI runs `bazel query | xargs bazel test` which
will include manual targets.
Commit: e148d2d422c4f310785e38942c8eb7243b065d7a
https://github.com/llvm/llvm-project/commit/e148d2d422c4f310785e38942c8eb7243b065d7a
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads.ll
Log Message:
-----------
[LV] Simplify existing load/store sink/hoisting tests, extend coverage.
Clean up some of the existing predicated load/store sink/hosting tests
and add additional test coverage for more complex cases.
Commit: 12131d5cd39025c1e9e521fde6ffbfffd51dff1c
https://github.com/llvm/llvm-project/commit/12131d5cd39025c1e9e521fde6ffbfffd51dff1c
Author: Mikhail Gudim <mgudim at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-loads.ll
Log Message:
-----------
[SLPVectorizer] Widen constant strided loads. (#162324)
Given a set of pointers, check if they can be rearranged as follows (%s is a constant):
%b + 0 * %s + 0
%b + 0 * %s + 1
%b + 0 * %s + 2
...
%b + 0 * %s + w
%b + 1 * %s + 0
%b + 1 * %s + 1
%b + 1 * %s + 2
...
%b + 1 * %s + w
...
If the pointers can be rearanged in the above pattern, it means that the
memory can be accessed with a strided loads of width `w` and stride `%s`.
Commit: df58c38b5a831da1cd96317297c9482402c60216
https://github.com/llvm/llvm-project/commit/df58c38b5a831da1cd96317297c9482402c60216
Author: Kai Lin <50469469+OMG-link at users.noreply.github.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvv/combine-vl-vw-macc.ll
Log Message:
-----------
[RISCV][DAGCombiner] Fix potential missed combine in VL->VW extension (#168026)
The previous implementation of `combineOp_VLToVWOp_VL` manually replaced
old
nodes with newly created widened nodes, but only added the new node
itself to
the `DAGCombiner` worklist. Since the users of the new node were not
added,
some combine opportunities could be missed when external `DAGCombiner`
passes
expected those users to be reconsidered.
This patch replaces the custom replacement logic with a call to
`DCI.CombineTo()`, which performs node replacement in a way consistent
with
`DAGCombiner::Run`:
- Replace all uses of the old node.
- Add the new node and its users to the worklist.
- Clean up unused nodes when appropriate.
Using `CombineTo` ensures that `combineOp_VLToVWOp_VL` behaves
consistently with
the standard `DAGCombiner` update model, avoiding discrepancies between
the
private worklist inside this routine and the global worklist managed by
the
combiner.
This resolves missed combine cases involving VL -> VW operator widening.
---------
Co-authored-by: Kai Lin <omg_link at qq.com>
Commit: e00314be1cf5e7ebba25339439d427174eb6f24b
https://github.com/llvm/llvm-project/commit/e00314be1cf5e7ebba25339439d427174eb6f24b
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M .github/workflows/libclang-abi-tests.yml
Log Message:
-----------
workflows/libclang-abi-tests: Remove use of install-ninja action (#168642)
This is not needed now that we are using the container to run the
workflow.
Commit: 2f9f492b3d160dee8ae080e981dd6e92aadf56ce
https://github.com/llvm/llvm-project/commit/2f9f492b3d160dee8ae080e981dd6e92aadf56ce
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M .github/workflows/hlsl-test-all.yaml
Log Message:
-----------
workflows/hlsl-test-all: Drop use of setup-windows action (#167437)
It doesn't look like these tests are actually run on Windows, so we
don't need it.
Commit: f85942728fe2edfc681831abf8ecd2f245e1aaaa
https://github.com/llvm/llvm-project/commit/f85942728fe2edfc681831abf8ecd2f245e1aaaa
Author: Thibault Monnier <97551402+Thibault-Monnier at users.noreply.github.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/test/CIR/CodeGen/X86/sse-builtins.c
Log Message:
-----------
[CIR] Upstream CIR codegen for mxcsr x86 builtins (#167948)
Commit: c34927ab5ac9f359616657c3f5e05f868db901f6
https://github.com/llvm/llvm-project/commit/c34927ab5ac9f359616657c3f5e05f868db901f6
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M .github/workflows/commit-access-review.py
Log Message:
-----------
commit-access-review.py: Remove new contributor check (#168629)
We don't need this anymore since all new contributors in the last year
have applied for commit access using GitHub issues. There is already
code in the script that removes anyone who submitted a request, so we
don't need the old code any more (which was way too conservitave and
very slow).
Commit: 11dff3a0e06d6471863f4e997f6c4e5d05de3466
https://github.com/llvm/llvm-project/commit/11dff3a0e06d6471863f4e997f6c4e5d05de3466
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/Generators.h
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/HTMLMustacheGenerator.cpp
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
Log Message:
-----------
[clang-doc][NFC] Lift Mustache template generation from HTML (#167815)
To prepare for more backends to use Mustache templates, this patch lifts
the Mustache utilities from `HTMLMustacheGenerator.cpp` to
`Generators.h`. A MustacheGenerator interface is created to share code for
template creation.
Commit: c9f573463ebd7b4e46da4877802f2364f700e54a
https://github.com/llvm/llvm-project/commit/c9f573463ebd7b4e46da4877802f2364f700e54a
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
A llvm/include/llvm/Analysis/CMakeLists.txt
R llvm/include/llvm/Analysis/TargetLibraryInfo.def
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
A llvm/include/llvm/Analysis/TargetLibraryInfo.td
A llvm/include/llvm/Analysis/TargetLibraryInfoImpl.td
M llvm/include/llvm/CMakeLists.txt
M llvm/include/llvm/TableGen/StringToOffsetTable.h
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/CMakeLists.txt
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/LTO/UpdateCompilerUsed.cpp
M llvm/lib/TableGen/StringToOffsetTable.cpp
M llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
A llvm/test/TableGen/TargetLibraryInfo.td
M llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp
M llvm/unittests/Analysis/TargetLibraryInfoTest.cpp
M llvm/utils/TableGen/Basic/CMakeLists.txt
A llvm/utils/TableGen/Basic/TargetLibraryInfoEmitter.cpp
Log Message:
-----------
[Analysis] Move TargetLibraryInfo data to TableGen (#165009)
The collection of library function names in TargetLibraryInfo faces
similar challenges as RuntimeLibCalls in the IR component. The number of
function names is large, there are numerous customizations based on the
triple (including alternate names), and there is a lot of replicated
data in the signature table.
The ultimate goal would be to capture all lbrary function related
information in a .td file. This PR brings the current .def file to
TableGen, almost as a 1:1 replacement. However, there are some
improvements which are not possible in the current implementation:
- the function names are now stored as a long string together with an
offset table.
- the table of signatures is now deduplicated, using an offset table for
access.
The size of the object file decreases about 34kB with these changes. The
hash table of all function names is still constructed dynamically. A
static table like for RuntimeLibCalls is the next logical step.
The main motivation for this change is that I have to add a large number
of custom names for z/OS (like in RuntimeLibCalls.td), and the current
infrastructur does not support this very well.
Commit: 2b16ae0d42ebc5b9c42a9d14c8a40bef4c9a6683
https://github.com/llvm/llvm-project/commit/2b16ae0d42ebc5b9c42a9d14c8a40bef4c9a6683
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/cfi-multiple-locations.mir
Log Message:
-----------
[RISCV] Fix CFI Multiple Locations Test (#168772)
Commit: 609c88a1fd8bdfd67f86a1c129325e2ccd6b959c
https://github.com/llvm/llvm-project/commit/609c88a1fd8bdfd67f86a1c129325e2ccd6b959c
Author: Marco Elver <elver at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaChecking.cpp
M clang/test/SemaCXX/alloc-token.cpp
Log Message:
-----------
[Clang][Sema] Fix __builtin_infer_alloc_token() return type (#168773)
Using the builtin failed on 32-bit architectures:
```
clang/lib/AST/ExprConstant.cpp:14299: [..]: Assertion `I.getBitWidth() == Info.Ctx.getIntWidth(E->getType()) && "Invalid evaluation result."' failed.
```
The return type is meant to be size_t. Fix it.
Commit: e0c265d1c0cb8650cbfcffa81c297f2cdacc85d9
https://github.com/llvm/llvm-project/commit/e0c265d1c0cb8650cbfcffa81c297f2cdacc85d9
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang-tools-extra/clang-doc/assets/class-template.mustache
M clang-tools-extra/clang-doc/assets/comment-template.mustache
M clang-tools-extra/clang-doc/assets/function-template.mustache
M clang-tools-extra/test/clang-doc/basic-project.mustache.test
Log Message:
-----------
[clang-doc] Fix whitespace issues in Mustache basic test (#168491)
I found that the issues we've been seeing in the HTML
whitespace/alignment are due to partials inserting their own whitespace
and calling partials on indented lines or lines containing text already.
This patch gets rid of unnecessary whitespace in the comment and
function partials so that they are properly indented when inserted.
Commit: 12d72050e1255decb67d53125e86d348db2951d6
https://github.com/llvm/llvm-project/commit/12d72050e1255decb67d53125e86d348db2951d6
Author: Igor Kudrin <ikudrin at accesssoftek.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/invalid-string/TestDataFormatterLibcxxInvalidString.py
Log Message:
-----------
[lldb][test] Correctly skip a test on a 32-bit target (#168631)
The test was added in #147252. On a 32-bit target, it fails with error:
```
File "...\TestDataFormatterLibcxxInvalidString.py", line 23, in test
self.skip()
^^^^^^^^^
AttributeError: 'LibcxxInvalidStringDataFormatterTestCase' object has no attribute 'skip'
```
Commit: 253ed524365e20309e0f615415c9433bd9bda44d
https://github.com/llvm/llvm-project/commit/253ed524365e20309e0f615415c9433bd9bda44d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/X86/matrix-multiply.ll
M llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
Log Message:
-----------
DAG: Use poison for some vector result widening (#168290)
Commit: eea62159e853b59a4e4e69da22175222ccd8c663
https://github.com/llvm/llvm-project/commit/eea62159e853b59a4e4e69da22175222ccd8c663
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[Offload] Make the RPC thread sleep briefly when idle (#168596)
Summary:
We start this thread if the RPC client symbol is detected in the loaded
binary. We should make this sleep if there's no work to avoid the thread
running at high priority when the (scarecely used) RPC call is actually
required. So, right now after 25 microseconds we will assume the server
is inactive and begin sleeping. This resets once we do find work.
AMD supports a more intelligent way to do this. HSA signals can wake a
sleeping thread from the kernel, and signals can be sent from the GPU
side. This would be nice to have and I'm planning on working with it in
the future to make this infrastructure more usable with existing AMD
workloads.
Commit: 5c43385319c3976edf6857487273af22eac3abae
https://github.com/llvm/llvm-project/commit/5c43385319c3976edf6857487273af22eac3abae
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGValue.h
M clang/test/CIR/CodeGen/coro-task.cpp
A clang/test/CIR/IR/await.cir
M clang/test/CIR/IR/func.cir
A clang/test/CIR/IR/invalid-await.cir
Log Message:
-----------
[CIR] Upstream CIR await op (#168133)
This PR upstreams `cir.await` and adds initial codegen for emitting a
skeleton of the ready, suspend, and resume branches. Codegen for these
branches is left for a future PR. It also adds a test for the invalid
case where a `cir.func` is marked as a coroutine but does not contain a
`cir.await` op in its body.
Commit: 040d9c94bebfc441f555de4617baf7da410ed959
https://github.com/llvm/llvm-project/commit/040d9c94bebfc441f555de4617baf7da410ed959
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Collect FMFs for in-loop reduction chain in VPlan. (NFC)
Replace retrieving FMFs for in-loop reduction via underlying instruction
+ legal by collecting the flags during reduction chain traversal in
VPlan.
Commit: 3b49c927427a6e818fee154725b3a05ead6c09de
https://github.com/llvm/llvm-project/commit/3b49c927427a6e818fee154725b3a05ead6c09de
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
Log Message:
-----------
Fix build breakage from: #167948 (#168781)
It appears that this broke the build by not using the 'correct' name for
the expression. This is probably something that crossed in review.
Commit: f2c9c7d654947cb1317f96547c15c256a1df4ce4
https://github.com/llvm/llvm-project/commit/f2c9c7d654947cb1317f96547c15c256a1df4ce4
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/include/clang/AST/StmtOpenACC.h
M clang/lib/AST/StmtOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/atomic-capture.cpp
Log Message:
-----------
[OpenACC][CIR] Fix atomic-capture single-line-postfix (#168717)
In my last patch, it became clear during code review that the postfix
operation was actually a read THEN update, not update/read like other
single line versions. It wasn't clear at the time how much additional
work this would be to make postfix work correctly (and they are a bit of
a 'special' thing in codegen anyway), so this patch adds some
functionality to sense this and special-cases it when generating the
statement info for capture.
Commit: 90ea49a9d17b01cc51d69bdd0c79b959955e605f
https://github.com/llvm/llvm-project/commit/90ea49a9d17b01cc51d69bdd0c79b959955e605f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/test/Transforms/InstSimplify/ConstProp/vector-calls.ll
Log Message:
-----------
[ConstantFolding] Generalize constant folding for vector_deinterleave2 to deinterleave3-8. (#168640)
Commit: 3f55f8b4e5512e5d50a077800a190afb3aa65ffc
https://github.com/llvm/llvm-project/commit/3f55f8b4e5512e5d50a077800a190afb3aa65ffc
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenRecordLayout.h
M clang/test/CIR/CodeGen/ctor-null-init.cpp
Log Message:
-----------
[CIR] Handle non-empty null base class initialization (#168646)
This implements null base class initialization for non-empty bases.
Commit: 308185e61abb5a06af1786902f1b3768b5d46be5
https://github.com/llvm/llvm-project/commit/308185e61abb5a06af1786902f1b3768b5d46be5
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/utils/TableGen/CallingConvEmitter.cpp
Log Message:
-----------
[NFC][TableGen] Use `IfGuardEmitter` in CallingConvEmitter (#168763)
Use `IfGuardEmitter` in CallingConvEmitter. Additionally refactor the
code a bit to extract duplicated code to emit the CC function prototype
into a helper function.
Commit: 9b7fd0099e79b0f5b824027cbae8a25356486ac9
https://github.com/llvm/llvm-project/commit/9b7fd0099e79b0f5b824027cbae8a25356486ac9
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/test/SemaOpenACC/declare-construct.cpp
Log Message:
-----------
[OpenACC] Fix crash when checking an section in a 'link' clause (#168783)
I saw this while doing lowering, we were not properly looking into the
array sections for the variable. Presumably we didn't do a good job of
making sure we did this right when making this extension, and missed
this spot.
Commit: 19fe9b477b570fd395a161638c59e66b35d1a9ac
https://github.com/llvm/llvm-project/commit/19fe9b477b570fd395a161638c59e66b35d1a9ac
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/SemaHLSL/BuiltIns/buffer_update_counter-errors.hlsl
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
Log Message:
-----------
[HLSL][TableGen] Add `__hlsl_resource_t` to known built-in function types (#163465)
This change adds resource handle type `__hlsl_resource_t` to the list of types recognized in the Clang's built-in functions prototype string.
HLSL has built-in resource classes and some of them have many methods, such as
[Texture2D](https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/sm5-object-texture2d).
Most of these methods will be implemented by built-in functions that will take resource handle as an argument. This change enables us to move from generic `void(...)` prototype string for these methods and explicit argument checking in `SemaHLSL.cpp` to a prototype string with explicit argument types. Argument checking in `SemaHLSL.cpp` can be reduced to handle just the rules that cannot be expressed in the prototype string (for example verifying that the offset value in `__builtin_hlsl_buffer_update_counter` is `1` or `-1`).
In order to make this work, we now allow conversions from attributed resource handle type such as `__hlsl_resource_t [[hlsl::resource_class(UAV)]] [[hlsl::contained_type(float)]]` to a plain non-attributed `__hlsl_resource_t` type.
Commit: e99c83ff38b006f12b78704c8e9b9751bf100659
https://github.com/llvm/llvm-project/commit/e99c83ff38b006f12b78704c8e9b9751bf100659
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/Inputs/simplified_template_names.cpp
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
M llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
Log Message:
-----------
[llvm][DebugInfo] Add support for _BitInt in DWARFTypePrinter (#168382)
As of recent, LLVM includes the bit-size as a `DW_AT_bit_size` (and as
part of `DW_AT_name`) of `_BitInt`s in DWARF. This allows us to mark
`_BitInt`s as "reconstitutable" when compiling with
`-gsimple-template-names`. However, before doing so we need to make sure
the `DWARFTypePrinter` can reconstruct template parameter values that
have `_BitInt` type. This patch adds support for printing
`DW_TAG_template_value_parameter`s that have `_BitInt` type. Since
`-gsimple-template-names` only omits template parameters that are `<=
64` bit wide, we don't support `_BitInt`s larger than 64 bits.
Commit: 3f6cbdea4fecf11ffa4fa29151c69f53c7a59bf7
https://github.com/llvm/llvm-project/commit/3f6cbdea4fecf11ffa4fa29151c69f53c7a59bf7
Author: Andrew Haberlandt <ndrewh at users.noreply.github.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/utils/lit/lit/TestRunner.py
A llvm/utils/lit/tests/Inputs/shtest-env-positive/env-current-testcase.txt
M llvm/utils/lit/tests/Inputs/shtest-env-positive/env-no-subcommand.txt
M llvm/utils/lit/tests/shtest-env-positive.py
Log Message:
-----------
[lit] Add LIT_CURRENT_TESTCASE environment variable when running tests (#168762)
I'm not aware of any way for `%run` wrapper scripts like
`iosssim_run.py`
([ref](https://github.com/llvm/llvm-project/blob/d2c7c6064259320def7a74e111079725958697d4/compiler-rt/test/sanitizer_common/ios_commands/iossim_run.py#L4))
to know what testcase they are currently running. This can be useful if
these wrappers need to create a (potentially remote) temporary directory
for each test case.
This adds the `LIT_CURRENT_TESTCASE` environment variable to both the
internal shell and the external shell, containing the full name of the
current test being run.
Commit: 7e85b790b02a770a003dbb13a7476590d045f58e
https://github.com/llvm/llvm-project/commit/7e85b790b02a770a003dbb13a7476590d045f58e
Author: anoopkg6 <anoop.kumar6 at ibm.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
Log Message:
-----------
[SystemZ] Fix linux s390x main can't bootstrap itself on SanitizerSpecialCaseList.cpp #168088 (#168779)
This test has long call chain in recursion. Search tree can be pruned
early by swapping CC test and recursive simplifyAssumingCCVal.
Fixes: https://github.com/llvm/llvm-project/issues/168088
Co-authored-by: anoopkg6 <anoopkg6 at github.com>
Commit: be955e5ac9a0b0c979221efb28b0f52aad7bd3d6
https://github.com/llvm/llvm-project/commit/be955e5ac9a0b0c979221efb28b0f52aad7bd3d6
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/test/SemaOpenACC/declare-construct-ast.cpp
Log Message:
-----------
[OpenACC] Make sure 'link' gets the right node in the AST with ASE
Another miss when working through 'link', we didn't properly handle
giving the whole array-section expression or array index expression,
instead allowed it to only get the decl-ref-expr. This patch makes
sure we don't add the wrong thing.
Commit: db1e73ea6d9390c811ab7d41d9ceefb2620be668
https://github.com/llvm/llvm-project/commit/db1e73ea6d9390c811ab7d41d9ceefb2620be668
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/test/DebugInfo/CXX/simple-template-names.cpp
Log Message:
-----------
[clang][DebugInfo] Mark _BitInt's as reconstitutable when emitting -gsimple-template-names (#168383)
Depends on:
* https://github.com/llvm/llvm-project/pull/168382
As of recent, LLVM includes the bit-size as a `DW_AT_bit_size` (and as
part of `DW_AT_name`) of `_BitInt`s in DWARF. This allows us to mark
`_BitInt`s as "reconstitutable" when compiling with
`-gsimple-template-names`. We still only omit template parameters that
are `<= 64` bit wide. So support `_BitInt`s larger than 64 bits is not
part of this patch.
Commit: 88305251fe809ba384ea4ff4893bf671757504fb
https://github.com/llvm/llvm-project/commit/88305251fe809ba384ea4ff4893bf671757504fb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/test/Transforms/InstSimplify/ConstProp/vector-calls.ll
Log Message:
-----------
[ConstantFolding] Add constant folding for scalable vector interleave intrinsics. (#168668)
We can constant fold interleave of identical splat vectors to a larger
splat vector.
Commit: 2aa2290af51a033849878b30ee30aae5d11394f3
https://github.com/llvm/llvm-project/commit/2aa2290af51a033849878b30ee30aae5d11394f3
Author: mitchell <mitchell.xu2 at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.cpp
M clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/duplicate-include.rst
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/duplicate-include/pack_begin.h
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/duplicate-include/pack_end.h
A clang-tools-extra/test/clang-tidy/checkers/readability/duplicate-include-ignored-files.cpp
Log Message:
-----------
[clang-tidy] Add `IgnoredFilesList` option to `readability-duplicate-include` (#168196)
Closes [#166938](https://github.com/llvm/llvm-project/issues/166938)
Commit: 1278d47e9f9773972ff17deaf4d69db48dccdad8
https://github.com/llvm/llvm-project/commit/1278d47e9f9773972ff17deaf4d69db48dccdad8
Author: Jasmine Tang <jjasmine at igalia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGen/builtin-isfpclass.c
Log Message:
-----------
[CIR] Upstream isfpclass op (#166037)
Ref commit in incubator: ee17ff67f3e567585db991cdad1159520c516bb4
There is a minor change in the assumption for emitting a direct callee.
In incubator, `bool hasAttributeNoBuiltin = false`
(`llvm-project/clang/lib/CIR/CodeGen/CIRGenExpr.cpp:1671`), while in
upstream, it's true, therefore, the call to finite(...) is not converted
to a builtin anymore.
Fixes #163892
Commit: 03f4d4d492b3f5e68645eac4e907f3f0fc7a4489
https://github.com/llvm/llvm-project/commit/03f4d4d492b3f5e68645eac4e907f3f0fc7a4489
Author: Hendrik Hübner <117831077+HendrikHuebner at users.noreply.github.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
A clang/test/CIR/CodeGen/cxx-special-member-attr.cpp
M clang/test/CIR/IR/func.cir
Log Message:
-----------
[CIR] Add CxxCTorAttr, CxxDTorAttr, CxxAssignAttr, CxxSpecialMemberAttr to cir::FuncOp (#167975)
This PR adds a special member attribute to `cir::FuncOp`. This attribute
is also present in the incubator repo. Additionally, I added a
"is_trivial" flag, to mark trivial members. I think that might be useful
when trying to replace calls to the copy constructor with memcpy for
example, but please let me know your thoughts on this. [Here in the
incubator
repo](https://github.com/llvm/clangir/blob/823e943d1b9aaba0fc46f880c5a6ac8c29fc761d/clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp#L1537-L1550)
this function is called `LowerTrivialConstructorCall`, but I don't see a
check that ensures the constructor is actually trivial.
Commit: 82380f33de0ef22e645cf53ba4bf859e38df6623
https://github.com/llvm/llvm-project/commit/82380f33de0ef22e645cf53ba4bf859e38df6623
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
Log Message:
-----------
[AMDGPU] Prioritize allocation of low 256 VGPR classes (#167978)
If we have 1024 VGPRs available we need to give priority to the
allocation of these registers where operands can only use low 256.
That is noteably scale operands of V_WMMA_SCALE instructions.
Otherwise large tuples will be allocated first and take all low
registers, so we would have to spill to get a room for these
scale registers.
Allocation priority itself does not eliminate spilling completely
in large kernels, although helps to some degree. Increasing spill
weight of a restricted class on top of it helps.
Commit: 80f862b6923f08b365d30c8480783aa91005e07a
https://github.com/llvm/llvm-project/commit/80f862b6923f08b365d30c8480783aa91005e07a
Author: Haocong Lu <haoconglu at qq.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
A clang/test/CIR/CodeGen/X86/bmi-builtins.c
A clang/test/CIR/CodeGen/X86/lzcnt-builtins.c
Log Message:
-----------
[CIR] Upstream CIR codegen for `lzcnt` and `tzcnt` x86 builtins (#168479)
Support CIR codegen for x86 builtins `__builtin_ia32_lzcnt` and
`__builtin_ia32_tzcnt`.
Commit: 835951325ec7aaf3336b19b53c9978d986e260df
https://github.com/llvm/llvm-project/commit/835951325ec7aaf3336b19b53c9978d986e260df
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/Tooling/DependencyScanning/DependencyScanningFilesystem.cpp
M clang/unittests/Tooling/DependencyScanning/DependencyScanningFilesystemTest.cpp
Log Message:
-----------
[clang][deps] Enable calling `DepScanFile::getBuffer()` repeatedly (#168789)
This PR makes it possible to call `getBuffer()` on `DepScanFile` (a
`llvm::vfs::File`) repeatedly. Previously, this function would return a
moved-from `unique_ptr`. This doesn't fix any existing bugs, I
discovered this while experimenting with the VFSs in the scanner. Note
that the returned instances of `llvm::MemoryBuffer` are non-owning and
share the underlying buffer storage.
Commit: ff39d59000df23a88ee25e180ecc1edae42998e7
https://github.com/llvm/llvm-project/commit/ff39d59000df23a88ee25e180ecc1edae42998e7
Author: Paddy McDonald <padriff at hotmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/stack_container_dynamic_lib.cpp
Log Message:
-----------
Disable test under GCC (#168792)
New test stack_container_dynamic_lib.cpp has errors under gcc.
Require clang while better fix is investigated
Commit: ef0cd1dae3a182fd721d18809ef38736cfd363c9
https://github.com/llvm/llvm-project/commit/ef0cd1dae3a182fd721d18809ef38736cfd363c9
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
Log Message:
-----------
[CIR][NFC] Fix warnings in release builds (#168791)
This fixes several warnings that occur in CIR release builds.
Commit: 7de59f0b247a481d81a3f2a4ce9f322c5a5c68ef
https://github.com/llvm/llvm-project/commit/7de59f0b247a481d81a3f2a4ce9f322c5a5c68ef
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
M mlir/test/Conversion/XeGPUToXeVM/create_nd_tdesc.mlir
M mlir/test/Conversion/XeGPUToXeVM/loadstore_1d.mlir
M mlir/test/Conversion/XeGPUToXeVM/loadstore_nd.mlir
Log Message:
-----------
[MLIR][Conversion] XeGPU to XeVM: Use adaptor for getting base address from memref. (#168610)
adaptor already lowers memref to base address.
Conversion patterns should use it instead of generating code to get base
address from memref.
Commit: af73aeaa19929127655d544b48a5145105e9e28c
https://github.com/llvm/llvm-project/commit/af73aeaa19929127655d544b48a5145105e9e28c
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
Log Message:
-----------
[MLIR][Vector] Add unroll pattern for vector.shape_cast (#167738)
This PR adds pattern for unrolling shape_cast given a targetShape. This
PR is a follow up of #164010 which was very general and was using
inserts and extracts on each element (which is also
LowerVectorShapeCast.cpp is doing).
After doing some more research on use cases, we (me and @Jianhui-Li )
realized that the previous version in #164010 is unnecessarily generic
and doesn't fit our performance needs.
Our use case requires that targetShape is contiguous in both source and
result vector.
This pattern only applies when contiguous slices can be extracted from
the source vector and inserted into the result vector such that each
slice remains in vector form with targetShape (and not decompose to
scalars). In these cases, the unrolling proceeds as:
vector.extract_strided_slice -> vector.shape_cast (on the slice
unrolled) -> vector.insert_strided_slice
Commit: 94e4ee38aa3b7085409b72702437822b5cec9e4e
https://github.com/llvm/llvm-project/commit/94e4ee38aa3b7085409b72702437822b5cec9e4e
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
Log Message:
-----------
[AMDGPU] Fixed crash in getLastMIForRegion when the region is empty. (#168653)
PreRARematStage builds region live-outs if GCN trackers are enabled. If
rematerialization leads to empty regions, this can cause a crash because
of dereference of an invalid iterator in getLastMIForRegion. The fix is
to skip calling getLastMIForRegion for empty regions.
This patch fixes another bug in the same code region. getLastMIForRegion
calls skipDebugInstructionsBackward which may immediately return the
RegionEnd if it is not the begin instruction and it is a non-debug
instruction. That would imply considering an instruction that is outside
the relevant region. The fix is to always pass the previous of RegionEnd
to skipDebugInstructionsBackward.
This bug was found while using GCN trackers on the existing LIT test
machine-scheduler-sink-trivial-remats.mir. Here's the assertion failure.
llvm-project/llvm/include/llvm/ADT/ilist_iterator.h:168:
llvm::ilist_iterator<OptionsT, IsReverse, IsConst>::reference
llvm::ilist_iterator<OptionsT, IsReverse, IsConst>::operator*() const
[with OptionsT = llvm::ilist_detail::node_options<llvm::MachineInstr,
true, true, void, false, void>; bool IsReverse = false; bool IsConst =
false; llvm::ilist_iterator<OptionsT, IsReverse, IsConst>::reference =
llvm::MachineInstr&]: Assertion `!NodePtr->isKnownSentinel()' failed.
Commit: b1c4b55118131cdf3d6d47ba31578b2e0cd78ec7
https://github.com/llvm/llvm-project/commit/b1c4b55118131cdf3d6d47ba31578b2e0cd78ec7
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/RenameIndependentSubregs.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/use-after-free-after-cleanup-failed-vreg.ll
Log Message:
-----------
RenameIndependentSubregs: try to only implicit def used subregs (#167486)
Attempt to only define used subregisters when creating IMPLICIT_DEF fix
ups for live interval subranges. This avoids the appearance at the MIR
level of entire (wide) registers becoming live rather than relying only
on transient LiveIntervals dead definitions for unused subregisters.
Commit: 4e275f727439af9589ee54bc6ac2e95fac9f63ae
https://github.com/llvm/llvm-project/commit/4e275f727439af9589ee54bc6ac2e95fac9f63ae
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/CodeGen/ABIInfo.cpp
M clang/lib/CodeGen/ABIInfo.h
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/X86.cpp
A clang/test/CodeGen/arm64ec-varargs.c
Log Message:
-----------
[Arm64EC][clang] Implement varargs support in clang. (#152411)
The clang side of the calling convention code for arm64 vs. arm64ec is
close enough that this isn't really noticeable in most cases, but the
rule for choosing whether to pass a struct directly or indirectly is
significantly different.
(Adapted from my old patch https://reviews.llvm.org/D125419 .)
Fixes #89615.
Commit: 2c3aa92089695713a1fd4264e80941fd9679150b
https://github.com/llvm/llvm-project/commit/2c3aa92089695713a1fd4264e80941fd9679150b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/gathered-node-with-in-order-parent.ll
A llvm/test/Transforms/SLPVectorizer/X86/matching-insert-point-for-nodes.ll
A llvm/test/Transforms/SLPVectorizer/X86/reused-last-instruction-in-split-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/shuffle-mask-emission.ll
Log Message:
-----------
[SLP]Fix insertion point for setting for the nodes
The problem with the many def-use chain problems in SLP vectorizer are
related to the fact that some nodes reuse the same instruction as
insertion point. Insertion point is not the instruction, but the place
between instructions. To set it correctly, better to generate pseudo
instruction immediately after the last instruction, and use it as
insertion point. It resolves the issues in most cases.
Fixes #168512 #168576
Commit: def8ecbda9f146d5ba5bbc8c92f7d5ccd242ad2b
https://github.com/llvm/llvm-project/commit/def8ecbda9f146d5ba5bbc8c92f7d5ccd242ad2b
Author: Sayan Saha <sayans at mathworks.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeDepthwise.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/test/Dialect/Tosa/tosa-decompose-depthwise.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
Log Message:
-----------
[tosa] : Relax dynamic dimension checks for batch for conv decompositions (#168764)
This PR relaxes the validation checks to allow input/output data to have
dynamic batch dimensions.
Commit: f9696949c3295c495e7337f4b1da9639610a15aa
https://github.com/llvm/llvm-project/commit/f9696949c3295c495e7337f4b1da9639610a15aa
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/include/clang/Basic/TargetID.h
M clang/lib/Basic/TargetID.cpp
M clang/lib/Driver/Driver.cpp
M clang/test/Driver/linker-wrapper-hip-no-rdc.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
Log Message:
-----------
[ClangLinkerWrapper] Refactor target ID sanitization for Windows file… (#168744)
… names
Fix non-RDC mode HIP compilation for the new driver on Windows due to
invalid temporary file names when offload arch is a target ID containing
':', which is invalid in file names on Windows.
Refactor the existing handling of ':' in file names on Windows from
clang driver into a shared function sanitizeTargetIDInFileName in
clang/Basic/TargetID.h. This function replaces ':' with '@' on Windows
only, preserving the original behavior.
Update both clang/lib/Driver/Driver.cpp and
clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp to use this
shared function, ensuring consistent handling across both tools.
Commit: 9e9fe08b16ea2c4d9867fb4974edf2a3776d6ece
https://github.com/llvm/llvm-project/commit/9e9fe08b16ea2c4d9867fb4974edf2a3776d6ece
Author: Gang Chen <gangc at amd.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vect-ptr-ptr-size-mismatch.ll
A llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/subchain-interleaved.ll
A llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-redund-loads.ll
Log Message:
-----------
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)
This is the fixed version of
https://github.com/llvm/llvm-project/pull/163019
Commit: beac880da5d265510806a2db004370808b974f44
https://github.com/llvm/llvm-project/commit/beac880da5d265510806a2db004370808b974f44
Author: Paddy McDonald <padriff at hotmail.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/stack_container_dynamic_lib.cpp
Log Message:
-----------
Better fix for the stack_container_dynamic_lib test (#168798)
Add the missing %libdl to the link command
Commit: 79fffed60a64ec548250d4d9bab236745c4987e4
https://github.com/llvm/llvm-project/commit/79fffed60a64ec548250d4d9bab236745c4987e4
Author: Jinjie Huang <huangjinjie at bytedance.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/DWP/DWP.cpp
A llvm/test/tools/llvm-dwp/X86/incompatible_dwarf_version.test
Log Message:
-----------
[llvm-dwp] Give more information when incompatible version found (#168511)
Provide more information when detecting a DWARF version mismatch in .dwo
files to help locate the issue and align with other similar errors.
Commit: fda20d99ae203d3c967072702f489ee993d1ffb9
https://github.com/llvm/llvm-project/commit/fda20d99ae203d3c967072702f489ee993d1ffb9
Author: Pranav Kant <prka at google.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Fix #165009 (#168804)
Commit: 3f151a3fa6ccb00523d8e0e36fa8d9046d5a936f
https://github.com/llvm/llvm-project/commit/3f151a3fa6ccb00523d8e0e36fa8d9046d5a936f
Author: Hristo Hristov <hristo.goshev.hristov at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/test/libcxx/utilities/smartptr/nodiscard.verify.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.obs/unique.deprecated_in_cxx17.verify.cpp
Log Message:
-----------
[libc++][memory] Applied `[[nodiscard]]` to smart pointers (#168483)
Applied `[[nodiscard]]` where relevant to smart pointers and related
functions.
- [x] - `std::unique_ptr`
- [x] - `std::shared_ptr`
- [x] - `std::weak_ptr`
See guidelines:
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
- `[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue. For example a locking
constructor in unique_lock.
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: 47b756a5a6c91e2a73f3965a1cbabb1801f2cb0c
https://github.com/llvm/llvm-project/commit/47b756a5a6c91e2a73f3965a1cbabb1801f2cb0c
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
Log Message:
-----------
[RISCV] Only reduce VLs of instructions with demanded VLs (#168693)
In RISCVVLOptimizer we first compute all the demanded VLs, then we walk
backwards through the function and try to reduce any VLs.
We don't actually need to walk backwards anymore since after #124530 the
order in which we modify the instructions doesn't matter.
This patch changes it to just iterate over the instructions with a
demanded VL computed, which means we don't iterate over scalar
instructions etc.
This also fixes #168665, where we triggered an assert on instructions
with a dead $vxsat implicit-def:
dead %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */,
0 /* tu, mu */, implicit-def dead $vxsat
Because $vxsat is a reserved register, DeadMachineInstructionElim won't
remove it and the instruction makes it to RISCVVLOptimizer.
And because the def of %x is dead, we don't reach this instruction in
the dataflow analysis. This instruction returns true for isCandidate, so
we would try to lookup its demanded VL which doesn't exist and assert.
But with this patch we don't try to reduce instructions that aren't in
DemandedVLs, which fixes the crash.
Commit: 7198279707cb77b7a81b54184a6293a49af16f7c
https://github.com/llvm/llvm-project/commit/7198279707cb77b7a81b54184a6293a49af16f7c
Author: marius doerner <marius.doerner1 at icloud.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/switch.cpp
Log Message:
-----------
[clang][bytecode] Implement case ranges (#168418)
Fixes #165969
Implement GNU case ranges for constexpr bytecode interpreter.
Commit: 13ed14f47eb3995942b2e4bba4ab37851b2751f9
https://github.com/llvm/llvm-project/commit/13ed14f47eb3995942b2e4bba4ab37851b2751f9
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
Log Message:
-----------
AMDGPU: Autogenerate checks in a test (#168815)
Commit: b39a9db3abc7abfa033a728ef29b5e5d3beb1cb5
https://github.com/llvm/llvm-project/commit/b39a9db3abc7abfa033a728ef29b5e5d3beb1cb5
Author: Volodymyr Sapsai <vsapsai at apple.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
A clang/test/ClangScanDeps/modules-current-modulemap-file-dep.c
M clang/test/ClangScanDeps/modules-fmodule-name-no-module-built.m
M clang/test/ClangScanDeps/modules-header-sharing.m
M clang/test/ClangScanDeps/modules-implementation-module-map.c
M clang/test/ClangScanDeps/modules-implementation-private.m
Log Message:
-----------
[clang][deps] Add module map describing compiled module to file dependencies. (#160226)
When we add the module map describing the compiled module to the command
line, add it to the file dependencies as well.
Discovered while working on reproducers where a command line input was
missing in the captured files as it wasn't considered a dependency.
Commit: 765208b3131ce26dc5845babe86457e204f97c02
https://github.com/llvm/llvm-project/commit/765208b3131ce26dc5845babe86457e204f97c02
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/test/Transforms/remove-dead-values.mlir
Log Message:
-----------
[mlir] Make remove-dead-values remove block and successorOperands before delete ops (#166766)
Reland https://github.com/llvm/llvm-project/pull/165725, fix the Failed
test by removing successor operands before delete operations. Following
the deletion of cond.branch, its successor operands will subsequently be
removed.
Commit: 7f0dbf049ab88e43b28db1999d8b2d49f9bf793b
https://github.com/llvm/llvm-project/commit/7f0dbf049ab88e43b28db1999d8b2d49f9bf793b
Author: Jinjie Huang <huangjinjie at bytedance.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/test/tools/llvm-dwp/X86/incompatible_dwarf_version.test
Log Message:
-----------
[NFC] Reduce the size of test input in incompatible_dwarf_version.test (#168825)
Use smaller test inputs in in incompatible_dwarf_version.test to reduce
disk usage and execution time.
Commit: db20a7f2bcec85490e6ff5c998a948ccbe88ae46
https://github.com/llvm/llvm-project/commit/db20a7f2bcec85490e6ff5c998a948ccbe88ae46
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Log Message:
-----------
DAG: Fix constructing a temporary TargetTransformInfo instance (#168480)
Commit: 86083447788f4d87eb61a1840a3f7374c24e46e0
https://github.com/llvm/llvm-project/commit/86083447788f4d87eb61a1840a3f7374c24e46e0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-19 (Wed, 19 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/CFIInstrInserter.cpp
M llvm/test/CodeGen/RISCV/cfi-multiple-locations.mir
M llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-loc.mir
Log Message:
-----------
[CFIInserter] Turn a reachable llvm_unreachable into a report_fatal_error. (#168777)
This prevents it from being optimized out in non-asserts builds.
Update X86 test to remove REQUIRES: asserts and check for LLVM ERROR.
Add FileCheck to RISC-V test and remove UNSUPPORTED.
This is the more complete fix for #168772 and #168525.
Commit: fde2aadb80020fe4a0fa887be5b6ca9d6df9564d
https://github.com/llvm/llvm-project/commit/fde2aadb80020fe4a0fa887be5b6ca9d6df9564d
Author: zhangtianhao6 <zhangtianhao6 at huawei.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/include/llvm/Support/CodeGen.h
Log Message:
-----------
[CodeGen] update code generation optimization level(nfc) (#168190)
Commit: 3e5fafdc223a937f371d22dc05d4ab8398b13f3f
https://github.com/llvm/llvm-project/commit/3e5fafdc223a937f371d22dc05d4ab8398b13f3f
Author: Brandon Wu <songwu0813 at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
Log Message:
-----------
[RISCV][llvm] Select splat_vector(constant) with PLI (#168204)
Default DAG combiner combine BUILD_VECTOR with same elements to
SPLAT_VECTOR, we can just map constant splat to PLI if possible.
Commit: dbf45253511616ee90bc39da8746caea4a9d3f10
https://github.com/llvm/llvm-project/commit/dbf45253511616ee90bc39da8746caea4a9d3f10
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
Log Message:
-----------
[AMDGPU] Add wave reduce intrinsics for float types - 1 (#161814)
Supported Ops: `fmin`, `fmax`
Commit: dcab4cb49bfb0aa17df3d3fabe582696100e0d35
https://github.com/llvm/llvm-project/commit/dcab4cb49bfb0aa17df3d3fabe582696100e0d35
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
Log Message:
-----------
[AMDGPU] Add wave reduce intrinsics for float types - 2 (#161815)
Supported Ops: `fadd`, `fsub`
Commit: e44646b79594006c9dc7deda6a9ae447243bd9e3
https://github.com/llvm/llvm-project/commit/e44646b79594006c9dc7deda6a9ae447243bd9e3
Author: Sam Parker <sam.parker at arm.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/test/CodeGen/WebAssembly/simd-arith.ll
M llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
Log Message:
-----------
[WebAssembly] Lower ANY_EXTEND_VECTOR_INREG (#167529)
Treat it in the same manner of zero_extend_vector_inreg and generate an
extend_low_u if possible. This is to try an prevent expensive shuffles
from being generated instead. computeKnownBitsForTargetNode has also
been updated to specify known zeros on extend_low_u.
Commit: 07a31adf287ca4d338232c6d79fe108a191007b4
https://github.com/llvm/llvm-project/commit/07a31adf287ca4d338232c6d79fe108a191007b4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bitcnt-big-integer.ll
M llvm/test/CodeGen/X86/build-vector-256.ll
M llvm/test/CodeGen/X86/chain_order.ll
M llvm/test/CodeGen/X86/merge-consecutive-loads-128.ll
M llvm/test/CodeGen/X86/merge-consecutive-loads-256.ll
M llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll
Log Message:
-----------
[X86] EltsFromConsecutiveLoads - recognise reverse load patterns. (#168706)
See if we can create a vector load from the src elements in reverse and
then shuffle these back into place.
SLP will (usually) catch this in the middle-end, but there are a few
BUILD_VECTOR scalarizations etc. that appear during DAG legalization.
I did start looking at a more general permute fold, but I haven't found
any good test examples for this yet - happy to take another look if
somebody has examples.
Commit: bdf598f8ddce4dbbd103b0a16c2253b7d71081fa
https://github.com/llvm/llvm-project/commit/bdf598f8ddce4dbbd103b0a16c2253b7d71081fa
Author: Jim Lin <jim at andestech.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/ARC/ARCISelLowering.cpp
M llvm/lib/Target/CSKY/CSKYISelLowering.cpp
M llvm/lib/Target/M68k/M68kISelLowering.cpp
Log Message:
-----------
CodeGen: Add missing subtarget to TargetLoweringBase constructor for ARC, CSKY and M68K (#168811)
Those were missing in https://github.com/llvm/llvm-project/pull/168620.
Commit: dc343d2f05ddffadae2b98760ff139622baa25f6
https://github.com/llvm/llvm-project/commit/dc343d2f05ddffadae2b98760ff139622baa25f6
Author: Kiran Kumar T P <50909805+kiranktp at users.noreply.github.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M flang/test/Lower/Intrinsics/command_argument_count.f90
M flang/test/Lower/Intrinsics/modulo.f90
M flang/test/Lower/OpenMP/Todo/omp-clause-indirect.f90
M flang/test/Lower/OpenMP/Todo/omp-declarative-allocate.f90
M flang/test/Lower/OpenMP/Todo/omp-declare-reduction-initsub.f90
M flang/test/Lower/OpenMP/Todo/omp-declare-reduction.f90
M flang/test/Lower/OpenMP/Todo/omp-declare-simd.f90
M flang/test/Lower/OpenMP/cray-pointers01.f90
M flang/test/Lower/OpenMP/cray-pointers02.f90
M flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90
M flang/test/Lower/OpenMP/parallel-wsloop-reduction-byref.f90
M flang/test/Lower/OpenMP/parallel-wsloop-reduction.f90
M flang/test/Semantics/indirect01.f90
M flang/test/Semantics/indirect02.f90
Log Message:
-----------
[NFC][flang] Replace use of flang -fc1 with %flang_fc1 in few test case (#168830)
Replace use of flang -fc1 with %flang_fc1 in few test case
Commit: 131cf7d5b2aa29b8018ac6422515ad2f522008c9
https://github.com/llvm/llvm-project/commit/131cf7d5b2aa29b8018ac6422515ad2f522008c9
Author: Aleksandr Nogikh <nogikh at google.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/CodeGenCXX/alloc-token.cpp
Log Message:
-----------
[AllocToken] Enable alloc token instrumentation for size-returning functions (#168840)
Consider a newly added "malloc_span" attribute in the allocation token
instrumentation to ensure that allocation functions with the
"malloc_span" attribute are processed similarly to other memory
allocation functions.
Update the tests to demonstrate applicability to __size_returning_new.
Commit: 54f69caf1f3e92ee147bac7e508ba65aff5ed1d5
https://github.com/llvm/llvm-project/commit/54f69caf1f3e92ee147bac7e508ba65aff5ed1d5
Author: Matthias Springer <me at m-sp.org>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/include/mlir/Pass/Pass.h
M mlir/lib/Pass/Pass.cpp
M mlir/test/Dialect/Transform/test-pass-application.mlir
A mlir/test/Pass/invalid-unsupported-operation.mlir
M mlir/test/Pass/pipeline-invalid.mlir
Log Message:
-----------
[mlir][Pass] Fix crash when applying a pass to an optional interface (#168499)
Interfaces can be optional: whether an op implements an interface or not
can depend on the state of the operation.
```
// An optional code block for adding additional "classof" logic. This can
// be used to better enable "optional" interfaces, where an entity only
// implements the interface if some dynamic characteristic holds.
// `$_attr`/`$_op`/`$_type` may be used to refer to an instance of the
// interface instance being checked.
code extraClassOf = "";
```
The current `Pass::canScheduleOn(RegisteredOperationName)` is
insufficient. This commit adds an additional overload to inspect
`Operation *`.
This commit fixes a crash when scheduling an `InterfacePass` for an
optional interface on an operation that does not actually implement the
interface.
Commit: 74cebce264bbfa335a411f08b647c05ce5a7eba3
https://github.com/llvm/llvm-project/commit/74cebce264bbfa335a411f08b647c05ce5a7eba3
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
Log Message:
-----------
Revert "[AMDGPU] Add wave reduce intrinsics for float types - 2 (#161… (#168845)
…815)"
This reverts commit dcab4cb49bfb0aa17df3d3fabe582696100e0d35.
Commit: 2cf550a040414aee51f7958812573723380b7a4b
https://github.com/llvm/llvm-project/commit/2cf550a040414aee51f7958812573723380b7a4b
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir
A llvm/test/DebugInfo/X86/no-prologue-end-after-line0-calls.mir
Log Message:
-----------
[DebugInfo] Force early line-zero calls to have meaningful locations (#156850)
In functions that have been seriously deformed during optimisation,
there can be call instructions with line-zero immediately after frame
setup (see C reproducer in the test added). Our previous algorithms for
prologue_end ignored these, meaning someone entering a function at
prologue_end would break-in after a function call had completed. Prefer
instead to place prologue_end and the function scope-line on the line
zero call: this isn't false (it's the first meaningful instruction of the
function) and is approximately true. Given a less than ideal function,
this is an OK solution.
Commit: 3396b4654b119a943f04f24cc582627597d0ba28
https://github.com/llvm/llvm-project/commit/3396b4654b119a943f04f24cc582627597d0ba28
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
Log Message:
-----------
[LV] Allow partial reductions with an extended bin op (#165536)
A pattern of the form reduce.add(ext(mul)) is valid for a partial
reduction as long as the mul and its operands fulfill the requirements
of a normal partial reduction. The mul's extend operands will be
optimised to the wider extend, and we already have oneUse checks in
place to make sure the mul and operands can be modified safely.
1. -> https://github.com/llvm/llvm-project/pull/165536
2. https://github.com/llvm/llvm-project/pull/165543
Commit: 95d788c76151222b7a28bdea9bf7eadc4a89fd02
https://github.com/llvm/llvm-project/commit/95d788c76151222b7a28bdea9bf7eadc4a89fd02
Author: Matthias Springer <me at m-sp.org>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/include/mlir/Pass/Pass.h
M mlir/lib/Pass/Pass.cpp
M mlir/test/Dialect/Transform/test-pass-application.mlir
R mlir/test/Pass/invalid-unsupported-operation.mlir
M mlir/test/Pass/pipeline-invalid.mlir
Log Message:
-----------
Revert "[mlir][Pass] Fix crash when applying a pass to an optional interface" (#168847)
Reverts llvm/llvm-project#168499
Commit: 53dfdf7ffd31b47e0b67d541b8d3aabd3948ddae
https://github.com/llvm/llvm-project/commit/53dfdf7ffd31b47e0b67d541b8d3aabd3948ddae
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
Log Message:
-----------
[X86] BuiltinsX86.td - attempt to pack the builtins for each SSE level close together. NFC. (#168844)
Avoid some repeated feature blocks - we should have a single place in
each file that we can find most builtins for a particular ISA level.
Also, avoid some of the 80col wrapping that just makes it harder to find
anything at all.
There's a lot more we can do - but I don't want to completely refactor
this while we still have so much work to do for #30794
Commit: 0a88e9622891aa111d07928d144e042174a9d570
https://github.com/llvm/llvm-project/commit/0a88e9622891aa111d07928d144e042174a9d570
Author: Zichen Lu <mikaovo2000 at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp
M mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir
Log Message:
-----------
[MLIR][LLVM] Extend DIScopeForLLVMFuncOp to handle cross-file operatio… (#167844)
The current `DIScopeForLLVMFuncOp` pass handles debug information for
inlined code by processing `CallSiteLoc` attributes. However, some
compilation scenarios compose code from multiple source files directly
into a single function without generating `CallSiteLoc`.
**Scenario:**
```python
# a.py
def kernel_a(tensor):
print("a: {}", tensor) # a.py:3
jit_func_b(tensor) # Calls b.py code
# b.py
def func_b(tensor):
print("b: {}", tensor) # b.py:7
```
The scenario executes Python at compile-time and directly inserts
operations from `b.py` into the kernel function, resulting in MLIR like:
```mlir
@kernel_a(...) {
print("a: {}", %arg0) loc(#loc_a) // a.py:3
print("b: {}", %arg0) loc(#loc_b) // b.py:7 <- FileLineColLoc, not CallSiteLoc
} loc(#loc_kernel) // a.py:1
#loc1 = loc("a.py":3:.)
#loc2 = loc("b.py":7:.)
#loc_a = loc("print"(#loc1))
#loc_b = loc("print"(#loc2))
```
```llvm
!6 = !DIFile(filename: "a.py", directory: "...")
!9 = distinct !DISubprogram(name: "...", linkageName: "...", scope: !6, file: !6, line: 13, ...)
!10 = !DILocation(line: 7, column: ., scope: !9) // Points to kernel's DISubprogram, not correct
```
Commit: 02db2de905136f291d0ed23bb51c72e7159016a9
https://github.com/llvm/llvm-project/commit/02db2de905136f291d0ed23bb51c72e7159016a9
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-vector-compress.ll
M llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll
Log Message:
-----------
[AArch64][SVE] Implement demanded bits for @llvm.aarch64.sve.cntp (#168714)
This allows DemandedBits to see that the SVE CNTP intrinsic will only
ever produce small positive integers. The maximum value you could get
here is 256, which is CNTP on a nxv16i1 on a machine with a 2048bit
vector size (the maximum for SVE).
Using this various redundant operations (zexts, sexts, ands, ors, etc)
can be eliminated.
Commit: a2b4c0fbe03896ee5a9218e1ec6e4184de6ed4be
https://github.com/llvm/llvm-project/commit/a2b4c0fbe03896ee5a9218e1ec6e4184de6ed4be
Author: sskzakaria <ssskzakaria at proton.me>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/avx512bwintrin.h
M clang/lib/Headers/avx512dqintrin.h
M clang/lib/Headers/avx512vlbwintrin.h
M clang/lib/Headers/avx512vldqintrin.h
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512dq-builtins.c
M clang/test/CodeGen/X86/avx512vlbw-builtins.c
M clang/test/CodeGen/X86/avx512vldq-builtins.c
Log Message:
-----------
[X86][Clang] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - allow AVX512 mask predicate intrinsics to be used in constexpr (#165054)
Enables constexpr evaluation for the following AVX512 Instrinsics:
```
_mm_movepi8_mask _mm256_movepi8_mask _mm512_movepi8_mask
_mm_movepi16_mask _mm256_movepi16_mask _mm512_movepi16_mask
_mm_movepi32_mask _mm256_movepi32_mask _mm512_movepi32_mask
_mm_movepi64_mask _mm256_movepi64_mask _mm512_movepi64_mask
```
Part of #162072
Commit: c6a79a55ff4cd79a6ebeb53109785abc5a010d06
https://github.com/llvm/llvm-project/commit/c6a79a55ff4cd79a6ebeb53109785abc5a010d06
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-identifier-naming in LLVMToLLVMIRTranslation.cpp (NFC)
Commit: 9e86c0d5daecf3a3095eb481764c4a5073cfcf2c
https://github.com/llvm/llvm-project/commit/9e86c0d5daecf3a3095eb481764c4a5073cfcf2c
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-container-size-empty in LinalgOps.cpp (NFC)
Commit: 3da82af83f0fa95860dc7cb661a7c64616a9425c
https://github.com/llvm/llvm-project/commit/3da82af83f0fa95860dc7cb661a7c64616a9425c
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseBufferRewriting.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for bugprone-argument-comment in SparseBufferRewriting.cpp (NFC)
Commit: 21c4c1502e3383988ba77eac75b13da7b9426957
https://github.com/llvm/llvm-project/commit/21c4c1502e3383988ba77eac75b13da7b9426957
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/sve-bf16-arith.ll
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Only use unpredicated bfloat instructions when all lanes are in use. (#168387)
While SVE support for exception safe floating point code generation is
bare bones we try to ensure inactive lanes remiain inert. I mistakenly
broke this rule when adding support for SVE-B16B16 by lowering some
bfloat operations of unpacked vectors to unpredicated instructions.
Commit: 76f1949cfa0d8fed73c153af83a7054073686506
https://github.com/llvm/llvm-project/commit/76f1949cfa0d8fed73c153af83a7054073686506
Author: Alexander Johnston <alexander.javen.johnston at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsSPIRVVK.td
M clang/lib/CodeGen/TargetBuiltins/SPIR.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaSPIRV.cpp
A clang/test/CodeGenHLSL/builtins/fwidth.hlsl
A clang/test/CodeGenSPIRV/Builtins/fwidth.c
A clang/test/SemaSPIRV/BuiltIns/fwidth-errors.c
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/DirectX/ddx_coarse-errors.ll
M llvm/test/CodeGen/DirectX/ddy_coarse-errors.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fwidth.ll
A llvm/test/CodeGen/SPIRV/opencl/fwidth-error.ll
Log Message:
-----------
[HLSL] Implement the `fwidth` intrinsic for DXIL and SPIR-V target (#161378)
Adds the fwidth intrinsic for HLSL.
The DXIL path only requires modification to the hlsl headers.
The SPIRV path implements the OpFwidth builtin in Clang and instruction
selection for the OpFwidth instruction in LLVM.
Also adds shader stage tests to the ddx_coarse and ddy_coarse
instructions used by fwidth.
Closes #99120
---------
Co-authored-by: Alexander Johnston <alexander.johnston at amd.com>
Commit: cfda27d0fbda65de4a7f482d46231933c9f2c678
https://github.com/llvm/llvm-project/commit/cfda27d0fbda65de4a7f482d46231933c9f2c678
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/LowerVectorScan.cpp
M mlir/test/Dialect/Vector/vector-scan-transforms.mlir
Log Message:
-----------
[mlir][Vector] Add support for scalable vectors to `ScanToArithOps` (#123117)
Note, scalable reductions dims are left as a TODO.
Commit: 150d9b7a779f405021b5a08718394772360a9ef8
https://github.com/llvm/llvm-project/commit/150d9b7a779f405021b5a08718394772360a9ef8
Author: mitchell <mitchell.xu2 at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M .git-blame-ignore-revs
Log Message:
-----------
[clang-tidy][NFC] Add clang-tidy formatting commit to `.git-blame-ignore-revs` (#167126)
Co-authored-by: Baranov Victor <bar.victor.2002 at gmail.com>
Commit: aeba7a8adef9a8ea624aa5be3b95a8a9fb5a17dd
https://github.com/llvm/llvm-project/commit/aeba7a8adef9a8ea624aa5be3b95a8a9fb5a17dd
Author: GrumpyPigSkin <130710602+GrumpyPigSkin at users.noreply.github.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDecl.cpp
A clang/test/Sema/warn-enum-compare-typo.c
Log Message:
-----------
[clang][diagnostics] added warning for possible enum compare typo (#168445)
Added diagnosis and fixit comment for possible accidental comparison
operator in an enum.
Closes: #168146
Commit: 4544ff68dc53ad427cfdbc9017d7328f09318484
https://github.com/llvm/llvm-project/commit/4544ff68dc53ad427cfdbc9017d7328f09318484
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M openmp/runtime/src/CMakeLists.txt
Log Message:
-----------
[OpenMP][AIX] Not to create symbolic links to libomp.so in install step (NFC) (#168585)
Commit bb563b1 handles the links in the build directory but
misses the case in the install step. This patch is to link only
the libomp.a on AIX.
Commit: e0850825cce17ebab14df41afa6fe19582a65de3
https://github.com/llvm/llvm-project/commit/e0850825cce17ebab14df41afa6fe19582a65de3
Author: Simone Pellegrini <simone.pellegrini at arm.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp
M mlir/test/Dialect/MemRef/transform-ops.mlir
Log Message:
-----------
[mlir][memref] Generalize dead store detection to all view-like ops (#168507)
The dead alloc elimination pass previously considered only subviews when
checking for dead stores. This change generalizes the logic to support
all view-like operations, ensuring broader coverage.
Commit: 4bb4ad477d80f66a267311afe9b656330caf3893
https://github.com/llvm/llvm-project/commit/4bb4ad477d80f66a267311afe9b656330caf3893
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
Log Message:
-----------
[AArch64][PAC] Use enum to describe LR signing condition (NFC) (#168548)
Express the condition of signing the return address in a function using
an `enum class` instead of a pair of `bool`s. Define `enum class
SignReturnAddress` with the values corresponding to the three possible
modes that can be requested via "sign-return-address" function
attribute.
Previously, there were two overloads of `shouldSignReturnAddress`
accepting either `const MachineFunction &` or `bool` argument. Due to
pointer-to-bool conversion, when `shouldSignReturnAddress` was
incorrectly called with `const MachineFunction *` argument, the latter
overload was used instead of reporting a compile-time error.
Commit: 5d0bfd1bf8ac6b1ceb37c7f30058d0f62e636036
https://github.com/llvm/llvm-project/commit/5d0bfd1bf8ac6b1ceb37c7f30058d0f62e636036
Author: Shashi Shankar <shashishankar1687 at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/lib/Conversion/SCFToGPU/SCFToGPU.cpp
M mlir/test/Conversion/SCFToGPU/parallel_loop.mlir
Log Message:
-----------
[MLIR][SCFToGPU] Guard operands before AffineApplyOp::create to avoid crash (#167959)
This fixes a crash in SCF→GPU when building the per‑dim index for mapped
scf.parallel.
**Change**:
- Map step/lb through cloningMap, then run ensureLaunchIndependent.
- If either is still unavailable at launch scope, emit a match‑failure;
otherwise build the affine.apply.
**Why this is correct:**
- Matches how the pass already handles launch bounds; avoids creating an
op with invalid operands and replaces a segfault with a clear
diagnostic.
**Tests**:
- Added two small regressions that lower to gpu.launch and exercise the
affine.apply path.
Fixes : #167654
Signed-off-by: Shashi Shankar <shashishankar1687 at gmail.com>
Commit: 0e8222b84b60c022b2cee308f79a185a943ff514
https://github.com/llvm/llvm-project/commit/0e8222b84b60c022b2cee308f79a185a943ff514
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.td
M flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/test/Fir/declare-codegen.fir
A flang/test/Integration/debug-module-equivalence.f90
M flang/test/Transforms/debug-common-block.fir
Log Message:
-----------
[flang][debug] Make common blocks data extraction more robust. (#168752)
Our current implementation for extracting information about common block
required traversal of FIR which was not ideal but previously there was
no other way to obtain that information. The `[hl]fir.declare` was
extended in commit https://github.com/llvm/llvm-project/pull/155325 to
include storage and storage_offset. This commit adds these operands in
`fircg.ext_declare` and then use them in `AddDebugInfoPass` to create
debug data for common blocks.
Commit: a9a14d64d20bfb28abdd7a63cac459b5f6b5ee91
https://github.com/llvm/llvm-project/commit/a9a14d64d20bfb28abdd7a63cac459b5f6b5ee91
Author: Carlos Seo <carlos.seo at linaro.org>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M flang-rt/lib/runtime/type-code.cpp
M flang-rt/unittests/Runtime/CMakeLists.txt
A flang-rt/unittests/Runtime/TypeCode.cpp
Log Message:
-----------
[flang-rt] Fix TypeCategory for quad-precision COMPLEX (#168090)
Modify the TypeCategory for quad-precision COMPLEX to
CFI_type_float128_Complex so it matches the TypeCode returned
by SELECT TYPE lowering.
Fixes #134565
Commit: 364fe55c42aaac63b2a28e54fa4e31cc6efcf4a8
https://github.com/llvm/llvm-project/commit/364fe55c42aaac63b2a28e54fa4e31cc6efcf4a8
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/test/Lower/HLFIR/allocatable-and-pointer-status-change.f90
M flang/test/Lower/HLFIR/issue80884.f90
M flang/test/Lower/HLFIR/proc-pointer-comp-nopass.f90
M flang/test/Lower/HLFIR/procedure-pointer.f90
M flang/test/Lower/OpenMP/parallel-private-clause.f90
A flang/test/Lower/pointer-disassociate-character.f90
M flang/test/Lower/volatile3.f90
M flang/test/Lower/volatile4.f90
Log Message:
-----------
[flang] simplify pointer assignments (#168732)
Pointer assignment lowering was done in different ways depending on
contexts and types, sometimes still using runtime calls when this is not
needed and the complexity of doing this inline is very limited (the
pointer and target descriptors were already prepared inline, the runtime
is just doing the descriptor assignment and ensuring the pointer
descriptor keep its pointer flag).
Slightly extent the inline version that was used for Forall and use it
for all cases.
When lowering without HLFIR is removed, this will allow removing more
code.
Commit: a74bfc06e83c30bc48e05caa2b27b012d57c5d36
https://github.com/llvm/llvm-project/commit/a74bfc06e83c30bc48e05caa2b27b012d57c5d36
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
Log Message:
-----------
[mlir][tosa] Fix select folder when operands are broadcast (#165481)
This commit addresses a crash in the dialects folder. The currently
folder assumes no broadcasting of the input operand happens and
therefore the folder can complain that the returned value was not the
same
shape as the result.
For now, this commit ensures no folding happens when broadcasting is
involved. In the future, folding with a broadcast could likely be
supported by inserting a `tosa.tile` operation before returning the
operand. This type of transformation is likely better suited for a
canonicalization pass. This commit only aims to avoid the crash.
Commit: aa3f930931e65b02bacac0c7dfa52a181a0fd5bb
https://github.com/llvm/llvm-project/commit/aa3f930931e65b02bacac0c7dfa52a181a0fd5bb
Author: lntue <lntue at google.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M libc/src/__support/math/CMakeLists.txt
M libc/src/__support/math/atanf.h
A libc/src/__support/math/atanf_float.h
M libc/test/src/math/atanf_test.cpp
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/atanf_float_test.cpp
Log Message:
-----------
[libc][math] Add float-only implementation for atanf. (#167004)
Algorithm:
```
1) atan(x) = sign(x) * atan(|x|)
2) If |x| > 1 + 1/32, atan(|x|) = pi/2 - atan(1/|x|)
3) For 1/16 < |x| < 1 + 1/32, we find k such that: | |x| - k/16 | <= 1/32.
Let y = |x| - k/16, then using the angle summation formula, we have:
atan(|x|) = atan(k/16) + atan( (|x| - k/16) / (1 + |x| * k/16) )
= atan(k/16) + atan( y / (1 + (y + k/16) * k/16 )
= atan(k/16) + atan( y / ((1 + k^2/256) + y * k/16) )
4) Let u = y / (1 + k^2/256), then we can rewritten the above as:
atan(|x|) = atan(k/16) + atan( u / (1 + u * k/16) )
~ atan(k/16) + (u - k/16 * u^2 + (k^2/256 - 1/3) * u^3 +
+ (k/16 - (k/16)^3) * u^4) + O(u^5)
```
With all the computations are done in single precision (float), the
total of approximation errors and rounding errors is bounded by 4 ULPs.
Commit: 07e893205ae78da3d6b46a87e05b3af6d09c5abd
https://github.com/llvm/llvm-project/commit/07e893205ae78da3d6b46a87e05b3af6d09c5abd
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/test/Analysis/CostModel/AMDGPU/shufflevector.ll
Log Message:
-----------
AMDGPU: Expand cost model shufflevector test (#168816)
Add a few corner cases of the "simplified" shuffle kinds.
Commit: 0b6a74ced013fcbcc7e3d072efa9af39d33b4520
https://github.com/llvm/llvm-project/commit/0b6a74ced013fcbcc7e3d072efa9af39d33b4520
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-chain-to-shuffles.ll
A llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-i8.ll
Log Message:
-----------
VectorCombine/AMDGPU: Cleanup a test and add a new one (#168817)
The existing, recently added test contains a whole lot of noise in the
form of dead instructions. Also, prefer named values.
The new test isolates a separate issue with concatenating i8 vectors.
Commit: 0e5466767268096bd7d03c50810f2d4c0b37a598
https://github.com/llvm/llvm-project/commit/0e5466767268096bd7d03c50810f2d4c0b37a598
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
Log Message:
-----------
[CodeGen] Use MCRegister in MachineBasicBlock::liveout_iterator. NFC (#168834)
MachineBasicBlock::liveout_begin() calls this constructor with
MCRegisters so this removes an implicit cast.
Commit: 891b3cf63e160c83309b90728034ab832184c964
https://github.com/llvm/llvm-project/commit/891b3cf63e160c83309b90728034ab832184c964
Author: Igor Wodiany <igor.wodiany at imgtec.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/docs/Dialects/SPIR-V.md
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td
M mlir/lib/Dialect/SPIRV/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOpDefinition.cpp
M mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.h
M mlir/lib/Target/SPIRV/Serialization/SerializeOps.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.h
M mlir/test/Dialect/SPIRV/IR/control-flow-ops.mlir
M mlir/test/Target/SPIRV/selection.mlir
Log Message:
-----------
[mlir][spirv] Add support for SwitchOp (#168713)
The dialect implementation mostly copies the one of `cf.switch`, but
aligns naming to the SPIR-V spec.
Commit: bb0a95d5b16dabd8e64c6672ec381215a144d92d
https://github.com/llvm/llvm-project/commit/bb0a95d5b16dabd8e64c6672ec381215a144d92d
Author: David Tenty <daltenty at ibm.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/cmake/modules/HandleLLVMOptions.cmake
Log Message:
-----------
[CMake] handle the AIX form of the lto cache dir option (#168868)
This handles the AIX form of the thinLTO cache dir option, which get's
turned on when thinLTO is enabled.
Commit: b5812c0cf789aa4cb60d42681cb2e46a417e1bc7
https://github.com/llvm/llvm-project/commit/b5812c0cf789aa4cb60d42681cb2e46a417e1bc7
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/LoongArch/CMakeLists.txt
M llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
A llvm/lib/Target/LoongArch/LoongArchSelectionDAGInfo.cpp
A llvm/lib/Target/LoongArch/LoongArchSelectionDAGInfo.h
M llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
M llvm/lib/Target/LoongArch/LoongArchSubtarget.h
Log Message:
-----------
[LoongArch] TableGen-erate SDNode descriptions (#168129)
This allows SDNodes to be validated against their expected type profiles
and reduces the number of changes required to add a new node.
I had to split `VSHUF4I` into two variants (`VSHUF4I` and `VSHUF4I_D`)
since `loongarch_vshuf4i` and `loongarch_vshuf4i_d` have different
number of operands, and this prevented the node from being imported.
There is just one node that currently fails validation, see
`LoongArchSelectionDAGInfo::verifyTargetNode()`.
Part of #119709.
Pull Request: https://github.com/llvm/llvm-project/pull/168129
Commit: 0c085c43a120c6a05107d208f002b97a29375cf2
https://github.com/llvm/llvm-project/commit/0c085c43a120c6a05107d208f002b97a29375cf2
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/include/module.modulemap
Log Message:
-----------
Fix build breakage when using modules (#168883)
Commit c9f573463ebd7b4e46da4877802f2364f700e54a removed the file
TargetLibraryInfo.def but did not remove it from the module map.
Commit: 21fedcbf89a27521c1c4822c51232605e2c3a33f
https://github.com/llvm/llvm-project/commit/21fedcbf89a27521c1c4822c51232605e2c3a33f
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/include/llvm/Support/BranchProbability.h
M llvm/lib/Support/BranchProbability.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
A llvm/test/Transforms/LoopUnroll/branch-weights-freq/peel-last-iteration-no-guard.ll
Log Message:
-----------
[LoopPeel] Fix BFI when peeling last iteration without guard (#168250)
LoopPeel sometimes proves that, when reached, the original loop always
executes at least two iterations. LoopPeel then unconditionally executes
both the remaining loop's initial iteration and the peeled final
iteration. But that increases the latter's frequency above its frequency
in the original loop. To maintain the total frequency, this patch
compensates by decreasing the remaininng loop's latch probability.
This is another step in issue #135812 and was discussed at
<https://github.com/llvm/llvm-project/pull/166858#discussion_r2528968542>.
Commit: b725bdba1faf256c725f5fd12c581acb381bf0d3
https://github.com/llvm/llvm-project/commit/b725bdba1faf256c725f5fd12c581acb381bf0d3
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M compiler-rt/test/lit.common.cfg.py
Log Message:
-----------
Reapply "[compiler-rt] Default to Lit's Internal Shell (#168232)" (#168760)
This reverts commit eb20b5392599996ce94e4c0392095cacaa33687c.
This relands the compiler-rt internal shell after XRay and Darwin tests
that were failing under the internal shell have been fixed.
Commit: 67e35bbebbed5e33a173751d019c22e4effa65fd
https://github.com/llvm/llvm-project/commit/67e35bbebbed5e33a173751d019c22e4effa65fd
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
Log Message:
-----------
[LV] Check full partial reduction chains in order. (#168036)
https://github.com/llvm/llvm-project/pull/162822 added another
validation step to check if entries in a partial reduction chain have
the same scale factor. But the validation was still dependent on the
order of entries in PartialReductionChains, and would fail to reject
some cases (e.g. if the first first link matched the scale of the second
link, but the second link is invalidated later).
To fix that, group chains by their starting phi nodes, then perform the
validation for each chain, and if it fails, invalidate the whole chain
for the phi.
Fixes https://github.com/llvm/llvm-project/issues/167243.
Fixes https://github.com/llvm/llvm-project/issues/167867.
PR: https://github.com/llvm/llvm-project/pull/168036
Commit: 53b26971f5192713bd3cc01ed31e48b4ea0b4d2c
https://github.com/llvm/llvm-project/commit/53b26971f5192713bd3cc01ed31e48b4ea0b4d2c
Author: Mikhail Gudim <mgudim at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/cfi-multiple-locations.mir
Log Message:
-----------
[RISCV] Do not write .s file in a test (#168865)
Commit: d3c3c6bab5df051d9db12ea96add2211df9d81be
https://github.com/llvm/llvm-project/commit/d3c3c6bab5df051d9db12ea96add2211df9d81be
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
Log Message:
-----------
AMDGPU: Fix treating divergent loads as uniform (#168785)
Avoids regression which caused the revert 6d5f87fc42.
This is a hack on a hack. We currently have isUniformMMO,
which improperly treats unknown source value as known uniform.
This is hack from before we had divergence information in the
DAG, and should be removed. This is the minimum change to avoid
the regression; removing the aggressive handling of the unknown
case (or dropping isUniformMMO entirely) are more involved fixes.
Commit: 5b8656ccb12db34793a5a16a0a2c030763e00a07
https://github.com/llvm/llvm-project/commit/5b8656ccb12db34793a5a16a0a2c030763e00a07
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/test/CIR/CodeGen/vector-ext-element.cpp
Log Message:
-----------
[CIR] ExtVectorElementExpr with rvalue base (#168260)
Upstream ExtVectorElementExpr with rvalue base
Commit: b9d98110e198c864616593966d1dadc79a606309
https://github.com/llvm/llvm-project/commit/b9d98110e198c864616593966d1dadc79a606309
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Utils/ProfileVerify.cpp
A llvm/test/Transforms/PGOProfile/profcheck-exclusions.ll
Log Message:
-----------
[profcheck] Exclude `naked`, asm-only functions from profcheck (#168447)
We can't do anything meaningful to such functions: they aren't optimizable, and even if inlined, they would bring no code open to optimization.
Commit: 6c79cc7ff7901e9c8a3a4e924abd0e9dbfae039c
https://github.com/llvm/llvm-project/commit/6c79cc7ff7901e9c8a3a4e924abd0e9dbfae039c
Author: Kavin Gnanapandithan <kavin.balag at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/ldexp-avx512.ll
Log Message:
-----------
[X86] Lower mathlib call ldexp into scalef when avx512 is enabled (#166839)
Resolves #165694
Commit: 6ce4794c547600842eace9e01012f93850a22556
https://github.com/llvm/llvm-project/commit/6ce4794c547600842eace9e01012f93850a22556
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
Log Message:
-----------
[AMDGPU] Precommit tests for V_CVT_PK_[IU]16_F32 (#168893)
Commit: 602fa0c7ce4282be916613f5d056adaff11a3900
https://github.com/llvm/llvm-project/commit/602fa0c7ce4282be916613f5d056adaff11a3900
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Log Message:
-----------
[SDAG] Fix whitespace errors (NFC) (#168897)
To make life easier for future contributors. Note that formatting
changes are due to git clang-format on the touched whitespace-error
lines.
Commit: 7ca737d632d387c9471b84b9ae916eae2a210640
https://github.com/llvm/llvm-project/commit/7ca737d632d387c9471b84b9ae916eae2a210640
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M flang/test/Lower/select-case-statement.f90
Log Message:
-----------
[flang] Switch select-case-statement.f90 to new lowering (#168754)
test/Lower/select-case-statement.f90 was still using the old lowering.
Modified the test with FIR generated using the new lowering. Changed the
test to use flang_fc1 instead of bbc and added testing for -O0 and -O1,
since character comparison lowering is done differently at -O0 (uses
runtime function) and -O1 (inlines some cases). Use different FileCheck
prefixes for different optimization levels (CHECK-O0 for -O0, CHECK-O1
for -O1, CHECK for both).
Commit: 0e1cb2de90aafa1d5dbd46fc9e6c4e743700fa8b
https://github.com/llvm/llvm-project/commit/0e1cb2de90aafa1d5dbd46fc9e6c4e743700fa8b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
M llvm/test/CodeGen/AMDGPU/select-load-to-load-select-ptr-combine.ll
M llvm/test/CodeGen/AMDGPU/select-vectors.ll
M llvm/test/CodeGen/AMDGPU/select64.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/bug22246.ll
M llvm/test/CodeGen/NVPTX/fast-math.ll
M llvm/test/CodeGen/NVPTX/i1-select.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
Log Message:
-----------
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
This reverts commit 6d5f87fc4284c4c22512778afaf7f2ba9326ba7b.
Previously this failed due to treating the unknown MachineMemOperand
value as known uniform.
Commit: 4aee501b0e6c4a0de6ab32dec1c8382847d56112
https://github.com/llvm/llvm-project/commit/4aee501b0e6c4a0de6ab32dec1c8382847d56112
Author: Nico Weber <thakis at chromium.org>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
A llvm/utils/gn/secondary/llvm/include/llvm/Analysis/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/Basic/BUILD.gn
Log Message:
-----------
[gn] port c9f573463ebd (TargetLibraryInfo.inc)
Commit: a07024080aea99808f5436d038887e46604d1615
https://github.com/llvm/llvm-project/commit/a07024080aea99808f5436d038887e46604d1615
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel][LoongArch] Port #168129: tablegen for sdnode (#168907)
Commit: 66ddc9b3e7e22a0c2464c54d96bc30c53ab9cbd1
https://github.com/llvm/llvm-project/commit/66ddc9b3e7e22a0c2464c54d96bc30c53ab9cbd1
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M offload/include/Shared/Debug.h
M offload/libomptarget/OffloadRTL.cpp
M offload/libomptarget/PluginManager.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
Log Message:
-----------
[OFFLOAD] Add support for more fine grained debug messages control (#165416)
This PR introduces new debug macros that allow a more fined control of
which debug message to output and introduce C++ stream style for debug
messages.
Changing existing messages (except a few that I changed for testing)
will come in subsequent PRs.
I also think that we should make debug enabling OpenMP agnostic but, for
now, I prioritized maintaing the current libomptarget behavior for now,
and we might need more changes further down the line as we we decouple
libomptarget.
Commit: ccdb71932aa84a36f3d9689eca97b80bf643c500
https://github.com/llvm/llvm-project/commit/ccdb71932aa84a36f3d9689eca97b80bf643c500
Author: Igor Kudrin <ikudrin at accesssoftek.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M lldb/test/API/functionalities/breakpoint/hardware_breakpoints/simple_hw_breakpoints/TestSimpleHWBreakpoints.py
Log Message:
-----------
[lldb] Fix a test if hardware breakpoints are not supported (#168813)
If `HardwareBreakpointTestBase.supports_hw_breakpoints()` returns False,
`SimpleHWBreakpointTest.does_not_support_hw_breakpoints()` returns None,
so the test runs and fails. However, it should be skipped instead.
The test was added in #146602, while `supports_hw_breakpoints()` was
changed in #146609, which was landed earlier despite having a bigger
number.
Commit: e96cc996875f58306aa7f28f2e47b51cadc180b7
https://github.com/llvm/llvm-project/commit/e96cc996875f58306aa7f28f2e47b51cadc180b7
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/simplified_template_names.test
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
Log Message:
-----------
[llvm][DebugInfo] Unwrap template parameters that are typedefs when reconstructing DIE names (#168734)
Depends on:
* https://github.com/llvm/llvm-project/pull/168725
When compiling with `-glldb`, we repoint the `DW_AT_type` of a DIE to be
a typedef that refers to the `preferred_name`. I.e.,:
```
template <typename T> structure t7;
using t7i = t7<int>;
template <typename T> struct __attribute__((__preferred_name__(t7i))) t7 {};
template <typename... Ts> void f1()
int main() { f1<t7i>(); }
```
would produce following (minified) DWARF:
```
DW_TAG_subprogram
DW_AT_name ("_STN|f1|<t7<int> >")
DW_TAG_template_type_parameter
DW_AT_type (0x0000299c "t7i")
...
DW_TAG_typedef
DW_AT_type (0x000029a7 "t7<int>")
DW_AT_name ("t7i")
```
Note how the `DW_AT_type` of the template parameter is a typedef itself
(instead of the canonical type). The `DWARFTypePrinter` would take the
`DW_AT_name` of this typedef when reconstructing the name of `f1`, so we
would end up with a verifier failure:
```
error: Simplified template DW_AT_name could not be reconstituted:
original: f1<t7<int> >
reconstituted: f1<t7i>
```
Fixing this allows us to un-XFAIL the `simplified-template-names.cpp`
test in `cross-project-tests`. Unfortunately this is only tested on
Darwin, where LLDB tuning is the default. AFAIK, there is no other case
where the template parameter type wouldn't be canonical.
Commit: f1630814ada4ce504f490440c3ae709d7bfa521a
https://github.com/llvm/llvm-project/commit/f1630814ada4ce504f490440c3ae709d7bfa521a
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
A llvm/test/tools/dsymutil/AArch64/DWARFLinkerParallel/accel-imported-declarations.test
A llvm/test/tools/dsymutil/AArch64/accel-imported-declarations.test
A llvm/test/tools/dsymutil/AArch64/call-pc-reloc.test
A llvm/test/tools/dsymutil/AArch64/debug-names-accel-table-types.ll
A llvm/test/tools/dsymutil/AArch64/discriminator.test
A llvm/test/tools/dsymutil/AArch64/discriminator_repeated.test
A llvm/test/tools/dsymutil/AArch64/dummy-debug-map-arm64.map
A llvm/test/tools/dsymutil/AArch64/dwarf5-addr-base.test
A llvm/test/tools/dsymutil/AArch64/dwarf5-addrx-0x0-last.test
A llvm/test/tools/dsymutil/AArch64/dwarf5-dwarf4-combination-macho.test
A llvm/test/tools/dsymutil/AArch64/dwarf5-macho.test
A llvm/test/tools/dsymutil/AArch64/dwarf5-str-offsets-base-strx.test
A llvm/test/tools/dsymutil/AArch64/extern-alias.test
A llvm/test/tools/dsymutil/AArch64/fat-arch-name.test
A llvm/test/tools/dsymutil/AArch64/fat-threading.test
A llvm/test/tools/dsymutil/AArch64/firmware.test
A llvm/test/tools/dsymutil/AArch64/inline-source.test
A llvm/test/tools/dsymutil/AArch64/inlined-low_pc.c
A llvm/test/tools/dsymutil/AArch64/lit.local.cfg
A llvm/test/tools/dsymutil/AArch64/missing-object-warning.test
A llvm/test/tools/dsymutil/AArch64/missing-symbol-warning.test
A llvm/test/tools/dsymutil/AArch64/preload.test
A llvm/test/tools/dsymutil/AArch64/remarks-linking-bundle-empty.test
A llvm/test/tools/dsymutil/AArch64/remarks-linking-bundle.test
A llvm/test/tools/dsymutil/AArch64/static-archive-collision.test
A llvm/test/tools/dsymutil/AArch64/stmt-seq-macho.test
A llvm/test/tools/dsymutil/AArch64/suppressions.txt
A llvm/test/tools/dsymutil/AArch64/swiftmodule-include-from-interface.test
A llvm/test/tools/dsymutil/AArch64/swiftmodule.test
A llvm/test/tools/dsymutil/AArch64/typedefs-with-same-name.test
R llvm/test/tools/dsymutil/ARM/DWARFLinkerParallel/accel-imported-declarations.test
R llvm/test/tools/dsymutil/ARM/accel-imported-declarations.test
R llvm/test/tools/dsymutil/ARM/call-pc-reloc.test
R llvm/test/tools/dsymutil/ARM/debug-names-accel-table-types.ll
R llvm/test/tools/dsymutil/ARM/discriminator.test
R llvm/test/tools/dsymutil/ARM/discriminator_repeated.test
R llvm/test/tools/dsymutil/ARM/dummy-debug-map-amr64.map
R llvm/test/tools/dsymutil/ARM/dwarf5-addr-base.test
R llvm/test/tools/dsymutil/ARM/dwarf5-addrx-0x0-last.test
R llvm/test/tools/dsymutil/ARM/dwarf5-dwarf4-combination-macho.test
R llvm/test/tools/dsymutil/ARM/dwarf5-macho.test
R llvm/test/tools/dsymutil/ARM/dwarf5-str-offsets-base-strx.test
R llvm/test/tools/dsymutil/ARM/extern-alias.test
R llvm/test/tools/dsymutil/ARM/fat-arch-name.test
R llvm/test/tools/dsymutil/ARM/fat-threading.test
R llvm/test/tools/dsymutil/ARM/firmware.test
R llvm/test/tools/dsymutil/ARM/inline-source.test
R llvm/test/tools/dsymutil/ARM/inlined-low_pc.c
M llvm/test/tools/dsymutil/ARM/lit.local.cfg
R llvm/test/tools/dsymutil/ARM/missing-object-warning.test
R llvm/test/tools/dsymutil/ARM/missing-symbol-warning.test
R llvm/test/tools/dsymutil/ARM/preload.test
R llvm/test/tools/dsymutil/ARM/remarks-linking-bundle-empty.test
R llvm/test/tools/dsymutil/ARM/remarks-linking-bundle.test
R llvm/test/tools/dsymutil/ARM/static-archive-collision.test
R llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test
R llvm/test/tools/dsymutil/ARM/swiftmodule-include-from-interface.test
R llvm/test/tools/dsymutil/ARM/swiftmodule.test
R llvm/test/tools/dsymutil/ARM/typedefs-with-same-name.test
Log Message:
-----------
[llvm][dsymutil][test] Create dedicated AArch64 directory (#168895)
Currently the tests for LLVM targets `AArch64` and `ARM` were in the
same directory. But if you only configured LLVM for one target (e.g.,
just `AArch64`, which is how I ran into this), then all tests under the
ARM directory are marked `UNSUPPORTED`.
This patch moves all the tests that are capable of running on
`AArch64`-only targets into a dedicated `AArch64` directory. The tests
that expected a plain `ARM` target were kept in the `ARM` directory.
Drive-by:
* Rename the `dummy-debug-map-amr64.map` to `dummy-debug-map-arm64.map`
(note the typo in `amr64`)
Commit: 62deee41592d7522d7fc3c3686d657bc36d80638
https://github.com/llvm/llvm-project/commit/62deee41592d7522d7fc3c3686d657bc36d80638
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M lldb/bindings/interface/SBFrameExtensions.i
Log Message:
-----------
[LLDB] Add a child property to compliment the existing parent property (#168619)
I've been working on some scripts that evaluate the parent and child
frame. It's been very annoying that the parent frame has a property but
not the child. So I've added this to the extensions, I would've
preferred to return None, but because the existing impl returns an
invalid SBFrame, so I'm conforming to that API.
```
(lldb) script
Python Interactive Interpreter. To exit, type 'quit()', 'exit()' or Ctrl-D.
>>> lldb.frame
frame #0: 0x0000555555555200 fib.out`main
>>> lldb.frame.parent
frame #1: 0x00007ffff782a610 libc.so.6`__libc_start_call_main + 128
>>> lldb.frame.parent.child
frame #0: 0x0000555555555200 fib.out`main
```
Commit: e79c7c18d675a10e03c2942960d68f02f1a54f1f
https://github.com/llvm/llvm-project/commit/e79c7c18d675a10e03c2942960d68f02f1a54f1f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
Log Message:
-----------
AMDGPU: Handle invariant loads when considering if a load can be scalar (#168787)
Commit: 6d52efca67789f2e8d575b426d97b1ddf6c8d937
https://github.com/llvm/llvm-project/commit/6d52efca67789f2e8d575b426d97b1ddf6c8d937
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M .github/workflows/bazel-checks.yml
Log Message:
-----------
[Github] Error on HTTP 4xx Errors (#168919)
When downloading bazelisk/buildifier, we use curl, which still returns
exit code zero on HTTP 4xx errors unless we pass --fail. This patch adds
--fail flags so that error messages are more clear.
Commit: 01e5e4fd001c960e197ac377cd06ea177b320964
https://github.com/llvm/llvm-project/commit/01e5e4fd001c960e197ac377cd06ea177b320964
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAGCombiner] Remove unneeded m_BitReverse from visitBITREVERSE. NFC (#168918)
We already know we're looking at BITREVERSE, we can match on the source
operand.
Commit: bfbd191f35352df2decde46d117bb940864889bf
https://github.com/llvm/llvm-project/commit/bfbd191f35352df2decde46d117bb940864889bf
Author: David Stone <davidfromonline at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/include/mlir/IR/PDLPatternMatch.h.inc
M mlir/lib/Rewrite/ByteCode.cpp
M mlir/lib/Rewrite/ByteCode.h
Log Message:
-----------
[mlir] Replace `llvm::OwningArrayRef` with `std::vector` (#168803)
There are several places where we use `llvm::OwningArrayRef`. The
interface to this requires us to first construct temporary storage, then
allocate space and set the allocated memory to 0, then copy the values
we actually want into that memory, then move the array into place.
Instead we can just do it all inline in a single pass by using
`std::vector`. In one case we actually allocate a completely separate
container and then allocate + copy the data over because
`llvm::OwningArrayRef` does not (and can't) support `push_back`.
Note that `llvm::SmallVector` is not a suitable replacement here because
we rely on reference stability on move construction: when the outer
container reallocates, we need the the contents of the inner containers
to be fixed in memory, and `llvm::SmallVector` does not give us that
guarantee.
Commit: 41008451260e4b95a901a5e073d7b14e55d6d303
https://github.com/llvm/llvm-project/commit/41008451260e4b95a901a5e073d7b14e55d6d303
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/lib/Interfaces/ValueBoundsOpInterface.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for llvm-qualified-auto in ValueBoundsOpInterface.cpp (NFC)
Commit: 6ff15f4b7176df9f704e34cab8e1c88438f34e1a
https://github.com/llvm/llvm-project/commit/6ff15f4b7176df9f704e34cab8e1c88438f34e1a
Author: Daniel Sanders <daniel_l_sanders at apple.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M pyproject.toml
Log Message:
-----------
[lldb] Configure pyright to the documented minimum python version (#162952)
Pyright is an MIT-licensed static type checker and can be found at
https://github.com/microsoft/pyright
there are also various integrations to use it as an LSP server in
various editors which is the main way I use it.
It's useful on our python scripts to detect issues such as where
functions are called with unexpected types or it's possible to access
obj.attr on an object that doesn't have that attribute. It can be used
without any configuration this config setting causes it to also report
issues with type hints that do not meet our python 3.8 minimum such as
this one from dap_server.py:
```
init_commands: list[str],
```
subscripting the builtin type like that requires python 3.9 while the
3.8 equivalent is:
```
from typing import List
...
init_commands: List[str],
```
In practice these scripts still work on 3.8 because type hints aren't
normally evaluated during normal execution but since we have a minimum,
we should fully comply with it.
Note: The error pyright reports for this particular issue isn't great:
```
error: Subscript for class "list" will generate runtime exception; enclose type expression in quotes
```
This is technically correct as it is possible to evaluate type hints at
runtime but I believe anything that would do so would also evaluate the
string form as well and still hit the runtime exception. A better
suggestion in this case would have been the 3.8 compatible `List[str]`.
However, it is better than silently passing code that doesn't confirm to
the minimum.
Commit: b5c0fcdadeed8803addf8d2aec6142fb9d8a5660
https://github.com/llvm/llvm-project/commit/b5c0fcdadeed8803addf8d2aec6142fb9d8a5660
Author: Andrew Haberlandt <ndrewh at users.noreply.github.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M compiler-rt/test/sanitizer_common/TestCases/Posix/posix_spawn.c
Log Message:
-----------
[sanitizer_common] posix_spawn test should forward DYLD_LIBRARY_PATH (#168795)
This test explicitly sets the environment for a spawned process. Without
DYLD_LIBRARY_PATH, the spawned process may use a ASAN runtime other than
the one that was used by the parent process That other runtime library
may not work at all, or may not be in the default search path. Either
case can cause the spawned process to die before it makes it to main,
thus failing the test. The compiler-rt lit config sets the library path
variable
[here](https://github.com/llvm/llvm-project/blob/main/compiler-rt/test/lit.common.cfg.py#L84)
(i.e. to ensure that just-built runtimes are used for tests, in the case
of a standalone compiler-rt build), and that is currently used by the
parent process but not the spawned ones.
My change only forwards the variable for Darwin (DYLD_LIBRARY_PATH), but
we **_ought_** to also forward the variable for other platforms.
However, it's not clear that there's any good way to plumb this into the
test, since some platforms actually have multiple library path variables
which would need to be forwarded (see: SunOS
[here](https://github.com/llvm/llvm-project/blob/main/compiler-rt/test/lit.common.cfg.py#L102)).
I considered adding a substitution variable for the library path
variable, but that doesn't really work if there's multiple such
variables.
Commit: c90fb56b41cfaaee448700f6b068c830d8d0b5bd
https://github.com/llvm/llvm-project/commit/c90fb56b41cfaaee448700f6b068c830d8d0b5bd
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M compiler-rt/test/lit.common.cfg.py
Log Message:
-----------
Revert "[compiler-rt] Default to Lit's Internal Shell (#168232)"
This reverts commit b725bdba1faf256c725f5fd12c581acb381bf0d3.
This is still causing Darwin failures. There are six tests that are
still failing:
AddressSanitizer-x86_64-darwin.TestCases/Posix.deep_call_stack.cpp
AddressSanitizer-x86_64-darwin.TestCases.scariness_score_test.cpp
AddressSanitizer-x86_64h-darwin.TestCases/Posix.deep_call_stack.cpp
ORC-x86_64-darwin.TestCases/Darwin/x86-64.objc-imageinfo.S
UBSan-Minimal-x86_64-darwin.TestCases.test-darwin-interface.c
UBSan-Minimal-x86_64h-darwin.TestCases.test-darwin-interface.c
There are a couple failure modes:
1. deep_call_stack.cpp and scariness_score_test.cpp are failing due to
ulimit issues that we have observed previously.
2. objc-imageinfo.S is failing in the x86 variant because I only updated
the AArch64 variant.
3. test-darwin-interface.c is using subshells, so obviously fails with
the internal shell. Also looks like this one did not run on my system
due to it requiring x86_64 Darwin.
Commit: 827ff2c1ce11afa482ff2b113b9b2fe811372beb
https://github.com/llvm/llvm-project/commit/827ff2c1ce11afa482ff2b113b9b2fe811372beb
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/fold-tail-low-trip-count.ll
A llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
Log Message:
-----------
[LV] Add tests for loops with low trip counts requiring tail-folding.
Add extra tests for over-eager tail-folding for tiny trip-count loops.
Reduced from https://github.com/llvm/llvm-project/issues/167858.
Commit: 777935c2edae160d20760278a1b462d8408c62f8
https://github.com/llvm/llvm-project/commit/777935c2edae160d20760278a1b462d8408c62f8
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
R utils/bazel/WORKSPACE
Log Message:
-----------
[bazel] Delete WORKSPACE file (#168926)
This has been replaced by the MODULE.bazel file. Users can still use
their own WORKSPACE files, but they didn't inherit this file anyways.
Users should migrate to bzlmod as with bazel 9.x that is required.
Commit: 54d9d4d8683221776928a8aaf3dca3b36f2b879b
https://github.com/llvm/llvm-project/commit/54d9d4d8683221776928a8aaf3dca3b36f2b879b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/commutable-node-with-non-sched-parent.ll
Log Message:
-----------
[SLP]Check if the non-schedulable phi parent node has unique operands
Need to check if the non-schedulable phi parent node has unique
operands, if the incoming node has copyables, and the node is
commutative. Otherwise, there might be issues with the correct
calculation of the dependencies.
Fixes #168589
Commit: b3d1e921aa7aea7dfdb4dc40786570ba5ac2aba5
https://github.com/llvm/llvm-project/commit/b3d1e921aa7aea7dfdb4dc40786570ba5ac2aba5
Author: Andrew Haberlandt <ndrewh at users.noreply.github.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/disable_container_overflow_checks.cpp
M compiler-rt/test/asan/TestCases/stack_container_dynamic_lib.cpp
Log Message:
-----------
[ASAN] Disable broken __SANITIZER_DISABLE_CONTAINER_OVERFLOW__ tests on iOS/Android (#168821)
The tests added by #163468 appear to be broken due to lack of libcxx support (?).
Marking unsupported everywhere for now since it passes on some platforms and fails on others, and
I don't know the full list.
Android fail: https://lab.llvm.org/buildbot/#/builders/186/builds/14106
Commit: 155a7d8e80fc268bdb99b9b31e6acaaccb94a3f8
https://github.com/llvm/llvm-project/commit/155a7d8e80fc268bdb99b9b31e6acaaccb94a3f8
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/include/llvm/Support/JSON.h
Log Message:
-----------
[Support] Add vector::erase to JSON::Array (#168835)
Commit: 7acfbc23a71cf66bbba89de55568064d732a61d1
https://github.com/llvm/llvm-project/commit/7acfbc23a71cf66bbba89de55568064d732a61d1
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction-index-width-smaller-than-iv-width.ll
Log Message:
-----------
[VPlan] Remove PtrIV::IsScalarAfterVectorization, use VPlan analysis. (#168289)
Remove `VPWidenPointerInductionRecipe::IsScalarAfterVectorization` and
replace it with `onlyScalarValuesUsed`. This removes the need to carry
state from the legacy cost model through VPlan, and the VPlan-based
analysis gives more accurate results, avoiding a number of extracts.
PR: https://github.com/llvm/llvm-project/pull/168289
Commit: 88055b3a56c6080f08dd83b954f61d84e8cdefe2
https://github.com/llvm/llvm-project/commit/88055b3a56c6080f08dd83b954f61d84e8cdefe2
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M clang-tools-extra/clang-doc/BitcodeReader.cpp
M clang-tools-extra/clang-doc/BitcodeReader.h
M clang-tools-extra/clang-doc/BitcodeWriter.h
M clang-tools-extra/clang-doc/ClangDoc.cpp
M clang-tools-extra/clang-doc/ClangDoc.h
M clang-tools-extra/clang-doc/Mapper.h
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clang-doc/Serialize.h
M clang-tools-extra/clang-doc/support/File.h
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
Log Message:
-----------
[clang-doc][NFC] Remove unused headers (#168806)
Removes unused headers or replaces them with headers that directly
provide the symbol instead. For example, `Serialize.h` included `AST.h`,
but it was actually `Serialize.cpp` that needed concept expressions, so
now it includes just `ExprConcepts.h`.
Commit: 930066f6e4e499a93d0f3799f275c5d37de48f6b
https://github.com/llvm/llvm-project/commit/930066f6e4e499a93d0f3799f275c5d37de48f6b
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel] Add explicit dep on protobuf (#168928)
This is required for correctly loading the protobuf rules. It's
possible we could drop the version here to a lower version, as long as
that version supports the versions of bazel we support. I picked this
because it is the current version being used by bazel 8.0.0 (which is
defined in the .bazelversion). Users can override this in their project
anyways if they need an older one
Commit: 1552efe8873310625ceef840ad0d56d33311015b
https://github.com/llvm/llvm-project/commit/1552efe8873310625ceef840ad0d56d33311015b
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M utils/bazel/.bazelversion
M utils/bazel/MODULE.bazel.lock
Log Message:
-----------
[bazel] Bump to 8.4.2 (#168933)
Just staying up to date
Commit: 318e7df4091adad966634d10e99956b5e87e5051
https://github.com/llvm/llvm-project/commit/318e7df4091adad966634d10e99956b5e87e5051
Author: Julian Pokrovsky <raventid at users.noreply.github.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Docs: more detailed categories for Vector intrinsics (#168924)
Fixes: https://github.com/llvm/llvm-project/issues/167132
Commit: 91e777f26d9e4cd298f10c51aba76a6c452682be
https://github.com/llvm/llvm-project/commit/91e777f26d9e4cd298f10c51aba76a6c452682be
Author: Petr Hosek <phosek at google.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M libc/cmake/caches/armv6m-none-eabi.cmake
M libc/cmake/caches/armv7em-none-eabi.cmake
M libc/cmake/caches/armv7m-none-eabi.cmake
Log Message:
-----------
[libc] Removed unused flags from baremetal cache files (#168942)
These flags are not needed for building libc.
Commit: 7e43715477b2b8cc05c532c216c003ef9c4d57c1
https://github.com/llvm/llvm-project/commit/7e43715477b2b8cc05c532c216c003ef9c4d57c1
Author: anoopkg6 <anoop.kumar6 at ibm.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/test/ExecutionEngine/JITLink/ppc64/ELF_ppc64_relocations.s
Log Message:
-----------
[JITLINK] Disable ELF_ppc64_relocations.s on SystemZ host (#168939)
Mark ELF_ppc64_relocations.s as unsupported on SystemZ because of cross
build issue related to using dlsym for host symbols.
Test fails to resolve __tls_get_aadr on SystemZ host.
Co-authored-by: anoopkg6 <anoopkg6 at github.com>
Commit: 1b8a4aa6a5cd92f06ef9c1d6705b3426107bc655
https://github.com/llvm/llvm-project/commit/1b8a4aa6a5cd92f06ef9c1d6705b3426107bc655
Author: Zhen Wang <37195552+wangzpgi at users.noreply.github.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUFCommon.h
M flang/lib/Optimizer/Builder/CUFCommon.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
Log Message:
-----------
[flang][cuda] Extract element count computation into helper function (#168937)
This patch extracts the common logic for computing array element counts
from shape operands into a reusable helper function in CUFCommon.
Commit: 10565847467b9978f2c9a9e4540b324e39c69096
https://github.com/llvm/llvm-project/commit/10565847467b9978f2c9a9e4540b324e39c69096
Author: Thurston Dang <thurston at google.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx2-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-i386.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-i386.ll
Log Message:
-----------
[msan] Fix handling of 256-bit hadd/hsub instructions (#168121)
These horizontal add/sub instructions are currently handled by
adding/subtracting tuples of the first operand, followed by tuples of
the second operand. This is not the correct semantics for the 256-bit
insructions: they process the first half of the first operand, then the
first half of the second operand, then the second half of the first
operand, and finally the second half of the second operand (trust me bro
[*]).
This patch fixes the issue by applying the "shards" functionality that
was added in https://github.com/llvm/llvm-project/pull/167954, to handle
the top and bottom 128-bit "shards" in turn.
[*] clang/test/CodeGen/X86/avx2-builtins.c:
```
TEST_CONSTEXPR(match_v8si(_mm256_hadd_epi32(
(__m256i)(__v8si){10, 20, 30, 40, 50, 60, 70, 80},
(__m256i)(__v8si){5, 15, 25, 35, 45, 55, 65, 75}),
30,70,20,60,110,150,100,140));
```
Commit: a3f6c4308ab4c36d2b58419d7f69744794fbb9ba
https://github.com/llvm/llvm-project/commit/a3f6c4308ab4c36d2b58419d7f69744794fbb9ba
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
Log Message:
-----------
[LV] Add test a low-trip count test without folding the tail.
Add a low trip count test that is currently vectorized but unprofitable,
for https://github.com/llvm/llvm-project/issues/167858.
Commit: 244b23046cf8b49167b69a221eb7516490278906
https://github.com/llvm/llvm-project/commit/244b23046cf8b49167b69a221eb7516490278906
Author: hjagasiaAMD <harsha.jagasia at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-scale-to-agpr.mir
Log Message:
-----------
[AMDGPU] Precommit test for issue in amdgpu-rewrite-agpr-copy-mfma, (#168609)
which reassigns scale operand in vgpr_32 register to agpr_32, not
permitted by instruction format. Reduced from ck.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Co-authored-by: theRonShark <ron.lieberman at amd.com>
Commit: 04acac2c90cfef84c25d89d4ead7363ed697ad68
https://github.com/llvm/llvm-project/commit/04acac2c90cfef84c25d89d4ead7363ed697ad68
Author: Martin Storsjö <martin at martin.st>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/stack_container_dynamic_lib.cpp
Log Message:
-----------
[compiler-rt] [test] Generalize an UNSUPPORTED marking (#168858)
Don't specifically target windows-msvc - the same goes for any windows
target; mingw doesn't have dlfcn.h either.
Commit: 76d614b7c1222f459d42c6cfdf619da19ac3f739
https://github.com/llvm/llvm-project/commit/76d614b7c1222f459d42c6cfdf619da19ac3f739
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/Transforms/InstSimplify/compare.ll
Log Message:
-----------
[InstSimplify] Extend icmp-of-add simplification to sle/sgt/sge (#168900)
When comparing additions with the same base where one has `nsw`, the
following simplification can be performed:
```llvm
icmp slt/sgt/sle/sge (x + C1), (x +nsw C2)
=>
icmp slt/sgt/sle/sge C1, C2
```
Previously this was only done for `slt`. This patch extends it to the
`sgt`, `sle`, and `sge` predicates when either of the conditions hold:
- `C1 <= C2 && C1 >= 0`, or
- `C2 <= C1 && C1 <= 0`
This patch also handles the `C1 == C2` case, which was previously
excluded.
Proof: https://alive2.llvm.org/ce/z/LtmY4f
Commit: 5c8db7ab880472525a8f06538ee56d0e77808abd
https://github.com/llvm/llvm-project/commit/5c8db7ab880472525a8f06538ee56d0e77808abd
Author: Sebastian Pop <spop at nvidia.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/lib/Analysis/DependenceAnalysis.cpp
R llvm/test/Analysis/DependenceAnalysis/Coupled.ll
R llvm/test/Analysis/DependenceAnalysis/Separability.ll
Log Message:
-----------
[DA] remove constraint propagation (#160924)
Remove all constraint propagation functions in Dependence Analysis.
Commit: 11362395615a6d728f98440e41bbebb3976d1941
https://github.com/llvm/llvm-project/commit/11362395615a6d728f98440e41bbebb3976d1941
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M libc/include/CMakeLists.txt
Log Message:
-----------
[libc] Add missing dependencies for arpa/inet.h header. (#168951)
Add dependency on headers with `in_addr` and `in_addr_t` type
definitions to ensure that these headers will be properly installed by
"install-libc" CMake target.
Commit: dbeda4f4199de87c7ecd8dabcc1c58944a7a37ad
https://github.com/llvm/llvm-project/commit/dbeda4f4199de87c7ecd8dabcc1c58944a7a37ad
Author: MaheshRavishankar <1663364+MaheshRavishankar at users.noreply.github.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/Dialect/SCF/Transforms/TileUsingInterface.h
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/test/Dialect/Linalg/transform-tile-and-fuse-pack-unpack.mlir
A mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer-using-slices.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
M mlir/test/lib/Interfaces/TilingInterface/TestTilingInterfaceTransformOps.cpp
M mlir/test/lib/Interfaces/TilingInterface/TestTilingInterfaceTransformOps.td
Log Message:
-----------
[mlir][SCF] Add `scf::tileAndFuseConsumer` that tiles a consumer into a given tiled loop nest. (#167634)
The existing `scf::tileAndFuseConsumerOfSlices` takes a list of slices
(and loops they are part of), tries to find the consumer of these slices
(all slices are expected to be the same consumer), and then tiles the
consumer into the loop nest using the `TilingInterface`. A more natural
way of doing consumer fusion is to just start from the consumer, look
for operands that are produced by the loop nest passed in as `loops`
(presumably these loops are generated by tiling, but that is not a
requirement for consumer fusion). Using the consumer you can find the
slices of the operands that are accessed within the loop which you can
then use to tile and fuse the consumer (using `TilingInterface`). This
handles more naturally the case where multiple operands of the consumer
come from the loop nest.
The `scf::tileAndFuseConsumerOfSlices` was implemented as a mirror of
`scf::tileAndFuseProducerOfSlice`. For the latter, the slice has a
single producer for the source of the slice, which makes it a natural
way of specifying producer fusion. But for consumers, the result might
have multiple users, resulting in multiple candidates for fusion, as
well as a fusion candidate using multiple results from the tiled loop
nest. This means using slices
(`tensor.insert_slice`/`tensor.parallel_insert_slice`) as a hook for
consumer fusion turns out to be quite hard to navigate. The use of the
consumer directly avoids all those pain points. In time the
`scf::tileAndFuseConsumerOfSlices` should be deprecated in favor of
`scf::tileAndFuseConsumer`. There is a lot of tech-debt that has
accumulated in `scf::tileAndFuseConsumerOfSlices` that needs to be
cleanedup. So while that gets cleaned up, and required functionality is
moved to `scf::tileAndFuseConsumer`, the old path is still maintained.
The test for `scf::tileAndFuseConsumerUsingSlices` is copied to
`tile-and-fuse-consumer.mlir` to
`tile-and-fuse-consumer-using-slices.mlir`. All the tests that were
there in this file are now using the `tileAndFuseConsumer` method. The
test op `test.tile_and_fuse_consumer` is modified to call
`scf::tileAndFuseConsumer`, while a new op
`test.tile_and_fuse_consumer_of_slice` is used to keep the old path
tested while it is deprecated.
---------
Signed-off-by: MaheshRavishankar <mahesh.ravishankar at gmail.com>
Commit: 9e2ca0d7d49b34ff55361a0556bb59f8c593a4da
https://github.com/llvm/llvm-project/commit/9e2ca0d7d49b34ff55361a0556bb59f8c593a4da
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
[mlir] Add kuhar to code owners for arith (#168945)
Commit: bf91a62269964398836544020def699e3f019b9b
https://github.com/llvm/llvm-project/commit/bf91a62269964398836544020def699e3f019b9b
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/tools/bugpoint/BugDriver.h
M llvm/tools/bugpoint/CrashDebugger.cpp
M llvm/tools/bugpoint/ExecutionDriver.cpp
M llvm/tools/bugpoint/ExtractFunction.cpp
M llvm/tools/bugpoint/Miscompilation.cpp
M llvm/tools/bugpoint/OptimizerDriver.cpp
Log Message:
-----------
[NFC][bugpoint] Namespace cleanup in `bugpoint` (#168921)
Add declaration of command line options to BugDriver.h and remove extern
declarations in individual .cpp files.
Commit: b83e458fe5330227581e1e65f3866ddfcd597837
https://github.com/llvm/llvm-project/commit/b83e458fe5330227581e1e65f3866ddfcd597837
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/tools/bugpoint/BugDriver.h
M llvm/tools/bugpoint/CrashDebugger.cpp
M llvm/tools/bugpoint/ExecutionDriver.cpp
M llvm/tools/bugpoint/ExtractFunction.cpp
M llvm/tools/bugpoint/Miscompilation.cpp
M llvm/tools/bugpoint/OptimizerDriver.cpp
Log Message:
-----------
Revert "[NFC][bugpoint] Namespace cleanup in `bugpoint`" (#168961)
Reverts llvm/llvm-project#168921
Causes build failures.
Commit: 70311b453c73c8bc92362bb4035449f3a87210fc
https://github.com/llvm/llvm-project/commit/70311b453c73c8bc92362bb4035449f3a87210fc
Author: Sebastian Pop <spop at nvidia.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopUnrollAndJam/dependencies.ll
Log Message:
-----------
[unroll-and-jam] Document dependency patterns in dependencies.ll (NFC) (#156577)
Add detailed comments explaining each function's memory access patterns
and why they should/shouldn't be unroll-and-jammed:
- fore_aft_*: Dependencies between fore block and aft block
- fore_sub_*: Dependencies between fore block and sub block
- sub_aft_*: Dependencies between sub block and aft block
- sub_sub_*: Dependencies within sub block
- *_less: Backward dependency (i-1) - safe for fore/aft, fore/sub,
sub/aft; unsafe for sub/sub due to jamming conflicts
- *_eq: Same iteration dependency (i+0) - safe due to preserved
execution order
- *_more: Forward dependency (i+1) - unsafe due to write-after-write
races between unrolled iterations, except sub/sub case creates conflicts
Commit: 0f12abe47c15c28949f9b609f2c90333176f17d1
https://github.com/llvm/llvm-project/commit/0f12abe47c15c28949f9b609f2c90333176f17d1
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M lldb/docs/CMakeLists.txt
Log Message:
-----------
[lldb] Building the documentation should not depend on libLLDB (#168962)
The only thing the docs should depend on is on the SWIG wrapper
(lldb.py) which only requires parsing the API headers. It should not
depend on building libLLDB.
The dependency was (I believe accidentally) introduced by 59f4267.
Fixes #123316
Commit: fbc093588f654ba771dfc055687676edf4d76884
https://github.com/llvm/llvm-project/commit/fbc093588f654ba771dfc055687676edf4d76884
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Log Message:
-----------
[RISCV] Only add v2i32 to GPR regclass in the RV64 hardware mode. (#168930)
Removes about 200 bytes of unneeded patterns from RISCVGenDAGISel.inc
Commit: 310abe0e4b4ebb57976928cc0b520f9e878b54a7
https://github.com/llvm/llvm-project/commit/310abe0e4b4ebb57976928cc0b520f9e878b54a7
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
Log Message:
-----------
[MLIR] [XeGPU] Add distribution pattern for vector.constant_mask from Wg To Sg (#168118)
Commit: a9435cb8924dc00d3a34570785284e73049662e4
https://github.com/llvm/llvm-project/commit/a9435cb8924dc00d3a34570785284e73049662e4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
Log Message:
-----------
[RISCV] Use SDT_RISCVIntUnaryOpW for RISCVISD::ABSW type profile. NFC (#168932)
This removes an unnecessary isel pattern for the RV32 HwMode.
Commit: 925ce5adde46f8347d5d7e438f63203f2d003df7
https://github.com/llvm/llvm-project/commit/925ce5adde46f8347d5d7e438f63203f2d003df7
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.h
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
Log Message:
-----------
[clang][deps] NFC: Fix typo in function name (#168958)
Commit: 3723a8b0ac82e3c90d55cc086a3a3708949e44a7
https://github.com/llvm/llvm-project/commit/3723a8b0ac82e3c90d55cc086a3a3708949e44a7
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M utils/bazel/.bazelrc
Log Message:
-----------
[bazel] Replace --experimental_guard_against_concurrent_changes usage (#168957)
On startup, bazel prints: `WARNING: Option
'experimental_guard_against_concurrent_changes' is deprecated: Use
--guard_against_concurrent_changes instead`
Commit: 49e46a57cc1575271179c8c9c6fec5639781e9c6
https://github.com/llvm/llvm-project/commit/49e46a57cc1575271179c8c9c6fec5639781e9c6
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
M compiler-rt/test/ubsan_minimal/TestCases/test-darwin-interface.c
Log Message:
-----------
[UBSan] [compiler-rt] add preservecc variants of handlers (#168643)
Commit: 418204d9c108351340fe21194ace0e31157b7189
https://github.com/llvm/llvm-project/commit/418204d9c108351340fe21194ace0e31157b7189
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
M compiler-rt/test/ubsan_minimal/TestCases/test-darwin-interface.c
Log Message:
-----------
Revert "[UBSan] [compiler-rt] add preservecc variants of handlers" (#168973)
Reverts llvm/llvm-project#168643
Commit: ac55d7859fc53d9ca8444a29a93fc45d16ecb26a
https://github.com/llvm/llvm-project/commit/ac55d7859fc53d9ca8444a29a93fc45d16ecb26a
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir
Log Message:
-----------
AMDGPU: Don't duplicate implicit operands in 3-address conversion (#168426)
We previously got a duplicate implicit $exec operand. It didn't really
hurt anything (other than being a slight drag on compile-time
performance). Still, let's keep things clean.
Commit: 06eac9feb92cba1d24e8a674c643aae1200d2bc8
https://github.com/llvm/llvm-project/commit/06eac9feb92cba1d24e8a674c643aae1200d2bc8
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M lldb/include/lldb/Core/SourceManager.h
M lldb/include/lldb/Symbol/CompileUnit.h
M lldb/include/lldb/Symbol/Function.h
M lldb/include/lldb/Symbol/LineEntry.h
M lldb/include/lldb/Utility/FileSpecList.h
A lldb/include/lldb/Utility/NonNullSharedPtr.h
M lldb/include/lldb/Utility/SupportFile.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/Breakpoint/BreakpointResolverFileLine.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/Disassembler.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/Expression/REPL.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Symbol/CompileUnit.cpp
M lldb/source/Symbol/Function.cpp
M lldb/source/Symbol/LineTable.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/ThreadPlanStepRange.cpp
M lldb/source/Utility/FileSpecList.cpp
M lldb/unittests/Symbol/LineTableTest.cpp
Log Message:
-----------
[lldb] Eliminate SupportFileSP nullptr derefs (#168624)
This patch fixes and eliminates the possibility of SupportFileSP ever
being nullptr. The support file was originally treated like a value
type, but became a polymorphic type and therefore has to be stored and
passed around as a pointer.
To avoid having all the callers check the validity of the pointer, I
introduced the invariant that SupportFileSP is never null and always
default constructed. However, without enforcement at the type level,
that's fragile and indeed, we already identified two crashes where
someone accidentally broke that invariant.
This PR introduces a NonNullSharedPtr to prevent that. NonNullSharedPtr
is a smart pointer wrapper around std::shared_ptr that guarantees the
pointer is never null. If default-constructed, it creates a
default-constructed instance of the contained type. Note that I'm using
private inheritance because you shouldn't inherit from standard library
classes due to the lack of virtual destructor. So while the new
abstraction looks like a `std::shared_ptr`, it is in fact **not** a
shared pointer. Given that our destructor is trivial, we could use
public inheritance, but currently there's no need for it.
rdar://164989579
Commit: 3954df93384f10de2ec35501650120949972fbb1
https://github.com/llvm/llvm-project/commit/3954df93384f10de2ec35501650120949972fbb1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
Log Message:
-----------
AMDGPU: Convert constant-address-space-32bit test to generated checks (#168975)
Commit: 8439aebd3dd3e9d0586d44f0e8a68bba86785ae6
https://github.com/llvm/llvm-project/commit/8439aebd3dd3e9d0586d44f0e8a68bba86785ae6
Author: Jim Lin <jim at andestech.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/include/clang/Frontend/CompilerInvocation.h
M clang/lib/Frontend/CompilerInvocation.cpp
Log Message:
-----------
[Clang] Refactor getOptimizationLevel and getOptimizationLevelSize to non-static. NFC. (#168839)
So that we can reuse these functions in few place, such as in
clang/lib/Driver/ToolChains/CommonArgs.cpp. Part of the code there is
currently copied from getOptimizationLevel.
Commit: 423bdb2bf257e19271d62e60b6339d84b8ce05aa
https://github.com/llvm/llvm-project/commit/423bdb2bf257e19271d62e60b6339d84b8ce05aa
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/docs/OpenCLSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/OpenCLExtensions.def
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Headers/opencl-c-base.h
M clang/test/Headers/opencl-c-header.cl
M clang/test/SemaOpenCL/extension-version.cl
M clang/test/SemaOpenCL/features.cl
Log Message:
-----------
[OpenCL] Add missing OpenCL 3.0 features to OpenCLExtensions.def; revert header-only macros (#168016)
Adds the remaining optional feature macros from the OpenCL C 3.0 spec
(section 6.2.1 table). Targets can now enable these via
OpenCLFeaturesMap returned by getSupportedOpenCLOpts().
Revert a84599f177a6 (header‑only feature macros).
Header‑only macros are difficult to disable on SPIR-V targets,
and the prior undef approach (a60b8f468119) does not scale.
After this PR, they can be disabled via `-cl-ext=-<feature>`.
https://github.com/KhronosGroup/OpenCL-Docs/issues/1328 also notes that
unconditional definition of the header‑only macros in opencl-c-base.h
should be removed.
Commit: c34f76dd553c3404962c3d6c3d38cbdc6ff9d778
https://github.com/llvm/llvm-project/commit/c34f76dd553c3404962c3d6c3d38cbdc6ff9d778
Author: Ch1p <hduch1p at gmail.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/tools/dsymutil/MachOUtils.cpp
Log Message:
-----------
[dsymutil] Add missing validation for zero alignment section (#168925)
Commit: 1d73b68463ba5ef75434f8d13390537b8e66efa9
https://github.com/llvm/llvm-project/commit/1d73b68463ba5ef75434f8d13390537b8e66efa9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-20 (Thu, 20 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/TargetLoweringBase.cpp
Log Message:
-----------
TargetLowering: Avoid hardcoding OpenBSD + __guard_local name (#167744)
Query RuntimeLibcalls for the support and the name. The check
that the implementation is exactly __guard_local instead of
unsupported feels a bit strange.
Commit: bf4dc96bc15464fc4af9dde3a5a686a129abfdbd
https://github.com/llvm/llvm-project/commit/bf4dc96bc15464fc4af9dde3a5a686a129abfdbd
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
Log Message:
-----------
[mlir][linalg] Clean up op verifiers without custom checks(NFC) (#168712)
This PR removes op verifiers that do not implement any custom
verification logic.
Commit: 3d3307ecd8bdd6d9af0d82245c5fc50e4d624a7a
https://github.com/llvm/llvm-project/commit/3d3307ecd8bdd6d9af0d82245c5fc50e4d624a7a
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang-tools-extra/clang-tidy/ClangTidy.cpp
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/CreateInvocationFromCommandLine.cpp
M clang/lib/Frontend/DependencyFile.cpp
M clang/lib/Frontend/DependencyGraph.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Frontend/HeaderIncludeGen.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Frontend/Rewrite/FixItRewriter.cpp
M clang/lib/Frontend/SerializedDiagnosticPrinter.cpp
M clang/lib/Frontend/TestModuleFileExtension.cpp
M clang/lib/Frontend/VerifyDiagnosticConsumer.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M clang/lib/StaticAnalyzer/Frontend/CheckerRegistry.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/tools/clang-repl/ClangRepl.cpp
M clang/tools/driver/cc1_main.cpp
M clang/tools/driver/cc1as_main.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[clang][NFC] Inline Frontend/FrontendDiagnostic.h -> Basic/DiagnosticFrontend.h (#162883)
d076608d58d1ec55016eb747a995511e3a3f72aa moved some deps around to avoid
cycles and left clang/Frontend/FrontendDiagnostic.h as a shim that
simply includes clang/Basic/DiagnosticFrontend.h. This PR inlines it so
that nothing in tree still includes clang/Frontend/FrontendDiagnostic.h.
Doing this will help prevent future layering issues. See #162865.
Frontend already depends on Basic, so no new deps need to be added
anywhere except for places that do strict dep checking.
Commit: 2ab9492d8163de8d04704467939389d55a9b7d3e
https://github.com/llvm/llvm-project/commit/2ab9492d8163de8d04704467939389d55a9b7d3e
Author: Prasoon Mishra <Prasoon.Mishra at amd.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/tools/llc/NewPMDriver.cpp
Log Message:
-----------
[llc][NPM] Use buffer_ostream support for non-seekable streams (#168842)
NPM was missing buffering for non-seekable output streams (stdout,
pipes), causing assertion failures when generating object files with `-o
-`.
Use buffer_ostream to provide seekable buffering, matching legacy PM
behavior.
Co-authored-by: vikhegde <vikram.hegde at amd.com>
Commit: cf837e2ffe7b89a861f7145235190a1a000f3559
https://github.com/llvm/llvm-project/commit/cf837e2ffe7b89a861f7145235190a1a000f3559
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M lldb/include/lldb/Utility/NonNullSharedPtr.h
Log Message:
-----------
[lldb] Add assert to NonNullSharedPtr move constructor (#168979)
As suggested by Augusto, add an assert to the NonNullSharedPtr move
constructor.
Commit: 645e0dcbff33248bd2cdc4ac258420de9b5936b1
https://github.com/llvm/llvm-project/commit/645e0dcbff33248bd2cdc4ac258420de9b5936b1
Author: Brandon Wu <songwu0813 at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/RISCV.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
A llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/CodeGen/RISCV/zilsd-ldst-opt-postra.mir
A llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir
A llvm/test/CodeGen/RISCV/zilsd-regalloc-hints.mir
Log Message:
-----------
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
This commit implements a complete load/store optimization pass for the
RISC-V Zilsd extension, which combines pairs of 32-bit load/store
instructions into single 64-bit LD/SD instructions when possible.
Default alignment is 8, it also provide zilsd-4byte-align feature for
looser condition.
Related work: https://reviews.llvm.org/D144002
---------
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: 0a231c9ad9c8db10380379e2e6f021d6af9a7e7f
https://github.com/llvm/llvm-project/commit/0a231c9ad9c8db10380379e2e6f021d6af9a7e7f
Author: SunilKuravinakop <98882378+SunilKuravinakop at users.noreply.github.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
A clang/test/OpenMP/parallel_default_variableCategory_codegen.cpp
Log Message:
-----------
[Clang][OpenMP] Bug fix Default clause variable category (#168846)
Same changes as in fix for
https://github.com/llvm/llvm-project/pull/165276 except for changes in
test case :
1) remove unnecessary include in test to restore Ubuntu build.
This is not needed as allocatable modifier is not applicable to the
default clause in C/C++.
2) Changes in CHECK statements to accommodate testing failure on
toolchain
builders at Google, Reported by Prabhu Rajasekaran.
---------
Co-authored-by: Sunil Kuravinakop <kuravina at pe31.hpc.amslabs.hpecorp.net>
Commit: 5c5c83d8bc7172b16631ed874482568444e0625a
https://github.com/llvm/llvm-project/commit/5c5c83d8bc7172b16631ed874482568444e0625a
Author: Jim Lin <jim at andestech.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[PowerPC] Fix Wparentheses warning
PPCISelLowering.cpp:15567:27: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
15567 | CC == ISD::SETEQ && "CC mus be ISD::SETNE or ISD::SETEQ");
| ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Commit: b4a0d7e89fac280b2917b3fca906ad2f3a52da74
https://github.com/llvm/llvm-project/commit/b4a0d7e89fac280b2917b3fca906ad2f3a52da74
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
Log Message:
-----------
[NVPTX] Fix PTX and SM conditions for narrow FP conversions (#168680)
This change fixes the PTX and SM conditions for narrow FP
conversion intrinsics and adds support for family-conditionals.
Commit: cc5185bd146bed96d0d9e23263a56b6965d8572f
https://github.com/llvm/llvm-project/commit/cc5185bd146bed96d0d9e23263a56b6965d8572f
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaModule.cpp
A clang/test/Modules/reference-tu-local-var.cppm
Log Message:
-----------
[C++20] [Modules] Check TULocal entity within exported entities
See the attached test for example.
Commit: e4a4bb0f6d3b3b9f3ccba79202a9074415b7dd71
https://github.com/llvm/llvm-project/commit/e4a4bb0f6d3b3b9f3ccba79202a9074415b7dd71
Author: Himadhith <79003240+Himadhith at users.noreply.github.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/addition-vector-all-ones.ll
M llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
Log Message:
-----------
[PowerPC] Replace vspltisw+vadduwm instructions with xxleqv+vsubuwm for adding the vector {1, 1, 1, 1} (#160882)
This patch optimizes vector addition operations involving **`all-ones`**
vectors by leveraging the generation of vectors of -1s(using `xxleqv`,
which is cheaper than generating vectors of 1s(`vspltisw`). These are
the respective vector types.
`v2i64`: **`A + vector {1, 1}`**
`v4i32`: **`A + vector {1, 1, 1, 1}`**
`v8i16`: **`A + vector {1, 1, 1, 1, 1, 1, 1, 1}`**
`v16i8`: **`A + vector {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1}`**
The optimized version replaces `vspltisw (4 cycles)` with `xxleqv (2
cycles)` using the following identity:
`A - (-1) = A + 1`.
---------
Co-authored-by: himadhith <himadhith.v at ibm.com>
Co-authored-by: Tony Varghese <tonypalampalliyil at gmail.com>
Commit: ea9ec7cfb538d9059a04777c5b738b4b49b6fb83
https://github.com/llvm/llvm-project/commit/ea9ec7cfb538d9059a04777c5b738b4b49b6fb83
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M orc-rt/include/orc-rt-c/WrapperFunction.h
M orc-rt/include/orc-rt/SPSWrapperFunction.h
M orc-rt/include/orc-rt/SimpleNativeMemoryMap.h
M orc-rt/include/orc-rt/WrapperFunction.h
M orc-rt/lib/executor/SimpleNativeMemoryMap.cpp
M orc-rt/unittests/DirectCaller.h
M orc-rt/unittests/SPSWrapperFunctionTest.cpp
Log Message:
-----------
[orc-rt] Rename 'Session' variables to avoid ambiguity with type. NFCI. (#168999)
Re-using Session as a variable name risks confusion with the Session
type.
Commit: 31127b9e225c50ebadcdc268bccb16319b8db72d
https://github.com/llvm/llvm-project/commit/31127b9e225c50ebadcdc268bccb16319b8db72d
Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Target/LLVMIR/Import/import-failure.ll
Log Message:
-----------
[mlir][llvm] Handle debug record import edge cases (#168774)
This commit enables the direct import of debug records by default and
fixes issues with two edge cases:
- Detect early on if the address operand is an argument list (calling
getAddress() for argument lists asserts)
- Use getAddress() to check if the address operand is null, which means
the address operand is an empty metadata node, which currently is not
supported.
- Add support for debug label records.
This is a follow-up to:
https://github.com/llvm/llvm-project/pull/167812
Commit: 4c81b92e602165e3f680236dde92a34de74f5e06
https://github.com/llvm/llvm-project/commit/4c81b92e602165e3f680236dde92a34de74f5e06
Author: Tuomas Kärnä <tuomas.karna at intel.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
[MLIR][CODEOWNERS] Add XeGPU transform ops code owners (#168940)
Add charithaintc, Jianhui-Li and tkarna as code owners of XeGPU/TransformOps directories.
Commit: e9fc393a9e431d1a0aebc3fe448f3cf1668fbb34
https://github.com/llvm/llvm-project/commit/e9fc393a9e431d1a0aebc3fe448f3cf1668fbb34
Author: Tuomas Kärnä <tuomas.karna at intel.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/TransformOps/XeGPUTransformOps.td
M mlir/lib/Dialect/XeGPU/TransformOps/XeGPUTransformOps.cpp
M mlir/python/mlir/dialects/transform/xegpu.py
M mlir/test/Dialect/XeGPU/transform-ops.mlir
M mlir/test/python/dialects/transform_xegpu_ext.py
Log Message:
-----------
[MLIR][XeGPU][TransformOps] Add slice_dims argument to set_op_layout_attr and set_desc_layout (#168929)
`set_op_layout_attr` and `set_desc_layout` transform ops wrap
`xegpu.layout` in an `xegpu.slice` attribute if `slice_dims` argument is
set.
Commit: 299ea95747a5f4eb052fe37e5e10f043b8c11cf8
https://github.com/llvm/llvm-project/commit/299ea95747a5f4eb052fe37e5e10f043b8c11cf8
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/streaming-compatible-sve-no-maximize-bandwidth.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-too-many-deps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/check-prof-info.ll
M llvm/test/Transforms/LoopVectorize/induction-step.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/instruction-only-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-gep-nowrap-flags.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/pr35773.ll
M llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
M llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll
Log Message:
-----------
[VPlan] Drop poison-generating flags on induction trunc (#168922)
After truncating an integer-induction, neither nuw nor nsw hold.
Fixes #168902.
Co-authored-by: Florian Hahn <flo at fhahn.com>
Commit: 8b7c49536ef3035524de09d58b6aaaea6bcc749b
https://github.com/llvm/llvm-project/commit/8b7c49536ef3035524de09d58b6aaaea6bcc749b
Author: David Green <david.green at arm.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/test/tools/llvm-ir2vec/entities.mir
R llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
R llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
M llvm/test/tools/llvm-ir2vec/triplets.mir
Log Message:
-----------
[IR2VEC] Rewrite triples.mir and entities.mir. NFC (#168574)
These test change and need updating every time a new instruction is
added, including generic G_ global isel instructions. The opcodes of all
instructions change force a manual update of the file, which makes it
very high cost for what it is testing.
I have rewritten it to use regexes for the triplets.mir test and just
test a couple of opcodes in the entities.mir file.
Commit: af098e009695c07d5f56d1d8a1f9c8380919f26d
https://github.com/llvm/llvm-project/commit/af098e009695c07d5f56d1d8a1f9c8380919f26d
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
M compiler-rt/test/ubsan_minimal/TestCases/misalignment.cpp
M compiler-rt/test/ubsan_minimal/TestCases/null.cpp
Log Message:
-----------
Revert "[ubsan_minimal] Allow UBSan handler from Minimal runtime to accept arguments (#152192)" (#168812)
This partially reverts #152192, keeping updated tests and
some code reordering in clang/lib/CodeGen/CGExpr.cpp.
compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp is exact revert
(with followup #152419)
We don't have a good use case for that, so revert it before we are stuck
maintaining this API.
21.x does not have this patch.
This reverts commit a1209d868632b8aea10450cd2323848ab0b6776a.
Commit: 316dbb4c1c661f08988ff8f86bf455e282012f2e
https://github.com/llvm/llvm-project/commit/316dbb4c1c661f08988ff8f86bf455e282012f2e
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang-tools-extra/clang-tidy/.clang-format
M clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
M clang-tools-extra/clang-tidy/altera/KernelNameRestrictionCheck.cpp
M clang-tools-extra/clang-tidy/boost/UseRangesCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/BranchCloneCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/ComparePointerToMemberVirtualFunctionCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/DanglingHandleCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/IncDecInConditionsCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/MacroParenthesesCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/NondeterministicPointerIterationOrderCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/OptionalValueConversionCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SpuriouslyWakeUpFunctionsCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SuspiciousMemsetUsageCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SuspiciousStringviewDataUsageCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/TaggedUnionMemberCountCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/ProBoundsAvoidUncheckedContainerAccessCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeMemberInitCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/VirtualClassDestructorCheck.cpp
M clang-tools-extra/clang-tidy/google/AvoidThrowingObjCExceptionCheck.cpp
M clang-tools-extra/clang-tidy/llvm/PreferStaticOverAnonymousNamespaceCheck.cpp
M clang-tools-extra/clang-tidy/misc/ConfusableIdentifierCheck.cpp
M clang-tools-extra/clang-tidy/misc/RedundantExpressionCheck.cpp
M clang-tools-extra/clang-tidy/misc/UnusedParametersCheck.cpp
M clang-tools-extra/clang-tidy/modernize/AvoidBindCheck.cpp
M clang-tools-extra/clang-tidy/modernize/DeprecatedHeadersCheck.cpp
M clang-tools-extra/clang-tidy/modernize/LoopConvertCheck.cpp
M clang-tools-extra/clang-tidy/modernize/MinMaxUseInitializerListCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseConstraintsCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseDesignatedInitializersCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseOverrideCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseRangesCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStdPrintCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseTrailingReturnTypeCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseUsingCheck.h
M clang-tools-extra/clang-tidy/performance/NoexceptSwapCheck.cpp
M clang-tools-extra/clang-tidy/readability/AvoidConstParamsInDeclsCheck.cpp
M clang-tools-extra/clang-tidy/readability/AvoidUnconditionalPreprocessorIfCheck.cpp
M clang-tools-extra/clang-tidy/readability/ElseAfterReturnCheck.cpp
M clang-tools-extra/clang-tidy/readability/FunctionCognitiveComplexityCheck.cpp
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
M clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.cpp
M clang-tools-extra/clang-tidy/readability/MagicNumbersCheck.cpp
M clang-tools-extra/clang-tidy/readability/OperatorsRepresentationCheck.cpp
M clang-tools-extra/clang-tidy/readability/SuspiciousCallArgumentCheck.cpp
M clang-tools-extra/clang-tidy/readability/UniqueptrDeleteReleaseCheck.cpp
M clang-tools-extra/clang-tidy/readability/UseAnyOfAllOfCheck.cpp
M clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.cpp
M clang-tools-extra/clang-tidy/utils/FormatStringConverter.cpp
M clang-tools-extra/clang-tidy/utils/LexerUtils.cpp
M clang-tools-extra/clang-tidy/utils/Matchers.cpp
Log Message:
-----------
[clang-tidy][NFC] Reformat code and set 'KeepEmptyLines' to false (#168131)
Currently, default `clang-format` LLVM style is configured like this:
```
KeepEmptyLines:
AtEndOfFile: false
AtStartOfBlock: true
AtStartOfFile: true
```
This PR sets `AtStartOfBlock` and `AtStartOfFile` to false.
I think this is the general style pattern we tend to follow, in
particular Eugene made comments about empty newlines at start of
functions.
Commit: f2cb5d7a05bacb3e39df8dd355b2fbd16f96c856
https://github.com/llvm/llvm-project/commit/f2cb5d7a05bacb3e39df8dd355b2fbd16f96c856
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
Log Message:
-----------
[DAGCombiner] Strip outer match in visitBITREVERSE (NFC) (#169020)
Commit: bb1b82af395fe4a717c9b10948312e260b5ca666
https://github.com/llvm/llvm-project/commit/bb1b82af395fe4a717c9b10948312e260b5ca666
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/AST/Decl.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/test/ASTMerge/struct/test.c
M clang/test/CXX/drs/cwg6xx.cpp
M clang/test/Index/print-type.c
M clang/test/Layout/ms-x86-alias-avoidance-padding.cpp
M clang/test/Modules/compare-record.c
M clang/test/SemaObjCXX/arc-0x.mm
M clang/unittests/AST/TypePrinterTest.cpp
Log Message:
-----------
[clang][TypePrinter] Replace AppendScope with printNestedNameSpecifier (#168534)
In debug-info we soon have the need to print names using the full scope
of the entity (see discussion in
https://github.com/llvm/llvm-project/pull/159592). Particularly, when a
structure is scoped inside a function, we'd like to emit the name as
`func()::foo`. `CGDebugInfo` uses the `TypePrinter` to print type names
into debug-info. However, `TypePrinter` stops (and ignores)
`DeclContext`s that are functions. I.e., it would just print `foo`.
Ideally it would behave the same way `printNestedNameSpecifier` does.
The FIXME in
https://github.com/llvm/llvm-project/blob/47c1aa4cef638c97b74f3afb7bed60e92bba1f90/clang/lib/AST/TypePrinter.cpp#L1520-L1521
motivated this patch.
See https://github.com/llvm/llvm-project/pull/168533 for how this will
be used by `CGDebugInfo`. The plan is to introduce a new
`PrintingPolicy` that prints anonymous entities using their full scope
(including function/anonymous scopes) and the mangling number.
Commit: 5a3c2573a9644efe3384c4144b119148088b48ef
https://github.com/llvm/llvm-project/commit/5a3c2573a9644efe3384c4144b119148088b48ef
Author: Yexuan Xiao <bizwen at nykz.org>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M libcxx/src/thread.cpp
Log Message:
-----------
[libc++][Windows] Enable thread::hardware_concurrency to support more than 64 processors (#168229)
Starting with Windows 11, processes can utilize more than 64 processors
by default, but GetSystemInfo can only report a maximum of 64. Starting
with Windows Vista, GetActiveProcessorCount accurately retrieves the
total number of processors on the current system. I’ve implemented
similar improvements to Microsoft STL. The following links contain
additional background information:
https://github.com/microsoft/STL/issues/5453,
https://github.com/microsoft/STL/pull/5459 (note: Reason STL uses the
more complex GetLogicalProcessorInformationEx:
https://github.com/microsoft/STL/pull/5459#discussion_r2072242241.).
Commit: 18d3db4bcd42e21e45b499a2999834904a925af0
https://github.com/llvm/llvm-project/commit/18d3db4bcd42e21e45b499a2999834904a925af0
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/lib/Dialect/Shard/IR/ShardOps.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-container-size-empty in ShardOps.cpp (NFC)
Commit: 2f627c1878a3dba594c872773107c556992af3a1
https://github.com/llvm/llvm-project/commit/2f627c1878a3dba594c872773107c556992af3a1
Author: Kirill Vedernikov <kvedernikov at nvidia.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/wmma-ptx88-sm120a.py
M llvm/test/CodeGen/NVPTX/wmma.py
Log Message:
-----------
[NVPTX] Support for dense and sparse MMA intrinsics with block scaling. (#163561)
This change adds dense and sparse MMA intrinsics with block scaling. The
implementation is based on [PTX ISA version
9.0](https://docs.nvidia.com/cuda/parallel-thread-execution/). Tests for
new intrinsics are added for PTX 8.7 and SM 120a and are generated by
`llvm/test/CodeGen/NVPTX/wmma-ptx87-sm120a.py`. The tests have been
verified with ptxas from CUDA-13.0 release.
Dense MMA intrinsics with block scaling were supported by
@schwarzschild-radius.
Commit: a8058c177d0e45993108936cfca532d3dab037fc
https://github.com/llvm/llvm-project/commit/a8058c177d0e45993108936cfca532d3dab037fc
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/lib/IR/AsmPrinter.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in AsmPrinter.cpp (NFC)
Commit: 764c1d40ce89a2ece97d32240e5e943afdb2c9c9
https://github.com/llvm/llvm-project/commit/764c1d40ce89a2ece97d32240e5e943afdb2c9c9
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-container-size-empty in AffineOps.cpp (NFC)
Commit: 41a9df2389b6db45b5159073c52232dd867c7f25
https://github.com/llvm/llvm-project/commit/41a9df2389b6db45b5159073c52232dd867c7f25
Author: Willem Kaufmann <willem.kaufmann at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/JSONNodeDumper.h
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/test/AST/ast-dump-expr-json.cpp
A clang/test/AST/ast-dump-lambda-json.cpp
Log Message:
-----------
[Clang] Fix handling of explicit parameters in `SemaLambda` (#168558)
Previously, the presence of an explicit parameter list was detected by
querying `getNumTypeObjects()` from the `Declarator` block of the lambda
definition. This breaks for lambdas which do not have a parameter list
but _do_ have a trailing return type; that is, both of
```
[]() -> int { return 0; };
[] -> int { return 0; };
```
would return `true` when inspecting
`LambdaExpr::hasExplicitParameters()`.
Fix this by instead querying the `LParenLoc()` from the `Declarator`'s
`FunctionTypeInfo`. If `isValid() == true`, then an explicit parameter
list must be present, and if it is `false`, then it is not.
This commit also adds `hasExplicitParameters` as an attribute to a
`LambdaExpr`'s JSON AST dump. A new test (`ast-dump-lambda-json.cpp`) is
also added to validate the fix and presence of the new attribute in the
output. `ast-dump-expr-json.cpp` is also updated to validate the new
attribute.
Fixes https://github.com/llvm/llvm-project/issues/168452.
Commit: 622f72f4bef8b177e1e4f318465260fbdb7711ef
https://github.com/llvm/llvm-project/commit/622f72f4bef8b177e1e4f318465260fbdb7711ef
Author: Sairudra More <sairudra60 at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/test/OpenMP/target_codegen.cpp
M clang/test/OpenMP/target_defaultmap_codegen_01.cpp
M clang/test/OpenMP/target_depend_codegen.cpp
A clang/test/OpenMP/target_firstprivate_pointer_codegen.cpp
M clang/test/OpenMP/target_map_codegen_01.cpp
M clang/test/OpenMP/target_map_codegen_09.cpp
M clang/test/OpenMP/target_map_codegen_10.cpp
M clang/test/OpenMP/target_map_codegen_26.cpp
M clang/test/OpenMP/target_parallel_depend_codegen.cpp
M clang/test/OpenMP/target_parallel_for_depend_codegen.cpp
M clang/test/OpenMP/target_parallel_for_simd_depend_codegen.cpp
M clang/test/OpenMP/target_simd_depend_codegen.cpp
M clang/test/OpenMP/target_teams_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_depend_codegen.cpp
Log Message:
-----------
[OpenMP] Fix firstprivate pointer handling in target regions (#167879)
Firstprivate pointers in OpenMP target regions were not being lowered
correctly, causing the runtime to perform unnecessary present table
lookups instead of passing pointer values directly.
This patch adds the OMP_MAP_LITERAL flag for firstprivate pointers,
enabling the runtime to pass pointer values directly without lookups.
The fix handles both explicit firstprivate clauses and implicit
firstprivate semantics from defaultmap clauses.
Key changes:
- Track defaultmap(firstprivate:...) clauses in MappableExprsHandler
- Add isEffectivelyFirstprivate() to check both explicit and implicit
firstprivate semantics
- Apply OMP_MAP_LITERAL flag to firstprivate pointers in
generateDefaultMapInfo()
Map type values:
- 288 = OMP_MAP_TARGET_PARAM | OMP_MAP_LITERAL (explicit firstprivate)
- 800 = OMP_MAP_TARGET_PARAM | OMP_MAP_LITERAL | OMP_MAP_IS_PTR
(implicit firstprivate from defaultmap)
Before: Pointers got 544 (TARGET_PARAM | IS_PTR) causing runtime lookups
After: Pointers get 288 or 800 (includes LITERAL) for direct pass
Updated the 16 existing test cases in OpenMP that were expecting the
previous (buggy) behavior. The tests were checking for map type values
of 544 (TARGET_PARAM | IS_PTR) and 32 (TARGET_PARAM) for firstprivate
pointers, which lacked the LITERAL flag (256). With this fix,
firstprivate pointers now correctly include the LITERAL flag, resulting
in map types 800 (TARGET_PARAM | LITERAL | IS_PTR) for implicit
firstprivate and 288 (TARGET_PARAM | LITERAL) for explicit firstprivate.
The updated tests now validate the correct behavior as per OpenMP 5.2
semantics, where firstprivate variables should be passed by value rather
than requiring runtime present table lookups.
---------
Co-authored-by: Sairudra More <moresair at pe31.hpc.amslabs.hpecorp.net>
Co-authored-by: Alexey Bataev <a.bataev at gmx.com>
Commit: 274a4c0c03af8f37108479328285299414268cfa
https://github.com/llvm/llvm-project/commit/274a4c0c03af8f37108479328285299414268cfa
Author: Alcaro <floating at muncher.se>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M libcxx/include/__bit/has_single_bit.h
Log Message:
-----------
[libc++] Optimize std::has_single_bit (#133063)
Clang translates most implementations of has_single_bit to `(v ^ (v-1))
> v-1` - except the one definition libc++ actually uses.
Proof of correctness: https://godbolt.org/z/d61bxW4r1
(Could also be fixed by teaching Clang to optimize better, but making
source match output feels clearer to me. And it improves unoptimized
performance.)
Commit: 347512ff38748ac6ebfacbfda172edb5cf1edbe2
https://github.com/llvm/llvm-project/commit/347512ff38748ac6ebfacbfda172edb5cf1edbe2
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/include/fstream
R libcxx/test/benchmarks/streams/fstream.bench.cpp
A libcxx/test/benchmarks/streams/ofstream.bench.cpp
M libcxx/test/libcxx/input.output/file.streams/fstreams/filebuf/traits_mismatch.verify.cpp
M libcxx/test/libcxx/input.output/file.streams/fstreams/traits_mismatch.verify.cpp
Log Message:
-----------
[libc++] Revert fstream::read optimizations (#168894)
This causes various runtime failures, as reported in #168628.
This reverts both #165223 and #167779
Commit: d36e2b621fd9e3354cef00135ad0cb8923ae4269
https://github.com/llvm/llvm-project/commit/d36e2b621fd9e3354cef00135ad0cb8923ae4269
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M openmp/runtime/src/kmp.h
Log Message:
-----------
[OpenMP][libomp] Add transparent task flag bit to kmp_tasking_flags (#168873)
Clang is adding support for the new `OpenMP transparent` clause on
`task` and `taskloop` directives.
The parsing and semantic handling for this clause is introduced in
https://github.com/llvm/llvm-project/pull/166810 .
To allow the compiler to communicate this clause to the `OpenMP`
runtime, a dedicated bit in `kmp_tasking_flags` is required.
This patch adds a new compiler-reserved bit `transparent` to the`
kmp_tasking_flags` structure.
Commit: 4fca7b05e397e381466d6943a56f8407349c7594
https://github.com/llvm/llvm-project/commit/4fca7b05e397e381466d6943a56f8407349c7594
Author: Kashika Akhouri <akhourik at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/test/Sema/warn-lifetime-safety-dataflow.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
Log Message:
-----------
[LifetimeSafety] Detect expiry of loans to trivially destructed types (#168855)
Handling Trivially Destructed Types
This PR uses `AddLifetime` to handle expiry of loans to trivially
destructed types.
Example:
```cpp
int * trivial_uar(){
int *ptr;
int x = 1;
ptr = &x;
return ptr;
}
```
The CFG created now has an Expire Fact for trivially destructed types:
```
Function: trivial_uar
Block B2:
End of Block
Block B1:
Issue (0 (Path: x), ToOrigin: 0 (Expr: DeclRefExpr))
OriginFlow (Dest: 1 (Expr: UnaryOperator), Src: 0 (Expr: DeclRefExpr))
Use (2 (Decl: ptr), Write)
OriginFlow (Dest: 2 (Decl: ptr), Src: 1 (Expr: UnaryOperator))
Use (2 (Decl: ptr), Read)
OriginFlow (Dest: 3 (Expr: ImplicitCastExpr), Src: 2 (Decl: ptr))
Expire (0 (Path: x))
OriginEscapes (3 (Expr: ImplicitCastExpr))
End of Block
Block B0:
End of Block
```
This Expire Fact issues UAR and UAF warnings.
Fixes https://github.com/llvm/llvm-project/issues/162862
Commit: 5ab49edde282814f41b90431194afaff694deba7
https://github.com/llvm/llvm-project/commit/5ab49edde282814f41b90431194afaff694deba7
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/include/mlir-c/IR.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/test/python/ir/blocks.py
Log Message:
-----------
[mlir][py][c] Enable setting block arg locations. (#169033)
This enables changing the location of a block argument. Follows the
approach for updating type of block arg.
Commit: fe743233579113594f7ef964d735f41d60a211e3
https://github.com/llvm/llvm-project/commit/fe743233579113594f7ef964d735f41d60a211e3
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Avoid introducing illegal types in LowerVECTOR_COMPRESS (NFC) (#168520)
This does not seem to be an issue currently, but when using
VECTOR_COMPRESS as part of another lowering, I found these BITCASTs
would result in "Unexpected illegal type!" errors.
For example, this would convert the legal nxv2f32 type into the illegal
nxv2i32 type. This patch avoids this by using no-op casts for unpacked
types.
Commit: d69320e775a7c4af8f6e6bb6bd0574ead8e3d69c
https://github.com/llvm/llvm-project/commit/d69320e775a7c4af8f6e6bb6bd0574ead8e3d69c
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/Basic/OpenMPKinds.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/OpenACC/ACC.td
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/lib/Frontend/OpenMP/OMP.cpp
M llvm/test/TableGen/directive1.td
M llvm/test/TableGen/directive2.td
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
Log Message:
-----------
[OpenMP] Introduce "loop sequence" as directive association (#168934)
OpenMP 6.0 introduced a `fuse` directive, and with it a "loop sequence"
as the associated code. What used to be "loop association" has become
"loop-nest association".
Rename Association::Loop to LoopNest, add Association::LoopSeq to
represent the "loop sequence" association.
Change the association of fuse from "block" to "loop sequence".
Commit: e6f3cca4e846ff45eaf1d1e57cf297904da7189a
https://github.com/llvm/llvm-project/commit/e6f3cca4e846ff45eaf1d1e57cf297904da7189a
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
Log Message:
-----------
[RISCV] Update SpacemiT-X60 vector mask instructions latencies (#150644)
This PR adds hardware-measured latencies for all instructions defined in
Section 15 of the RVV specification: "Vector Mask Instructions" to the
SpacemiT-X60 scheduling model.
Commit: 6a5231e2005edce724844354f17060c5dd3c68aa
https://github.com/llvm/llvm-project/commit/6a5231e2005edce724844354f17060c5dd3c68aa
Author: Roger Ferrer Ibáñez <rofirrim at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGStmtOpenMP.cpp
Log Message:
-----------
[clang][OpenMP][CodeGen] Use an else if instead of checking twice (#168776)
These two classes are mutually exclusive so avoid doing the two checks
when the first succeeded.
Commit: db5eeddbd3f1d5cdb86e365a2a80b036bd66de7f
https://github.com/llvm/llvm-project/commit/db5eeddbd3f1d5cdb86e365a2a80b036bd66de7f
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Debugging/ELFDebugObjectPlugin.h
M llvm/lib/ExecutionEngine/Orc/Debugging/ELFDebugObjectPlugin.cpp
Log Message:
-----------
[ORC] Tailor ELF debugger support plugin to load-address patching only (#168518)
In 4 years the ELF debugger support plugin wasn't adapted to other
object formats or debugging approaches. After the renaming NFC in
https://github.com/llvm/llvm-project/pull/168343, this patch tailors the
plugin to ELF and section load-address patching. It allows removal of
abstractions and consolidate processing steps with the newly enabled
AllocActions from https://github.com/llvm/llvm-project/pull/168343.
The key change is to process debug sections in one place in a
post-allocation pass. Since we can handle the endianness of the ELF file
the single `visitSectionLoadAddresses()` visitor function now, we don't
need to track debug objects and sections in template classes anymore. We
keep using the `DebugObject` class and drop `DebugObjectSection`,
`ELFDebugObjectSection<ELFT>` and `ELFDebugObject`.
Furthermore, we now use the allocation's working memory for load-address
fixups directly. We can drop the `WritableMemoryBuffer` from the debug
object and most of the `finalizeWorkingMemory()` step, which saves one
copy of the entire debug object buffer. Inlining `finalizeAsync()` into
the pre-fixup pass simplifies quite some logic.
We still track `RegisteredObjs` here, because we want to free memory
once the corresponding code is freed. There will be a follow-up patch
that turns it into a dealloc action.
Commit: 31a552def53964025ccc507c6c90002a5d8d7e25
https://github.com/llvm/llvm-project/commit/31a552def53964025ccc507c6c90002a5d8d7e25
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/LoopCacheAnalysis.h
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
M llvm/test/Analysis/LoopCacheAnalysis/interchange-refcost-overflow.ll
M llvm/test/Transforms/LoopInterchange/pr43326.ll
Log Message:
-----------
[LoopCacheAnalysis] Replace delinearization for fixed size array (#164798)
This patch replaces the delinearization function used in
LoopCacheAnalysis, switching from one that depends on type information
in GEPs to one that does not. Once this patch and
https://github.com/llvm/llvm-project/pull/161822 are landed, we can
delete `tryDelinearizeFixedSize` from Delienarization, which is an
optimization heuristic guided by GEP type information. After Polly
eliminates its use of `getIndexExpressionsFromGEP`, we will be able to
completely delete GEP-driven heuristics from Delinearization.
Commit: 49995b2af0abbec1095031dfe9eb049945b6d4f7
https://github.com/llvm/llvm-project/commit/49995b2af0abbec1095031dfe9eb049945b6d4f7
Author: Giacomo Castiglioni <giacastiglioni at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h
M mlir/include/mlir/Dialect/GPU/IR/GPUBase.td
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/test/Conversion/GPUToNVVM/wmma-ops-to-nvvm.mlir
M mlir/test/Dialect/GPU/invalid.mlir
A mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f64.mlir
Log Message:
-----------
[MLIR][GPU] subgroup_mma fp64 extension (#165873)
This PR extends the `gpu.subgroup_mma_*` ops to support fp64 type.
The extension requires special handling during the lowering to `nvvm`
due to the return type for load ops for fragment a and b (they return a
scalar instead of a struct).
Commit: a2dc4e02e7ba77ddcb0afca0304535d8f142c98b
https://github.com/llvm/llvm-project/commit/a2dc4e02e7ba77ddcb0afca0304535d8f142c98b
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/add_u64.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/ds_read2-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
M llvm/test/CodeGen/AMDGPU/flat-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/s-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/sub_u64.ll
M llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
Log Message:
-----------
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
This patch enables the multi-group xnack replay mode by
configuring the hardware MODE register at kernel entry.
This aligns the hardware behavior with the compiler's
existing multi-group s_wait_xcnt insertion logic.
Commit: f4ebee0ca980f807de32841288b3785dadbc471d
https://github.com/llvm/llvm-project/commit/f4ebee0ca980f807de32841288b3785dadbc471d
Author: Ferran Toda <f.toda.c at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M flang/include/flang/Parser/openmp-utils.h
M flang/include/flang/Semantics/openmp-directive-sets.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/openmp-utils.cpp
M flang/lib/Semantics/canonicalize-omp.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-parse-tree.cpp
A flang/test/Parser/OpenMP/fail-looprange.f90
A flang/test/Parser/OpenMP/fuse-looprange.f90
A flang/test/Parser/OpenMP/fuse01.f90
A flang/test/Parser/OpenMP/fuse02.f90
A flang/test/Parser/OpenMP/loop-transformation-construct04.f90
A flang/test/Parser/OpenMP/loop-transformation-construct05.f90
A flang/test/Semantics/OpenMP/loop-transformation-clauses01.f90
M flang/test/Semantics/OpenMP/loop-transformation-construct01.f90
A flang/test/Semantics/OpenMP/loop-transformation-construct02.f90
A flang/test/Semantics/OpenMP/loop-transformation-construct03.f90
A flang/test/Semantics/OpenMP/loop-transformation-construct04.f90
M flang/test/Semantics/OpenMP/tile02.f90
Log Message:
-----------
[Flang][OpenMP] Add semantic support for Loop Sequences and OpenMP loop fuse (#161213)
This patch adds semantics for the `omp fuse` directive in flang, as
specified in OpenMP 6.0. This patch also enables semantic support for
loop sequences which are needed for the fuse directive along with
semantics for the `looprange` clause. These changes are only semantic.
Relevant tests have been added , and previous behavior is retained with
no changes.
---------
Co-authored-by: Ferran Toda <ferran.todacasaban at bsc.es>
Co-authored-by: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Commit: 3005886fee0402cbe7ae9fd93e765fa3a68e68eb
https://github.com/llvm/llvm-project/commit/3005886fee0402cbe7ae9fd93e765fa3a68e68eb
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M flang/test/Semantics/OpenMP/loop-transformation-construct01.f90
Log Message:
-----------
[flang][OpenMP] Fix some typo-like things in test case (#168582)
Commit: 31711c908fbd391601122c3457e71d0714fe4117
https://github.com/llvm/llvm-project/commit/31711c908fbd391601122c3457e71d0714fe4117
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
Log Message:
-----------
[VPlan] Only apply forced cost to recipes with underlying values. (#168372)
Only apply forced instruction costs to recipes with underlying values to
match the legacy cost model. A VPlan may have a number of additional
VPInstructions without underlying values that are not considered for its
cost, and assigning forced costs to them would incorrectly inflate its
cost.
This fixes a cost divergence between legacy and VPlan-based cost models
with forced instruction costs.
PR: https://github.com/llvm/llvm-project/pull/168372
Commit: b98f6a54f6ccff67d6eb1cfa25a3f3d919c8f6c9
https://github.com/llvm/llvm-project/commit/b98f6a54f6ccff67d6eb1cfa25a3f3d919c8f6c9
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
Log Message:
-----------
[VPlan] Cast to VPIRMetadata in getMemoryLocation (NFC) (#169028)
This allows us to strip an unnecessary TypeSwitch.
Commit: 2a3e745eaa75047e368024ad437950fa239a4aeb
https://github.com/llvm/llvm-project/commit/2a3e745eaa75047e368024ad437950fa239a4aeb
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-scale-to-agpr.mir
Log Message:
-----------
Fix test from #168609 (#169041)
Commit: 560b83c0cd814562ed3542583b0f62a908bcd767
https://github.com/llvm/llvm-project/commit/560b83c0cd814562ed3542583b0f62a908bcd767
Author: Matthew Nagy <matthew.nagy at sony.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/docs/TypeSanitizer.rst
M clang/docs/UsersManual.rst
M clang/include/clang/Driver/SanitizerArgs.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/SanitizerArgs.cpp
A clang/test/CodeGen/sanitize-type-outlined.cpp
M llvm/docs/ReleaseNotes.md
M llvm/lib/Transforms/Instrumentation/TypeSanitizer.cpp
M llvm/test/Instrumentation/TypeSanitizer/access-with-offset.ll
M llvm/test/Instrumentation/TypeSanitizer/alloca-only.ll
M llvm/test/Instrumentation/TypeSanitizer/alloca.ll
M llvm/test/Instrumentation/TypeSanitizer/anon.ll
M llvm/test/Instrumentation/TypeSanitizer/basic-nosan.ll
M llvm/test/Instrumentation/TypeSanitizer/basic.ll
R llvm/test/Instrumentation/TypeSanitizer/basic_outlined.ll
M llvm/test/Instrumentation/TypeSanitizer/byval.ll
M llvm/test/Instrumentation/TypeSanitizer/globals.ll
R llvm/test/Instrumentation/TypeSanitizer/globals_outlined.ll
M llvm/test/Instrumentation/TypeSanitizer/invalid-metadata.ll
M llvm/test/Instrumentation/TypeSanitizer/memintrinsics.ll
M llvm/test/Instrumentation/TypeSanitizer/nosanitize.ll
M llvm/test/Instrumentation/TypeSanitizer/sanitize-no-tbaa.ll
M llvm/test/Instrumentation/TypeSanitizer/swifterror.ll
Log Message:
-----------
[TySan][Clang] Add clang flag to use tysan outlined instrumentation a… (#166170)
…nd update docs
Commit: 8c3f59f1b297ec65b5870ebfd727a40f632de966
https://github.com/llvm/llvm-project/commit/8c3f59f1b297ec65b5870ebfd727a40f632de966
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h
M mlir/include/mlir/Dialect/GPU/IR/GPUBase.td
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/test/Conversion/GPUToNVVM/wmma-ops-to-nvvm.mlir
M mlir/test/Dialect/GPU/invalid.mlir
R mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f64.mlir
Log Message:
-----------
Revert "[MLIR][GPU] subgroup_mma fp64 extension" (#169049)
Reverts llvm/llvm-project#165873
The revert is triggered by a failing integration test on a couple of
buildbots.
Commit: 77c329f54ca5cc884001e216afa47990aad27de4
https://github.com/llvm/llvm-project/commit/77c329f54ca5cc884001e216afa47990aad27de4
Author: Muzammiluddin Syed <muzasyed at amd.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[mlir][ROCDL] Adds wmma scaled intrinsics for gfx1250 (#165915)
Signed-off-by: Muzammiluddin Syed <muzasyed at amd.com>
Commit: bc323b609bd54747b8acda45d91a19f7a343a91b
https://github.com/llvm/llvm-project/commit/bc323b609bd54747b8acda45d91a19f7a343a91b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
R llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
A llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
Log Message:
-----------
AMDGPU: Stop implementing shouldCoalesce (#168988)
Use the default, which freely coalesces anything it can.
This mostly shows improvements, with a handful of regressions.
The main concern would be if introducing wider registers is more
likely to push the register usage up to the next occupancy tier.
Commit: 0b6db777ba9821bc17b969ddf6fefee54519c4f4
https://github.com/llvm/llvm-project/commit/0b6db777ba9821bc17b969ddf6fefee54519c4f4
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-av-classes.ll
M llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
Log Message:
-----------
[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)
Fix a problem exposed by #166483 using AV classes in more places.
`isVectorRegister` only accepts registers of VGPR or AGPR classes.
`hasVectorRegisters` additionally accepts the combined AV classes.
Fixes: #168761
Commit: 89bb99dd0ed9c7e5dbbc80c6cfb369768bfee96b
https://github.com/llvm/llvm-project/commit/89bb99dd0ed9c7e5dbbc80c6cfb369768bfee96b
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenACC/Support/RegisterOpenACCExtensions.cpp
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
Log Message:
-----------
[acc][flang] Implement acc interface for tracking type descriptors (#168982)
FIR operations that use derived types need to have type descriptor
globals available on device when offloading. Examples of this can be
seen in `CUFDeviceGlobal` which ensures that such type descriptor uses
work on device for CUF.
Similarly, this is needed for OpenACC. This change introduces a new
interface to the OpenACC dialect named
`IndirectGlobalAccessOpInterface` which can be attached to operations
that may result in generation of accesses that use type descriptor
globals. This functionality is needed for the `ACCImplicitDeclare` pass
that is coming in a follow-up change which implicitly ensures that all
referenced globals are available in OpenACC compute contexts.
The interface provides a `getReferencedSymbols` method that collects all
global symbols referenced by an operation. When a symbol table is
provided, the implementation for FIR recursively walks type descriptor
globals to find all transitively referenced symbols.
Note that alternately this could have been implemented in different
ways:
- Codegen could implicitly generate such type globals as needed by
changing the technique that relies on populating them during lowering
(eg generate them directly in gpu.module during codegen).
- This interface could attach to types instead of operations for a
potentially more conservative implementation which maps all type
descriptors even if the underlying implementation using it won't
necessarily need such mapping.
The technique chosen here is consistent with `CUFDeviceGlobal` (which
walks operations inside `prepareImplicitDeviceGlobals`) and avoids
conservative mapping of all type descriptors.
Commit: 4538818c797a486edf48cbdf047a354210c3843b
https://github.com/llvm/llvm-project/commit/4538818c797a486edf48cbdf047a354210c3843b
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/test/OpenMP/spirv_target_codegen_basic.cpp
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
A mlir/test/Target/LLVMIR/omptarget-runtimecc.mlir
Log Message:
-----------
[OpenMP][OMPIRBuilder] Use runtime CC for runtime calls (#168608)
Some targets have a specific calling convention that should be used for
generated calls to runtime functions.
Pass that down and use it.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: bb2e4686c1c8e4955ff5d18a7baaef3fe14ba36e
https://github.com/llvm/llvm-project/commit/bb2e4686c1c8e4955ff5d18a7baaef3fe14ba36e
Author: Andrew Haberlandt <ndrewh at users.noreply.github.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_platform_mac.cpp
Log Message:
-----------
[TSan] [Darwin] Fix off by one in TSAN init due to MemoryRangeIsAvailable (#169008)
Commit: 76a68164bb29171664c91f3583b047e2913f5e73
https://github.com/llvm/llvm-project/commit/76a68164bb29171664c91f3583b047e2913f5e73
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M flang/lib/Lower/Runtime.cpp
Log Message:
-----------
[flang][NFC] replace std::exit by fir::emitFatalError in Lower/Runtime.cpp (#169050)
Commit: f56ddde410cd143792ce165958bc42fdcc9f7bb5
https://github.com/llvm/llvm-project/commit/f56ddde410cd143792ce165958bc42fdcc9f7bb5
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMInstrThumb2.td
A llvm/test/CodeGen/Thumb2/LowOverheadLoops/pr168209.ll
Log Message:
-----------
[ARM] Restore hasSideEffects flag on t2WhileLoopSetup (#168948)
ARM relies on deprecated TableGen behavior of guessing instruction
properties from patterns (`def ARM : Target` doesn't have
`guessInstructionProperties` set to false).
Before #168209, TableGen conservatively guessed that `t2WhileLoopSetup`
has side effects because the instruction wasn't matched by any pattern.
After the patch, TableGen guesses it has no side effects because the
added pattern uses only `arm_wlssetup` node, which has no side effects.
Add `SDNPSideEffect` to the node so that TableGen guesses the property
right, and also `hasSideEffects = 1` to the instruction in case ARM ever
sets `guessInstructionProperties` to false.
Commit: 01227abf8d0f2c4f8d0718354dab2e8ddca8640e
https://github.com/llvm/llvm-project/commit/01227abf8d0f2c4f8d0718354dab2e8ddca8640e
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel][ORC] Port #168518: orc deps (#169059)
Commit: e724009f2f449dfcfb44c29f39872b56f6a85af1
https://github.com/llvm/llvm-project/commit/e724009f2f449dfcfb44c29f39872b56f6a85af1
Author: David Peixotto <peix at meta.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M lldb/unittests/Expression/DWARFExpressionTest.cpp
Log Message:
-----------
[lldb] Add MockMemory class for dwarf expression testing (#168467)
This change unifies the way that we specify mocked memory to make it
easy to control the process and target memory contents for unit tests.
We add a MockMemory class that can be used in dwarf expression testing
to specify the output of the `ReadMemory` function.
The MockMemory class is built on a map that maps a `(address, size)`
pair to a vector of bytes that is `size` bytes long and contains the
memory contents for that `address`.
The MockProcessWithMemRead and MockTarget classes are updated to use the
new MockMemory interface. The MockProcessWithMemRead class was renamed
to MockProcess and the old MockProcess was deleted. The old MockProcess had
and ReadMemory implementation that returned the value `i & 0xff` for reading the
address `i` and was easily be replaced with the MockMemory object.
The CreateTestContext function now takes optional values for process memory and
target memory and uses those to create the mock objects.
Commit: 9d2b7ecb46e1c9e0f07679238bc060aebae24072
https://github.com/llvm/llvm-project/commit/9d2b7ecb46e1c9e0f07679238bc060aebae24072
Author: Sebastian Pop <spop at nvidia.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/Propagating.ll
M llvm/test/Analysis/DependenceAnalysis/SymbolicSIV.ll
M llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
M llvm/test/Analysis/DependenceAnalysis/run-specific-dependence-test.ll
Log Message:
-----------
[DA] remove getSplitIteration (#167698)
Remove getSplitIteration.
A follow-up patch will also remove DVEntry::Splitable and Dependnece::isSplitable.
Commit: 8be46410248f8298af1f12be1c52e2824ce25951
https://github.com/llvm/llvm-project/commit/8be46410248f8298af1f12be1c52e2824ce25951
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/select-case-statement.f90
Log Message:
-----------
[flang] Use hlfir.cmpchar for SELECT CASE of charsSelect case hlfir cmpchar (#168476)
For SELECT CASE with character selector, instead of allways calling
runtime comparison function, emit hlfir.cmpchar. This has different
behaviors at different optimization levels: at -O0, it still emits
flang-rt call, but at higher optimization levels it does inline
comparison. Modify test/Lower/select-case-statement.f90 to test both
comparison cases.
Commit: b27749d8c7191f894e337a402344af7a9de9a5b0
https://github.com/llvm/llvm-project/commit/b27749d8c7191f894e337a402344af7a9de9a5b0
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/memtag.h
M compiler-rt/lib/scudo/standalone/tests/memtag_test.cpp
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
Log Message:
-----------
[scudo] Small cleanup of memory tagging code part 2. (#168807)
Make the systemSupportsMemoryTagging() function return even on system
that don't support memory tagging. This avoids the need to always check
if memory tagging is supported before calling the function.
Modify iterateOverChunks() to call useMemoryTagging<>(Options) to
determine if mte is supported. This already uses the cached check of
systemSupportsMemoryTagging() rather than directly calling that
function.
Updated the code that calls systemSupportsMemoryTagging().
Commit: f7e0432219b2c9de80d0ccd198748f563d2a71ea
https://github.com/llvm/llvm-project/commit/f7e0432219b2c9de80d0ccd198748f563d2a71ea
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/LTO/LTOModule.cpp
Log Message:
-----------
[LTO] Use a range-based for loop (NFC) (#169000)
Identified with modernize-loop-convert.
Commit: 2185379528cb3d7f29c3eca1501fec2121fd1c02
https://github.com/llvm/llvm-project/commit/2185379528cb3d7f29c3eca1501fec2121fd1c02
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/include/llvm/CAS/OnDiskTrieRawHashMap.h
Log Message:
-----------
[CAS] Remove redundant casts (NFC) (#169002)
FileOffset::get already returns uint64_t.
Identified with readability-redundant-casting.
Commit: b6c2c100347b11bbf79277e442f505ca2d6bc021
https://github.com/llvm/llvm-project/commit/b6c2c100347b11bbf79277e442f505ca2d6bc021
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/ExprObjC.h
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/AST/Stmt.h
M clang/lib/AST/ExprObjC.cpp
Log Message:
-----------
[AST] Construct iterator_range with the conversion constructor (NFC) (#169004)
This patch simplifies iterator_range construction with the conversion
constructor.
Commit: 28c048ec0f0a677115a0b00a88a7d013f925f2b8
https://github.com/llvm/llvm-project/commit/28c048ec0f0a677115a0b00a88a7d013f925f2b8
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
R compiler-rt/test/profile/Linux/instrprof-debug-info-correlate-warnings.c
A compiler-rt/test/profile/Linux/instrprof-debug-info-correlate-warnings.ll
M llvm/lib/ProfileData/InstrProfCorrelator.cpp
Log Message:
-----------
[profdata] Skip probes with missing counter and function pointers (#163254)
Commit: 55d8b63195882d07ec4dc390d2c558bebc4e295d
https://github.com/llvm/llvm-project/commit/55d8b63195882d07ec4dc390d2c558bebc4e295d
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M lldb/cmake/modules/LLDBConfig.cmake
Log Message:
-----------
[lldb] Don't enable the Limited C API with Python 3.13 and SWIG 4.4.0 (#169065)
Don't automatically enable the Limited C API when we're targeting Python
3.13 or later in combination with SWIG 4.4.0 due to a bug in the latter.
SWIG Issue: https://github.com/swig/swig/issues/3283
SWIG PR: https://github.com/swig/swig/pull/3285
Commit: f8a803952e9e8daa2c2714d8346b696799e9c833
https://github.com/llvm/llvm-project/commit/f8a803952e9e8daa2c2714d8346b696799e9c833
Author: Fabrice de Gans <Steelskin at users.noreply.github.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/include/llvm/Support/ThreadPool.h
Log Message:
-----------
llvm: Disable copy for SingleThreadExecutor (#168782)
This is a workaround for the MSVC compiler, which attempts to generate a
copy assignment operator implementation for classes marked as
`__declspec(dllexport)`. Explicitly marking the copy assignment operator
as deleted works around the problem.
DevCom ticket:
https://developercommunity.microsoft.com/t/Classes-marked-with-__declspecdllexport/11003192
Commit: 39d4dfbe55cbea6ca7d506b8acd8455ed0443bf9
https://github.com/llvm/llvm-project/commit/39d4dfbe55cbea6ca7d506b8acd8455ed0443bf9
Author: Ryan Buchner <buchner.ryan at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
A llvm/test/CodeGen/RISCV/vmadd-reassociate.ll
Log Message:
-----------
[RISCV] Incorporate scalar addends to extend vector multiply accumulate chains (#168660)
Previously, the following:
%mul0 = mul nsw <8 x i32> %m00, %m01
%mul1 = mul nsw <8 x i32> %m10, %m11
%add0 = add <8 x i32> %mul0, splat (i32 32)
%add1 = add <8 x i32> %add0, %mul1
lowered to:
vsetivli zero, 8, e32, m2, ta, ma
vmul.vv v8, v8, v9
vmacc.vv v8, v11, v10
li a0, 32
vadd.vx v8, v8, a0
After this patch, now lowers to:
li a0, 32
vsetivli zero, 8, e32, m2, ta, ma
vmv.v.x v12, a0
vmadd.vv v8, v9, v12
vmacc.vv v8, v11, v10
Modeled on 0cc981e0 from the AArch64 backend.
C-code for the example case (`clang -O3 -S -mcpu=sifive-x280`):
```
int madd_fail(int a, int b, int * restrict src, int * restrict dst, int loop_bound) {
for (int i = 0; i < loop_bound; i += 2) {
dst[i] = src[i] * a + src[i + 1] * b + 32;
}
}
```
Commit: 4511c355c35153c6b8f5fd3d0b75f77c126fe8e6
https://github.com/llvm/llvm-project/commit/4511c355c35153c6b8f5fd3d0b75f77c126fe8e6
Author: Nathan Corbyn <n_corbyn at apple.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
Log Message:
-----------
Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)
PR causes build failures with expensive checks enabled
Reverts llvm/llvm-project#168546
Commit: dbac91743aa0167d783568a593dfe8b675b38b46
https://github.com/llvm/llvm-project/commit/dbac91743aa0167d783568a593dfe8b675b38b46
Author: Hendrik Hübner <117831077+HendrikHuebner at users.noreply.github.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
Log Message:
-----------
[CIR] Add NYI cases to builtin switch statement and move existing cases into functions (#168699)
This PR adds a number of cases to the switch statement in
`CIRGenBUiltin.cpp`. Some existing cases were relocated, so the order
matches the order from the switch statement in clangs codegen.
Additionally, some exisiting cases were moved to functions, to keep the
code a little cleaner. In the future, it will be easier to keep track of
which builtins have not been implemented, since there would always be a
NYI case for unimplemented builtins.
Commit: 36d7e911dcb5f87145ad079e658bd564933ba19c
https://github.com/llvm/llvm-project/commit/36d7e911dcb5f87145ad079e658bd564933ba19c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/test/Target/SPIRV/mlir-translate.mlir
M mlir/test/Target/SPIRV/module.mlir
Log Message:
-----------
[MLIR] Drop use of REQUIRES:shell from tests (#168989)
This patch drops two instances of REQUIRES: shell from MLIR tests. This
feature does not mean much given the internal shell is the default for
MLIR. It does prevent these tests from running on Windows, but it does
not seem like there is anything inherent to these tests preventing them
from running on Windows (minus maybe the lack of spirv-tools, which is
explicitly required anyways.
Commit: 226c51c58b6a26b78f0884a2a45ecc527afdc4b1
https://github.com/llvm/llvm-project/commit/226c51c58b6a26b78f0884a2a45ecc527afdc4b1
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaStmt.cpp
R clang/test/OpenMP/nvptx_target_exceptions_messages.cpp
A clang/test/OpenMP/target_exceptions_messages.cpp
Log Message:
-----------
[clang][Sema][OpenMP] Fix GPU exception target check (#169056)
Looks like I missed this when I added `Triple::isGPU()`.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 00fb67af95635009f1539c88e8706665f4a2d017
https://github.com/llvm/llvm-project/commit/00fb67af95635009f1539c88e8706665f4a2d017
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Support/CommandLine.cpp
Log Message:
-----------
[Support] Use range-based for loops (NFC) (#169001)
Identified with modernize-loop-convert.
Commit: fea070b610e0dc08447be60db7f13c150b2892d5
https://github.com/llvm/llvm-project/commit/fea070b610e0dc08447be60db7f13c150b2892d5
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-methods-lib.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-methods-ps.hlsl
M clang/test/CodeGenHLSL/resources/TypedBuffers-methods.hlsl
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
Log Message:
-----------
[HLSL] Add Load overload with status (#166449)
This PR adds a Load method for resources, which takes an additional
parameter by reference, status. It fills the status parameter with a 1
or 0, depending on whether or not the resource access was mapped.
CheckAccessFullyMapped is also added as an intrinsic, and called in the
production of this status bit.
Only addresses DXIL for the below issue:
https://github.com/llvm/llvm-project/issues/138910
Also only addresses the DXIL variant for the below issue:
https://github.com/llvm/llvm-project/issues/99204
Commit: 0182a76970e4e7a9faa3be049ea371128a28ee39
https://github.com/llvm/llvm-project/commit/0182a76970e4e7a9faa3be049ea371128a28ee39
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Debugging/ELFDebugObjectPlugin.h
M llvm/lib/ExecutionEngine/Orc/Debugging/ELFDebugObjectPlugin.cpp
Log Message:
-----------
Revert "[ORC] Tailor ELF debugger support plugin to load-address patching only" (#169073)
Reverts llvm/llvm-project#168518
Commit: 5dbe83c3023a795595b52e75cdfc7835882e5db1
https://github.com/llvm/llvm-project/commit/5dbe83c3023a795595b52e75cdfc7835882e5db1
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/test/CIR/CodeGenOpenACC/declare-link.cpp
M clang/test/CIR/CodeGenOpenACC/openacc-not-implemented.cpp
Log Message:
-----------
[OpenACC][CIR] Handle 'declare' construct local lowering (&link clause) (#168793)
'declare' is a declaration directive, so it can appear at 3 places:
Global/NS scope, class scope, or local scope. This patch implements ONLY
the 'local' scope lowering for 'declare'.
A 'declare' is lowered as a 'declare_enter' and 'declare_exit'
operation, plus data operands like all others. Sema restricts the form
of some of these, but they are otherwise identical.
'declare' DOES require at least 1 clause for the examples to make sense,
so this ALSO implements 'link', which is the 'simpliest' one. It is ONLY
attached to the 'declare_enter', and doesn't require any additional work
besides a very small addition to how we handle clauses.
Commit: c6876603e9870fd16252f7796871b1a797a10bf1
https://github.com/llvm/llvm-project/commit/c6876603e9870fd16252f7796871b1a797a10bf1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
Log Message:
-----------
AMDGPU: Add baseline test for split/widen invariant loads (#168913)
This works fine on main, but broke after a future patch.
Commit: f8bbb21fb9d25c18cad6e197eb29378f060975aa
https://github.com/llvm/llvm-project/commit/f8bbb21fb9d25c18cad6e197eb29378f060975aa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
AMDGPU: Handle invariant when lowering global loads (#168914)
Global with invariant should be treated identically to
constant.
Commit: 76425fd368f68813ed4b26759d9e91cc40a1c1bd
https://github.com/llvm/llvm-project/commit/76425fd368f68813ed4b26759d9e91cc40a1c1bd
Author: Matthew Nagy <matthew.nagy at sony.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/test/CodeGen/sanitize-type-outlined.cpp
Log Message:
-----------
fix tysan test failing on unsupported arches (#169066)
Commit: 1a29a2359b70f1bb4141324162dcfe4d27a6f026
https://github.com/llvm/llvm-project/commit/1a29a2359b70f1bb4141324162dcfe4d27a6f026
Author: venk-ks <156861430+venk-ks at users.noreply.github.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaChecking.cpp
M clang/test/Sema/warn-fortify-source.c
Log Message:
-----------
[Clang][Sema] Add fortify warnings for strcat (#168965)
Continue to add fortify warnings that are missing in Clang for string
functions as part of #142230
Commit: ebb04b2b4c38e6bb7b6068f3474a8e8edf912f4d
https://github.com/llvm/llvm-project/commit/ebb04b2b4c38e6bb7b6068f3474a8e8edf912f4d
Author: Jin Huang <jinhuang1102 at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/test/Transforms/ExpandVariadics/expand-va-intrinsic-split-linkage.ll
M llvm/test/Transforms/ExpandVariadics/expand-va-intrinsic-split-simple.ll
M llvm/test/Transforms/ExpandVariadics/intrinsics.ll
Log Message:
-----------
[profcheck] Propagate profile metadata to Wrapper function in optimize mode of ExpandVariadic. (#168161)
This PR fixes the issue where profile metadata (`!prof`) is dropped from
the `VariadicWrapper` when `ExpandVariadics` runs in
`--expand-variadics-override=optimize` mode.
In optimize mode, the pass splits the original variadic function into
two parts:
- A **VariadicWrapper** (retaining the original name) that handles the
`va_list` setup.
- A **FixedArityReplacement** (new function) that contains the original
core logic.
During this process, the basic blocks and associated metadata are
spliced into the `FixedArityReplacement`. Consequently, the
`VariadicWrapper`—which serves as the entry point for callers—is left
without function entry count metadata.
This change explicitly copies the `MD_prof` metadata from the
`FixedArityReplacement` back to the `VariadicWrapper` after the split is
defined.
Co-authored-by: Jin Huang <jingold at google.com>
Commit: 52f9a57b2961da168b2a5ffe9eee687fe9068c2b
https://github.com/llvm/llvm-project/commit/52f9a57b2961da168b2a5ffe9eee687fe9068c2b
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang-tools-extra/clang-doc/assets/namespace-template.mustache
M clang-tools-extra/test/clang-doc/mustache-separate-namespace.cpp
Log Message:
-----------
[clang-doc] Fix `</section>` mismatch in the namespace template (#168966)
A `</section>` tag wasn't inside the `{{#HasRecords}}` Mustache tag, which caused a
mismatch if there weren't any records to render.
Commit: 69589dd2c0b34a664c24f7ffbb084d2eea848ab6
https://github.com/llvm/llvm-project/commit/69589dd2c0b34a664c24f7ffbb084d2eea848ab6
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AMDGPU/shufflevector.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-chain-to-shuffles.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-i8.ll
Log Message:
-----------
AMDGPU: Improve getShuffleCost accuracy for 8- and 16-bit shuffles (#168818)
These shuffles can always be implemented using v_perm_b32, and so this
rewrites the analysis from the perspective of "how many v_perm_b32s does
it take to assemble each register of the result?"
The test changes in Transforms/SLPVectorizer/reduction.ll are
reasonable: VI (gfx8) has native f16 math, but not packed math.
Commit: 3fec26e3294ae0f276ff08fd810850421444588c
https://github.com/llvm/llvm-project/commit/3fec26e3294ae0f276ff08fd810850421444588c
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
Log Message:
-----------
[DAGCombiner] Don't optimize insert_vector_elt into shuffle if implicit truncation exists (#169022)
Fixes #169017
Commit: ad9bc6a1b5f5dc51d25fe4c9715318b1023bcc80
https://github.com/llvm/llvm-project/commit/ad9bc6a1b5f5dc51d25fe4c9715318b1023bcc80
Author: Sebastian Pop <spop at nvidia.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
[DA] remove Constraints class (#168963)
Remove the Constraints class from dependence analysis as it is now unused.
Commit: 9a56e55ee9b3ee174bef9d74710819c68908615f
https://github.com/llvm/llvm-project/commit/9a56e55ee9b3ee174bef9d74710819c68908615f
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/test/CIR/CodeGenOpenACC/declare-deviceptr.cpp
Log Message:
-----------
[OpenACC][CIR] deviceptr clause lowering for local 'declare' (#169085)
This is very similar to the 'link' that was done in the last patch,
except this works on all storage, but only on pointers. This also shows
a bit more of how the enter/exit pairs work in the test.
Implementation itself is very simple, as it is just properly handling it
in the clause handler.
Commit: 45081fb706a6c4983d06285e0d0da991964a624a
https://github.com/llvm/llvm-project/commit/45081fb706a6c4983d06285e0d0da991964a624a
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang-tools-extra/clang-doc/assets/class-template.mustache
M clang-tools-extra/clang-doc/assets/namespace-template.mustache
M clang-tools-extra/test/clang-doc/mustache-index.cpp
Log Message:
-----------
[clang-doc] `<ul>` must be nested in `<li>` (#168972)
The HTML spec states that only `<li>` can be children of `<ul>`. Nested
`<ul>` tags in an unordered list must be children of `<li>`.
Commit: 6be7cf085ba9e2c02ecb490992f59bbcf111289e
https://github.com/llvm/llvm-project/commit/6be7cf085ba9e2c02ecb490992f59bbcf111289e
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/include/mlir/Analysis/Presburger/PresburgerSpace.h
Log Message:
-----------
[mlir][presburger] Fix PresburgerSpace comment (#167292)
Commit: 427c18208f73e8d193c4e8f0e05493cb9d2272eb
https://github.com/llvm/llvm-project/commit/427c18208f73e8d193c4e8f0e05493cb9d2272eb
Author: Sebastian Pop <spop at nvidia.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopUnrollAndJam/dependencies_multidims.ll
Log Message:
-----------
[unroll-and-jam] Document dependencies_multidims.ll and fix loop bounds (NFC) (#156578)
Add detailed comments explaining why each function should/shouldn't be
unroll-and-jammed based on memory access patterns and dependencies.
Fix loop bounds to ensure array accesses are within array bounds:
* sub_sub_less: j starts from 1 (not 0) to ensure j-1 >= 0
* sub_sub_less_3d: k starts from 1 (not 0) to ensure k-1 >= 0
* sub_sub_outer_scalar: j starts from 1 (not 0) to ensure j-1 >= 0
Commit: a52e1af7f766e26a78d10d31da98af041dd66410
https://github.com/llvm/llvm-project/commit/a52e1af7f766e26a78d10d31da98af041dd66410
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang-tools-extra/clang-tidy/objc/AssertEqualsCheck.cpp
M clang/docs/LibASTMatchersReference.html
M clang/include/clang/ASTMatchers/ASTMatchers.h
Log Message:
-----------
[ASTMatchers] Make isExpandedFromMacro accept llvm::StringRef (#167060)
We can use non-owning `StringRef` in `MacroName` parameter to avoid
unnecessary copy because `MacroName` only used as an argument to
`internal::getExpansionLocOfMacro` which already accept `StringRef`.
Commit: 4d97b78b8fa1f5e1a9ea1d7ab5ac181a239e0813
https://github.com/llvm/llvm-project/commit/4d97b78b8fa1f5e1a9ea1d7ab5ac181a239e0813
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang-tools-extra/clang-tidy/.clang-tidy
M clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.cpp
Log Message:
-----------
[clang-tidy][NFC] Enable misc-const-correctness rule in clang-tidy codebase (#167172)
After successful `misc-const-correctness` cleanup (last patch
https://github.com/llvm/llvm-project/pull/167131), we can enable
`misc-const-correctness` rule for the whole project.
During cleanup, I didn't encounter any false positives so it's safe to
assume that we will have minimal FP in the future.
Commit: 778e104dee8186c8a8c8ed781692825fb3a8bec8
https://github.com/llvm/llvm-project/commit/778e104dee8186c8a8c8ed781692825fb3a8bec8
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
Log Message:
-----------
[MLIR] [XeGPU] Fix dropSgLayoutAndData & dropInstData in SliceAttr (#168618)
Commit: 68ba2864d936a59ac1e382f754a15b975b04900d
https://github.com/llvm/llvm-project/commit/68ba2864d936a59ac1e382f754a15b975b04900d
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
Log Message:
-----------
[SCEVExp] Remove early exit, rely on InstSimplifyFolder (NFCI).
Remove the SCEV-based check refined in
https://github.com/llvm/llvm-project/pull/156910, as InstSimplifyFolder
manages to simplify the generated code to false directly as well.
Commit: 86cbb36b36c15af82a87e89c08fb84792657583d
https://github.com/llvm/llvm-project/commit/86cbb36b36c15af82a87e89c08fb84792657583d
Author: Frankie Robertson <frankier at users.noreply.github.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M lld/COFF/DriverUtils.cpp
M lld/COFF/Options.td
M lld/test/COFF/driver.test
Log Message:
-----------
[lld] Add (ignored) /link flag to lld-link for compatibility with MSVC link.exe (#168364)
Various build tools may produce command lines invoking clang-cl and
lld-link which contain /link twice like so: e.g. `clang-cl.exe
sanitycheckcpp.cc /Fesanitycheckcpp.exe .... /link /link ...`
If link.exe is used, it ignores the extra `/link` and just issues a
warning, however lld-link tries to treat `/link` as a file name.
This PR adds a flag which is ignored in order to improve compatibility
with link.exe
There's some extra context including an "in-the-wild" example and
reproducer of the problem here:
https://github.com/frankier/meson_clang_win_activation
Co-authored-by: Frankie Robertson <frankie at robertson.name>
Commit: 6ed829baa3861adbe053c16878fbae74b9c1e9d6
https://github.com/llvm/llvm-project/commit/6ed829baa3861adbe053c16878fbae74b9c1e9d6
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M lldb/bindings/lua/lua-typemaps.swig
Log Message:
-----------
[lldb] Restore the old behavior in lua-typemaps.swig (#169103)
Restore the original behavior (i.e. before #167764), which uses
eOpenOptionWriteOnly, not eOpenOptionReadWrite. Fixes TestLuaAPI.py.
Commit: 2fcbdc18dfdf13a13d693b3e6523c25d65246d8c
https://github.com/llvm/llvm-project/commit/2fcbdc18dfdf13a13d693b3e6523c25d65246d8c
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/test/CodeGen/sanitize-type-outlined.cpp
Log Message:
-----------
Really fix tysan test failing on unsupported arches (#169096)
'target' is not one of the features recognized by clang tests, and the
test doesn't require X86 backend to be built. Specify the target
explicitly instead. Remove duplicate `-fsanitize=type` as well.
Commit: 3d5191fd7508caaff5435c2ed1d90fe472d3f0c1
https://github.com/llvm/llvm-project/commit/3d5191fd7508caaff5435c2ed1d90fe472d3f0c1
Author: Jessica Clarke <jrtc27 at jrtc27.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/unittests/Support/SignalsTest.cpp
Log Message:
-----------
[test][Support] Disable SignalsTest.PrintsSymbolizerMarkup (#168974)
This test checks that DSOMarkupPrinter::printDSOMarkup prints the module
and segment mappings, but that is only done if we can determine the GNU
build ID for the given object, and in many environments that is not
enabled by default (e.g. the FreeBSD Clang driver never enables it, and
various other Clang drivers only do so when ENABLE_LINKER_BUILD_ID is
opted into at configure time). GCC tends to enable it by default, and
many distributions enable it for Clang, so this has gone unnoticed for a
while, but this test has been failing on FreeBSD since its creation.
Fixes: 22b9404f09dc ("Optionally print symbolizer markup backtraces.")
See: https://github.com/llvm/llvm-project/issues/168891
Commit: bf6e3f1deed81b8783a6b4ceccbbc3f6a4f65283
https://github.com/llvm/llvm-project/commit/bf6e3f1deed81b8783a6b4ceccbbc3f6a4f65283
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang-tools-extra/include-cleaner/test/lit.cfg.py
Log Message:
-----------
[include-cleaner] Use lit internal shell by default for tests (#169092)
All of the tests seem to be compatible with the internal shell and the
internal shell is typically faster by 10-15% on top of providing a
better debugging experience.
Commit: d7307f458cd3522470859ce0cee8d47d37a70670
https://github.com/llvm/llvm-project/commit/d7307f458cd3522470859ce0cee8d47d37a70670
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M compiler-rt/test/orc/TestCases/Darwin/x86-64/objc-imageinfo.S
Log Message:
-----------
[ORC] Fix obj-imageinfo.S on X86 Darwin with Internal Shell (#169104)
d464c99f595b69d3a34b361b6a935e803c60d308 fixes this test on AArch64
Darwin, but I did not realize that there was another X86 version of the
test. This patch also updates the X86 version of the test in a similar
manner.
Commit: 9fa7627d891007e495eb701a30c09761403f8042
https://github.com/llvm/llvm-project/commit/9fa7627d891007e495eb701a30c09761403f8042
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
DAG: Handle poison in m_Undef (#168288)
Commit: 7e6c913f35de79d89eefb35f0ce5086f11a6f454
https://github.com/llvm/llvm-project/commit/7e6c913f35de79d89eefb35f0ce5086f11a6f454
Author: John Harrison <harjohn at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M lldb/unittests/Editline/EditlineTest.cpp
Log Message:
-----------
[lldb] Fix EditlineTest closing files multiple times. (#169100)
This updates the EditlineTest to use `lldb::FileSP` to ensure the
associated FDs are only closed a single time.
Currently, there is some confusion between the `FilePointer`,
`PseudoTerminal` and `LockableStreamFile` about when the files are
closed resulting in a crash in some due to a `fflush` on a closed file.
Commit: 677fbf8edbc5057f43e8cc178c4aa50a857aa7c1
https://github.com/llvm/llvm-project/commit/677fbf8edbc5057f43e8cc178c4aa50a857aa7c1
Author: Thibault Monnier <97551402+Thibault-Monnier at users.noreply.github.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
A clang/test/CIR/CodeGen/X86/avx-builtins.c
A clang/test/CIR/CodeGen/X86/avx10_2_512bf16-builtins.c
A clang/test/CIR/CodeGen/X86/avx10_2bf16-builtins.c
A clang/test/CIR/CodeGen/X86/avx512f-builtins.c
A clang/test/CIR/CodeGen/X86/avx512fp16-builtins.c
M clang/test/CIR/CodeGen/X86/sse-builtins.c
M clang/test/CIR/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[CIR] Upstream CIR codegen for undef x86 builtins (#167945)
Commit: 136c9da55f72f692b9d2e9f623e09ae619a86e37
https://github.com/llvm/llvm-project/commit/136c9da55f72f692b9d2e9f623e09ae619a86e37
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCXX.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/test/CIR/CodeGen/global-init.cpp
Log Message:
-----------
[CIR] Implement global array dtor support (#169070)
This implements handling to destroy global arrays that require
destruction. Unlike classic codegen, CIR emits the destructor loop into
a 'dtor' region associated with the global array variable. Later, during
LoweringPrepare, this code is moved into a helper function and a call to
__cxa_atexit arranges for it to be called during the shared object
shutdown.
Commit: 13011fe5c16be3ac12e9d7f5530d5301ebeb484e
https://github.com/llvm/llvm-project/commit/13011fe5c16be3ac12e9d7f5530d5301ebeb484e
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M lldb/include/lldb/Utility/NonNullSharedPtr.h
Log Message:
-----------
[lldb] Remove Base::unique from NonNullSharedPtr (#169130)
It seems like this fails on macOS with C++20
Commit: 5bf7e8a59a281988a0f5d2b659ba9d71b2c389c8
https://github.com/llvm/llvm-project/commit/5bf7e8a59a281988a0f5d2b659ba9d71b2c389c8
Author: adams381 <adams at nvidia.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGen/builtins-overflow.cpp
Log Message:
-----------
[CIR] Upstream overflow builtins (#166643)
This implements the builtins that handle overflow.
This fixes issue https://github.com/llvm/llvm-project/issues/163888
Commit: dc3c5a5ffceb64c5c948e1d22b6d81023bef65b6
https://github.com/llvm/llvm-project/commit/dc3c5a5ffceb64c5c948e1d22b6d81023bef65b6
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M utils/bazel/.bazelrc
Log Message:
-----------
[bazel] Remove old config option (#169133)
The default of this has been flipped since we're on 8.x
Commit: 99120bb51bf728d7ba7fad5068227f8c6e707159
https://github.com/llvm/llvm-project/commit/99120bb51bf728d7ba7fad5068227f8c6e707159
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M .ci/premerge_advisor_explain.py
Log Message:
-----------
[CI] Make Premerge only Comment if Tests Failed (#169102)
Before, we were unconditionally writing a message. After this patch, we
only write a message when the tests failed, or there is already an
existing comment. This is how this workflow was intended to work
originally, but is not how it ended up working, mostly due to my
misconceptions around how the existing code formatter pass handled this
case (we need to actually not write out any comments, not write out a
specific message).
Commit: 58e2dde45f775328b71b532e65762a9696ccccbd
https://github.com/llvm/llvm-project/commit/58e2dde45f775328b71b532e65762a9696ccccbd
Author: Joshua Haberman <jhaberman at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M lld/MachO/SymbolTable.cpp
A lld/test/MachO/weak-alias-override.s
Log Message:
-----------
[lld:MachO] Allow independent override of weak symbols aliased via .set (#167825)
Currently, if multiple external weak symbols are defined at the same
address in an object file (e.g., by using the .set assembler directive
to alias them to a single weak variable), ld64.lld treats them as a
single unit. When any one of these symbols is overridden by a strong
definition, all of the original weak symbols resolve to the strong
definition.
This patch changes the behavior in `transplantSymbolsAtOffset`. When a
weak symbol is being replaced by a strong one, only non-external (local)
symbols at the same offset are moved to the new symbol's section. Other
*external* symbols are no longer transplanted.
This allows each external weak symbol to be overridden independently.
This behavior is consistent with Apple's ld-classic, but diverges from
ld-prime in one case, as noted on
https://github.com/llvm/llvm-project/issues/167262 (this discrepancy has
recently been reported to Apple).
### Backward Compatibility
This change alters linker behavior for a specific scenario. The creation
of multiple external weak symbols aliased to the same address via
assembler directives is primarily an advanced technique. It's unlikely
that existing builds rely on the current behavior of all aliases being
overridden together.
If there are concerns, this could be put behind a linker option, but the
new default seems more correct, less surprising, and is consistent with
ld-classic.
### Testing
The new lit test `test/MachO/weak-alias-override.s` verifies this
behavior using llvm-nm.
Fixes #167262
Commit: 54a4da9df6906b63878ad6d0ea6da3ed7d2d8432
https://github.com/llvm/llvm-project/commit/54a4da9df6906b63878ad6d0ea6da3ed7d2d8432
Author: Zequan Wu <zequanwu at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/ASTMutationListener.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/VTableBuilder.h
M clang/include/clang/Basic/ABI.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/VTableBuilder.cpp
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CodeGen/CGCXX.cpp
M clang/lib/CodeGen/CGCXXABI.cpp
M clang/lib/CodeGen/CGCXXABI.h
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Serialization/ASTCommon.h
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/CodeGenCXX/dllexport.cpp
M clang/test/CodeGenCXX/microsoft-abi-extern-template.cpp
M clang/test/CodeGenCXX/microsoft-abi-structors.cpp
M clang/test/CodeGenCXX/microsoft-abi-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-vftables.cpp
M clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-multiple-nonvirtual-inheritance-vdtors.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-return-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-single-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-virtual-inheritance-vtordisps.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-virtual-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-no-rtti-data.cpp
R clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
M clang/test/CodeGenCXX/vtable-consteval.cpp
M clang/test/DebugInfo/CXX/windows-dtor.cpp
R clang/test/Modules/Inputs/msvc-vector-deleting-dtors/module.modulemap
R clang/test/Modules/Inputs/msvc-vector-deleting-dtors/msvc-vector-deleting-dtors.h
R clang/test/Modules/msvc-vector-deleting-destructors.cpp
M clang/test/Modules/vtable-windows.cppm
R clang/test/PCH/Inputs/msvc-vector-deleting-dtors.h
R clang/test/PCH/msvc-vector-deleting-destructors.cpp
M clang/test/Profile/cxx-abc-deleting-dtor.cpp
R clang/test/SemaCXX/gh134265.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
Log Message:
-----------
Revert "Reland [MS][clang] Add support for vector deleting destructors" (#169116)
This reverts 4d10c1165442cbbbc0017b48fcdd7dae1ccf3678 and its two
dependent commits: e6b9805b574bb5c90263ec7fbcb94df76d2807a4 and
c243406a695ca056a07ef4064b0f9feee7685320, see discussion in
https://github.com/llvm/llvm-project/pull/165598#issuecomment-3563825509.
Commit: 8bdbc57b8975d77da88562392299ee5d9c2b6cbb
https://github.com/llvm/llvm-project/commit/8bdbc57b8975d77da88562392299ee5d9c2b6cbb
Author: Dan Liew <dan at su-root.co.uk>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/test/Shell/helper/toolchain.py
M llvm/utils/lit/lit/llvm/config.py
Log Message:
-----------
[NFC][LLDB] Make it possible to detect if the compiler used in tests supports -fbounds-safety (#169112)
This patch makes it possible to detect in LLDB shell and API tests if
`-fbounds-safety` is supported by the compiler used for testing. The
motivation behind this is to allow upstreaming
https://github.com/swiftlang/llvm-project/pull/11835 but with the tests
disabled in upstream because the full implementation of -fbounds-safety
isn't available in Clang yet.
For shell tests when -fbounds-safety is available the
`clang-bounds-safety` feature is available which means tests can be
annotated with `# REQUIRES: clang-bounds-safety`.
API tests that need -fbounds-safety support in the compiler can use the
new `@skipUnlessBoundsSafety` decorator.
rdar://165225507
Commit: b6dadc7e4d263e9983418d5362653edd4575c1b2
https://github.com/llvm/llvm-project/commit/b6dadc7e4d263e9983418d5362653edd4575c1b2
Author: dpalermo <dan.palermo at amd.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/test/OpenMP/target_codegen.cpp
M clang/test/OpenMP/target_defaultmap_codegen_01.cpp
M clang/test/OpenMP/target_depend_codegen.cpp
R clang/test/OpenMP/target_firstprivate_pointer_codegen.cpp
M clang/test/OpenMP/target_map_codegen_01.cpp
M clang/test/OpenMP/target_map_codegen_09.cpp
M clang/test/OpenMP/target_map_codegen_10.cpp
M clang/test/OpenMP/target_map_codegen_26.cpp
M clang/test/OpenMP/target_parallel_depend_codegen.cpp
M clang/test/OpenMP/target_parallel_for_depend_codegen.cpp
M clang/test/OpenMP/target_parallel_for_simd_depend_codegen.cpp
M clang/test/OpenMP/target_simd_depend_codegen.cpp
M clang/test/OpenMP/target_teams_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_depend_codegen.cpp
Log Message:
-----------
Revert "[OpenMP] Fix firstprivate pointer handling in target regions" (#169143)
Reverts llvm/llvm-project#167879
This PR is causing assertions in the check-offload tests:
https://lab.llvm.org/staging/#/builders/105
https://lab.llvm.org/staging/#/builders/105/builds/37057
Commit: cc7e2067b1a0fd799a5bfeab4b11d399ea7831a2
https://github.com/llvm/llvm-project/commit/cc7e2067b1a0fd799a5bfeab4b11d399ea7831a2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M lldb/source/Target/Target.cpp
M lldb/source/Utility/StringExtractorGDBRemote.cpp
Log Message:
-----------
[lldb] Remove redundant declarations (NFC) (#169003)
In C++17, static constexpr members are implicitly inline, so they no
longer require an out-of-line definition.
Identified with readability-redundant-declaration.
Commit: 89189218b8ba0a2a64ae1f0f76f485eaf06ad6c6
https://github.com/llvm/llvm-project/commit/89189218b8ba0a2a64ae1f0f76f485eaf06ad6c6
Author: Sergei Druzhkov <serzhdruzhok at gmail.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/LibStdcpp.cpp
M lldb/source/Plugins/Language/ObjC/NSSet.cpp
Log Message:
-----------
[NFC][lldb] Remove duplicated checks (#169093)
Removed duplicated checks reported by cppcheck
Commit: 3841e7d818de2b7581351c6de3bfc9b13bdaeb30
https://github.com/llvm/llvm-project/commit/3841e7d818de2b7581351c6de3bfc9b13bdaeb30
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/test/AST/ByteCode/new-delete.cpp
Log Message:
-----------
[clang][bytecode] Don't call getThis() on the bottom function frame (#169044)
We can't access the calling frame in that case.
Fixes https://github.com/llvm/llvm-project/issues/169032
Commit: 6b75b44ed5ed6e6e72955132a60ce8cca38bcbad
https://github.com/llvm/llvm-project/commit/6b75b44ed5ed6e6e72955132a60ce8cca38bcbad
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_pointer.pass.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_reference.pass.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_request_invalid_value_category.verify.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/const_correctness.verify.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/not_copy_constructible.verify.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/reference_types.verify.cpp
Log Message:
-----------
[libc++][any][NFC] Reformat and refactor any_cast tests (#169057)
...in preparation for https://github.com/llvm/llvm-project/pull/168826
as requested in the review.
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: 226765b60cc54e03386f38874a177c906f5aa6e7
https://github.com/llvm/llvm-project/commit/226765b60cc54e03386f38874a177c906f5aa6e7
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-21 (Fri, 21 Nov 2025)
Changed paths:
M libcxx/utils/libcxx/test/features/availability.py
Log Message:
-----------
[NFC] [test] [libcxx] Fix invalid escape sequences (#168636)
```
>>> "_target-has-llvm-21 || target={{.+}}-apple-macosx{{26.[0-9](.\d+)?}}" == r"_target-has-llvm-21 || target={{.+}}-apple-macosx{{26.[0-9](.\\
d+)?}}"
<python-input-6>:1: SyntaxWarning: invalid escape sequence '\d'
True
>>> "_target-has-llvm-20 || target={{.+}}-apple-macosx{{15.[4-9](.\d+)?}}" == r"_target-has-llvm-20 || target={{.+}}-apple-macosx{{15.[4-9](.\\
d+)?}}"
<python-input-7>:1: SyntaxWarning: invalid escape sequence '\d'
True
>>> "_target-has-llvm-19 || target={{.+}}-apple-macosx{{15.[0-3](.\d+)?}}" == r"_target-has-llvm-19 || target={{.+}}-apple-macosx{{15.[0-3](.\\
d+)?}}"
<python-input-8>:1: SyntaxWarning: invalid escape sequence '\d'
True
>>> "_target-has-llvm-18 || target={{.+}}-apple-macosx{{14.[4-9](.\d+)?}}" == r"_target-has-llvm-18 || target={{.+}}-apple-macosx{{14.[4-9](.\\
d+)?}}"
<python-input-9>:1: SyntaxWarning: invalid escape sequence '\d'
True
```
Commit: ad7a5d4e059741819baa1561bfd9bc98d29260f3
https://github.com/llvm/llvm-project/commit/ad7a5d4e059741819baa1561bfd9bc98d29260f3
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/CallBrPrepare.h
M llvm/lib/CodeGen/CallBrPrepare.cpp
Log Message:
-----------
[CallBrPrepare] Prefer Function &F over Function &Fn
Function &F is the more standard abbreviation (~4000 uses in llvm versus
~300 uses).
Commit: 20ebc7ea8209cb8f1ff3916706b6e7d8232c9f3f
https://github.com/llvm/llvm-project/commit/20ebc7ea8209cb8f1ff3916706b6e7d8232c9f3f
Author: Shubham Sandeep Rastogi <Shubham.Rastogi at sony.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M llvm/docs/SourceLevelDebugging.rst
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfo.h
M llvm/include/llvm/IR/DebugProgramInstruction.h
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugProgramInstruction.cpp
M llvm/lib/IR/Verifier.cpp
A llvm/test/Assembler/dbg_declare_value.ll
Log Message:
-----------
Add new llvm.dbg.declare_value intrinsic. (#168132)
For swift async code, we need to use a debug intrinsic that behaves like
an llvm.dbg.declare but can take any location type rather than just a
pointer or integer.
To solve this, a new debug instrinsic called llvm.dbg.declare_value has
been created, which behaves exactly like an llvm.dbg.declare but can
take non pointer and integer location types.
More information here:
https://discourse.llvm.org/t/rfc-introduce-new-llvm-dbg-coroframe-entry-intrinsic/88269
This is the first patch as part of a stack of patches, with the one
succeeding it being: https://github.com/llvm/llvm-project/pull/168134
Commit: b8f8ef5109fe117dc53f4f8f6afb1b2d3bd4101d
https://github.com/llvm/llvm-project/commit/b8f8ef5109fe117dc53f4f8f6afb1b2d3bd4101d
Author: Marco Elver <elver at google.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/lib/Driver/SanitizerArgs.cpp
M clang/test/Driver/fsanitize-coverage.c
Log Message:
-----------
[Clang][Driver] Allow -fsanitize-coverage with -fsanitize=alloc-token (#169128)
These are not incompatible; allow them to be combined.
Commit: 4128b213ee93750766c57b5b37d239be53b80c26
https://github.com/llvm/llvm-project/commit/4128b213ee93750766c57b5b37d239be53b80c26
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/test/CIR/CodeGen/atomic.c
Log Message:
-----------
[CIR] Add support for non-compile-time memory order (#168892)
This patch upstreams CIR support for atomic operations with memory
orders that are not known at compile time.
Commit: 7305b6eb5458b5cea62b3ab70da95b790cf988f3
https://github.com/llvm/llvm-project/commit/7305b6eb5458b5cea62b3ab70da95b790cf988f3
Author: Muhammad Abdul <alilo.ghazali at gmail.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
Log Message:
-----------
[clang][X86] Allow VALIGND/Q element-shift intrinsics in constexpr evaluation (#168206)
Fixes #167681
Commit: 9daf4345ec836d50740805c878bd570dd4093354
https://github.com/llvm/llvm-project/commit/9daf4345ec836d50740805c878bd570dd4093354
Author: Michael Klemm <michael.klemm at amd.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/include/flang/Support/LangOptions.def
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Driver/fast-real-mod.f90
M flang/test/Lower/Intrinsics/fast-real-mod.f90
Log Message:
-----------
[Flang] Add -ffast-real-mod back for further control of MOD optimizations (#167118)
It turns out that having `-ffast-math` as the only option to control
optimizations for MOD for REAL kinds (PR #160660) is too coarse-grained
for some applications. Thus, this PR adds back `-ffast-real-mod` to have
more control over the optimization. The `-ffast-math` flag will still
enable the optimization, and `-fno-fast-real-mod` allows one to disable
it.
Commit: 8ba27138b2f948224fefdd0d2a44862d6100d119
https://github.com/llvm/llvm-project/commit/8ba27138b2f948224fefdd0d2a44862d6100d119
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M libcxx/include/any
A libcxx/test/libcxx/utilities/any/nodiscard.verify.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_request_invalid_value_category.verify.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/const_correctness.verify.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/not_copy_constructible.verify.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/reference_types.verify.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/void.verify.cpp
Log Message:
-----------
[libc++][any] Applied `[[nodiscard]]` (#168826)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 2e424deeb6180d112323f4df955c8034eb56780c
https://github.com/llvm/llvm-project/commit/2e424deeb6180d112323f4df955c8034eb56780c
Author: stomfaig <55883018+stomfaig at users.noreply.github.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avx512vlintrin.h
M clang/lib/Headers/avxintrin.h
M clang/test/CodeGen/X86/avx-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
Log Message:
-----------
[Clang][X86] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - allow VPERMILPD/S variable mask intrinsics to be used in constexpr (#168861)
Allowing VPERMILPD/S intrinsics to be used in constexpr
Closes #167878
Commit: cc4dd015ad4a1b33d43fbac00d62f6b309a96ff4
https://github.com/llvm/llvm-project/commit/cc4dd015ad4a1b33d43fbac00d62f6b309a96ff4
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
Log Message:
-----------
[clang][bytecode][NFC] Remove VariableScope::emitDestruction (#169148)
destroyLocals() does the same thing.
Commit: e8af134bb7f891caa49178c8a04a8ca944c611df
https://github.com/llvm/llvm-project/commit/e8af134bb7f891caa49178c8a04a8ca944c611df
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp-trunc.ll
Log Message:
-----------
[InstCombine] Generalize trunc-shift-icmp fold from (1 << Y) to (Pow2 << Y) (#169163)
Extends the `icmp(trunc(shl))` fold to handle any power of 2 constant as
the shift base, not just 1. This generalizes the following patterns by
adjusting the comparison offsets by `log2(Pow2)`.
```llvm
(trunc (1 << Y) to iN) == 0 --> Y u>= N
(trunc (1 << Y) to iN) != 0 --> Y u< N
(trunc (1 << Y) to iN) == 2**C --> Y == C
(trunc (1 << Y) to iN) != 2**C --> Y != C
; to
(trunc (Pow2 << Y) to iN) == 0 --> Y u>= N - log2(Pow2)
(trunc (Pow2 << Y) to iN) != 0 --> Y u< N - log2(Pow2)
(trunc (Pow2 << Y) to iN) == 2**C --> Y == C - log2(Pow2)
(trunc (Pow2 << Y) to iN) != 2**C --> Y != C - log2(Pow2)
```
Proof: https://alive2.llvm.org/ce/z/2zwTkp
Commit: c4921b75a96ccebbad57a9938ec34ca7d0c89c42
https://github.com/llvm/llvm-project/commit/c4921b75a96ccebbad57a9938ec34ca7d0c89c42
Author: n2h9 <13541181+n2h9 at users.noreply.github.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M lldb/include/lldb/Core/Disassembler.h
M lldb/source/Core/Disassembler.cpp
Log Message:
-----------
[lldb] [disassembler] chore: update VariableAnnotator::Annotate to except only Instruction as param and drop module and target (#168276)
Commit: 126462035a1eb7adeb97f6beac48b6bddac65d09
https://github.com/llvm/llvm-project/commit/126462035a1eb7adeb97f6beac48b6bddac65d09
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M compiler-rt/test/ubsan_minimal/TestCases/test-darwin-interface.c
Log Message:
-----------
[UBSan] Fix test-darwin-interface.c on X86 Darwin with Internal Shell (#169105)
This test was failing with the internal shell due to the use of
subshells. This was not caught in my initial round of testing due to me
only using a M4 Mac for running my tests.
Commit: 456ca91815c3fdb60b5ca695c8bb05b75016a343
https://github.com/llvm/llvm-project/commit/456ca91815c3fdb60b5ca695c8bb05b75016a343
Author: NagaChaitanya Vellanki <pnagato at protonmail.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/avx512bitalgintrin.h
M clang/lib/Headers/avx512vlbitalgintrin.h
M clang/test/CodeGen/X86/avx512bitalg-builtins.c
M clang/test/CodeGen/X86/avx512vlbitalg-builtins.c
Log Message:
-----------
[Clang] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - Allow AVX512 VPSHUFBITQMB intrinsics to be used in constexpr (#168100)
Resolves #161337
Commit: b00c620b3504565d9769a434bc7d4e97854cd788
https://github.com/llvm/llvm-project/commit/b00c620b3504565d9769a434bc7d4e97854cd788
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
Log Message:
-----------
[X86] Move _mm512_mask_blend_pd/ps tests to avx512f-builtins.c (#169170)
These aren't AVX512VL tests
Commit: 216e85bdda22ae7eda3f3e04c51d9d6d82e2b617
https://github.com/llvm/llvm-project/commit/216e85bdda22ae7eda3f3e04c51d9d6d82e2b617
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M mlir/python/mlir/dialects/linalg/opdsl/lang/yaml_helper.py
M mlir/python/requirements.txt
Log Message:
-----------
[MLIR][Python] remove PyYAML as a dep (#169145)
PyYAML is not an actual use-time/runtime dependency of our bindings. It
is necessary only if someone wants to regenerate
`LinalgNamedStructuredOps.yaml`:
https://github.com/llvm/llvm-project/blob/93097b2d47c87bf5eee0a2612d961c7a01831eab/mlir/tools/mlir-linalg-ods-gen/update_core_linalg_named_ops.sh.in#L29
This PR does the minimal refactor to remove the need during actual run/use time.
Commit: c2d659b9b8efac9f80b8ebcb2b38b61295d82bdc
https://github.com/llvm/llvm-project/commit/c2d659b9b8efac9f80b8ebcb2b38b61295d82bdc
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/executable-parsers.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/parse-tree.cpp
M flang/lib/Semantics/canonicalize-omp.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Lower/OpenMP/nested-loop-transformation-construct02.f90
M flang/test/Parser/OpenMP/fail-looprange.f90
M flang/test/Parser/OpenMP/loop-transformation-construct01.f90
M flang/test/Parser/OpenMP/loop-transformation-construct02.f90
M flang/test/Parser/OpenMP/tile-fail.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/do21.f90
M flang/test/Semantics/OpenMP/loop-association.f90
M flang/test/Semantics/OpenMP/loop-transformation-construct01.f90
M flang/test/Semantics/OpenMP/loop-transformation-construct02.f90
M flang/test/Semantics/OpenMP/loop-transformation-construct03.f90
M flang/test/Semantics/OpenMP/tile02.f90
Log Message:
-----------
[flang][OpenMP] Implement loop nest parser (#168884)
Previously, loop constructs were parsed in a piece-wise manner: the
begin directive, the body, and the end directive were parsed separately.
Later on in canonicalization they were all coalesced into a loop
construct. To facilitate that end-loop directives were given a special
treatment, namely they were parsed as OpenMP constructs. As a result
syntax errors caused by misplaced end-loop directives were handled
differently from those cause by misplaced non-loop end directives.
The new loop nest parser constructs the complete loop construct,
removing the need for the canonicalization step. Additionally, it is the
basis for parsing loop-sequence-associated constructs in the future.
It also removes the need for the special treatment of end-loop
directives. While this patch temporarily degrades the error messaging
for misplaced end-loop directives, it enables uniform handling of any
misplaced end-directives in the future.
Commit: 8baa5bf499e6bf2f43ec7fddf9601524159ec5ea
https://github.com/llvm/llvm-project/commit/8baa5bf499e6bf2f43ec7fddf9601524159ec5ea
Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
M llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-analysis.ll
M llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll
Log Message:
-----------
[DFAJumpThreading] Try harder to avoid cycles in paths. (#169151)
If a threading path has cycles within it then the transformation is not
correct. This patch fixes a couple of cases that create such cycles.
Fixes https://github.com/llvm/llvm-project/issues/166868
Commit: e83cc896e7c2378914a391f942c188d454b517d2
https://github.com/llvm/llvm-project/commit/e83cc896e7c2378914a391f942c188d454b517d2
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M flang/lib/Parser/openmp-parsers.cpp
Log Message:
-----------
[flang][OpenMP] Fix build with gcc 7.5.0 (#169184)
Commit: 080ca902c6aaf1a1bf48df04a65ed163825b2006
https://github.com/llvm/llvm-project/commit/080ca902c6aaf1a1bf48df04a65ed163825b2006
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
Log Message:
-----------
[VPlan] Create resume phis in scalar preheader early. (NFC) (#166099)
Create phi recipes for scalar resume value up front in addInitialSkeleton during initial construction. This will allow moving the remaining code dealing with resume values to VPlan transforms/construction.
PR: https://github.com/llvm/llvm-project/pull/166099
Commit: d96a93ff00ac02bc523d36dd2e687d597a068ae1
https://github.com/llvm/llvm-project/commit/d96a93ff00ac02bc523d36dd2e687d597a068ae1
Author: Fangrui Song <i at maskray.me>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M lld/ELF/InputFiles.cpp
M lld/ELF/Symbols.h
M lld/ELF/SyntheticSections.cpp
M lld/test/ELF/linkerscript/version-script.s
M lld/test/ELF/version-script-extern-undefined.s
M llvm/include/llvm/BinaryFormat/ELF.h
Log Message:
-----------
ELF: Use index 0 for unversioned undefined symbols (#168189)
The GNU documentation is ambiguous about the version index for
unversioned undefined symbols. The current specification at
https://sourceware.org/gnu-gabi/program-loading-and-dynamic-linking.txt
defines VER_NDX_LOCAL (0) as "The symbol is private, and is not
available outside this object."
However, this naming is misleading for undefined symbols. As suggested
in
discussions, VER_NDX_LOCAL should conceptually be VER_NDX_NONE and apply
to unversioned undefined symbols as well.
GNU ld has used index 0 for unversioned undefined symbols both before
version 2.35 (see https://sourceware.org/PR26002) and in the upcoming
2.46 release (see https://sourceware.org/PR33577). This change aligns
with GNU ld's behavior by switching from index 1 to index 0.
While here, add a test to dso-undef-extract-lazy.s that undefined
symbols of index 0 in DSO are treated as unversioned symbols.
Commit: ebb0c9c559b5809be491aa71cbe8235611081194
https://github.com/llvm/llvm-project/commit/ebb0c9c559b5809be491aa71cbe8235611081194
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M flang/include/flang/Parser/openmp-utils.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/openmp-utils.cpp
Log Message:
-----------
[flang][OpenMP] Move some utilities from openmp-parsers to openmp-uti… (#169188)
…ls, NFC
Commit: 29d1e1857d445ca9a6e60c69fe2e1e5b30767e62
https://github.com/llvm/llvm-project/commit/29d1e1857d445ca9a6e60c69fe2e1e5b30767e62
Author: tyb0807 <sontuan.vu119 at gmail.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
A llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir
A llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-name-error.mir
A llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-mfi.ll
A llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-stack-type-error.mir
Log Message:
-----------
[AMDGPU] Enable serializing of allocated preload kernarg SGPRs info (#168374)
- Support serialization of the number of allocated preload kernarg SGPRs
- Support serialization of the first preload kernarg SGPR allocated
Together they enable reconstructing correctly MIR with preload kernarg
SGPRs.
Commit: a2231af5ddafbc82c9d6ecc994690639958c6661
https://github.com/llvm/llvm-project/commit/a2231af5ddafbc82c9d6ecc994690639958c6661
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
Log Message:
-----------
[VPlan] Share PreservesUniformity logic between isSingleScalar and isUniformAcrossVFsAndUFs
Extract the PreservesUniformity logic from isSingleScalar into a shared
static helper function. Update isUniformAcrossVFsAndUFs to use this
logic for VPWidenRecipe and VPInstruction, so that any opcode that
preserves uniformity is considered uniform-across-vf-and-uf if its
operands are.
This unifies the uniformity checking logic and makes it easier to extend
in the future.
This should effectively by NFC currently.
Commit: c81a189c5083b72c128ec33cda8d39367c2e2f1f
https://github.com/llvm/llvm-project/commit/c81a189c5083b72c128ec33cda8d39367c2e2f1f
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M flang/include/flang/Parser/openmp-utils.h
M flang/lib/Parser/openmp-utils.cpp
M flang/lib/Semantics/canonicalize-do.cpp
A flang/test/Parser/OpenMP/atomic-label-do.f90
A flang/test/Parser/OpenMP/cross-label-do.f90
Log Message:
-----------
[flang][OpenMP] Canonicalize loops with intervening OpenMP constructs (#169191)
Example based on the gfortran test a.6.1.f90
```
do 100 i = 1,10
!$omp do
do 100 j = 1,10
call work(i,j)
100 continue
```
During canonicalization of label-DO loops, if the body of an OpenMP
construct ends with a label, treat the label as ending the construct
itself.
This will also allow handling of cases like
```
do 100 i = 1, 10
!$omp atomic write
100 x = i
```
which we were unable to before.
Commit: 9de880e03076e7d9611a205974463465d47d3e21
https://github.com/llvm/llvm-project/commit/9de880e03076e7d9611a205974463465d47d3e21
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Utils/DebugSSAUpdater.cpp
M llvm/utils/TableGen/Basic/TargetLibraryInfoEmitter.cpp
Log Message:
-----------
[llvm] Remove unused local variables (NFC) (#169171)
Identified with bugprone-unused-local-non-trivial-variable.
Commit: 637299e7e079b7d80f508691103092753d282ffa
https://github.com/llvm/llvm-project/commit/637299e7e079b7d80f508691103092753d282ffa
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/utils/TableGen/NeonEmitter.cpp
Log Message:
-----------
[clang] Use llvm::equal (NFC) (#169172)
Identified with llvm-use-ranges.
Commit: b296386d2ca8595c23bc2f90eef902f3c485b1a0
https://github.com/llvm/llvm-project/commit/b296386d2ca8595c23bc2f90eef902f3c485b1a0
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/CallingConvLower.cpp
M llvm/lib/TextAPI/InterfaceFile.cpp
Log Message:
-----------
[llvm] Use llvm::equal (NFC) (#169173)
While I am at it, this patch uses const l-value references for
std::shared_ptr. We don't need to increment the reference count by
passing std::shared_ptr by value.
Identified with llvm-use-ranges.
Commit: c5939937a4d1b7da4477762389dee0afa756bd9c
https://github.com/llvm/llvm-project/commit/c5939937a4d1b7da4477762389dee0afa756bd9c
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/lib/Lex/Preprocessor.cpp
Log Message:
-----------
[Lex] Use a range-based for loop (NFC) (#169174)
Identified with modernize-loop-convert.
Commit: 1c05dfb0e2b14d783e2e08d5c02abdb8cf73877f
https://github.com/llvm/llvm-project/commit/1c05dfb0e2b14d783e2e08d5c02abdb8cf73877f
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/CallAndMessageChecker.cpp
Log Message:
-----------
[StaticAnalyzer] Use a range-based for loop (NFC) (#169175)
Identified with modernize-loop-convert.
Commit: 2d051adc75b45ff7f213bb5d4ee208ac999fc125
https://github.com/llvm/llvm-project/commit/2d051adc75b45ff7f213bb5d4ee208ac999fc125
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M flang/lib/Semantics/canonicalize-do.cpp
Log Message:
-----------
[flang] Add missing include, fix build break after c81a189c50 (#169192)
Commit: 0619292195ecd47ac05b0c7759992b400abec52c
https://github.com/llvm/llvm-project/commit/0619292195ecd47ac05b0c7759992b400abec52c
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/utils/TableGen/CodeEmitterGen.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/Common/CodeGenInstAlias.h
M llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
M llvm/utils/TableGen/DAGISelEmitter.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[TableGen] Constify CodeGenInstruction where possible (NFC) (#169193)
Commit: 0ef522ff68fff4266bf85e7b7a507a16a8fd34ee
https://github.com/llvm/llvm-project/commit/0ef522ff68fff4266bf85e7b7a507a16a8fd34ee
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M llvm/utils/TableGen/CallingConvEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/Common/CodeGenInstruction.cpp
M llvm/utils/TableGen/Common/CodeGenInstruction.h
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.h
M llvm/utils/TableGen/Common/DAGISelMatcher.cpp
M llvm/utils/TableGen/Common/DAGISelMatcher.h
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
M llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/DAGISelMatcherOpt.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/TableGen/SDNodeInfoEmitter.cpp
Log Message:
-----------
[TableGen] Use MVT instead of MVT::SimpleValueType. NFC (#169180)
This improves type safety and is less verbose. Use SimpleTy only where
an integer is needed like switches or emitting a VBR.
---------
Co-authored-by: Sergei Barannikov <barannikov88 at gmail.com>
Commit: 0859ac5866a0228f5607dd329f83f4a9622dedcc
https://github.com/llvm/llvm-project/commit/0859ac5866a0228f5607dd329f83f4a9622dedcc
Author: hstk30-hw <hanwei62 at huawei.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
M llvm/test/CodeGen/AArch64/machine-sink-kill-flags.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/CodeGen/Hexagon/swp-stages5.ll
M llvm/test/CodeGen/NVPTX/atomics-b128.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll
M llvm/test/CodeGen/PowerPC/licm-xxsplti.ll
M llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
M llvm/test/CodeGen/PowerPC/sink-side-effect.ll
M llvm/test/CodeGen/PowerPC/sms-phi-1.ll
M llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/remat.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-reduct.ll
M llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
M llvm/test/CodeGen/WebAssembly/simd-shift-in-loop.ll
M llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
M llvm/test/CodeGen/X86/i128-mul.ll
M llvm/test/CodeGen/X86/loop-strength-reduce5.ll
M llvm/test/CodeGen/X86/madd.ll
M llvm/test/CodeGen/X86/pr49451.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
M llvm/test/CodeGen/X86/xor.ll
Log Message:
-----------
[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)
This maybe a bug which is introduced by commit
6749ae36b4a33769e7a77cf812d7cd0a908ae3b9, and has been present ever
since.
In this case, `OtherReg` always overlaps with `DstReg` cause they from
the `Copy` all.
Commit: 525e68e9e9a44e88eb88ef2d6f058a482972c989
https://github.com/llvm/llvm-project/commit/525e68e9e9a44e88eb88ef2d6f058a482972c989
Author: Daniel M. Katz <katzdm at gmail.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/TreeTransform.h
M clang/test/SemaCXX/cxx2a-consteval.cpp
Log Message:
-----------
Don't mark lambda non-dependent if nested in a generic lambda. (#149121)
Fixes #118187
Fixes #156579
An instantiated `LambdaExpr` can currently be marked as
`LDK_NeverDependent` if it's nested within a generic lambda. If that
`LambdaExpr` in fact depends on template parameters introduced by the
enclosing generic lambda, then its dependence will be misreported as
"never dependent" and spurious diagnostics can result.
The fix here proposed is a bit ugly, but the condition that it's being
bolted onto already seems like a bit of a hack, so this seems no worse
for wear.
Note that #89702 surfaced this change because it caused the inner lambda
expression to (correctly) be considered in a constant-evaluated context.
The affected check for whether to mark the inner lambda as
`LDK_NeverDependent` therefore started to apply, whereas it didn't
before.
**Tested**: `check-clang` and `check-cxx`.
Commit: d5f3ab8ec97786476a077b0c8e35c7c337dfddf2
https://github.com/llvm/llvm-project/commit/d5f3ab8ec97786476a077b0c8e35c7c337dfddf2
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
M llvm/test/CodeGen/AArch64/machine-sink-kill-flags.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/CodeGen/Hexagon/swp-stages5.ll
M llvm/test/CodeGen/NVPTX/atomics-b128.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll
M llvm/test/CodeGen/PowerPC/licm-xxsplti.ll
M llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
M llvm/test/CodeGen/PowerPC/sink-side-effect.ll
M llvm/test/CodeGen/PowerPC/sms-phi-1.ll
M llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/remat.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-reduct.ll
M llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
M llvm/test/CodeGen/WebAssembly/simd-shift-in-loop.ll
M llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
M llvm/test/CodeGen/X86/i128-mul.ll
M llvm/test/CodeGen/X86/loop-strength-reduce5.ll
M llvm/test/CodeGen/X86/madd.ll
M llvm/test/CodeGen/X86/pr49451.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
M llvm/test/CodeGen/X86/xor.ll
Log Message:
-----------
Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)"
This reverts commit 0859ac5866a0228f5607dd329f83f4a9622dedcc.
This caused a couple test failures, likely due to a mid-air collision.
Reverting for now to get the tree back to green and allow the original
author to run UTC/friends and verify the output.
Commit: b9107bfc1faa8aa74e736169626e0cf7eb0925ba
https://github.com/llvm/llvm-project/commit/b9107bfc1faa8aa74e736169626e0cf7eb0925ba
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-22 (Sat, 22 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
M llvm/test/CodeGen/RISCV/zilsd.ll
Log Message:
-----------
[RISCV] Support zilsd-4byte-align for i64 load/store in SelectionDAG. (#169182)
I think we need to keep the SelectionDAG code for volatile load/store so
we should support 4 byte alignment when possible.
Commit: 08f72fe77a53762c94dc04f9fc7c6e038141aa55
https://github.com/llvm/llvm-project/commit/08f72fe77a53762c94dc04f9fc7c6e038141aa55
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
Log Message:
-----------
[TableGen] Remove unnecessary use of MVT::SimpleTy. NFC
This was missed in 0ef522ff68fff4266bf85e7b7a507a16a8fd34ee
Commit: a088e745b7211ab732c99a210ec99345913f668c
https://github.com/llvm/llvm-project/commit/a088e745b7211ab732c99a210ec99345913f668c
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/test/Analysis/suppression-attr.cpp
Log Message:
-----------
[analyzer] Fix [[clang::suppress]] for template instantiations (#168954)
BugSuppression works by traversing the lexical decl context of the
decl-with-issue to record what source ranges should be suppressed by
some attribute.
Note that the decl-with-issue will be changed to the lexical decl
context of the original decl-with-issue, to make suppression attributes
work that were attached to the CXXRecordDecl containing the
CXXMethodDecl (bug report's DeclWithIssue).
It happens so that it uses a DynamicRecursiveASTVisitor, which has a
couple of traversal options. Namely:
- ShouldVisitTemplateInstantiations
- ShouldWalkTypesOfTypeLocs
- ShouldVisitImplicitCode
- ShouldVisitLambdaBody
By default, these have the correct values, except for
ShouldVisitTemplateInstantiations. We should traverse template
instantiations because that might be where the bug is reported - thus,
where we might have a [[clang::suppress]] that we should honor.
In this patch I'll explicitly set these traversal options to avoid
further confusion.
rdar://164646398
Commit: 8ea5e20ce4c44784e970f81a2edbb9680ba85b01
https://github.com/llvm/llvm-project/commit/8ea5e20ce4c44784e970f81a2edbb9680ba85b01
Author: Artem Kroviakov <71938912+akroviakov at users.noreply.github.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
Log Message:
-----------
[MLIR][XeGPU] Disable block count usage in layout propagation (#168504)
Commit: d8b6524d31d32717cf1f314de591f041b045684e
https://github.com/llvm/llvm-project/commit/d8b6524d31d32717cf1f314de591f041b045684e
Author: Hervé Poussineau <hpoussin at reactos.org>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M lld/MinGW/Driver.cpp
M lld/test/MinGW/driver.test
Log Message:
-----------
[LLD][MinGW] Handle MIPS machine (#157742)
Commit: a83e09a788926eb70acdfeee851c6c2fcefd0515
https://github.com/llvm/llvm-project/commit/a83e09a788926eb70acdfeee851c6c2fcefd0515
Author: owenca <owenpiano at gmail.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Handle `&&` in requires clause in requires requires (#169207)
Fixes #152266
Commit: 93b20e7d1f1d72c19c450a81ef5d84376e474b77
https://github.com/llvm/llvm-project/commit/93b20e7d1f1d72c19c450a81ef5d84376e474b77
Author: Guy David <guyda96 at gmail.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll
M llvm/test/CodeGen/AArch64/itofp.ll
Log Message:
-----------
[AArch64] Extend int-to-fp load optimization to support f16 (#168076)
Commit: 06fc87bcd3d61a08f8c035e60949631f61bccee7
https://github.com/llvm/llvm-project/commit/06fc87bcd3d61a08f8c035e60949631f61bccee7
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/executable-parsers.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/type-parsers.h
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Parser/OpenMP/fail-construct2.f90
M flang/test/Parser/OpenMP/tile-fail.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/loop-association.f90
M flang/test/Semantics/OpenMP/loop-transformation-construct02.f90
M flang/test/Semantics/OpenMP/loop-transformation-construct03.f90
Log Message:
-----------
[flang][OpenMP] Better diagnostics for invalid or misplaced directives (#168885)
Add two more AST nodes, one for a misplaced end-directive, and one for
an invalid string following the OpenMP sentinel (e.g. "!$OMP XYZ").
Emit error messages when either node is encountered in semantic
analysis.
Commit: 7485f34802f0ea1e00ac69499050e79692609b85
https://github.com/llvm/llvm-project/commit/7485f34802f0ea1e00ac69499050e79692609b85
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
A llvm/test/CodeGen/X86/pr169205.ll
Log Message:
-----------
[X86] X86ISelDAGToDAG - don't let ADD/SUB(X,1) -> SUB/ADD(X,-1) constant fold (#169217)
Extension to #168726 - ensure we peek through bitcasts to look for
constants (as constant folding will)
DAG should have constant folded this, but we're still fighting the lack
of proper topological sorting.
Fixes #169205
Commit: 21378fb75a6e4df1525067d408ebbf241aa63c75
https://github.com/llvm/llvm-project/commit/21378fb75a6e4df1525067d408ebbf241aa63c75
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
Log Message:
-----------
[VPlan] Merge `fcmp uno` feeding AnyOf. (#166823)
Fold
any-of (fcmp uno %A, %A), (fcmp uno %B, %B), ... ->
any-of (fcmp uno %A, %B), ...
This pattern is generated to check if any vector lane is NaN, and
combining multiple compares is beneficial on architectures that have
dedicated instructions.
Alive2 Proof: https://alive2.llvm.org/ce/z/vA_aoM
Combine suggested as part of
https://github.com/llvm/llvm-project/pull/161735
PR: https://github.com/llvm/llvm-project/pull/166823
Commit: 0332af25b9e33dad9b4d4ba4bef1400bbfe9383d
https://github.com/llvm/llvm-project/commit/0332af25b9e33dad9b4d4ba4bef1400bbfe9383d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
Log Message:
-----------
[X86] BuiltinsX86.td - merge avx512 cmp/ucmp builtins into common Features/Attributes blocks. NFC. (#169223)
Commit: a54edafa02bb4c11c1e4425c7da1e34864c9fde2
https://github.com/llvm/llvm-project/commit/a54edafa02bb4c11c1e4425c7da1e34864c9fde2
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
M llvm/include/llvm/ADT/MapVector.h
M llvm/unittests/ADT/DenseMapTest.cpp
M llvm/unittests/ADT/MapVectorTest.cpp
Log Message:
-----------
ADT: Complete the at() methods for DenseMap and MapVector (#169147)
Make it easier to use these containers as drop-in replacements for
std::map.
Commit: 8b7401f13d89fe7e1815a7ab95209afe49493d72
https://github.com/llvm/llvm-project/commit/8b7401f13d89fe7e1815a7ab95209afe49493d72
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
Log Message:
-----------
Fix MSVC "not all control paths return a value" warning. NFC. (#169222)
Commit: 3773bbe9e7916ec89fb3e3cd02e29c54cabac82b
https://github.com/llvm/llvm-project/commit/3773bbe9e7916ec89fb3e3cd02e29c54cabac82b
Author: Naveen Seth Hanig <naveen.hanig at outlook.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/Compiler.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/CommonArgs.h
A clang/include/clang/Driver/CreateASTUnitFromArgs.h
A clang/include/clang/Driver/CreateInvocationFromArgs.h
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Frontend/ChainedDiagnosticConsumer.h
M clang/include/clang/Frontend/CompilerInvocation.h
A clang/include/clang/Frontend/StandaloneDiagnostic.h
M clang/include/clang/Frontend/Utils.h
M clang/include/clang/Options/OptionUtils.h
M clang/lib/CrossTU/CMakeLists.txt
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Driver/CMakeLists.txt
A clang/lib/Driver/CreateASTUnitFromArgs.cpp
A clang/lib/Driver/CreateInvocationFromArgs.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CMakeLists.txt
M clang/lib/Frontend/CompilerInvocation.cpp
R clang/lib/Frontend/CreateInvocationFromCommandLine.cpp
A clang/lib/Frontend/StandaloneDiagnostic.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Options/OptionUtils.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/tools/c-index-test/CMakeLists.txt
M clang/tools/c-index-test/core_main.cpp
M clang/tools/diagtool/CMakeLists.txt
M clang/tools/diagtool/ShowEnabledWarnings.cpp
M clang/tools/driver/cc1_main.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexer.cpp
M clang/tools/libclang/CMakeLists.txt
M clang/tools/libclang/Indexing.cpp
M clang/unittests/Driver/DXCModeTest.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M clang/unittests/Frontend/UtilsTest.cpp
M clang/unittests/Sema/CMakeLists.txt
M clang/unittests/Sema/SemaNoloadLookupTest.cpp
M clang/unittests/Serialization/ForceCheckFileInputTest.cpp
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Serialization/NoCommentsTest.cpp
M clang/unittests/Serialization/PreambleInNamedModulesTest.cpp
M clang/unittests/Serialization/VarDeclConstantInitTest.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
M clang/unittests/Tooling/Syntax/TreeTestBase.cpp
M flang/lib/Frontend/CMakeLists.txt
M flang/lib/Frontend/CompilerInvocation.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangHost.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/unittests/Expression/ClangParserTest.cpp
Log Message:
-----------
[clang] Refactor to remove clangDriver dependency from clangFrontend and flangFrontend (#165277)
This removes the dependency on clangDriver from clangFrontend and
flangFrontend.
This refactoring is part of a broader effort to support driver-managed
builds for compilations using C++ named modules and/or Clang modules.
It is required for linking the dependency scanning tooling against the
driver without introducing cyclic dependencies, which would otherwise
cause build failures when dynamic linking is enabled.
In particular, clangFrontend must no longer depend on clangDriver
for this to be possible.
This change was discussed in the following RFC:
https://discourse.llvm.org/t/rfc-new-clangoptions-library-remove-dependency-on-clangdriver-from-clangfrontend-and-flangfrontend/88773
Commit: 8e2f5442f8a5caaa968b6215bd416ece8ed694c7
https://github.com/llvm/llvm-project/commit/8e2f5442f8a5caaa968b6215bd416ece8ed694c7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
Log Message:
-----------
[TableGen] Use std::array::fill instead of std::memset. NFC (#169204)
Commit: e6f60a61cdaae8fcf79d4f001096f2c826628074
https://github.com/llvm/llvm-project/commit/e6f60a61cdaae8fcf79d4f001096f2c826628074
Author: Hendrik Hübner <117831077+HendrikHuebner at users.noreply.github.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/test/CIR/CodeGen/builtin_new_delete.cpp
Log Message:
-----------
[CIR] Add builtin operator new/delete (#168578)
This PR adds `__builtin_operator_new` and `__builtin_operator_delete`.
The implementation is taken from clang code gen.
Commit: e5edb512072bc040face27ed6c9e92f4a5f1e910
https://github.com/llvm/llvm-project/commit/e5edb512072bc040face27ed6c9e92f4a5f1e910
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[bazel] Port 3773bbe9e7916ec89fb3e3cd02e29c54cabac82b
Commit: 362de2213e54d16449487cf87b4ee33a99e41e3d
https://github.com/llvm/llvm-project/commit/362de2213e54d16449487cf87b4ee33a99e41e3d
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M lldb/cmake/modules/LLDBConfig.cmake
Log Message:
-----------
[lldb] Fix SWIG bug detection in CMake (#169212)
The CMake
[`set()`](https://cmake.org/cmake/help/latest/command/set.html) command
does not accept a conditional expression as a value. As a result,
AFFECTED_BY_SWIG_BUG was being set to a string representation of the
condition rather than a boolean value, causing it to always evaluate as
truthy in subsequent if-checks.
Commit: d40c8dccff70c0ffd4a6120334e4fcd472d2fd91
https://github.com/llvm/llvm-project/commit/d40c8dccff70c0ffd4a6120334e4fcd472d2fd91
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang/test/OpenMP/parallel_default_variableCategory_codegen.cpp
Log Message:
-----------
[Clang][OpenMP] Make test use clang_cc1 (#169233)
This test does not actually need to use the clang driver. Using the
driver means that the environment plays much more into the tests
results. We ran into a situation where the driver decided not to pass
-fopenmp to the cc1 invocation, causing the test to fail.
This also makes the test more consistent with the other OpenMP tests and
should make it slightly faster (no subprocess invocation).
Commit: c543615744d61e0967b956c402e310946d741570
https://github.com/llvm/llvm-project/commit/c543615744d61e0967b956c402e310946d741570
Author: Owen Anderson <resistor at mac.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Add myself to the former maintainers list. (#169201)
I was the SelectionDAG maintainer (then called code owner) from
aebfacb008246b912e2fc5a454939a3de942303b (requested to take it up by
Evan Cheng) and yielded the role to Justin Bogner as of
d8ed65dda0b10b5d9fa6ebd2da46e733fbde5512.
Commit: bbd99aa1f699071894ca7e5c86fb61ece0a96db5
https://github.com/llvm/llvm-project/commit/bbd99aa1f699071894ca7e5c86fb61ece0a96db5
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M lldb/unittests/Expression/DWARFExpressionTest.cpp
Log Message:
-----------
Fix #168467 (r598213) (#169232)
Co-authored-by: Aiden Grossman <agrossman154 at yahoo.com>
Commit: 996213c6ea0dc2e47624c6b06c0833a882c1c1f7
https://github.com/llvm/llvm-project/commit/996213c6ea0dc2e47624c6b06c0833a882c1c1f7
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanSLP.cpp
Log Message:
-----------
[VPlan] Refine mayRead/WriteFromMemory for VPInst, fix VPlan SLP check.
Fix VPlan SLP check incorrectly bailing out for non-VPInstructions.
Starting from the beginning of the block will include canonical IVs,
which in turn are not VPInstructions. If we hit a non-VPInstruction, we
should conservatively treat is as potentially unvectorizable.
To keep the tests working as expected, refine mayRead/WriteFromMemory
for Load and GEP VPInstructions.
Commit: f7ed15b9e734e63ab062a1f9a1b50588776a653d
https://github.com/llvm/llvm-project/commit/f7ed15b9e734e63ab062a1f9a1b50588776a653d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[bazel] Fully port 3773bbe9e7916ec89fb3e3cd02e29c54cabac82b (#169247)
e5edb512072bc040face27ed6c9e92f4a5f1e910 attempted to port this, but
seemed to miss a couple things that still showed up on CI. This patch
fixes up the missing pieces.
Commit: 4996645594cf9e2e318c0e693d9ec30d0aac5762
https://github.com/llvm/llvm-project/commit/4996645594cf9e2e318c0e693d9ec30d0aac5762
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang-tools-extra/clang-tidy/objc/AssertEqualsCheck.cpp
M clang/docs/LibASTMatchersReference.html
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
Log Message:
-----------
Revert "[ASTMatchers] Make isExpandedFromMacro accept llvm::StringRef… (#167060)" (#169238)
This reverts commit a52e1af7f766e26a78d10d31da98af041dd66410.
That commit reverted a change (making isExpandedFromMacro take a
std::string) that was explicitly added to avoid lifetime issues. We ran
into issues with some internal matchers due to this, and it probably is
not an uncommon downstream use case. This patch restroes the original
functionality and adds a test to ensure that the functionality is
preserved.
https://reviews.llvm.org/D90303 contains more discussion.
Commit: ded1311a28021c86814df34a00c8432bad02cc30
https://github.com/llvm/llvm-project/commit/ded1311a28021c86814df34a00c8432bad02cc30
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
Log Message:
-----------
[ORC] Fix typo in comment.
Commit: b73a281f026ca31330ee99dfb6e16a62363fe442
https://github.com/llvm/llvm-project/commit/b73a281f026ca31330ee99dfb6e16a62363fe442
Author: Nico Weber <thakis at chromium.org>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/LoongArch/BUILD.gn
Log Message:
-----------
[gn] port b5812c0cf789aa4cb (LoongArch SDNodeInfo)
Commit: 3c3e2a295254603c5fef271135cbe733139e78eb
https://github.com/llvm/llvm-project/commit/3c3e2a295254603c5fef271135cbe733139e78eb
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M orc-rt/include/orc-rt/WrapperFunction.h
M orc-rt/unittests/DirectCaller.h
Log Message:
-----------
[orc-rt] Remove unused Session argument from WrapperFunction::call. (#169255)
Commit: 28eee722aab153aaa8a257c935170aff3346d110
https://github.com/llvm/llvm-project/commit/28eee722aab153aaa8a257c935170aff3346d110
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
A llvm/test/Transforms/GlobalOpt/X86/apx.ll
Log Message:
-----------
[GlobalOpt] Add TTI interface useFastCCForInternalCall for FASTCC (#164768)
Background: X86 APX feature adds 16 registers within the same 64-bit
mode. PR #164638 is trying to extend such registers for FASTCC. However,
a blocker issue is calling convention cannot be changeable with or
without a feature.
The solution is to disable FASTCC if APX is not ready. This is an NFC
change to the final code generation, becasue X86 doesn't define an
alternative ABI for FASTCC in 64-bit mode. We can solve the potential
compatibility issue of #164638 with this patch.
Commit: a6cec3f3e5234d2646bc1a53715cda8324445ed2
https://github.com/llvm/llvm-project/commit/a6cec3f3e5234d2646bc1a53715cda8324445ed2
Author: hstk30-hw <hanwei62 at huawei.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
M llvm/test/CodeGen/AArch64/machine-sink-kill-flags.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/CodeGen/Hexagon/swp-stages5.ll
M llvm/test/CodeGen/NVPTX/atomics-b128.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll
M llvm/test/CodeGen/PowerPC/licm-xxsplti.ll
M llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
M llvm/test/CodeGen/PowerPC/sink-side-effect.ll
M llvm/test/CodeGen/PowerPC/sms-phi-1.ll
M llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/remat.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-reduct.ll
M llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
M llvm/test/CodeGen/WebAssembly/simd-shift-in-loop.ll
M llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
M llvm/test/CodeGen/X86/i128-mul.ll
M llvm/test/CodeGen/X86/loop-strength-reduce5.ll
M llvm/test/CodeGen/X86/madd.ll
M llvm/test/CodeGen/X86/pr49451.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
M llvm/test/CodeGen/X86/xor.ll
Log Message:
-----------
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" (#169219)
Reland d5f3ab8ec97786476a077b0c8e35c7c337dfddf2, fix testcases.
Commit: 25c2cc4b98092e8dccc8ff46162bea65e9a63bbc
https://github.com/llvm/llvm-project/commit/25c2cc4b98092e8dccc8ff46162bea65e9a63bbc
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/test/Transforms/GlobalOpt/X86/apx.ll
Log Message:
-----------
[GlobalOpt] Use `target triple` to fix Buildbot failures, NFCI (#169260)
This supposes to fix LLVM Buildbot failures after #164768. I don't have
the environment to verify though.
Commit: fe56f5c3d315bf3282a54a3b323cc462ce755136
https://github.com/llvm/llvm-project/commit/fe56f5c3d315bf3282a54a3b323cc462ce755136
Author: Matthias Springer <me at m-sp.org>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/include/mlir/Pass/Pass.h
M mlir/lib/Pass/Pass.cpp
M mlir/test/Dialect/Transform/test-pass-application.mlir
A mlir/test/Pass/invalid-unsupported-operation.mlir
M mlir/test/Pass/pipeline-invalid.mlir
Log Message:
-----------
[mlir][Pass] Fix crash when applying a pass to an optional interface (#169262)
Interfaces can be optional: whether an op implements an interface or not
can depend on the state of the operation.
```
// An optional code block for adding additional "classof" logic. This can
// be used to better enable "optional" interfaces, where an entity only
// implements the interface if some dynamic characteristic holds.
// `$_attr`/`$_op`/`$_type` may be used to refer to an instance of the
// interface instance being checked.
code extraClassOf = "";
```
The current `Pass::canScheduleOn(RegisteredOperationName)` is
insufficient. This commit adds an additional overload to inspect
`Operation *`.
This commit fixes a crash when scheduling an `InterfacePass` for an
optional interface on an operation that does not actually implement the
interface.
This is a re-upload of #168499, which was reverted.
Commit: c4254cd9bb52fb8ef101dcfbcec048447e6c99bb
https://github.com/llvm/llvm-project/commit/c4254cd9bb52fb8ef101dcfbcec048447e6c99bb
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/Basic/Targets/SPIR.h
A clang/test/CodeGenOpenCL/__bf16.cl
M clang/test/SemaSYCL/bf16.cpp
Log Message:
-----------
[Clang] Support __bf16 type for SPIR/SPIR-V (#169012)
SPIR/SPIR-V are generic targets. Assume they support __bf16.
Commit: e71f243a8d0ed1a5089a4f56dcb90be972dfa061
https://github.com/llvm/llvm-project/commit/e71f243a8d0ed1a5089a4f56dcb90be972dfa061
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
Log Message:
-----------
[TableGen] Simplify MachineValueTypeSet::iterator::find_from_pos. NFC (#169227)
Merge the SkipBits!=0 handling into the first iteration of the word
loop. This is the same code structure used by BitVector::find_first_in.
Commit: c33e50bdc73522ed07a6d636dad66bbd1677daec
https://github.com/llvm/llvm-project/commit/c33e50bdc73522ed07a6d636dad66bbd1677daec
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/test/Transforms/GlobalOpt/X86/apx.ll
Log Message:
-----------
[GlobalOpt] Use `x86-registered-target` to fix Buildbot failures, 2nd try (#169266)
Commit: acab67baa72c9def53ac8fcd57cbb3b386903405
https://github.com/llvm/llvm-project/commit/acab67baa72c9def53ac8fcd57cbb3b386903405
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M compiler-rt/cmake/builtin-config-ix.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
[M68k][compiler-rt] Allow compiler-rt builtins to be built for M68k (#169256)
I've tested this locally, and the builtins build proceeds without a
hitch for m68k-none-none. This is part of a larger effort to establish a
working m68k baremetal toolchain.
Commit: ee4f6478babbcc746ef610e4bc0cf3859714b1e2
https://github.com/llvm/llvm-project/commit/ee4f6478babbcc746ef610e4bc0cf3859714b1e2
Author: Leon Clark <Leon4116 at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll
Log Message:
-----------
[AMDGPU] Propagate AA info in vector load/store splitting. (#168871)
Fixes a bug in `AMDGPUISelLowering` where alias analysis info is not
propagated to split loads and stores.
This is required for #161375
---------
Co-authored-by: Leon Clark <leoclark at amd.com>
Commit: 7851b8a65c5481bdf4a56f61a2c9603c2880dbc2
https://github.com/llvm/llvm-project/commit/7851b8a65c5481bdf4a56f61a2c9603c2880dbc2
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vector-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
Log Message:
-----------
[RISCV] Combine vslide{up,down} x, poison -> x (#169013)
The motivation for this is that it would be useful to express a
vslideup/vslidedown in a target independent way e.g. from the loop
vectorizer.
We can do this today with @llvm.vector.splice by setting one operand to
poison:
- A slide down can be achieved with @llvm.vector.splice(%x, poison,
slideamt)
- A slide up can be done by @llvm.vector.splice(poison, %x, -slideamt)
E.g.:
splice(<a,b,c,d>, poison, 3) = <d,poison,poison,poison>
splice(poison, <a,b,c,d>, -3) = <poison,poison,poison,a>
These splices get lowered to a vslideup + vslidedown pair with one of
the vs2s being poison. We can optimize this away so that we are just
left with a single slideup/slidedown.
Commit: 202d7840ff965400804972454e9de39e7d30e0b5
https://github.com/llvm/llvm-project/commit/202d7840ff965400804972454e9de39e7d30e0b5
Author: Twice <twice at apache.org>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Dialect/IRDL/IRDLLoading.cpp
M mlir/test/Dialect/IRDL/variadics.mlir
Log Message:
-----------
[MLIR][IRDL] Support camelCase segment size attributes in IRDL verifier (#168836)
Two years ago, `operand_segment_sizes` and `result_segment_sizes` were
renamed to `operandSegmentSizes` and `resultSegmentSizes` (check related
commits, e.g.
https://github.com/llvm/llvm-project/commit/363b655920c49a4bcb0869f820ed40aac834eebd).
However, the op verifiers in IRDL loading phase is still using old
attributes like `operand_segment_sizes` and `result_segment_sizes`,
which causes some conflict, e.g. it is not compatible with the OpView
builder in MLIR python bindings (which generates camelCase segment
attributes).
This PR is to support to use camelCase segment size attributes in IRDL
verifier. Note that support of `operand_segment_sizes` and
`result_segment_sizes` is dropped.
I found this issue since I'm working on a new IRDL wrapper in the MLIR
python bindings.
Commit: 13a39eaa0bcf6c439e8b59571f4afe593d658623
https://github.com/llvm/llvm-project/commit/13a39eaa0bcf6c439e8b59571f4afe593d658623
Author: hstk30-hw <hanwei62 at huawei.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[Sema] Fix Wunused-but-set-variable warning(NFC) (#169220)
Fix warning:
llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp:1455:23: warning:
variable 'Store' set but not used [-Wunused-but-set-variable]
Commit: b53e46f71af06e0338ddff8d6d3c87230d4b441d
https://github.com/llvm/llvm-project/commit/b53e46f71af06e0338ddff8d6d3c87230d4b441d
Author: Arun Thangamani <arun.thangamani at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/X86Vector/CMakeLists.txt
A mlir/include/mlir/Dialect/X86Vector/TransformOps/CMakeLists.txt
A mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.h
A mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
M mlir/include/mlir/Dialect/X86Vector/Transforms.h
M mlir/lib/Dialect/X86Vector/CMakeLists.txt
A mlir/lib/Dialect/X86Vector/TransformOps/CMakeLists.txt
A mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
M mlir/lib/Dialect/X86Vector/Transforms/CMakeLists.txt
A mlir/lib/Dialect/X86Vector/Transforms/VectorContractToFMA.cpp
A mlir/lib/Dialect/X86Vector/Transforms/VectorContractToPackedTypeDotProduct.cpp
M mlir/lib/RegisterAllExtensions.cpp
A mlir/test/Dialect/X86Vector/vector-contract-to-fma.mlir
A mlir/test/Dialect/X86Vector/vector-contract-to-packed-type-dotproduct.mlir
Log Message:
-----------
[mlir][x86vector] Lower vector.contract to FMA or packed type dot-product (#168074)
A `transform` pass to lower `vector.contract` to (a) `vector.fma` for
`F32`, (b) `x86vector.avx512.dot` for `BF16`, (c) `x86vector.avx.dot.i8`
for `Int8` packed types.
The lowering works on condition with `m`, `batch`, `k` dims to be `one`
and `vnni` dim should be `2` for `bf16`; `4` for `int8`.
**The lowering pattern**: `batch_reduce.matmul` (input) ->
register-tiling(M, N) -> Vectorization (to `vector.contract`) ->
`unroll` vector.contract (`unit` dims) -> `hoisting` transformation
(move `C` loads/store outside batch/k loop) -> apply `licm`,
`canonicalization`, and `bufferize`.
Commit: 76e7e9fa109e424c18edc2b89e991dac99979599
https://github.com/llvm/llvm-project/commit/76e7e9fa109e424c18edc2b89e991dac99979599
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll
M llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll
Log Message:
-----------
[LoongArch][NFC] Add tests for combining vand(vnot) (#160830)
Commit: d124675e27a6abbce0bfea6a25ab9dfe66e9d657
https://github.com/llvm/llvm-project/commit/d124675e27a6abbce0bfea6a25ab9dfe66e9d657
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Dialect/X86Vector/Transforms/CMakeLists.txt
Log Message:
-----------
[mlir][x86vector] Add missing Linalg dependency (#169280)
Adds required dependency for `inferContractionDims`.
Fixes #168074
Commit: 54db657b9ebdbce70f902313e6b303d85d68a4dc
https://github.com/llvm/llvm-project/commit/54db657b9ebdbce70f902313e6b303d85d68a4dc
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/SarifDiagnostics.cpp
Log Message:
-----------
[StaticAnalyzer] Use llvm::find_if (NFC) (#169237)
Identified with llvm-use-ranges.
Commit: 67391fc039b27f4e82624a6de4493cdd0907878b
https://github.com/llvm/llvm-project/commit/67391fc039b27f4e82624a6de4493cdd0907878b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
Log Message:
-----------
[mlir] Construct SmallVector with initial values (NFC) (#169239)
Identified with llvm-use-ranges.
Commit: 2b81e9e8fea0cdb2eac1537c1f882b695615b141
https://github.com/llvm/llvm-project/commit/2b81e9e8fea0cdb2eac1537c1f882b695615b141
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Core.cpp
Log Message:
-----------
[Orc] Use a range-based for loop (NFC) (#169240)
Identified with modernize-loop-convert.
Commit: 7dd531f428614a310b6715fe9181432393d9095b
https://github.com/llvm/llvm-project/commit/7dd531f428614a310b6715fe9181432393d9095b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
Log Message:
-----------
[SPIRV] Use range-based for loops (NFC) (#169241)
Identified with modernize-loop-convert.
Commit: 9ce6fadbcaf60ed88302617b6301f68989d44e3e
https://github.com/llvm/llvm-project/commit/9ce6fadbcaf60ed88302617b6301f68989d44e3e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang/include/clang/AST/OpenMPClause.h
Log Message:
-----------
[AST] Construct iterator_range with the conversion constructor (NFC) (#169245)
This patch simplifies iterator_range construction with the conversion
constructor.
Commit: 95f0fab7fab48bbf37d3c02c0ea8b01ca73c30dd
https://github.com/llvm/llvm-project/commit/95f0fab7fab48bbf37d3c02c0ea8b01ca73c30dd
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/test/AST/ByteCode/cxx23.cpp
Log Message:
-----------
[clang][bytecode] Fix conditional operator scoping wrt. local variables (#169030)
We used to create a scope for the true- and false expression of a
conditional operator. This was done so e.g. in this example:
```c++
struct A { constexpr A(){}; ~A(); constexpr int get() { return 10; } }; // all-note 2{{declared here}}
static_assert( (false ? A().get() : 1) == 1);
```
we did _not_ evaluate the true branch at all, meaning we did not
register the local variable for the temporary of type `A`, which means
we also didn't call it destructor.
However, this breaks the case where the temporary needs to outlive the
conditional operator and instead be destroyed via the surrounding
`ExprWithCleanups`:
```
constexpr bool test2(bool b) {
unsigned long __ms = b ? (const unsigned long &)0 : __ms;
return true;
}
static_assert(test2(true));
```
Before this patch, we diagnosed this example:
```console
./array.cpp:180:15: error: static assertion expression is not an integral constant expression
180 | static_assert(test2(true));
| ^~~~~~~~~~~
./array.cpp:177:24: note: read of temporary whose lifetime has ended
177 | unsigned long __ms = b ? (const unsigned long &)0 : __ms;
| ^
./array.cpp:180:15: note: in call to 'test2(true)'
180 | static_assert(test2(true));
| ^~~~~~~~~~~
./array.cpp:177:51: note: temporary created here
177 | unsigned long __ms = b ? (const unsigned long &)0 : __ms;
| ^
1 error generated.
```
because the temporary created for the true branch got immediately
destroyed.
The problem in essence is that since the conditional operator doesn't
create a scope at all, we register the local variables for both its
branches, but we later only execute one of them, which means we should
also only destroy the locals of one of the branches.
We fix this similar to clang codgen's `is_active` flag: In the case of a
conditional operator (which is so far the only case where this is
problematic, and this also helps minimize the performance impact of this
change), we make local variables as disabled-by-default and then emit a
`EnableLocal` opcode later, which marks them as enabled. The code
calling their destructors checks whether the local was enabled at all.
Commit: f5cae7b805946337f30437871ea6e13844507775
https://github.com/llvm/llvm-project/commit/f5cae7b805946337f30437871ea6e13844507775
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/unittests/ExecutionEngine/Orc/WaitingOnGraphTest.cpp
Log Message:
-----------
[ORC] Add unit test for simple cycle in WaitingOnGraph::emit. (#169281)
WaitingOnGraphTests.Emit_SingleContainerSimpleCycle tests a pair of emit
operations where the second completes a simple cycle (1: A -> B, 2: B ->
A).
We already had a test of WaitingOnGraph::simplify's behavior in this
case, but did not have one for WaitingOnGraph::emit.
Commit: 02a997cf365d7cf9759ee732f27241f1242a84b3
https://github.com/llvm/llvm-project/commit/02a997cf365d7cf9759ee732f27241f1242a84b3
Author: owenca <owenpiano at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Handle `import` when used as template function name (#169279)
Fixes #149960
Commit: c15a6cc00b1a0e3a47d99172b839ec45c72168ae
https://github.com/llvm/llvm-project/commit/c15a6cc00b1a0e3a47d99172b839ec45c72168ae
Author: ganenkokb-yandex <160136233+ganenkokb-yandex at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/include/clang/AST/ASTImporter.h
M clang/lib/AST/ASTImporter.cpp
M clang/unittests/AST/ASTImporterTest.cpp
Log Message:
-----------
[Clang][ASTImporter] Fix cycle in importing template specialization on auto type with typename (#162514)
ASTImporter on importing template specialization with auto return type
faces cycle when return type is not nested one, but typename from
template arguments and other template.
There is code, that prevents cycle to auto return types when nested type
declared. Solved case differs somehow from nested types, but have same
solution with UsedDifferentProtoType - with delayed return type
determining.
Commit: e888cf863d5c0a83933f97cac04ae5dc5010e1a1
https://github.com/llvm/llvm-project/commit/e888cf863d5c0a83933f97cac04ae5dc5010e1a1
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
Log Message:
-----------
[AMDGPU] Add wave reduce intrinsics for float types - 2 (#168859)
Supported Ops: `fadd`, `fsub`
Commit: 1abb055c57c977f98267bdb89c856adfaa71e892
https://github.com/llvm/llvm-project/commit/1abb055c57c977f98267bdb89c856adfaa71e892
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[IVDesc] Make getCastInsts return an ArrayRef (NFC) (#169021)
To make it clear that the return value is immutable.
Commit: ce70d4b5b5130f2ac8586c3dd2198dc91771f534
https://github.com/llvm/llvm-project/commit/ce70d4b5b5130f2ac8586c3dd2198dc91771f534
Author: Gil Rapaport <gil.rapaport at mobileye.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
Log Message:
-----------
[mlir][emitc] Refactor getEmittedExpression (NFC) (#168361)
This method returns the current expression being emitted, but is only
used testing whether an expression is being emitted or not. This patch
therefore replaces it with a boolean isEmittingExpression() method.
Commit: f21857313dfab543e66ef43b1aed43b685794a7c
https://github.com/llvm/llvm-project/commit/f21857313dfab543e66ef43b1aed43b685794a7c
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/CAS/OnDiskGraphDB.cpp
Log Message:
-----------
[llvm][CAS] Remove unused functions (#168856)
Building with GCC I got:
```
<...>/OnDiskGraphDB.cpp:624:18: warning: ‘static {anonymous}::DataRecordHandle {anonymous}::DataRecordHandle::construct(char*, const {anonymous}::DataRecordHandle::Input&)’ defined but not used [-Wunused-function]
624 | DataRecordHandle DataRecordHandle::construct(char *Mem, const Input &I) {
| ^~~~~~~~~~~~~~~~
<...>/OnDiskGraphDB.cpp:456:1: warning: ‘static {anonymous}::DataRecordHandle {anonymous}::DataRecordHandle::create(llvm::function_ref<char*(long unsigned int)>, const {anonymous}::DataRecordHandle::Input&)’ defined but not used [-Wunused-function]
456 | DataRecordHandle::create(function_ref<char *(size_t Size)> Alloc,
| ^~~~~~~~~~~~~~~~
```
These implement parts of a class that is defined in an anonymous
namespace. All llvm tests passed with them removed.
Commit: c745a512dcfaa550c58b42bedd06464b7f593a26
https://github.com/llvm/llvm-project/commit/c745a512dcfaa550c58b42bedd06464b7f593a26
Author: Ingo Müller <ingomueller at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir:x86vector:transform] Fix bazel build after #168074. (#169294)
This PR fixes the bazel build that went out of sync with the changes
introduced in #168074.
Signed-off-by: Ingo Müller <ingomueller at google.com>
Commit: 6413e5a2df8ca75c4b54b2577bbec9a9d31911b0
https://github.com/llvm/llvm-project/commit/6413e5a2df8ca75c4b54b2577bbec9a9d31911b0
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/SemanticSelection.cpp
M clang-tools-extra/clangd/unittests/SemanticSelectionTests.cpp
Log Message:
-----------
[clangd] Implement fold range for #pragma region (#168177)
The implementation is based on the directive tree.
Fixes https://github.com/clangd/clangd/issues/1623
Commit: 30b1d1422733c012c274f173a3f4986615f7c1c7
https://github.com/llvm/llvm-project/commit/30b1d1422733c012c274f173a3f4986615f7c1c7
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/test/Analysis/stackaddrleak.c
Log Message:
-----------
[analyzer] Fix inf recursion in StackAddrEscapeChecker for self referencing blocks (#169208)
Objective-C blocks are like lambdas. They have captures, just like lambdas.
However, they can also implicitly capture themselves unlike lambdas.
This means that when walking the captures of a block, we may end up in
infinite recursion. This is not possible with lambdas, but happened in
practice with blocks downstream.
In this patch, I just use a set to keep track of the visited MemRegions.
Note that theoretically, there is nothing preventing usual lambdas or
functors from falling for the same trap, but probably slightly more
difficult to do so. You would likely need a pointer to itself, etc. I'll
not speculate here.
This inf recursion was likely caused by #126620, released in clang-21.
rdar://162215172
Commit: 4604762cc336317b0f02f7d8c1576f6205f4ea61
https://github.com/llvm/llvm-project/commit/4604762cc336317b0f02f7d8c1576f6205f4ea61
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
Log Message:
-----------
[AMDGPU] Add builtins for wave reduction intrinsics (#161816)
Commit: 4b65cafa182a9b91131bfce986e815c9a4ab6ae5
https://github.com/llvm/llvm-project/commit/4b65cafa182a9b91131bfce986e815c9a4ab6ae5
Author: Benjamin Maxwell <macdue at dueutil.tech>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/sve-bf16-arith.ll
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
Log Message:
-----------
[AArch64][SVE] Add custom lowering for bfloat FMUL (with +bf16) (#167502)
This lowers an SVE FMUL of bf16 using the BFMLAL top/bottom instructions
rather than extending to an f32 mul. This does require zeroing the
accumulator, but requires fewer extends/unpacking.
Commit: 121e2e9e377c1db6b5cb536e7fd0b78244c0ce04
https://github.com/llvm/llvm-project/commit/121e2e9e377c1db6b5cb536e7fd0b78244c0ce04
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/string
Log Message:
-----------
[libc++] Introduce basic_string::__allocate_long_buffer_for_growing (#162633)
Introducing this utility makes the `__grow_by{,_and_replace}`
significantly easier to understand and allows us to migrate away from
these functions in the future.
Commit: f3ce5dec690e11645e0b838132d3306b56c0ec97
https://github.com/llvm/llvm-project/commit/f3ce5dec690e11645e0b838132d3306b56c0ec97
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/__algorithm/all_of.h
M libcxx/include/__algorithm/none_of.h
A libcxx/test/std/algorithms/robust_against_nonbool.compile.pass.cpp
Log Message:
-----------
[libc++] Forward std::all_of and std::none_of to std::any_of (#167670)
This allows propagating optimizations to different algorithms by just
optimizing the lowest one. This is especially relevant now that we start
optimizing how we're iterating through ranges (e.g. the segmented
iterator optimizations) and adding assumptions so the compier can better
leverage semantics guaranteed by the standard (e.g.
`__builtin_assume_dereferenceable`).
Commit: 4b35ff583fbc61074bdf7b1ebf908d31e578f5ac
https://github.com/llvm/llvm-project/commit/4b35ff583fbc61074bdf7b1ebf908d31e578f5ac
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/remat.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
Log Message:
-----------
[RISCV] Enable rematerialization for scalar loads (#166774)
In some workloads we see an argument passed on the stack where it is
loaded, only for it to be immediately spilled to a different slot on the
stack and then reloaded from that spill slot later on.
We can avoid the unnecessary spill by marking loads as rematerializable
and just directly loading from where the argument was originally passed
on the stack. TargetTransformInfo::isReMaterializableImpl checks to make
sure that any loads are `MI.isDereferenceableInvariantLoad()`, so we
should be able to move the load down to the remat site.
This gives a 14.8% reduction in spills in 544.nab_r on rva23u64 -O3, and
a few other smaller reductions on llvm-test-suite. I didn't find any
benchmarks where the number of spills/reloads increased.
Related: #165761
Commit: 9be30e50c2bf878bd15ac8ed1270f1714c32b30f
https://github.com/llvm/llvm-project/commit/9be30e50c2bf878bd15ac8ed1270f1714c32b30f
Author: hev <wangrui at loongson.cn>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsLoongArchLASX.def
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Headers/lasxintrin.h
M clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
M clang/test/CodeGen/LoongArch/lasx/builtin.c
M clang/test/Preprocessor/init-loongarch.c
Log Message:
-----------
[clang][LoongArch] Introduce LASX and LSX conversion intrinsics (#157819)
This patch introduces the LASX and LSX conversion intrinsics:
- __m256 __lasx_cast_128_s (__m128)
- __m256d __lasx_cast_128_d (__m128d)
- __m256i __lasx_cast_128 (__m128i)
- __m256 __lasx_concat_128_s (__m128, __m128)
- __m256d __lasx_concat_128_d (__m128, __m128d)
- __m256i __lasx_concat_128 (__m128, __m128i)
- __m128 __lasx_extract_128_lo_s (__m256)
- __m128d __lasx_extract_128_lo_d (__m256d)
- __m128i __lasx_extract_128_lo (__m256i)
- __m128 __lasx_extract_128_hi_s (__m256)
- __m128d __lasx_extract_128_hi_d (__m256d)
- __m128i __lasx_extract_128_hi (__m256i)
- __m256 __lasx_insert_128_lo_s (__m256, __m128)
- __m256d __lasx_insert_128_lo_d (__m256d, __m128d)
- __m256i __lasx_insert_128_lo (__m256i, __m128i)
- __m256 __lasx_insert_128_hi_s (__m256, __m128)
- __m256d __lasx_insert_128_hi_d (__m256d, __m128d)
- __m256i __lasx_insert_128_hi (__m256i, __m128i)
Relevant GCC patch:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c2013267642fea4a6e89b826940c8aa80a76089d
Commit: 8c6ec1212720ebbbd7dc10e1fea2602a5d58eef5
https://github.com/llvm/llvm-project/commit/8c6ec1212720ebbbd7dc10e1fea2602a5d58eef5
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/array
M libcxx/test/libcxx/diagnostics/array.nodiscard.verify.cpp
M libcxx/test/std/containers/sequences/array/array.creation/to_array.verify.cpp
Log Message:
-----------
[libc++][array] Applied `[[nodiscard]]` (#168829)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: 4c4cf71095c4e2e2063793d889db3ca984dd375e
https://github.com/llvm/llvm-project/commit/4c4cf71095c4e2e2063793d889db3ca984dd375e
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/list
M libcxx/test/libcxx/diagnostics/list.nodiscard.verify.cpp
Log Message:
-----------
[libc++][list] Applied `[[nodiscard]]` (#169015)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 74a62b12b0461cf051dbb4c3842fdccad305411b
https://github.com/llvm/llvm-project/commit/74a62b12b0461cf051dbb4c3842fdccad305411b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/test/CodeGen/X86/avx2-builtins.c
Log Message:
-----------
[X86] avx2-builtins.c - add constexpr test coverage for _mm256_bslli_epi128/_mm256_bsrli_epi128 intrinsics (#169309)
Commit: d44d329c0b2f13bd1c259c822f5c4fc47d1240d5
https://github.com/llvm/llvm-project/commit/d44d329c0b2f13bd1c259c822f5c4fc47d1240d5
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/test/AST/ByteCode/intap.cpp
Log Message:
-----------
[clang][bytecode] Fix compound assign operators for IntAP(S) (#169303)
We didn't take `IntAP`/`IntAPS` into account when casting to and from
the computation LHS type. This broke the
`std/ranges/range.factories/range.iota.view/end.pass.cpp` test.
Commit: c73de9777e67df4411020a7909f0eadbbf1de08b
https://github.com/llvm/llvm-project/commit/c73de9777e67df4411020a7909f0eadbbf1de08b
Author: Julian Nagele <j.nagele at apple.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/test/Transforms/LoopUnroll/partial-unroll-reductions.ll
M llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
Log Message:
-----------
[IVDesciptors] Support detecting reductions with vector instructions. (#166353)
In combination with https://github.com/llvm/llvm-project/pull/149470
this will introduce parallel accumulators when unrolling reductions with
vector instructions. See also
https://github.com/llvm/llvm-project/pull/166630, which aims to
introduce parallel accumulators for FP reductions.
Commit: 840a43bbe3a7361f99e9444dfcfd9eefe60ba487
https://github.com/llvm/llvm-project/commit/840a43bbe3a7361f99e9444dfcfd9eefe60ba487
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/utils/ci/buildkite-pipeline.yml
Log Message:
-----------
[libcxx][ci] Temporarily disable ARM jobs (#169318)
Linaro is doing network maintenance and I don't have an estimated time
these will be back online.
Commit: fe9c8e4f10c74990a06f8837e4a45c56f725cb65
https://github.com/llvm/llvm-project/commit/fe9c8e4f10c74990a06f8837e4a45c56f725cb65
Author: Ingo Müller <ingomueller at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir:x86vector:transform] Fix bazel build (again) after #168074. (#169316)
This is a second attempt to fix the bazel build (after the first in
#169294, which was accidentally merged before CI passed). In the first
attempt, not all bazel dependencies had been added; this PR should add
them all and make CI pass.
Signed-off-by: Ingo Müller <ingomueller at google.com>
Commit: 5d2fc9408e99201a32f090ba263de05a362dfa2b
https://github.com/llvm/llvm-project/commit/5d2fc9408e99201a32f090ba263de05a362dfa2b
Author: Meredith Julian <35236176+mjulian31 at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/test/Transforms/InstCombine/scalarization.ll
Log Message:
-----------
[InstCombine] Fix phi scalarization with binop (#169120)
InstCombine phi scalarization would always create a new binary op with
the phi as the first operand, which is not correct for non-commutable
binary ops such as sub. This fix preserves the original binary op
ordering in the new binary op and adds a test for this behavior.
Currently, this transformation can produce silently incorrect IR, and in
the case of the added test, would optimize it out entirely.
Commit: d162c91c01a66e4af0af190044961e60db0eeb3d
https://github.com/llvm/llvm-project/commit/d162c91c01a66e4af0af190044961e60db0eeb3d
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
Log Message:
-----------
[ORC] Avoid self-dependence in SuperNode dependence graph. (#169286)
Avoid adding any given SuperNode SN to its own SuperNode-deps set. This
saves us from trying to redundantly merge its dependencies back into
itself (a no-op, but a potentially expensive one).
Commit: 1dc6ad008164353e05bfe857f905028827834dbb
https://github.com/llvm/llvm-project/commit/1dc6ad008164353e05bfe857f905028827834dbb
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M lldb/include/lldb/Target/UnixSignals.h
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Target/UnixSignals.cpp
M lldb/unittests/Signals/UnixSignalsTest.cpp
Log Message:
-----------
[lldb] Show signal number description (#164176)
show information about the signal when the user presses `process handle
<unix-signal>` i.e
```sh
(lldb) process handle SIGWINCH
NAME PASS STOP NOTIFY DESCRIPTION
=========== ===== ===== ====== ===================
SIGWINCH true false false window size changes
```
Wanted to use the existing `GetSignalDescription` but it is expected
behaviour to return the signal name if no signal code is passed. It is
used in stop info.
https://github.com/llvm/llvm-project/blob/65c895dfe084860847e9e220ff9f1b283ebcb289/lldb/source/Target/StopInfo.cpp#L1192-L1195
Commit: d41628941743b778432e30d93f25028ffb375fbc
https://github.com/llvm/llvm-project/commit/d41628941743b778432e30d93f25028ffb375fbc
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
Log Message:
-----------
[TableGen] Eliminate the dependency on SDNode definition order (#168745)
Fix the dependency of `CodeGenDAGPatterns::ParseDefaultOperands()` on
the particular order of SDNode definitions. Implicit usage of the first
definition as a placeholder makes `llvm-tblgen -gen-dag-isel` fail if
that SDNode is not usable as an output pattern operator and an instance
of `OperandWithDefaultOps` is used in a pattern.
Presently, each `OperandWithDefaultOps` record is processed by
constructing an instance of TreePattern from its `DefaultOps` argument
that has the form `(ops ...)`. Even though the result of processing the
root operator of that DAG is not inspected by `ParseDefaultOperands()`
function itself, that operator has to be supported by the underlying
`TreePattern::ParseTreePattern()` function. For that reason, a temporary
DAG is created by replacing the root operator of `DefaultOps` argument
with the first SDNode defined, which is usually `def imm : ...` defined
in `TargetSelectionDAG.td` file.
This results in misleading errors being reported when implementing new
`SDNode` types, if the new definition happens to be added before the
`def imm : ...` line. The error is reported by several test cases
executed by `check-llvm` target, as well as by the regular build, if one
of the enabled targets inherit one of its operand types from
`OperandWithDefaultOps`:
OptionalIntOperand: ../llvm/test/TableGen/DAGDefaultOps.td:28:5: error: In OptionalIntOperand: Cannot use 'unexpected_node' in an output pattern!
def OptionalIntOperand: OperandWithDefaultOps<i32, (ops (i32 0))>;
This commit implements a dedicated constructor of `TreePattern` to be
used if the caller does not care about the particular root operator of
the pattern being processed.
Commit: d90bc3bc609d3ef2254e85cfcd435a99eb2b019b
https://github.com/llvm/llvm-project/commit/d90bc3bc609d3ef2254e85cfcd435a99eb2b019b
Author: Dmitry Chigarev <dmitry.chigarev at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
Log Message:
-----------
[mlir][XeGPU][VectorToXeGPU] Use 'xegpu.load' to lower 1D 'vector.transfer_read' for PVC & BMG (#168910)
The PR changes the `TransferReadLowering` to always use `xegpu.load`
(and not `xegpu.load_nd`) for 1D cases as it has more developed
interface (e.g. layouts capabilites).
Signed-off-by: dchigarev <dmitry.chigarev at intel.com>
Commit: 72bfa28c07c810112da0778f504b91e87ab63600
https://github.com/llvm/llvm-project/commit/72bfa28c07c810112da0778f504b91e87ab63600
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/test/CodeGen/X86/avx2-builtins.c
Log Message:
-----------
[X86] avx2-builtins.c - fix copy+paste typo in _mm256_cmpeq_epi8 constexpr test - still tested _mm_cmpeq_epi8 (#169311)
Commit: 74f5548bbc916a6c23731561f3808e64633760c7
https://github.com/llvm/llvm-project/commit/74f5548bbc916a6c23731561f3808e64633760c7
Author: Nathan Gauër <brioche at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/AST/HLSL/semantic-input-struct-shadow.hlsl
A clang/test/AST/HLSL/semantic-input-struct.hlsl
A clang/test/AST/HLSL/semantic-input.hlsl
A clang/test/AST/HLSL/semantic-output-struct-shadow.hlsl
A clang/test/AST/HLSL/semantic-output-struct.hlsl
A clang/test/AST/HLSL/semantic-output.hlsl
M clang/test/CodeGenHLSL/semantics/SV_Position.ps.hlsl
A clang/test/CodeGenHLSL/semantics/SV_Position.vs.hlsl
M clang/test/SemaHLSL/Semantics/position.ps.hlsl
R clang/test/SemaHLSL/Semantics/position.vs.hlsl
A llvm/test/CodeGen/SPIRV/semantics/position.ps.ll
A llvm/test/CodeGen/SPIRV/semantics/position.vs.ll
Log Message:
-----------
[HLSL][SPIR-V] Implements SV_Position for VS/PS I/O (#168735)
Current implementation for SV_Position was very basic to allow
implementing/testing some semantics. Now that semantic support is more
robust, I can move forward and implement the whole semantic logic.
DX part is still a bit placeholder.
Commit: e4cff3c687fe909a2ff291576872aa06a55277ce
https://github.com/llvm/llvm-project/commit/e4cff3c687fe909a2ff291576872aa06a55277ce
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/ScalableValueBoundsConstraintSet.cpp
Log Message:
-----------
[mlir] Avoid else after return in ScalableValueBounds (NFC) (#169211)
Commit: 65fd9f1f891bcc4bc1a27a00a45a4c1d9670ae63
https://github.com/llvm/llvm-project/commit/65fd9f1f891bcc4bc1a27a00a45a4c1d9670ae63
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/test/Transforms/Attributor/dereferenceable-1.ll
M llvm/test/Transforms/Attributor/nonnull.ll
M llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
M llvm/test/Transforms/Attributor/willreturn.ll
M llvm/test/Transforms/FunctionAttrs/nonnull.ll
Log Message:
-----------
[Attributor] Support nested conditional branches (#168532)
The attributor can infer the alignment of %p at the call-site in this
example [1]:
```
define void @f(ptr align 8 %p, i1 %c1, i1 %c2) {
entry:
br i1 %c1, label %bb.1, label %exit
bb.1:
call void (...) @llvm.fake.use(ptr %p)
br label %exit
exit:
ret void
}
```
but not when there's an additional conditional branch:
```
define void @f(ptr align 8 %p, i1 %c1, i1 %c2) {
entry:
br i1 %c1, label %bb.1, label %exit
bb.1:
br i1 %c2, label %bb.2, label %exit
bb.2:
call void (...) @llvm.fake.use(ptr %p)
br label %exit
exit:
ret void
}
```
unless `-attributor-annotate-decl-cs` is enabled. This patch extends
`followUsesInMBEC` to handle such recursive branches.
n.b. admittedly I wrote this patch before discovering inferring the
alignment in this example is already possible with
`-attributor-annotate-decl-cs`, I came to realise this once writing the
tests, but this seems like a gap regardless looking at existing FIXMEs,
plus the alignment can now be inferred in this particular example
without the flag.
[1] https://godbolt.org/z/aKoc75so5
Commit: 999deef63df5a057350a1e3bf211e536d5cfbc82
https://github.com/llvm/llvm-project/commit/999deef63df5a057350a1e3bf211e536d5cfbc82
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGExprComplex.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/test/CodeGen/promoted-complex-div.c
Log Message:
-----------
Desugar complex element types for promoted complex division (#168943)
This patch fixes a crash in Clang that occurs when the compiler
retrieves the element type of a complex type but receives a sugared
type. See example here: https://godbolt.org/z/cdbdeMcaT
This patch fixes the crash.
Commit: e5755395417ceaa9cd049e69593cb0dcc7d0e65c
https://github.com/llvm/llvm-project/commit/e5755395417ceaa9cd049e69593cb0dcc7d0e65c
Author: Jack Frankland <jack.frankland at arm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
Log Message:
-----------
[milr][memref]: Fold expand_shape + transfer_read (#167679)
Extend the load of a expand shape rewrite pattern to support folding a
`memref.expand_shape` and `vector.transfer_read` when the permutation
map on `vector.transfer_read` is a minor identity.
---------
Signed-off-by: Jack Frankland <jack.frankland at arm.com>
Commit: a27842ce0698299eed4fbe076560b8d785d50444
https://github.com/llvm/llvm-project/commit/a27842ce0698299eed4fbe076560b8d785d50444
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/test/CodeGen/X86/apx/no-rex2-general.ll
M llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll
M llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll
M llvm/test/CodeGen/X86/apx/no-rex2-special.ll
Log Message:
-----------
[X86][NFC] Add `-show-mc-encoding` to check register misuse (#169264)
Commit: d14840779bf9e4ba80e8955b0e846d112106f287
https://github.com/llvm/llvm-project/commit/d14840779bf9e4ba80e8955b0e846d112106f287
Author: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
A llvm/test/CodeGen/X86/avx512-i386-setallones-pseudo.mir
A llvm/test/CodeGen/X86/avx512-setallones-pseudo.mir
M llvm/test/CodeGen/X86/eq-or-eq-range-of-2.ll
Log Message:
-----------
[X86][AVX512] Add pseudos for `AVX512_*_SETALLONES` (#169009)
Introduce `AVX512_128_SETALLONES`, `AVX512_256_SETALLONES` pseudos to
generate all-ones vectors.
Post-RA expansion:
- Use VEX vpcmpeqd for XMM/YMM0–15 when available (matches current
codegen as `AVX512_128/256_SETALLONES` will be preferred over
`AVX1/2_SETALLONES` for AVX512VL target).
- Use EVEX `vpternlogd imm=0xFF` for high regs.
Includes MIR tests for both VEX and EVEX paths.
Commit: 83765f435d1ca1ffc29ebe0ad979bfb70a22ff70
https://github.com/llvm/llvm-project/commit/83765f435d1ca1ffc29ebe0ad979bfb70a22ff70
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu-templates.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu-templates.s.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-templates.test
M llvm/utils/update_mc_test_checks.py
Log Message:
-----------
[Utils][update_mc_test_checks] Support generating asm tests from templates. (#168946)
Reduces the pain of manual editing tests applying the same
changes over multiple instructions and keeping them consistent.
Commit: d5927a6172ab9b95f7f533bfdff865c1ce2aad5b
https://github.com/llvm/llvm-project/commit/d5927a6172ab9b95f7f533bfdff865c1ce2aad5b
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M lldb/docs/dil-expr-lang.ebnf
M lldb/include/lldb/Symbol/TypeSystem.h
M lldb/include/lldb/ValueObject/DILAST.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
M lldb/source/Symbol/CompilerType.cpp
M lldb/source/Symbol/TypeSystem.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILParser.cpp
A lldb/test/API/commands/frame/var-dil/expr/Arithmetic/Makefile
A lldb/test/API/commands/frame/var-dil/expr/Arithmetic/TestFrameVarDILArithmetic.py
A lldb/test/API/commands/frame/var-dil/expr/Arithmetic/main.cpp
A lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/Makefile
A lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/TestFrameVarDILPointerArithmetic.py
A lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/main.cpp
Log Message:
-----------
[LLDB] Add unary plus and minus to DIL (#155617)
This patch adds unary nodes plus and minus, introduces unary type
conversions, and adds integral promotion to the type system.
Commit: cd13d9f9e5af7dad1b389f70bb01854134cb9df5
https://github.com/llvm/llvm-project/commit/cd13d9f9e5af7dad1b389f70bb01854134cb9df5
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
Log Message:
-----------
[lldb] Add test showing UnwindAssemblyInstEmulation can't handle backwards branches (#168398)
If we have a conditional branch, followed by an epilogue, followed by
more code, LLDB will incorrectly compute unwind information through
instruction emulation. Consider this:
```
// ...
<+16>: b.ne ; <+52> DO_SOMETHING_AND_GOTO_AFTER_EPILOGUE
// epilogue start
<+20>: ldp x29, x30, [sp, #0x20]
<+24>: add sp, sp, #0x30
<+28>: ret
// epilogue end
AFTER_EPILOGUE:
<+32>: do something
// ...
<+48>: ret
DO_SOMETHING_AND_GOTO_AFTER_EPILOGUE:
<+52>: stp x22, x23, [sp, #0x10]
<+56>: mov x22, #0x1
<+64>: b ; <+32> AFTER_EPILOGUE
```
LLDB will think that the unwind state of +32 is the same as +28. This is
false, as +32 _never_ executes after +28.
The root cause of the problem is the order in which instructions are
visited; they are visited in the order they appear in the text, with
unwind state always being forwarded to positive branch offsets, but
never to negative offsets.
In the example above, `AFTER_EPILOGUE` should inherit the state of the
branch in +64, but it doesn't because `AFTER_EPILOGUE` is visited right
after the `ret` in +28.
Fixing this should be simple: maintain a stack of instructions to visit.
While the stack is not empty, take the next instruction on stack and
visit it.
* After visiting a non-branching instruction, push the next instruction
and forward unwind state to it.
* After visiting a branch with one or more known targets, push the known
branch targets and forward state to them.
* In all other cases (ret, or branch to register), don't push nor
forward anything.
Never push an instruction already on the stack. Like the algorithm
today, this new algorithm also assumes that, if two instructions branch
to the same target, the unwind state in both better be the same.
(Note: yes, branch to register is also handled incorrectly today, and
will still be incorrect).
Commit: 4a567e3e7c35257e47ee2fb6de61c2c4fb0d4af0
https://github.com/llvm/llvm-project/commit/4a567e3e7c35257e47ee2fb6de61c2c4fb0d4af0
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/utils/lit/examples/many-tests/ManyTests.py
Log Message:
-----------
[llvm][utils][lit] Fix imports in ManyTests.py example (#169328)
Fixes #169297
Commit: 24abb0603a5f491943d05ea3a2b6513238d9937e
https://github.com/llvm/llvm-project/commit/24abb0603a5f491943d05ea3a2b6513238d9937e
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
Log Message:
-----------
[OpenAC][CIR] func-local-declare 'copy' clause lowering (#169115)
This patch implements the lowering for the 'copy' clause for a
function-local declare directive.
This is the first of the clauses that requires a 'cleanup' step, so it
also includes some basic infrastructure for that. Fortunately there are
only 8 clauses (only 6 of which require cleanup), so the if/else chain
won't get too long.
Also fortunately, we don't have to include any of the AST components, as
it is possible to tell all the required details from the entry operation
itself.
Commit: ceea07daa8a41562fdd884a224afbac1d7346e3e
https://github.com/llvm/llvm-project/commit/ceea07daa8a41562fdd884a224afbac1d7346e3e
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/forward_list
M libcxx/test/libcxx/diagnostics/forward_list.nodiscard.verify.cpp
Log Message:
-----------
[libc++][forward_list] Applied `[[nodiscard]]` (#169019)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 456b0512c927e37640fbdb9f6627466948f64305
https://github.com/llvm/llvm-project/commit/456b0512c927e37640fbdb9f6627466948f64305
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-cond-poison.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll
Log Message:
-----------
[VPlan] Set ZeroIsPoison=false for FirstActiveLane (#169298)
When interleaving a loop with an early exit, the parts before the active
lane will be all zero. Currently we emit @llvm.experimental.cttz.elts
with ZeroIsPoison=true for these parts, which means that they will
produce poison.
We don't see any miscompiles today on AArch64 because it has the same
lowering for cttz.elts regardless of ZeroIsPoison, but this may cause
issues on RISC-V when interleaving. This fixes it by setting
ZeroIsPoison=false.
The codegen is slightly worse on RISC-V when ZeroIsPoison=false and we
could potentially recover it by enabling it again when UF=1, but this is
left to another PR.
This is split off from #168738, where LastActiveLane can get expanded to
a FirstActiveLane with an all-zeroes mask.
Commit: 1580f4b038c9945bf73d33b25459bece2f67ace7
https://github.com/llvm/llvm-project/commit/1580f4b038c9945bf73d33b25459bece2f67ace7
Author: David Green <david.green at arm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
Log Message:
-----------
[AArch64] Update costs for fshl/r and add rotr/l variants. NFC
Commit: ad0acf4af001a3781b41b572788adcd7d652d18a
https://github.com/llvm/llvm-project/commit/ad0acf4af001a3781b41b572788adcd7d652d18a
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
Log Message:
-----------
AMDGPU/GlobalISel: Combine S16 copy-trunc-readanylane-anyext (#168410)
Commit: 71952df1f52c8d54ea00a9e836184ba0ece7c6c3
https://github.com/llvm/llvm-project/commit/71952df1f52c8d54ea00a9e836184ba0ece7c6c3
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGException.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
A clang/test/OpenMP/spirv_target_codegen_noexceptions.cpp
Log Message:
-----------
[OpenMP][SPIRV] Disable exceptions for OpenMP SPIR-V (#169094)
More missed target checks.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: d542dce0e6e65d8943c31fc99391572c0287128a
https://github.com/llvm/llvm-project/commit/d542dce0e6e65d8943c31fc99391572c0287128a
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/test/CIR/CodeGenOpenACC/declare-copyin.cpp
Log Message:
-----------
[OpenACC][CIR] copyin lowering for func-local- declare (#169336)
This is exactly like the 'copy', except the exit operation is a 'delete'
instead of a 'copyout'. Also, creating the 'delete' op has one less
argument to it, so we have to do some special handling when creating
that.
Commit: f4ba8e38ee0a3a2789b50d50e724fb90b1527708
https://github.com/llvm/llvm-project/commit/f4ba8e38ee0a3a2789b50d50e724fb90b1527708
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for G_FABS and G_FNEG (#168411)
Commit: 29cfef188088cb0101b3ec70b13d68c06a2d49d6
https://github.com/llvm/llvm-project/commit/29cfef188088cb0101b3ec70b13d68c06a2d49d6
Author: Mirko <mirkomueller97 at live.de>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/DebugInfo/PDB/Native/NativeSession.cpp
M llvm/unittests/DebugInfo/PDB/NativeSessionTest.cpp
Log Message:
-----------
[PDB][NativeSession] Use better error code for invalid format (#167885)
Replaces the default "Success" std::error_code with a more meaningful
one if `Magic != file_magic::pdb`.
Commit: 2bdd1357c826afe681ab0d6ddfa8fb814b2cef6a
https://github.com/llvm/llvm-project/commit/2bdd1357c826afe681ab0d6ddfa8fb814b2cef6a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/simd_utils.h
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_fallbacks.h
M libcxx/include/__locale_dir/locale_base_api/ibm.h
R libcxx/include/__locale_dir/locale_base_api/musl.h
M libcxx/include/__locale_dir/num.h
M libcxx/include/__locale_dir/support/bsd_like.h
M libcxx/include/__locale_dir/support/fuchsia.h
M libcxx/include/__locale_dir/support/linux.h
M libcxx/include/__locale_dir/support/no_locale/strtonum.h
M libcxx/include/__locale_dir/support/windows.h
M libcxx/include/__support/xlocale/__strtonum_fallback.h
M libcxx/include/module.modulemap.in
M libcxx/src/locale.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_long.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_int.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_long.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_long_long.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_short.pass.cpp
Log Message:
-----------
[libc++] Optimize num_get integral functions (#121795)
```
---------------------------------------------------
Benchmark old new
---------------------------------------------------
BM_num_get<bool> 86.5 ns 32.3 ns
BM_num_get<long> 82.1 ns 30.3 ns
BM_num_get<long long> 85.2 ns 33.4 ns
BM_num_get<unsigned short> 85.3 ns 31.2 ns
BM_num_get<unsigned int> 84.2 ns 31.1 ns
BM_num_get<unsigned long> 83.6 ns 31.9 ns
BM_num_get<unsigned long long> 87.7 ns 31.5 ns
BM_num_get<float> 116 ns 114 ns
BM_num_get<double> 114 ns 114 ns
BM_num_get<long double> 113 ns 114 ns
BM_num_get<void*> 151 ns 144 ns
```
This patch applies multiple optimizations:
- Stages two and three of do_get are merged and a custom integer parser
has been implemented
This avoids allocations, removes the need for strto{,u}ll and avoids
__stage2_int_loop (avoiding extra writes to memory)
- std::find has been replaced with __atoms_offset, which uses vector
instructions to look for a character
Fixes #158100
Fixes #158102
Commit: bb78728826ff57f3df859e79bfd857b5a175bb6d
https://github.com/llvm/llvm-project/commit/bb78728826ff57f3df859e79bfd857b5a175bb6d
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
A llvm/test/CodeGen/AArch64/pr151592.mir
A llvm/test/CodeGen/AArch64/pr151888.mir
A llvm/test/CodeGen/AArch64/pr164181-reduced.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
A llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
M llvm/test/CodeGen/PowerPC/combine-fneg.ll
M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
M llvm/test/CodeGen/PowerPC/frem.ll
M llvm/test/CodeGen/PowerPC/froundeven-legalization.ll
M llvm/test/CodeGen/PowerPC/half.ll
M llvm/test/CodeGen/PowerPC/ldexp.ll
M llvm/test/CodeGen/PowerPC/llvm.modf.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
A llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
A llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
A llvm/test/CodeGen/X86/pr76416.ll
M llvm/test/CodeGen/X86/subreg-fail.mir
A llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
Log Message:
-----------
Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG"
A SUBREG_TO_REG instruction expresses that the top bits of the result
register are set to a certain value (e.g. 0).
The example below expresses that the result of %1 will have the top 32
bits zeroed and the lower 32bits being equal to the result of INSTR.
```
%0:gpr32 = INSTR
%1:gpr64 = SUBREG_TO_REG 0, %0, sub32
```
When the RegisterCoalescer tries to remove SUBREG_TO_REG instructions by
coalescing %0 into %1, it must keep the same semantics. Currently
however, the RegisterCoalescer would emit:
```
%1.sub32:gpr64 = INSTR
```
which no longer expresses that the top 32-bits of the register are
defined (zeroed) by INSTR.
This may cause issues with e.g. machine copy propagation where the pass
may think it can remove a COPY-like instruction because the MIR says
only the bottom 32-bits are defined/used, even though other uses of the
register rely on the top 32-bits being zeroed by the COPY-like
instruction.
This PR changes the RegisterCoalescer to instead emit:
```
undef %1.sub32:gpr64 = MOVimm32 42, implicit-def %1
```
to express that the entire contents of %1:gpr64 are defined by the
instruction.
This tries to reland #134408 which had to be reverted due to a few reported
failures.
Commit: ccd2c3e3202d25f39775a39d1565522481a14565
https://github.com/llvm/llvm-project/commit/ccd2c3e3202d25f39775a39d1565522481a14565
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/utils/ci/buildkite-pipeline.yml
Log Message:
-----------
Revert "[libcxx][ci] Temporarily disable ARM jobs" (#169352)
Reverts llvm/llvm-project#169318
Our builders are back online. I see them picking up existing jobs.
Commit: e442c67a2c98a3e1e3bfcf90aaa82ba70fb92760
https://github.com/llvm/llvm-project/commit/e442c67a2c98a3e1e3bfcf90aaa82ba70fb92760
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/SemanticSelection.cpp
Log Message:
-----------
[clangd] Fix C++20 build failure
Commit: dc39fa34c3e27650bd111357d77247592b14baef
https://github.com/llvm/llvm-project/commit/dc39fa34c3e27650bd111357d77247592b14baef
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
Log Message:
-----------
[OpenACC][CIR] copyout clause lowering on func-local declare (#169350)
This is identical to 'copy' and 'copyin', except it uses 'create' and
'copyout' as its entry/exit op. This patch adds the same tests, and
similar code for all of it.
Commit: 870f581f702e6bb85c59670492c9998aacc3dacf
https://github.com/llvm/llvm-project/commit/870f581f702e6bb85c59670492c9998aacc3dacf
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/__config
M libcxx/test/std/depr/depr.cpp.headers/ccomplex.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/ciso646.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/cstdalign.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/cstdbool.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/ctgmath.verify.cpp
Log Message:
-----------
[libc++] Disable header deprecations until #168041 is landed (#169305)
The `#warning` causes diagnostics if system headers include deprecated
headers. #168041 will add a way to deprecated headers properly, which
then also interacts nicely with system header suppression.
Commit: ab7145231b9d6a87d528a344456a77793c75614d
https://github.com/llvm/llvm-project/commit/ab7145231b9d6a87d528a344456a77793c75614d
Author: Marco Elver <elver at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Support/AllocToken.cpp
Log Message:
-----------
[Support] Permit "default" string in AllocToken mode parsing (#169351)
Update getAllocTokenModeFromString() to recognize "default" as a valid
mode string, mapping it to `DefaultAllocTokenMode`.
Commit: f31e1cf012c3029ef7619db25f5074b69b550e59
https://github.com/llvm/llvm-project/commit/f31e1cf012c3029ef7619db25f5074b69b550e59
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
A libsycl/Maintainers.md
M llvm/Maintainers.md
Log Message:
-----------
[libsycl] Add Maintainers.md file (#168550)
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 51fef127f29fe2225358396728d95e2d9e6af75e
https://github.com/llvm/llvm-project/commit/51fef127f29fe2225358396728d95e2d9e6af75e
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
Log Message:
-----------
[lldb] Add const& to InstructionList parameter (#169342)
Commit: cc0371f2a4f95614c35601f898dde7745120e8d1
https://github.com/llvm/llvm-project/commit/cc0371f2a4f95614c35601f898dde7745120e8d1
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
Log Message:
-----------
[AMDGPU] Use ListSeparator. NFC. (#169347)
Commit: e3d0ac188665afe96df32bd2841f6b71b05b8790
https://github.com/llvm/llvm-project/commit/e3d0ac188665afe96df32bd2841f6b71b05b8790
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/string_view
M libcxx/test/libcxx/diagnostics/string_view.nodiscard.verify.cpp
M libcxx/test/libcxx/strings/string.view/nonnull.verify.cpp
Log Message:
-----------
[libc++][string_view] Applied `[[nodiscard]]` (#169010)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 78d829857656e23a7d3bc4510baf4ddcb6fce97b
https://github.com/llvm/llvm-project/commit/78d829857656e23a7d3bc4510baf4ddcb6fce97b
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/test/CIR/CodeGenOpenACC/declare-create.cpp
M clang/test/CIR/CodeGenOpenACC/openacc-not-implemented.cpp
Log Message:
-----------
[OpenACC][CIR] 'create' clause lowering on func-local-declare (#169356)
This one is another that is effectively identical to copy, copyin, and
copyout, except its entry/exit ops pair is create/delete.
Commit: bab1c2971a31f032a6c353a0076d16e564ab50fa
https://github.com/llvm/llvm-project/commit/bab1c2971a31f032a6c353a0076d16e564ab50fa
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Passes/Inliner.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
A bolt/test/AArch64/inline-armv8.3-returns.s
A bolt/test/AArch64/inline-armv8.3-tailcall.s
A bolt/test/AArch64/inline-pauth-lr.s
Log Message:
-----------
[BOLT] Extend Inliner to work on functions with Pointer Authentication (#162458)
The inliner uses DirectSP to check if a function has instructions that
modify the SP. Exceptions are stack Push and Pop instructions.
We can also allow pointer signing and authenticating instructions.
The inliner removes the Return instructions from the inlined functions.
If it is a fused pointer-authentication-and-return (e.g. RETAA), we have
to generate a new authentication instruction.
Commit: 23907a20a5fa5c6e065b73f4515a2a072675dad5
https://github.com/llvm/llvm-project/commit/23907a20a5fa5c6e065b73f4515a2a072675dad5
Author: Lucas Ste <38472950+LucasSte at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/BPF/BPF.td
M llvm/lib/Target/BPF/BPFISelLowering.cpp
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/BPF/BPFSubtarget.cpp
M llvm/lib/Target/BPF/BPFSubtarget.h
M llvm/test/CodeGen/BPF/atomic-oversize.ll
A llvm/test/CodeGen/BPF/builtin_calls.ll
M llvm/test/CodeGen/BPF/struct_ret1.ll
M llvm/test/CodeGen/BPF/struct_ret2.ll
Log Message:
-----------
[BPF] Allow libcalls behind a feature gate (#168442)
**Problem**
In Rust, checked math functions (like `checked_mul`, `overflowing_mul`,
`saturating_mul`) are part of the primitive implementation of integers
([see u64](https://doc.rust-lang.org/std/primitive.u64.html) for
instance). The Rust compiler builds the Rust
[compiler-builtins](https://github.com/rust-lang/compiler-builtins)
crate as a step in the compilation processes, since it contains the math
builtins to be lowered in the target.
For BPF, however, when using those functions in Rust we hit the
following errors:
```
ERROR llvm: <unknown>:0:0: in function func i64 (i64, i64): A call to built-in function '__multi3' is not supported.
ERROR llvm: <unknown>:0:0: in function func i64 (i64, i64): only small returns supported
```
Those errors come from the following code:
```
pub fn func(a: u64, b: u64) -> u64 {
a.saturating_mul(b)
}
```
Those functions invoke underneath the llvm instrinc `{ i64, i1 }
@llvm.umul.with.overflow.i64(i64, i64)` or its variants.
It is very useful to use safe math operations when writing BPF code in
Rust, and I would like to add support for those in the target.
**Changes**
1. Create a target feature `allow-builtin-calls` to enable code
generation for builtin functions.
2. Implement `CanLowerReturn` to fix the error `only small returns
supported`.
3. Add code to correctly invoke lib functions.
4. Add a test case together with the corresponding C code.
Commit: 38a5dd5bc7d7f59a2acfeaff3b6852337bb6704e
https://github.com/llvm/llvm-project/commit/38a5dd5bc7d7f59a2acfeaff3b6852337bb6704e
Author: Shota Matsubara <40222661+baramatsubonzo at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl02.rst
Log Message:
-----------
Fix typo in LLVM Kaleidoscope tutorial (Chapter 2) (#169319)
This patch fixes a minor typo in the **Kaleidoscope tutorial (Chapter
2)**.
The sentence:
“checks to see if **if** is too low”
has been corrected to:
“checks to see if **it** is too low”.
This is a documentation-only change and does not affect any semantic
behavior or code generation.
Thank you for maintaining the tutorial, and please let me know if any
further adjustments are needed.
Commit: ad1be4a589b3143c2a76d521bcf205d22bb22ffe
https://github.com/llvm/llvm-project/commit/ad1be4a589b3143c2a76d521bcf205d22bb22ffe
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
A clang/test/CIR/CodeGen/static-members.cpp
Log Message:
-----------
[CIR] Add handling for static data members (#169134)
This adds some trivial handling to force emitting of child decls inside
C++ records.
Commit: 76e9834b2908ec550bb2ca221b7652f6a5c32c46
https://github.com/llvm/llvm-project/commit/76e9834b2908ec550bb2ca221b7652f6a5c32c46
Author: PMylon <pmylonas at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/test/Target/LLVMIR/target-ext-type.mlir
Log Message:
-----------
[MLIR][LLVM] Support named barrier as a global variable type in llvm dialect (#169194)
Enables `amdgcn.named.barrier` target extension type as a global
variable type in MLIR.
Commit: 79c56e8f335b231d00b06c8031d5d4c31ceb7d96
https://github.com/llvm/llvm-project/commit/79c56e8f335b231d00b06c8031d5d4c31ceb7d96
Author: Shubham Sandeep Rastogi <Shubham.Rastogi at sony.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
A llvm/test/Transforms/Coroutines/declare-value.ll
Log Message:
-----------
Add support for llvm.dbg.declare_value in the CoroSplitter pass. (#168134)
Make sure the CoroSplitter pass correctly handles `#dbg_declare_value`
intrinsics. Which means, it should identify them, and convert them to
`#dbg_declares` so that any subsequent passes do not need to be amended
to support the `#dbg_declare_value` intrinsic.
More information here:
https://discourse.llvm.org/t/rfc-introduce-new-llvm-dbg-coroframe-entry-intrinsic/88269
This patch is the second and last in a stack of patches, with the one
preceding it being: https://github.com/llvm/llvm-project/pull/168132
Commit: c1f24a5205364686213a23182dc45df9c2383360
https://github.com/llvm/llvm-project/commit/c1f24a5205364686213a23182dc45df9c2383360
Author: Charles Zablit <c_zablit at apple.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M lldb/tools/driver/Driver.cpp
Log Message:
-----------
[windows] improve python3.dll load check (#168864)
Commit: 3843a50c69063a9440ccd65ff9a167be75baf442
https://github.com/llvm/llvm-project/commit/3843a50c69063a9440ccd65ff9a167be75baf442
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/AST/Decl.cpp
M clang/unittests/AST/TypePrinterTest.cpp
Log Message:
-----------
[Clang][TypePrinter] Make printNestedNameSpecifier look at typedefs (#169364)
This is to resolve a regression caused by #168534.
Now when we have an anonymous object like a struct or union that has a
typedef attached, we print the typedef name instead of listing it as
anonymous.
Commit: 81f4ab83eb6fbedcede35fb1b5a4d45c3e8d5c16
https://github.com/llvm/llvm-project/commit/81f4ab83eb6fbedcede35fb1b5a4d45c3e8d5c16
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang-tools-extra/test/clang-doc/namespace.cpp
Log Message:
-----------
[clang-doc] Add Mustache HTML output to namespace test (#169107)
This patch adds Mustache HTML tests alongside the legacy HTML backend
for namespace output. This way, we can see exactly where the output
currently differs before replacing the legacy backend.
The same thing will be done for all other tests where the legacy HTML
backend is tested.
Commit: 37f7b3128d8217e6a99cc6117ea709e8fa7b0704
https://github.com/llvm/llvm-project/commit/37f7b3128d8217e6a99cc6117ea709e8fa7b0704
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
A llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar-widen-gep-scalable.ll
M llvm/test/Transforms/LoopVectorize/widen-gep-all-indices-invariant.ll
Log Message:
-----------
Reland [VPlan] Handle WidenGEP in narrowToSingleScalars (#167880)
Changes: Fix a missed update to WidenGEP::usesFirstLaneOnly, and include
reduced-case test that was previously hitting the new assert: the
underlying reason was that VPWidenGEP::usesScalars was too weak, and the
single-scalar WidenGEP was not narrowed by narrowToSingleScalarRecipes.
This allows us to strip a special case in VPWidenGEP::execute.
Commit: 9688f88e57f369002157758b8399a235bf6763ca
https://github.com/llvm/llvm-project/commit/9688f88e57f369002157758b8399a235bf6763ca
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/pr128062-interleaved-accesses-narrow-group.ll
Log Message:
-----------
[LV] Pre-commit test for #128062 (#164801)
In preparation to extend the work done by dfa665f ([VPlan] Add
transformation to narrow interleave groups) to make the narrowing more
powerful, pre-commit a test case from #128062.
Commit: 621cbcde0161341494b546a1fb478cfd57d1a94f
https://github.com/llvm/llvm-project/commit/621cbcde0161341494b546a1fb478cfd57d1a94f
Author: Atmn Patel <atmnp at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/test/Transforms/OpenACC/acc-implicit-data.fir
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
Log Message:
-----------
[mlir][acc] Adds attr to acc.present to identify default clause origin (#169114)
The `acc.present` Op as generated by ACCImplicitData does not provide a
way to differentiate between `acc.present` ops that are generated
implicitly and the ones that are generated as result of an explicit
`default(present)` clause in the source code. This differentiation would
allow for better communication to the user on the decisions made by the
compiler while managing data automatically between the host and the
device. This commit adds this information as a discardable attribute on
the `acc.present` op.
Commit: a27bb38ee6f5762e715803d8eb6ffc5a8dd09575
https://github.com/llvm/llvm-project/commit/a27bb38ee6f5762e715803d8eb6ffc5a8dd09575
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/tools/bugpoint/BugDriver.h
M llvm/tools/bugpoint/ExecutionDriver.cpp
M llvm/tools/bugpoint/ExtractFunction.cpp
M llvm/tools/bugpoint/Miscompilation.cpp
M llvm/tools/bugpoint/OptimizerDriver.cpp
Log Message:
-----------
Reapply "[NFC][bugpoint] Namespace cleanup in `bugpoint`" (#168961) (#169055)
This reverts commit b83e458fe5330227581e1e65f3866ddfcd597837.
Also undo the use of namespace qualifier for `ReducePassList` as that
seems to cause build failures.
Commit: 1b65752d16045114ed381c95306517ff99147cda
https://github.com/llvm/llvm-project/commit/1b65752d16045114ed381c95306517ff99147cda
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/test/CIR/CodeGenOpenACC/declare-present.cpp
Log Message:
-----------
[OpenACC][CIR] Implement 'present' lowering on local-declare (#169381)
Just like the last handful of patches that did copy, copyin, copyout,
create, etc, this patch has the exact same behavior, except the
entry op is a present, and the exit is delete.
Commit: 740d0bd385967f6ae0171896722143d9a70b66a5
https://github.com/llvm/llvm-project/commit/740d0bd385967f6ae0171896722143d9a70b66a5
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/include/mlir-c/Dialect/LLVM.h
M mlir/lib/Bindings/Python/DialectLLVM.cpp
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/test/python/dialects/llvm.py
Log Message:
-----------
[MLIR][Python] add GetTypeID for llvm.struct_type and llvm.ptr and enable downcasting (#169383)
Commit: d4cd331b7efc8cd5f15faa846697d9d61b0ff246
https://github.com/llvm/llvm-project/commit/d4cd331b7efc8cd5f15faa846697d9d61b0ff246
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 2bdd1357c826
Commit: 0e86510c787d68f5f87708b2efdaf92a7501b6c3
https://github.com/llvm/llvm-project/commit/0e86510c787d68f5f87708b2efdaf92a7501b6c3
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
Log Message:
-----------
[gn build] Port 3773bbe9e791
Commit: 40fb2ca506a873b031f90dac619ccca1d6ff0de5
https://github.com/llvm/llvm-project/commit/40fb2ca506a873b031f90dac619ccca1d6ff0de5
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
Log Message:
-----------
[gn build] Port 645e0dcbff33
Commit: 445956443bdf5dcc7fb8beb7dd9e571f31551519
https://github.com/llvm/llvm-project/commit/445956443bdf5dcc7fb8beb7dd9e571f31551519
Author: Henry Baba-Weiss <henry.babaweiss at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDecl.cpp
M clang/test/CodeGen/attr-target-clones.c
M clang/test/Sema/attr-target-clones.c
Log Message:
-----------
[clang][Sema] Handle target_clones redeclarations that omit the attribute (#169259)
This patch adds a case to `CheckMultiVersionAdditionalDecl()` that
detects redeclarations of `target_clones` functions which omit the
attribute, and makes sure they are marked as redeclarations. It also
updates the comment at the call site of
`CheckMultiVersionAdditionalDecl()` to reflect this.
Previously, `target_clones` multiversioned functions that omitted the
attribute from subsequent declarations would cause Clang to hit an
`llvm_unreachable` and crash. In the following example, the second
declaration (the function definition) should inherit the `target_clones`
attribute from the first declaration (the forward declaration):
```
__attribute__((target_clones("arch=atom", "default")))
void foo(void);
void foo(void) { /* ... */ }
```
However, `CheckMultiVersionAdditionalDecl()` was not recognizing the
function definition as a redeclaration of the forward declaration, which
prevented `Sema::MergeFunctionDecl()` from automatically inheriting the
attribute.
A side effect of this fix is that Clang now catches redeclarations of
`target_clones` functions that have conflicting types, which previously
caused Clang to crash by hitting that same `llvm_unreachable`. The
`bad_overload1` case in `clang/test/Sema/attr-target-clones.c` has been
updated to reflect this.
Fixes #165517
Fixes #129483
Commit: f5e228b32ac0a59b5aa834caa80150ba877e82ce
https://github.com/llvm/llvm-project/commit/f5e228b32ac0a59b5aa834caa80150ba877e82ce
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll
M llvm/test/CodeGen/DirectX/scalarize-alloca.ll
M llvm/test/CodeGen/DirectX/scalarize-global.ll
Log Message:
-----------
[DirectX] Simplify DXIL data scalarization, and data scalarize whole GEP chains (#168096)
- The DXIL data scalarizer only needs to change vectors into arrays. It
does not need to change the types of GEPs to match the pointer type.
This PR simplifies the `visitGetElementPtrInst` method to do just that
while also accounting for nested GEPs from ConstantExprs. (Before this
PR, there were still vector types lingering in nested GEPs with
ConstantExprs.)
- The `equivalentArrayTypeFromVector` function was awkwardly placed near
the top of the file and away from the other helper functions. The
function is now moved next to the other helper functions.
- Removed an unnecessary `||` condition from `isVectorOrArrayOfVectors`
Related tests have also been cleaned up, and the test CHECKs have been
modified to account for the new simplified behavior.
Commit: 4a0d4850d77c13b71cd0bdd40b38a5afc46fb62b
https://github.com/llvm/llvm-project/commit/4a0d4850d77c13b71cd0bdd40b38a5afc46fb62b
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang-tools-extra/clang-doc/assets/class-template.mustache
M clang-tools-extra/test/clang-doc/namespace.cpp
Log Message:
-----------
[clang-doc] Add definition information to class templates (#169109)
Commit: 658675fad794197a2a41207b8e4b422becd78f28
https://github.com/llvm/llvm-project/commit/658675fad794197a2a41207b8e4b422becd78f28
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/test/CIR/CodeGenOpenACC/declare-deviceresident.cpp
Log Message:
-----------
[OpenACC][CIR] 'device_resident' clause lowering for local declare (#169389)
Just like the last handful of clauses, this is a pretty simple one,
doing device_resident (Entry op: declare_device_resident, and exit:
delete). This should be the last of the 'local' declare patches.
Commit: 0549aa11c2c1b619c673a0644a25f939bf13746f
https://github.com/llvm/llvm-project/commit/0549aa11c2c1b619c673a0644a25f939bf13746f
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/DWARFLinker/Classic/DWARFLinker.h
M llvm/include/llvm/DWARFLinker/Classic/DWARFLinkerDeclContext.h
M llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
M llvm/lib/DWARFLinker/Classic/DWARFLinkerDeclContext.cpp
M llvm/test/tools/dsymutil/AArch64/dummy-debug-map-arm64.map
M llvm/test/tools/dsymutil/AArch64/dwarf5-str-offsets-base-strx.test
M llvm/test/tools/dsymutil/AArch64/inlined-low_pc.c
A llvm/test/tools/dsymutil/AArch64/odr-uniquing-DW_AT_name-conflict.test
A llvm/test/tools/dsymutil/Inputs/odr-uniquing-DW_AT_name-conflict/1.o
A llvm/test/tools/dsymutil/Inputs/odr-uniquing-DW_AT_name-conflict/2.o
A llvm/test/tools/dsymutil/Inputs/odr-uniquing-DW_AT_name-conflict/lib1.cpp
A llvm/test/tools/dsymutil/Inputs/odr-uniquing-DW_AT_name-conflict/lib1.h
A llvm/test/tools/dsymutil/Inputs/odr-uniquing-DW_AT_name-conflict/lib2.cpp
A llvm/test/tools/dsymutil/Inputs/odr-uniquing-DW_AT_name-conflict/main.cpp
Log Message:
-----------
[llvm][dsymutil] Use the DW_AT_name of the uniqued DIE for insertion into .debug_names (#168513)
Depends on:
* https://github.com/llvm/llvm-project/pull/168895
Note, the last commit is the one with the actual fix. The others are
drive-by/test changes
We've been seeing dsymutil verification failures like:
```
error: Name Index @ 0x0: Entry @ 0x11949d: mismatched Name of DIE @ 0x9c644c:
index - apply<(lambda at /some/build/dir/lib/LLVMSupport/include/llvm/Support/Error.h:1070:35)>;
debug_info - apply<(lambda at /some/build/dir/lib/LLVMCustom/include/llvm/Support/Error.h:1070:35)>
apply, _ZN11custom_llvm18ErrorHandlerTraitsIRFvRNS_13ErrorInfoBaseEEE5applyIZNS_12consumeErrorENS_5ErrorEEUlRKS1_E_EES7_OT_NSt3__110unique_ptrIS1_NSD_14default_deleteIS1_EEEE.
```
Not how the name of the DIE has a different lambda path than the one
that was used to insert the DIE into debug_names.
The root cause of the issue is that we have a DW_AT_subprogram
definition whose DW_AT_specification DIE got deduplicated. But the
DW_AT_name of the original specification is different than the one it
got uniqued to. That’s technically fine because dsymutil uniques by
linkage name, which uniquely identifies any function with non-internal
linkage.
But we insert the definition DIE into the debug-names table using the
DW_AT_name of the original specification (we call
`getDIENames(InputDIE…)`). But what we really want to do is use the name
of the adjusted `DW_AT_specifcation` (i.e., the `DW_AT_specification` of
the output DIE). That’s not as simple as it sounds because we can’t just
get ahold of the DIE in the output CU. We have to grab the ODR
`DeclContext` of the input DIE’s specification. That is the only link
back to the canonical specification DIE. For that to be of any use, we
have to stash the `DW_AT_name` into `DeclContext` so we can use it in
`getDIENames`.
We have to account for the possibility of multiple levels of
`DW_AT_specification`/`DW_AT_abstract_origin`. So my proposed solution
is to recursively scan the referenced DIE’s, grab the canonical DIE for
those and get the name from the `DeclContext` (if none exists then use
the `DW_AT_name` of the DIE itself).
One remaining question is whether we need to handle the case where a DIE
has a `DW_AT_specification` *and* a `DW_AT_abstract_origin`? That
complicates the way we locate `DW_AT_name`. We'd have to adjust
`getCanonicalDIEName` to handle this. But it's not clear what a
`DW_AT_name` would be for such cases. Worst case at the moment we take
the wrong path up the specifications and don't find any `DW_AT_name`,
and don't end up indexing that DIE. Something to keep an eye out for.
rdar://149239553
Commit: e92bb83c1810c61a7fa81d55a1690cffa2b14b60
https://github.com/llvm/llvm-project/commit/e92bb83c1810c61a7fa81d55a1690cffa2b14b60
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
Log Message:
-----------
[AArch64][PAC] Simplify emission of authenticated pointer check (NFC) (#160899)
The `AArch64AsmPrinter::emitPtrauthCheckAuthenticatedValue` method accepts
two arguments, `bool ShouldTrap` and `const MCSymbol *OnFailure`, that
control the behavior of the emitted instruction sequence when the check
fails:
* `ShouldTrap` requests an error to be generated
* `OnFailure` requests branching to the given label after clearing the
PAC field
An assertion in `emitPtrauthCheckAuthenticatedValue` ensures that when
`ShouldTrap` is true, `OnFailure` must be null. But the opposite holds
as well: when `ShouldTrap` is false, `OnFailure` is always non-null,
as otherwise the entire sequence following `AUT[ID][AB]` instruction
would turn into a very expensive equivalent of XPAC (unless the CPU
implements FEAT_FPAC):
authenticate Xn
inspect PAC field of Xn
if PAC field was not cleared:
clear PAC field
In other words, the value of `ShouldTrap` argument can be computed as
`OnFailure == nullptr` at all existing call sites. In fact, at three
of four call sites, constant `true` and `nullptr` are passed as the
values of these function arguments. `emitPtrauthAuthResign` is the
only caller that potentially makes use of checking-but-not-trapping
mode of `emitPtrauthCheckAuthenticatedValue`, and it passes a non-null
pointer as `OnFailure` when `ShouldTrap` is false.
This commit makes the invariant explicit by omitting the `ShouldTrap`
argument and inferring its value from the `OnFailure` argument instead.
Commit: 48eb697441e20f2e1a66d953436b9d66e0fc466d
https://github.com/llvm/llvm-project/commit/48eb697441e20f2e1a66d953436b9d66e0fc466d
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
Log Message:
-----------
[LV] Count cost of middle block if TC <= VF. (#168949)
If the expected trip count is less than the VF, the vector loop will
only execute a single iteration. When that's the case, the cost of the
middle block has the same impact as the cost of the vector loop. Include
it in isOutsideLoopWorkProfitable to avoid vectorizing when the extra
work in the middle block makes it unprofitable.
Note that isOutsideLoopWorkProfitable already scales the cost of blocks
outside the vector region, but the patch restricts accounting for the
middle block to cases where VF <= ExpectedTC, to initially catch some
worst cases and avoid regressions.
This initial version should specifically avoid unprofitable tail-folding
for loops with low trip counts after re-applying
https://github.com/llvm/llvm-project/pull/149042.
PR: https://github.com/llvm/llvm-project/pull/168949
Commit: 7b186e4bf0f1485657697bc79c66b5792dcd562e
https://github.com/llvm/llvm-project/commit/7b186e4bf0f1485657697bc79c66b5792dcd562e
Author: Daan De Meyer <daan.j.demeyer at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix designated initializer detection (#169228)
Currently, in the following snippet, the second designated initializer
is incorrectly detected as an OBJC method expr. Fix that and a test to
make sure we don't regress.
```
Foo foo[] = {[0] = 1, [1] = 2};
```
Commit: 40334b8632f6d065e6672ada1c4342d07ecce629
https://github.com/llvm/llvm-project/commit/40334b8632f6d065e6672ada1c4342d07ecce629
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/Compiler.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/CommonArgs.h
R clang/include/clang/Driver/CreateASTUnitFromArgs.h
R clang/include/clang/Driver/CreateInvocationFromArgs.h
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Frontend/ChainedDiagnosticConsumer.h
M clang/include/clang/Frontend/CompilerInvocation.h
R clang/include/clang/Frontend/StandaloneDiagnostic.h
M clang/include/clang/Frontend/Utils.h
M clang/include/clang/Options/OptionUtils.h
M clang/lib/CrossTU/CMakeLists.txt
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Driver/CMakeLists.txt
R clang/lib/Driver/CreateASTUnitFromArgs.cpp
R clang/lib/Driver/CreateInvocationFromArgs.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CMakeLists.txt
M clang/lib/Frontend/CompilerInvocation.cpp
A clang/lib/Frontend/CreateInvocationFromCommandLine.cpp
R clang/lib/Frontend/StandaloneDiagnostic.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Options/OptionUtils.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/tools/c-index-test/CMakeLists.txt
M clang/tools/c-index-test/core_main.cpp
M clang/tools/diagtool/CMakeLists.txt
M clang/tools/diagtool/ShowEnabledWarnings.cpp
M clang/tools/driver/cc1_main.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexer.cpp
M clang/tools/libclang/CMakeLists.txt
M clang/tools/libclang/Indexing.cpp
M clang/unittests/Driver/DXCModeTest.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M clang/unittests/Frontend/UtilsTest.cpp
M clang/unittests/Sema/CMakeLists.txt
M clang/unittests/Sema/SemaNoloadLookupTest.cpp
M clang/unittests/Serialization/ForceCheckFileInputTest.cpp
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Serialization/NoCommentsTest.cpp
M clang/unittests/Serialization/PreambleInNamedModulesTest.cpp
M clang/unittests/Serialization/VarDeclConstantInitTest.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
M clang/unittests/Tooling/Syntax/TreeTestBase.cpp
M flang/lib/Frontend/CMakeLists.txt
M flang/lib/Frontend/CompilerInvocation.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangHost.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/unittests/Expression/ClangParserTest.cpp
Log Message:
-----------
Revert " [clang] Refactor to remove clangDriver dependency from clangFrontend and flangFrontend (#165277)"
This reverts commit 3773bbe9e7916ec89fb3e3cd02e29c54cabac82b.
Commit: 5a9c62ba48ea2fa899e3ff54d6b4779c1902f34b
https://github.com/llvm/llvm-project/commit/5a9c62ba48ea2fa899e3ff54d6b4779c1902f34b
Author: Vishruth Thimmaiah <vishruththimmaiah at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
A clang/test/CIR/CodeGen/X86/avx512bw-builtins.c
Log Message:
-----------
[CIR][X86] Add support for `kshiftl`/`kshiftr` builtins (#168591)
Adds support for the `__builtin_ia32_kshiftli` and
`__builtin_ia32_kshiftri` X86 builtins.
Part of #167765
---------
Signed-off-by: vishruth-thimmaiah <vishruththimmaiah at gmail.com>
Commit: 5c15f579234f0ac4e40037ebc7e250499525ac48
https://github.com/llvm/llvm-project/commit/5c15f579234f0ac4e40037ebc7e250499525ac48
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/Compiler.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/CommonArgs.h
A clang/include/clang/Driver/CreateASTUnitFromArgs.h
A clang/include/clang/Driver/CreateInvocationFromArgs.h
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Frontend/ChainedDiagnosticConsumer.h
M clang/include/clang/Frontend/CompilerInvocation.h
A clang/include/clang/Frontend/StandaloneDiagnostic.h
M clang/include/clang/Frontend/Utils.h
M clang/include/clang/Options/OptionUtils.h
M clang/lib/CrossTU/CMakeLists.txt
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Driver/CMakeLists.txt
A clang/lib/Driver/CreateASTUnitFromArgs.cpp
A clang/lib/Driver/CreateInvocationFromArgs.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CMakeLists.txt
M clang/lib/Frontend/CompilerInvocation.cpp
R clang/lib/Frontend/CreateInvocationFromCommandLine.cpp
A clang/lib/Frontend/StandaloneDiagnostic.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Options/OptionUtils.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/tools/c-index-test/CMakeLists.txt
M clang/tools/c-index-test/core_main.cpp
M clang/tools/diagtool/CMakeLists.txt
M clang/tools/diagtool/ShowEnabledWarnings.cpp
M clang/tools/driver/cc1_main.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexer.cpp
M clang/tools/libclang/CMakeLists.txt
M clang/tools/libclang/Indexing.cpp
M clang/unittests/Driver/DXCModeTest.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M clang/unittests/Frontend/UtilsTest.cpp
M clang/unittests/Sema/CMakeLists.txt
M clang/unittests/Sema/SemaNoloadLookupTest.cpp
M clang/unittests/Serialization/ForceCheckFileInputTest.cpp
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Serialization/NoCommentsTest.cpp
M clang/unittests/Serialization/PreambleInNamedModulesTest.cpp
M clang/unittests/Serialization/VarDeclConstantInitTest.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
M clang/unittests/Tooling/Syntax/TreeTestBase.cpp
M flang/lib/Frontend/CMakeLists.txt
M flang/lib/Frontend/CompilerInvocation.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangHost.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/unittests/Expression/ClangParserTest.cpp
Log Message:
-----------
Reapply " [clang] Refactor to remove clangDriver dependency from clangFrontend and flangFrontend (#165277)"
This reverts commit 40334b8632f6d065e6672ada1c4342d07ecce629.
Unfortunately the revert breaks the build.
Commit: dea330b38d9c18b68219abdb52baaa72c9f1103d
https://github.com/llvm/llvm-project/commit/dea330b38d9c18b68219abdb52baaa72c9f1103d
Author: Naveen Seth Hanig <naveen.hanig at outlook.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/Compiler.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/CommonArgs.h
R clang/include/clang/Driver/CreateASTUnitFromArgs.h
R clang/include/clang/Driver/CreateInvocationFromArgs.h
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Frontend/CompilerInvocation.h
R clang/include/clang/Frontend/StandaloneDiagnostic.h
M clang/include/clang/Frontend/Utils.h
M clang/include/clang/Options/OptionUtils.h
M clang/lib/CrossTU/CMakeLists.txt
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Driver/CMakeLists.txt
R clang/lib/Driver/CreateASTUnitFromArgs.cpp
R clang/lib/Driver/CreateInvocationFromArgs.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CMakeLists.txt
M clang/lib/Frontend/CompilerInvocation.cpp
A clang/lib/Frontend/CreateInvocationFromCommandLine.cpp
R clang/lib/Frontend/StandaloneDiagnostic.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Options/OptionUtils.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/tools/c-index-test/CMakeLists.txt
M clang/tools/c-index-test/core_main.cpp
M clang/tools/diagtool/CMakeLists.txt
M clang/tools/diagtool/ShowEnabledWarnings.cpp
M clang/tools/driver/cc1_main.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexer.cpp
M clang/tools/libclang/CMakeLists.txt
M clang/tools/libclang/Indexing.cpp
M clang/unittests/Driver/DXCModeTest.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M clang/unittests/Frontend/UtilsTest.cpp
M clang/unittests/Sema/CMakeLists.txt
M clang/unittests/Sema/SemaNoloadLookupTest.cpp
M clang/unittests/Serialization/ForceCheckFileInputTest.cpp
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Serialization/NoCommentsTest.cpp
M clang/unittests/Serialization/PreambleInNamedModulesTest.cpp
M clang/unittests/Serialization/VarDeclConstantInitTest.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
M clang/unittests/Tooling/Syntax/TreeTestBase.cpp
M flang/lib/Frontend/CMakeLists.txt
M flang/lib/Frontend/CompilerInvocation.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangHost.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/unittests/Expression/ClangParserTest.cpp
Log Message:
-----------
Revert " [clang] Refactor to remove clangDriver dependency from clangFrontend and flangFrontend (#165277)" (#169397)
This reverts commit 3773bbe and relands the last revert attempt 40334b8.
3773bbe broke the build for the build configuration described in here:
https://github.com/llvm/llvm-project/pull/165277#issuecomment-3572432250
Commit: 72dd4f75d6c6f7964a6612599ff09895ffd8d7e6
https://github.com/llvm/llvm-project/commit/72dd4f75d6c6f7964a6612599ff09895ffd8d7e6
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
Log Message:
-----------
[gn build] Port dea330b38d9c
Commit: 20929abb85633e4f17e5df21c9ac2fd80650f9d4
https://github.com/llvm/llvm-project/commit/20929abb85633e4f17e5df21c9ac2fd80650f9d4
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-data-use-dev-ordering.mlir
A mlir/test/Target/LLVMIR/omptarget-declare-target-to-host.mlir
M mlir/test/Target/LLVMIR/omptarget-nowait.mlir
A mlir/test/Target/LLVMIR/omptarget-overlapping-record-member-map.mlir
M mlir/test/Target/LLVMIR/omptarget-record-type-with-ptr-member-host.mlir
A offload/test/offloading/fortran/dtype-member-overlap-map.f90
Log Message:
-----------
[MLIR][OpenMP] Introduce overlapped record type map support (#119588)
This PR introduces a new additional type of map lowering for record
types that Clang currently supports, in which a user can map a top-level
record type and then individual members with different mapping,
effectively creating a sort of "overlapping" mapping that we attempt to
cut around.
This is currently most predominantly used in Fortran, when mapping
descriptors and there data, we map the descriptor and its data with
separate map modifiers and "cut around" the pointer data, so that wedo
not overwrite it unless the runtime deems it a neccesary action based on
its reference counting mechanism. However, it is a mechanism that will
come in handy/trigger when a user explitily maps a record type (derived
type or structure) and then explicitly maps a member with a different
map type.
These additions were predominantly in the OpenMPToLLVMIRTranslation.cpp
file and phase, however, one Flang test that checks end-to-end IR
compilation (as far as we care for now at least) was altered.
2/3 required PRs to enable declare target to mapping, should look at PR
3/3 to check for full green passes (this one will fail a number due to
some dependencies).
Co-authored-by: Raghu Maddhipatla raghu.maddhipatla at amd.com
Commit: 173600880b8f469ad9ae8da757bdc94959690ffa
https://github.com/llvm/llvm-project/commit/173600880b8f469ad9ae8da757bdc94959690ffa
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-allocatable.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-teams-private-implicit-scalar-map.f90
M flang/test/Lower/OpenMP/allocatable-array-bounds.f90
M flang/test/Lower/OpenMP/allocatable-map.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/declare-mapper.f90
M flang/test/Lower/OpenMP/declare-target-link-tarop-cap.f90
M flang/test/Lower/OpenMP/defaultmap.f90
M flang/test/Lower/OpenMP/derived-type-allocatable-map.f90
M flang/test/Lower/OpenMP/derived-type-map.f90
M flang/test/Lower/OpenMP/map-character.f90
M flang/test/Lower/OpenMP/map-descriptor-deferral.f90
M flang/test/Lower/OpenMP/map-neg-alloca-derived-type-array.f90
M flang/test/Lower/OpenMP/optional-argument-map-2.f90
M flang/test/Lower/OpenMP/optional-argument-map-3.f90
M flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/volatile-openmp.f90
M flang/test/Transforms/omp-map-info-finalization.fir
M mlir/include/mlir/Dialect/OpenMP/OpenMPEnums.td
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/omptarget-declare-target-to-device.mlir
A offload/test/offloading/fortran/declare-target-to-allocatable-vars-in-target-with-update.f90
A offload/test/offloading/fortran/declare-target-to-vars-target-region-and-update.f90
A offload/test/offloading/fortran/declare-target-to-zero-index-allocatable-target-map.f90
Log Message:
-----------
[Flang][OpenMP][MLIR] Initial declare target to for variables implementation (#119589)
While the infrastructure for declare target to/enter and link for
variables exists in the MLIR dialect and at the Flang level, the current
lowering from MLIR -> LLVM IR isn't in place, it's only in place for
variables that have the link clause applied.
This PR aims to extend that lowering to an initial implementation that
incorporates declare target to as well, which primarily requires changes
in the OpenMPToLLVMIRTranslation phase. However, a minor addition to the
OpenMP dialect was required to extend the declare target enumerator to
include a default None field as well.
This also requires a minor change to the Flang lowering's
MapInfoFinlization.cpp pass to alter the map type for descriptors to
deal with cases where a variable is marked declare to. Currently, when a
descriptor variable is mapped declare target to the descriptor component
can become attatched, and cannot be updated, this results in issues when
an unusual allocation range is specified (effectively an off-by X
error). The current solution is to map the descriptor always, as we
always require an up-to-date version of this data. However, this also
requires an interlinked PR that adds a more intricate type of mapping of
structures/record types that clang currently implements, to circumvent
the overwriting of the pointer in the descriptor.
3/3 required PRs to enable declare target to mapping, this PR should
pass all tests and provide an all green CI.
Co-authored-by: Raghu Maddhipatla raghu.maddhipatla at amd.com
Commit: ff80de72c4ce5cb5fa2a764e1e1a6097e82fc5f9
https://github.com/llvm/llvm-project/commit/ff80de72c4ce5cb5fa2a764e1e1a6097e82fc5f9
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
M compiler-rt/test/ubsan_minimal/TestCases/test-darwin-interface.c
Log Message:
-----------
Reapply "[UBSan] [compiler-rt] add preservecc variants of handlers" (#168973) (#169091)
This reverts commit 418204d9c108351340fe21194ace0e31157b7189.
Commit: 51d93e73975e5fc70008c286aaae2216fde097b6
https://github.com/llvm/llvm-project/commit/51d93e73975e5fc70008c286aaae2216fde097b6
Author: Danila Malyutin <danilaml at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/ADT/StringTable.h
Log Message:
-----------
[ADT] Fix implicit reliance on cassert in StringTable.h (#169324)
Adds an explicit include of `<cassert>` in StringTable.h rather than
relying on the one in StringRef.h. Fixes potential compile errors if
assert() was undef'ed between StringRef.h and StringTable.h inclusion.
Commit: f581d8ad8f0cd08da6465c6843f9c6841d49e522
https://github.com/llvm/llvm-project/commit/f581d8ad8f0cd08da6465c6843f9c6841d49e522
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
AMDGPU: Fix a comment (#169403)
This verifier check will complain if there aren't enough implicit
operands -- so it doesn't *allow* those operands, it *requires* them.
Commit: 3e86f056217afbe46cd515b3d3c2f1dc7664bebf
https://github.com/llvm/llvm-project/commit/3e86f056217afbe46cd515b3d3c2f1dc7664bebf
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/include/flang/Lower/Support/ReductionProcessor.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Optimizer/OpenMP/MarkDeclareTarget.cpp
A flang/test/Lower/OpenMP/Todo/omp-declare-reduction-advanced-types.f90
R flang/test/Lower/OpenMP/Todo/omp-declare-reduction-initsub.f90
R flang/test/Lower/OpenMP/Todo/omp-declare-reduction.f90
A flang/test/Lower/OpenMP/declare-target-deferred-marking-reductions.f90
A flang/test/Lower/OpenMP/omp-declare-reduction-derivedtype.f90
A flang/test/Lower/OpenMP/omp-declare-reduction-initsub.f90
A flang/test/Lower/OpenMP/omp-declare-reduction.f90
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A offload/test/offloading/fortran/target-custom-reduction-derivedtype.f90
Log Message:
-----------
[OpenMP][flang] Lowering of OpenMP custom reductions to MLIR (#168417)
This patch add support for lowering of custom reductions to MLIR. It
also enhances the capability of the pass to automatically mark functions
as "declare target" by traversing custom reduction initializers and
combiners.
Commit: 01a98b383c700c2580e11a166dce1180188cb236
https://github.com/llvm/llvm-project/commit/01a98b383c700c2580e11a166dce1180188cb236
Author: Martin Storsjö <martin at martin.st>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/test/std/input.output/file.streams/c.files/gets-removed.verify.cpp
Log Message:
-----------
[libcxx] [test] Fix the gets-removed.verify.cpp test with Clang 21 (#169235)
This fixes test errors like this, at least for a mingw target, if
building with Clang 21 instead of Clang 20, as in the CI environment:
# .---command stderr------------
# | error: 'expected-error' diagnostics seen but not expected:
# | File C:\a\llvm-mingw\llvm-mingw\llvm-project\libcxx\test\std\input.output\file.streams\c.files\gets-removed.verify.cpp Line 16: cannot initialize a parameter of type 'char *' with an lvalue of type 'const char *'
# | 1 error generated.
# `-----------------------------
# error: command failed with exit status: 1
This extra, unexpected diagnostic appears in Clang 21, since commit
9eef4d1c5fa6b1bcbbe675c14ca8301d5d346f7b ("Remove delayed typo
expressions"). Before this, we got the expected diagnostic `error: no
member named 'gets' in namespace 'std'`, with the typo correction hint
`did you mean 'puts'?`. After this change, we get the typo correction
hint `did you mean simply 'gets'?` instead. And with the typo correction
finding `::gets`, it goes on to produce a second diagnostic about
mismatched parameter for that function.
Avoid these unexpected diagnostics by passing the right type of
parameter to the gets function.
Commit: 89206de09c698f0f2e9ba106ebf3b67953041d2c
https://github.com/llvm/llvm-project/commit/89206de09c698f0f2e9ba106ebf3b67953041d2c
Author: David Peixotto <peix at meta.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M lldb/unittests/Expression/DWARFExpressionTest.cpp
Log Message:
-----------
[lldb] Add mock dwarf delegate for testing dwarf expressions (#168468)
This commit adds a `MockDwarfDelegate` class that can be used to control
what dwarf version is used when evaluating an expression. We also add a
simple test that shows how dwarf version can change the result of the
expression.
Commit: 3dcdb4c7658fb955d61fde5bd5232bdeadfc7eeb
https://github.com/llvm/llvm-project/commit/3dcdb4c7658fb955d61fde5bd5232bdeadfc7eeb
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__config
R libcxx/include/__memory/aligned_alloc.h
M libcxx/include/module.modulemap.in
A libcxx/src/include/aligned_alloc.h
M libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
M libcxxabi/src/fallback_malloc.cpp
M libcxxabi/src/stdlib_new_delete.cpp
Log Message:
-----------
[libc++][NFC] Move __memory/aligned_alloc.h into src/ (#166172)
This header is only ever used inside `src/`, so we might as well move it
there. As a drive-by this also removes some dead code.
Commit: 8a431db0045b33ad9a7e4d4d89f5691ffc897088
https://github.com/llvm/llvm-project/commit/8a431db0045b33ad9a7e4d4d89f5691ffc897088
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 3dcdb4c7658f
Commit: e737f67fcf883e90683e1dd46247bd176fe15b5f
https://github.com/llvm/llvm-project/commit/e737f67fcf883e90683e1dd46247bd176fe15b5f
Author: Yu Hao <yuhaoyu at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/Tooling/Transformer/RangeSelector.cpp
M clang/unittests/Tooling/RangeSelectorTest.cpp
Log Message:
-----------
[clang][transformer] Fix `node` range-selector to include type name qualifiers of type locs. (#167619)
Previously, e.g. for TypeLoc "MyNamespace::MyClass", `node()` selects
only "MyClass" without the qualifier. With this change, it now selects
"MyNamespace::MyClass".
---------
Co-authored-by: Florian Mayer <fmayer at google.com>
Commit: 1e1974a903c505de1f42257044b7a03a390d7a8b
https://github.com/llvm/llvm-project/commit/1e1974a903c505de1f42257044b7a03a390d7a8b
Author: Martin Storsjö <martin at martin.st>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M compiler-rt/test/lit.common.cfg.py
Log Message:
-----------
[compiler-rt] [test] Avoid error printouts if os.sysconf is missing (#168857)
This avoids dozens of instances of benign error messages being printed
when running the tests on e.g. Windows:
Traceback (most recent call last):
File "<stdin>", line 1, in <module>
AttributeError: module 'os' has no attribute 'sysconf'
Co-authored-by: Florian Mayer <fmayer at google.com>
Commit: adf4c1dbb62600747fc74843efcdca5c3ee9c26a
https://github.com/llvm/llvm-project/commit/adf4c1dbb62600747fc74843efcdca5c3ee9c26a
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel][clang] Port dea330b38d9c18b68219abdb52baaa72c9f1103d (#169410)
Commit: ba98668dcacc6d6b223f8a53b3c52a7cea2063e8
https://github.com/llvm/llvm-project/commit/ba98668dcacc6d6b223f8a53b3c52a7cea2063e8
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/test/Lower/identical-block-merge-disable.f90
M flang/test/Lower/implicit-interface.f90
M flang/test/Lower/inline_directive.f90
M flang/test/Lower/io-statement-1.f90
M flang/test/Lower/io-write.f90
M flang/test/Lower/location.f90
M flang/test/Lower/module_definition.f90
M flang/test/Lower/module_use.f90
M flang/test/Lower/module_use_in_same_file.f90
M flang/test/Lower/namelist-common-block.f90
M flang/test/Lower/nested-where.f90
M flang/test/Lower/nullify-polymorphic.f90
M flang/test/Lower/pointer-association-polymorphic.f90
M flang/test/Lower/pointer-disassociate.f90
M flang/test/Lower/polymorphic-temp.f90
M flang/test/Lower/polymorphic-types.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/procedure-declarations.f90
M flang/test/Lower/read-write-buffer.f90
M flang/test/Lower/select-type.f90
M flang/test/Lower/statement-function.f90
M flang/test/Lower/variable.f90
M flang/test/Lower/volatile-allocatable.f90
M flang/test/Lower/volatile-openmp1.f90
Log Message:
-----------
[flang][NFC] Strip trailing whitespace from tests (8 of N)
Only some fortran source files in flang/test/Lower have been modified.
The other files in the directory will be cleaned up in subsequent commits
Commit: 4650f8521d85a4dea310b47bd7edce9e0b73ecf0
https://github.com/llvm/llvm-project/commit/4650f8521d85a4dea310b47bd7edce9e0b73ecf0
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/test/Dialect/MemRef/canonicalize.mlir
Log Message:
-----------
[MemRef] Remove memref.dim OffsetSizeAndStrideOpInterface folding (#169327)
OffsetSizeAndStrideOpInterface does not specify whether it's operating
on the input or output shape and in fact different ops implement this in
different ways, which is also why SubviewOp is special cased here.
This "marked as dynamic but not really dynamic" folding is better
handled by shape inference, so just remove the bad fold.
Commit: 590bb3e8e63af0fb46eadf510761bd00e264c018
https://github.com/llvm/llvm-project/commit/590bb3e8e63af0fb46eadf510761bd00e264c018
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
[AArch64] Improve host feature detection. (#160410)
SVE depends on a combination of host support and operating system
support. Sometimes those don't line up with detected host CPU name; make
sure SVE is disabled when it isn't available. Implement this for both
Windows and Linux. (We don't have a codepath for other operating
systems. If someone wants to implement this, it should be possible to
adapt fmv code from compiler-rt.)
While I'm here, also add support for detecting other Windows CPU
features.
For Windows, declare constants ourselves so the code builds on older
SDKs; we also do this in compiler-rt.
Commit: a50824926c07bc42e3d9a9e39de19cc7c71714a5
https://github.com/llvm/llvm-project/commit/a50824926c07bc42e3d9a9e39de19cc7c71714a5
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/SanitizerArgs.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/SanitizerArgs.cpp
M clang/test/Driver/fsanitize.c
Log Message:
-----------
[UBsan] add -fsanitize-handler-preserve-all-regs flag (#168644)
This is currently a no op.
This will be supported for the minimal runtime in a follow up. This
allows
to improve codegen for fsanitize-recover by compiling the handlers with
[[clang::preserve_all]]. This makes sure that the caller does not need
to spill any registers. We do not expect this function to be called
frequently, so this is beneficial for code size.
Commit: ab5ae9a61febab0c76430acc061336b3b8fffe52
https://github.com/llvm/llvm-project/commit/ab5ae9a61febab0c76430acc061336b3b8fffe52
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/module/cooperative_groups.f90
Log Message:
-----------
[flang][cuda] Implement this_cluster for cooperative groups (#169414)
Implement `this_cluster` like `this_group` by lowering it directly like
an intrinsic function. Use the NVVM operation to get the rank and size
information and populate the derived type.
Commit: 4e7ce57e0e2ea04ab04c45127e6862a710460ebd
https://github.com/llvm/llvm-project/commit/4e7ce57e0e2ea04ab04c45127e6862a710460ebd
Author: Yury Plyakhin <yury.plyakhin at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h
M llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
Log Message:
-----------
[Offload][NFC] Offload wrapper cleanup/refactoring (#169411)
Addresses feedback from
https://github.com/llvm/llvm-project/pull/147508#pullrequestreview-3272708203
:
- Update access modifiers for SYCLWrapper members.
- Update comments.
- Update types.
Commit: 9cff3f51d35c4273a48b987bdeddd10248ecb5e4
https://github.com/llvm/llvm-project/commit/9cff3f51d35c4273a48b987bdeddd10248ecb5e4
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Semantics/OpenMP/compiler-directives-loop.f90
M flang/test/Semantics/OpenMP/loop-association.f90
Log Message:
-----------
[flang][OpenMP] Tolerate compiler directives in loop constructs (#169346)
PR168884 flagged compiler directives (!dir$ ...) inside OpenMP loop
constructs as errors. This caused some customer applications to fail to
compile (issue 169229).
Downgrade the error to a warning, and gracefully ignore compiler
directives when lowering loop constructs to MLIR.
Fixes https://github.com/llvm/llvm-project/issues/169229
Commit: 435dbbacad475b12b6cae0a8296e8a46ea684812
https://github.com/llvm/llvm-project/commit/435dbbacad475b12b6cae0a8296e8a46ea684812
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
A clang/test/CIR/CodeGen/global-array-dtor.cpp
Log Message:
-----------
[CIR] Fix a problem with global array dtor lowering (#169416)
In the LoweringPrepare pass, the handling for global array destructor
lowering was mishandling the insertion point, so that if this code
needed to create a declaration for the __cxa_atexit function, that
declaration was being created in the dtor region, rather than at module
scope. This change fixes that.
Commit: fd94b410ef60ca0a0494c2164d7897b698315443
https://github.com/llvm/llvm-project/commit/fd94b410ef60ca0a0494c2164d7897b698315443
Author: Scott Linder <scott.linder at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCDwarf.h
Log Message:
-----------
[MC] Use a variant to hold MCCFIInstruction state (NFC) (#164720)
AMDGPU requires more complex CFI rules, normally these would be
expressed with .cfi_escape, however this would make the CFI unreadable
and makes it difficult to update registers in CFI instructions (also
something AMDGPU requires).
Authored-by: Emma Pilkington <Emma.Pilkington at amd.com>
Commit: ab2a302f0ee8b31404aa4cc454caee40f46602bd
https://github.com/llvm/llvm-project/commit/ab2a302f0ee8b31404aa4cc454caee40f46602bd
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/module/cooperative_groups.f90
A flang/test/Lower/CUDA/cuda-cluster.cuf
Log Message:
-----------
[flang][cuda] Add support for cluster_dim_blocks in cooperative_groups (#169417)
Commit: 420f62e05cc8c54253f52bb99f9b44ad5b9c4f89
https://github.com/llvm/llvm-project/commit/420f62e05cc8c54253f52bb99f9b44ad5b9c4f89
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
M compiler-rt/lib/scudo/standalone/tests/quarantine_test.cpp
M compiler-rt/lib/scudo/standalone/tests/size_class_map_test.cpp
Log Message:
-----------
[scudo] Only print stats when the test fails. (#168000)
When running the tests on other platforms, printing the stats on all of
the passing tests makes it hard to see failure output. Therefore, this
change only prints the stats if the test actually fails.
Commit: d9cf0db2a26245394a1722f688f520e745358373
https://github.com/llvm/llvm-project/commit/d9cf0db2a26245394a1722f688f520e745358373
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/src/new.cpp
Log Message:
-----------
Fix path to aligned_alloc.h in #include statement (#169418)
This fixes #166172.
Commit: 73de1e26b4500f4ffd97c52922b0d45308d54f6d
https://github.com/llvm/llvm-project/commit/73de1e26b4500f4ffd97c52922b0d45308d54f6d
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
Log Message:
-----------
Orc fix waitingongraph coalescer remove (#169287)
Commit: a8a504a08d14b7e855af7616a2663f25508cc184
https://github.com/llvm/llvm-project/commit/a8a504a08d14b7e855af7616a2663f25508cc184
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
Log Message:
-----------
RuntimeLibcalls: Add definitions for vector math functions (#167026)
This is mostly the output of a vibe coded script running on
VecFuncs.def, with a lot of manual cleanups and fixing where the
vibes were off. This is not yet wired up to anything (except for the
handful of calls which are already manually enabled). In the future
the SystemLibrary mechanism needs to be generalized to allow plugging
these sets in based on the flag.
One annoying piece is there are some name conflicts across the
libraries. Some of the libmvec functions have name collisions with some
sleef functions. I solved this by just adding a prefix to the libmvec functions.
It would probably be a good idea to add a prefix to every group. It gets ugly,
particularly since some of the sleef functions started to use a Sleef_
prefix, but mostly do not.
Commit: 25dee656c7d2a3ba90cf4d243c047ea14616e91a
https://github.com/llvm/llvm-project/commit/25dee656c7d2a3ba90cf4d243c047ea14616e91a
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets.cpp
A clang/test/Misc/opencl-c-3.0.incorrect_define.cl
Log Message:
-----------
[OpenCL] Disable __opencl_c_ext_fp64_* features if cl_khr_fp64 is not supported (#169252)
Fix kernel build when cl_khr_fp64 is not enabled:
opencl-c.h:13785:50: error: unknown type name 'atomic_double'
13785 | double __ovld atomic_fetch_min(volatile __global atomic_double
*, double);
opencl-c.h:13785:67: error: use of type 'double' requires cl_khr_fp64
and __opencl_c_fp64 support
13785 | double __ovld atomic_fetch_min(volatile __global atomic_double
*, double);
This is a regression introduced by 423bdb2b. Before that commit,
__opencl_c_ext_fp64_global_atomic_add was guarded by cl_khr_fp64 in
opencl-c-base.h.
Commit: 8947ba017fd8968292e7541a1bbfb82863e54041
https://github.com/llvm/llvm-project/commit/8947ba017fd8968292e7541a1bbfb82863e54041
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A libclc/clc/include/clc/atomic/clc_atomic_flag_clear.h
A libclc/clc/include/clc/atomic/clc_atomic_flag_test_and_set.h
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/atomic/clc_atomic_flag_clear.cl
A libclc/clc/lib/generic/atomic/clc_atomic_flag_test_and_set.cl
A libclc/opencl/include/clc/opencl/atomic/atomic_flag_clear.h
A libclc/opencl/include/clc/opencl/atomic/atomic_flag_test_and_set.h
A libclc/opencl/include/clc/opencl/atomic/atomic_init.h
A libclc/opencl/include/clc/opencl/atomic/atomic_init.inc
A libclc/opencl/include/clc/opencl/types.h
A libclc/opencl/include/clc/opencl/utils.h
M libclc/opencl/lib/generic/SOURCES
A libclc/opencl/lib/generic/atomic/atomic_flag_clear.cl
A libclc/opencl/lib/generic/atomic/atomic_flag_test_and_set.cl
A libclc/opencl/lib/generic/atomic/atomic_init.cl
A libclc/opencl/lib/generic/atomic/atomic_init.inc
Log Message:
-----------
[libclc] Add atomic_init, atomic_flag_clear and atomic_flag_test_and_set (#168329)
Commit: 81e91ea1c52a77093a44a186958cca29cf4d3dd8
https://github.com/llvm/llvm-project/commit/81e91ea1c52a77093a44a186958cca29cf4d3dd8
Author: Chengjun <chengjunp at Nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/NVPTX/bswap.ll
Log Message:
-----------
[NVPTX] Use PRMT instruction to lower i16 bswap (#168968)
Previously, i16 `bswap` was lowered using multiple shift and OR
operations. This patch adds a pattern to directly lower i16 `bswap`
using the `PRMT` (permute) instruction, which is more efficient.
Additionally, the lowering of `bswap` is moved into operation
legalization, which allows for DAGCombiner to optimize the lowered code.
Commit: ac4cf404d8f39e316f37c3732ab75be729604107
https://github.com/llvm/llvm-project/commit/ac4cf404d8f39e316f37c3732ab75be729604107
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/extensions.bzl
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
A utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
A utils/bazel/llvm-project-overlay/third-party/cc_library_wrapper.bzl
M utils/bazel/third_party_build/zstd.BUILD
Log Message:
-----------
[bazel] Use zstd from the BCR (#169146)
This way if the downstream consuming project uses zstd we make sure
they are dedup'd. This uses a new rule to make sure layering_check still
works while allowing us to augment the upstream library rules with LLVM
specific `defines`.
Commit: e23328b45719683c76deae7fab9a24523bf25520
https://github.com/llvm/llvm-project/commit/e23328b45719683c76deae7fab9a24523bf25520
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/module/cooperative_groups.f90
M flang/test/Lower/CUDA/cuda-cluster.cuf
Log Message:
-----------
[flang][cuda] Add support for cluster_block_index in cooperative groups (#169427)
Commit: 1b8626b5064fc58caa8dfd268b8b854f9f1b8543
https://github.com/llvm/llvm-project/commit/1b8626b5064fc58caa8dfd268b8b854f9f1b8543
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/docs/HIPSupport.rst
Log Message:
-----------
Improve HIP docs on fat binary registration ordering (#168566)
Clarify how Clang-generated HIP fat binaries are registered and
unregistered with the HIP runtime, and how this interacts with global
constructors, destructors, and atexit handlers. Document that there is
no strong guarantee on ordering relative to user-defined global
ctors/dtors, recommend that HIP application developers avoid using
kernels or device variables from global ctors/dtors, and describe the
implications for HIP runtime developers (synchronization and guards in
__hipRegisterFatBinary/__hipUnregisterFatBinary). This is motivated by
questions from HIP application and runtime developers about fat binary
registration/unregistration order and its potential interference with
their own initialization and teardown code.
Commit: 2f8e71287542a597be246d34699c93345d096f22
https://github.com/llvm/llvm-project/commit/2f8e71287542a597be246d34699c93345d096f22
Author: Abhinav Gaba <abhinav.gaba at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
A offload/test/mapping/use_device_addr/target_data_use_device_addr_arrsec_fallback.c
A offload/test/mapping/use_device_addr/target_data_use_device_addr_var_fallback.c
A offload/test/mapping/use_device_ptr/target_data_use_device_ptr_var_fallback.c
Log Message:
-----------
[NFC][OpenMP] Add use_device_ptr/addr tests for when the lookup fails. (#169428)
As per OpenMP 5.1, the pointers are expected to retain their original
values when a lookup fails and there is no device pointer to translate
to.
Commit: 78994706d87e617e8063dfb73a585c8f7c7e738c
https://github.com/llvm/llvm-project/commit/78994706d87e617e8063dfb73a585c8f7c7e738c
Author: Matthias Springer <me at m-sp.org>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Conversion/ArithToAPFloat/ArithToAPFloat.cpp
M mlir/lib/ExecutionEngine/APFloatWrappers.cpp
M mlir/test/Conversion/ArithToApfloat/arith-to-apfloat.mlir
M mlir/test/Integration/Dialect/Arith/CPU/test-apfloat-emulation.mlir
Log Message:
-----------
[mlir][arith] Add support for `extf`, `truncf` to `ArithToAPFloat` (#169275)
Add support for `arith.extf` and `arith.truncf`. No support for custom
rounding modes yet.
Commit: e6f2fbb0fa6b519643916e11552c88d680958ede
https://github.com/llvm/llvm-project/commit/e6f2fbb0fa6b519643916e11552c88d680958ede
Author: Ryan Mast <3969255+nightlark at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M .gitattributes
A clang/bindings/python/.git_archival.txt
A clang/bindings/python/.gitignore
A clang/bindings/python/pyproject.toml
Log Message:
-----------
[libclang/python] Enable packaging clang python bindings (#125806)
This adds a pyproject.toml file for packaging the clang Python bindings
as a sdist tarball and pure Python wheel packages for the clang python
bindings. It is required to move updates of the clang and libclang PyPI
packages to the LLVM monorepo. Versioning information is derived from
LLVM git tags (using hatch-vcs, which is based on setuptools_scm), so no
manual updates are needed to bump version numbers. The minimum python
version required is set to 3.10 due to cindex.py using PEP 604 union
type syntax (str | bytes | None).
The .git_archival.txt file is populated with version information needed
to get accurate version information if the bindings are installed from
an LLVM/clang source code archive. The .gitignore file is populated with
files that may get created as part of building/testing the sdist and
wheel that should not be committed to source control.
This is first step for addressing #125220, and moving publishing of the
clang and libclang PyPI packages into the LLVM monorepo.
Signed-off-by: Ryan Mast <mast.ryan at gmail.com>
Commit: 1782d27e67b9cde01a3722a1380ae3558da64452
https://github.com/llvm/llvm-project/commit/1782d27e67b9cde01a3722a1380ae3558da64452
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchSelectionDAGInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchSelectionDAGInfo.h
Log Message:
-----------
[LoongArch] Fix for `VLDREPL` node validation (#168993)
Commit: 196f6de75a0fe6c66e58a9bbd90b30f7c4a69bde
https://github.com/llvm/llvm-project/commit/196f6de75a0fe6c66e58a9bbd90b30f7c4a69bde
Author: Mend Renovate <bot at renovateapp.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M .github/workflows/bazel-checks.yml
M .github/workflows/build-ci-container-tooling.yml
M .github/workflows/build-ci-container-windows.yml
M .github/workflows/build-ci-container.yml
M .github/workflows/build-metrics-container.yml
M .github/workflows/check-ci.yml
M .github/workflows/ci-post-commit-analyzer.yml
M .github/workflows/commit-access-greeter.yml
M .github/workflows/commit-access-review.yml
M .github/workflows/docs.yml
M .github/workflows/email-check.yaml
M .github/workflows/gha-codeql.yml
M .github/workflows/hlsl-test-all.yaml
M .github/workflows/issue-release-workflow.yml
M .github/workflows/issue-subscriber.yml
M .github/workflows/issue-write.yml
M .github/workflows/libc-fullbuild-tests.yml
M .github/workflows/libc-overlay-tests.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/libclang-python-tests.yml
M .github/workflows/libcxx-build-and-test.yaml
M .github/workflows/libcxx-build-containers.yml
M .github/workflows/libcxx-check-generated-files.yml
M .github/workflows/libcxx-run-benchmarks.yml
M .github/workflows/llvm-abi-tests.yml
M .github/workflows/merged-prs.yml
M .github/workflows/mlir-spirv-tests.yml
M .github/workflows/new-prs.yml
M .github/workflows/pr-code-format.yml
M .github/workflows/pr-code-lint.yml
M .github/workflows/pr-request-release-note.yml
M .github/workflows/pr-subscriber.yml
M .github/workflows/premerge.yaml
M .github/workflows/release-asset-audit.yml
M .github/workflows/release-binaries.yml
M .github/workflows/release-documentation.yml
M .github/workflows/release-doxygen.yml
M .github/workflows/release-lit.yml
M .github/workflows/release-sources.yml
M .github/workflows/release-tasks.yml
M .github/workflows/scorecard.yml
M .github/workflows/spirv-tests.yml
M .github/workflows/test-unprivileged-download-artifact.yml
M .github/workflows/version-check.yml
Log Message:
-----------
Update actions/checkout action to v6 (#169258)
This PR contains the following updates:
| Package | Type | Update | Change |
|---|---|---|---|
| [actions/checkout](https://redirect.github.com/actions/checkout) |
action | major | `v5.0.0` -> `v6.0.0` |
Commit: 3db8ed05004d4a1f2fb7cb34813c5e44a2e6722a
https://github.com/llvm/llvm-project/commit/3db8ed05004d4a1f2fb7cb34813c5e44a2e6722a
Author: Matthias Springer <me at m-sp.org>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Conversion/ArithToAPFloat/ArithToAPFloat.cpp
M mlir/lib/ExecutionEngine/APFloatWrappers.cpp
M mlir/test/Conversion/ArithToApfloat/arith-to-apfloat.mlir
M mlir/test/Integration/Dialect/Arith/CPU/test-apfloat-emulation.mlir
Log Message:
-----------
[mlir][arith] Add support for `fptosi`, `fptoui` to `ArithToAPFloat` (#169277)
Add support for `arith.fptosi` and `arith.fptoui`.
Commit: d7f630139023d3d13d38f0bc42536b67f1f5e38f
https://github.com/llvm/llvm-project/commit/d7f630139023d3d13d38f0bc42536b67f1f5e38f
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/string
M libcxx/test/libcxx/diagnostics/string.nodiscard.verify.cpp
Log Message:
-----------
[libc++][string] Applied `[[nodiscard]]` to non-member functions (#169330)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: b63a1883c153245837933e646bdf6c2b4a7bb36b
https://github.com/llvm/llvm-project/commit/b63a1883c153245837933e646bdf6c2b4a7bb36b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Use a switch in VSETVLIInfo::print(). NFC (#169441)
This allows the compiler to verify we've covered all enum values.
Commit: 8217c6415ab76c2a0f06705100c76207cd1e6bc0
https://github.com/llvm/llvm-project/commit/8217c6415ab76c2a0f06705100c76207cd1e6bc0
Author: Kewen Meng <Kewen.Meng at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCDwarf.h
Log Message:
-----------
Revert "[MC] Use a variant to hold MCCFIInstruction state (NFC)" (#169442)
Reverts llvm/llvm-project#164720
Revert to unblock bots.
https://lab.llvm.org/buildbot/#/builders/140/builds/34645
Commit: 6ec686735c850d05592b28783f8300c725a50d78
https://github.com/llvm/llvm-project/commit/6ec686735c850d05592b28783f8300c725a50d78
Author: Matthias Springer <me at m-sp.org>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Conversion/ArithToAPFloat/ArithToAPFloat.cpp
M mlir/lib/ExecutionEngine/APFloatWrappers.cpp
M mlir/test/Conversion/ArithToApfloat/arith-to-apfloat.mlir
M mlir/test/Integration/Dialect/Arith/CPU/test-apfloat-emulation.mlir
Log Message:
-----------
[mlir][arith] Add support for `sitofp`, `uitofp` to `ArithToAPFloat` (#169284)
Add support for `arith.sitofp` and `arith.uitofp`.
Commit: 31d4150fd476f204d3f2a8e2d656a668158a70d8
https://github.com/llvm/llvm-project/commit/31d4150fd476f204d3f2a8e2d656a668158a70d8
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
A llvm/test/TableGen/ValueTypeByHwModeMissingRegInfo.td
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Log Message:
-----------
[TableGen] Change a reachable assert to a fatal error
I hit this when using a RegisterClass with a ValueTypeByHwMode that
was missing the RegInfos field. Add a test for this error.
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/169439
Commit: f0bb5cfda7c54f3fa0c1ef0bbe82e3405ed80110
https://github.com/llvm/llvm-project/commit/f0bb5cfda7c54f3fa0c1ef0bbe82e3405ed80110
Author: Erik Enikeev <evonatarius at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsInstrFPU.td
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
A llvm/test/CodeGen/Mips/fp-intrinsics.ll
Log Message:
-----------
[Mips] Add instruction selection for strict FP (#168870)
This consists of marking the various strict opcodes as legal, and
adjusting instruction selection patterns so that 'op' is 'any_op'. The
changes are similar to those in D114946 for AArch64 and #160696 for ARM.
Only Mips32/64 FPU instructions are affected.
Added lowering for for STRICT_FP_TO_UINT and STRICT_FP_TO_SINT ops.
Commit: c6f433e880a01a29325f4d7d2b98c84feecf2297
https://github.com/llvm/llvm-project/commit/c6f433e880a01a29325f4d7d2b98c84feecf2297
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel][libc] Remove target compatibility restrictions for float128 (#169292)
The restrictions here aren't nearly as much about the OS as the compiler
and architecture, but the Bazel restriction was OS-based. Everything
seems to work well on even Arm64 macOS, and I would expect most BSDs and
other OSes to work well with Clang's support on x86-64.
The source code here already handles detecting when there is compiler
support for the type. And the users of this don't `select` or do
anything else to conditionally include the header, so it seems better to
not restrict access to the header from the build system, and instead
continue making the source code compatible or a no-op on relevant
configurations.
Commit: 26362c68579dd4375198aae4651b4d5f8a36c715
https://github.com/llvm/llvm-project/commit/26362c68579dd4375198aae4651b4d5f8a36c715
Author: Petr Penzin <ppenzin at tenstorrent.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add segmented tunes to tt-ascalon-d8 (#168800)
Add TuneOptimizedNFnSegmentedLoadStore tune flags to tt-ascalon-d8
processor definition.
Commit: b1111356e697a7f5c436846f97adf18a353766dc
https://github.com/llvm/llvm-project/commit/b1111356e697a7f5c436846f97adf18a353766dc
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
Log Message:
-----------
[AMDGPU] Pre-commit test for #169213 (NFC)
Commit: 9626c90c335cca55c1a8094f2e802c4139c7173d
https://github.com/llvm/llvm-project/commit/9626c90c335cca55c1a8094f2e802c4139c7173d
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/extensions.bzl
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
M utils/bazel/third_party_build/zlib-ng.BUILD
Log Message:
-----------
[bazel] Use zlib-ng from the BCR (#169450)
This way if a downstream project also uses this, it is dedup'd
Commit: 9c2d5e29947c0ccf5eaef2c11b4533a62bad1f67
https://github.com/llvm/llvm-project/commit/9c2d5e29947c0ccf5eaef2c11b4533a62bad1f67
Author: Erik Enikeev <evonatarius at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
A llvm/test/CodeGen/Mips/fp-strict-fcmp.ll
Log Message:
-----------
[Mips] Set custom lowering for STRICT_FSETCC/STRICT_FSETCCS ops. (#168303)
Commit: 28fde68501032b292f91246c0e79872558d0e74b
https://github.com/llvm/llvm-project/commit/28fde68501032b292f91246c0e79872558d0e74b
Author: Pranav Bhandarkar <pranav.bhandarkar at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
A flang/test/Semantics/OpenMP/target-teams-nesting.f90
Log Message:
-----------
[Flang] - Enhance testing for strictly-nested teams in target regions. (#168437)
This patch enhances the semantics test for checking that teams
directives are strictly nested inside target directives.
Fixes https://github.com/llvm/llvm-project/issues/153173
Commit: 488ed96d665f47d5c31b811288ec1be1b3fa01bc
https://github.com/llvm/llvm-project/commit/488ed96d665f47d5c31b811288ec1be1b3fa01bc
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M orc-rt/unittests/SessionTest.cpp
Log Message:
-----------
[orc-rt] Remove stray debugging output. NFCI. (#169451)
Commit: c25e0d3e2942007919e5a7a0738bea86907bcdb4
https://github.com/llvm/llvm-project/commit/c25e0d3e2942007919e5a7a0738bea86907bcdb4
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/mul-simplification.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-cond-poison.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
Log Message:
-----------
[VPlan] Simplify x + 0 -> x (#169394)
Commit: 675dc35d808d94011f52e650fe1e3218254b5041
https://github.com/llvm/llvm-project/commit/675dc35d808d94011f52e650fe1e3218254b5041
Author: Mend Renovate <bot at renovateapp.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M .github/workflows/gha-codeql.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/llvm-abi-tests.yml
M .github/workflows/scorecard.yml
Log Message:
-----------
Update [Github] Update GHA Dependencies (#169257)
This PR contains the following updates:
| Package | Type | Update | Change | Pending |
|---|---|---|---|---|
| ghcr.io/llvm/ci-ubuntu-24.04-abi-tests | container | digest |
`f80125c` -> `9138b6a` | |
|
[github/codeql-action](https://redirect.github.com/github/codeql-action)
| action | patch | `v4.31.3` -> `v4.31.4` | `v4.31.5` |
---
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##### CodeQL Action Changelog
See the [releases
page](https://redirect.github.com/github/codeql-action/releases) for the
relevant changes to the CodeQL CLI and language packs.
##### 4.31.4 - 18 Nov 2025
No user facing changes.
See the full
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for more information.
</details>
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Commit: 44a7d2f22aec6ac2019a3674e1390276c2ee7ca5
https://github.com/llvm/llvm-project/commit/44a7d2f22aec6ac2019a3674e1390276c2ee7ca5
Author: David Green <david.green at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/test/CodeGen/AArch64/combine-sdiv.ll
M llvm/test/CodeGen/AArch64/rem-by-const.ll
M llvm/test/CodeGen/AArch64/srem-lkk.ll
Log Message:
-----------
[AArch64] Add patterns for add(x, trunc(shift)) (#168927)
This can be lowered to a 64bit add where we only use the bottom 32bits
of the result. It is conceptually the same as
https://alive2.llvm.org/ce/z/Xfz3Rf, but with the sext replaced by an
anyext.
Commit: 1d64fd5d42671d15ed8cd0fc31f71a4ad1e791b6
https://github.com/llvm/llvm-project/commit/1d64fd5d42671d15ed8cd0fc31f71a4ad1e791b6
Author: David Green <david.green at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Basic/arm_mve_defs.td
M clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
M clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
M clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
M clang/utils/TableGen/MveEmitter.cpp
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
A llvm/test/CodeGen/Thumb2/mve-intrinsics/strict-intrinsics.ll
M llvm/test/CodeGen/Thumb2/mve-intrinsics/vabdq.ll
M llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
Log Message:
-----------
[ARM] Introduce intrinsics for MVE add/sub/mul under strict-fp. (#169156)
As far as I understand, the MVE fp vadd/vsub/vmul instructions will set
exception flags in the same ways as scalar fadd/fsub/fmul, but will not
honor flush-to-zero (for f32 they always flush, for f16 they follows the
fpsrc flags) and will always use the default rounding mode.
This means that we cannot convert the vadd_f23/vsub_f32/vmul_f32
intrinsics to llvm.constrained.fadd/fsub/fmul and then vadd/vsub/vmul
without changing the expected behaviour under strict-fp. This patch
introduces a set in intrinsics that we can use instead, going from
vadd_f32 -> llvm.arm.mve.vadd -> MVE_VADD.
The current implementations assumes that the standard variant of a
strictfp alternative will be a IRBuilder, this can be changed to take a
IRBuilder or IRInt.
Commit: 30c49a40222a8e2f90565370ab20253c1e426383
https://github.com/llvm/llvm-project/commit/30c49a40222a8e2f90565370ab20253c1e426383
Author: Men-cotton <mencotton0410 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
A mlir/test/Target/LLVMIR/anonymous-tbaa.mlir
Log Message:
-----------
[mlir][LLVMIR] Handle anonymous TBAA roots during metadata emission (#169167)
This commit enhances MLIR's TBAA export with support for anonymous TBAA roots. The import for this was around for a bit but the export was missing.
Fixes: #160721
Commit: 5490bcf4aa3c028e5c2cdbcd0d906e5a876d23bc
https://github.com/llvm/llvm-project/commit/5490bcf4aa3c028e5c2cdbcd0d906e5a876d23bc
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
Log Message:
-----------
[BOLT] Add missing new line. NFC
Commit: f817a1b0394b7f722b4bb13e9aeead5e177ff6d7
https://github.com/llvm/llvm-project/commit/f817a1b0394b7f722b4bb13e9aeead5e177ff6d7
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Optimizer/Builder/Runtime/Reduction.cpp
M lldb/include/lldb/API/SBStructuredData.h
M mlir/include/mlir/Analysis/DataFlow/IntegerRangeAnalysis.h
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
Log Message:
-----------
[NFC] Fix typo of `integer` (#169325)
Commit: a39af125dba2c07f100236d210b6a948b7316acb
https://github.com/llvm/llvm-project/commit/a39af125dba2c07f100236d210b6a948b7316acb
Author: Dharuni R Acharya <125176188+DharuniRAcharya at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
M llvm/lib/IR/CMakeLists.txt
A llvm/lib/IR/NVVMIntrinsicUtils.cpp
Log Message:
-----------
[NVVM] Move pretty-print functions from NVVMIntrinsicUtils.h to cpp file (#168997)
This patch moves the print functions from `NVVMIntrinsicUtils.h` to
`NVVMIntrinsicUtils.cpp`, a file created in the `llvm/lib/IR` directory.
Signed-off-by: Dharuni R Acharya <dharunira at nvidia.com>
Commit: 6193f2aeda1d5ca30cf990e28956824eefdc97f1
https://github.com/llvm/llvm-project/commit/6193f2aeda1d5ca30cf990e28956824eefdc97f1
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
Log Message:
-----------
[AArch64] Assert `expandMOVImm` prioritizes optimal single MOVZ/N (#169341)
The expansion of move immediate in `expandMOVImm` follows the priority
of the `MOV` alias. In addition, the selection there properly prefers
expansion based on perf optimality order. This change adds a simple
assert that `expandMOVImmSimple` expands a single optimal MOVZ/MOVK.
Commit: ed95c4d6ecf0a8e842cb9d91c09d9679c1f3bf79
https://github.com/llvm/llvm-project/commit/ed95c4d6ecf0a8e842cb9d91c09d9679c1f3bf79
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
Log Message:
-----------
[BOLT][BTI] Add MCPlusBuilder::createBTI (#167305)
- creates a BTI j|c landing pad MCInst.
- create getBTIHintNum utility in AArch64/Utils, to make sure BOLT
generates BTI immediates the same way as LLVM.
- add MCPlusBuilder unittests to cover new function.
Commit: 2ce363d25226c2d502d19917ca8502115c953599
https://github.com/llvm/llvm-project/commit/2ce363d25226c2d502d19917ca8502115c953599
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
Log Message:
-----------
[gn build] Port a39af125dba2
Commit: eb568d6d0ce1a2b0f26f47e20b0051842a3f9746
https://github.com/llvm/llvm-project/commit/eb568d6d0ce1a2b0f26f47e20b0051842a3f9746
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
M llvm/test/CodeGen/AArch64/sme-zt0-state.ll
Log Message:
-----------
[AArch64][SME] Handle zeroing ZA and ZT0 in functions with ZT0 state (#166361)
In the MachineSMEABIPass, if we have a function with ZT0 state, then
there are some additional cases where we need to zero ZA and ZT0.
If the function has a private ZA interface, i.e., new ZT0 (and new ZA if
present). Then ZT0/ZA must be zeroed when committing the incoming ZA
save.
If the function has a shared ZA interface, e.g. new ZA and shared ZT0.
Then ZA must be zeroed on function entry (without a ZA save commit).
The logic in the ABI pass has been reworked to use an "ENTRY" state to
handle this (rather than the more specific "CALLER_DORMANT" state).
Commit: a086fb2fbbc0f488dd2a2c60d09196ea7218742f
https://github.com/llvm/llvm-project/commit/a086fb2fbbc0f488dd2a2c60d09196ea7218742f
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
A llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/spillv16.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.mir
Log Message:
-----------
[AMDGPU][gfx1250] Add wait_xcnt before any access that cannot be repeated (#168852)
The xcnt wait is actually required before any memory access that can
only be done once, so atomic stores and volatile accesses are affected.
This patch also ensures buffer instructions are handled.
Commit: cf5234bac45567e2431b9e668999d4f6d65b7ac8
https://github.com/llvm/llvm-project/commit/cf5234bac45567e2431b9e668999d4f6d65b7ac8
Author: Jie Fu <jiefu at tencent.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
Log Message:
-----------
[AArch64] Silence a warning (NFC)
/llvm-project/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp:952:12:
error: unused variable 'SMEFnAttrs' [-Werror,-Wunused-variable]
SMEAttrs SMEFnAttrs = AFI->getSMEFnAttrs();
^
1 error generated.
Commit: a11e7347fb9618b981cde12f494f58d55b509e2c
https://github.com/llvm/llvm-project/commit/a11e7347fb9618b981cde12f494f58d55b509e2c
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M .gitignore
Log Message:
-----------
[llvm][nfc] Ignore OpenAI Codex artifacts (#162481)
Follow-up to #153853 to also ignore Codex artifacts [1]. AGENTS.md may
be at the root or in sub-directories, so unlike other Markdown config
files I've not prefixed it with '/'.
[1] https://github.com/openai/codex/blob/main/docs/getting-started.md#memory-with-agentsmd
Commit: 86fbaef99a53c5a0d3d5b96011797215296ec478
https://github.com/llvm/llvm-project/commit/86fbaef99a53c5a0d3d5b96011797215296ec478
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
A cmake/Modules/GetToolchainDirs.cmake
M flang-rt/CMakeLists.txt
M flang-rt/cmake/modules/AddFlangRT.cmake
M flang-rt/cmake/modules/AddFlangRTOffload.cmake
A flang-rt/cmake/modules/FlangRTIntrospection.cmake
R flang-rt/cmake/modules/GetToolchainDirs.cmake
M flang-rt/lib/runtime/CMakeLists.txt
A flang-rt/lib/runtime/__cuda_builtins.f90
A flang-rt/lib/runtime/__cuda_device.f90
A flang-rt/lib/runtime/__fortran_builtins.f90
A flang-rt/lib/runtime/__fortran_ieee_exceptions.f90
A flang-rt/lib/runtime/__fortran_type_info.f90
A flang-rt/lib/runtime/__ppc_intrinsics.f90
A flang-rt/lib/runtime/__ppc_types.f90
A flang-rt/lib/runtime/cooperative_groups.f90
A flang-rt/lib/runtime/cudadevice.f90
A flang-rt/lib/runtime/ieee_arithmetic.f90
A flang-rt/lib/runtime/ieee_exceptions.f90
A flang-rt/lib/runtime/ieee_features.f90
A flang-rt/lib/runtime/iso_c_binding.f90
A flang-rt/lib/runtime/iso_fortran_env.f90
A flang-rt/lib/runtime/iso_fortran_env_impl.f90
A flang-rt/lib/runtime/mma.f90
M flang-rt/test/lit.site.cfg.py.in
M flang-rt/unittests/CMakeLists.txt
M flang/CMakeLists.txt
M flang/include/flang/Frontend/CompilerInvocation.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Semantics/semantics.cpp
R flang/module/.clang-format
R flang/module/__cuda_builtins.f90
R flang/module/__cuda_device.f90
R flang/module/__fortran_builtins.f90
R flang/module/__fortran_ieee_exceptions.f90
R flang/module/__fortran_type_info.f90
R flang/module/__ppc_intrinsics.f90
R flang/module/__ppc_types.f90
R flang/module/cooperative_groups.f90
R flang/module/cudadevice.f90
R flang/module/ieee_arithmetic.f90
R flang/module/ieee_exceptions.f90
R flang/module/ieee_features.f90
R flang/module/iso_c_binding.f90
R flang/module/iso_fortran_env.f90
R flang/module/iso_fortran_env_impl.f90
R flang/module/mma.f90
M flang/test/CMakeLists.txt
M flang/test/Driver/Inputs/ieee_arithmetic.mod
M flang/test/Driver/Inputs/iso_fortran_env.mod
A flang/test/Driver/intrinsic-module-path.F90
R flang/test/Driver/intrinsic-module-path.f90
M flang/test/Driver/lto-fatlto.f90
M flang/test/Driver/pp-fixed-form.f90
M flang/test/Lower/HLFIR/type-bound-call-mismatch.f90
M flang/test/Lower/OpenMP/simd_aarch64.f90
M flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90
M flang/test/Preprocessing/fixed-free.f
M flang/test/Preprocessing/no-pp-if.f90
M flang/test/Semantics/bug163242.f90
M flang/test/Semantics/bug164303.f90
M flang/test/lit.cfg.py
M flang/test/lit.site.cfg.py.in
M flang/tools/CMakeLists.txt
M flang/tools/bbc/bbc.cpp
R flang/tools/f18/CMakeLists.txt
R flang/tools/f18/dump.cpp
M llvm/runtimes/CMakeLists.txt
M openmp/CMakeLists.txt
M openmp/runtime/CMakeLists.txt
R openmp/runtime/cmake/LibompCheckFortranFlag.cmake
M openmp/runtime/cmake/LibompHandleFlags.cmake
M openmp/runtime/cmake/config-ix.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/test/lit.cfg
M openmp/runtime/test/lit.site.cfg.in
M runtimes/CMakeLists.txt
Log Message:
-----------
[Flang] Move builtin .mod generation into runtimes (#137828)
Move building the .mod files from openmp/flang to openmp/flang-rt using
a shared mechanism. Motivations to do so are:
1. Most modules are target-dependent and need to be re-compiled for each
target separately, which is something the LLVM_ENABLE_RUNTIMES system
already does. Prime example is `iso_c_binding.mod` which encodes the
target's ABI. Most other modules have `#ifdef`-enclosed code as well.
2. CMake has support for Fortran that we should use. Among other things,
it automatically determines module dependencies so there is no need to
hardcode them in the CMakeLists.txt.
3. It allows using Fortran itself to implement Flang-RT. Currently, only
`iso_fortran_env_impl.f90` emits object files that are needed by Fortran
applications (#89403). The workaround of #95388 could be reverted.
Some new dependencies come into play:
* openmp depends on flang-rt for building `lib_omp.mod` and
`lib_omp_kinds.mod`. Currently, if flang-rt is not found then the
modules are not built.
* check-flang depends on flang-rt: If not found, the majority of tests
are disabled. If not building in a bootstrpping build, the location of
the module files can be pointed to using
`-DFLANG_INTRINSIC_MODULES_DIR=<path>`, e.g. in a flang-standalone
build. Alternatively, the test needing any of the intrinsic modules
could be marked with `REQUIRES: flangrt-modules`.
* check-flang depends on openmp: Not a change; tests requiring
`lib_omp.mod` and `lib_omp_kinds.mod` those are already marked with
`openmp_runtime`.
As intrinsic are now specific to the target, their location is moved
from `include/flang` to `<resource-dir>/finclude/flang/<triple>`. The
mechnism to compute the location have been moved from flang-rt
(previously used to compute the location of `libflang_rt.*.a`) to common
locations in `cmake/GetToolchainDirs.cmake` and
`runtimes/CMakeLists.txt` so they can be used by both, openmp and
flang-rt. Potentially the mechnism could also be shared by other
libraries such as compiler-rt.
`finclude` was chosen because `gfortran` uses it as well and avoids
misuse such as `#include <flang/iso_c_binding.mod>`. The search location
is now determined by `ToolChain` in the driver, instead of by the
frontend. Now the driver adds `-fintrinsic-module-path` for that
location to the frontend call (Just like gfortran does).
`-fintrinsic-module-path` had to be fixed for this because ironically it
was only added to `searchDirectories`, but not
`intrinsicModuleDirectories_`. Since the driver determines the location,
tests invoking `flang -fc1` and `bbc` must also be passed the location
by llvm-lit. This works like llvm-lit does for finding the include dirs
for Clang using `-print-file-name=...`.
Commit: f287abd53e03bf0fda9099c0845b25a340a20102
https://github.com/llvm/llvm-project/commit/f287abd53e03bf0fda9099c0845b25a340a20102
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bitcnt-big-integer.ll
M llvm/test/TableGen/CPtrWildcard.td
Log Message:
-----------
[DAG][X86] Improve custom i256/i512 AVX512 CTLZ/CTTZ Handling with MVT::i256/i512 (#168860)
This patch proposes to move the AVX512 CTLZ/CTTZ i256/i512 codegen to
ReplaceNodeResults to allow them to be declared as custom lowering -
this allows expansion of larger int types (e.g. i1024) to fallback to
them during their expansion.
However to declare these i256/i512 ops as custom, we need to add
MVT::i256/i512 simple types - I'm intending to add further large integer
handling in the future, some of which will use vector register
instructions, and its going to be much easier if this can be handled
with i128/i256/i512 types that match the vector register sizes.
This exposed a regression in NVPTX due to their use of EVT::isSimple()
to match their upper integer size bounds.
Commit: 5e7631e14ae334a708b6fc52991a12ab3bb95633
https://github.com/llvm/llvm-project/commit/5e7631e14ae334a708b6fc52991a12ab3bb95633
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll
M llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll
Log Message:
-----------
[LoongArch][DAGCombiner] Combine vand (vnot ..) to vandn (#161037)
After this commit, DAGCombiner will have more opportunities to perform
vector folding. This patch includes several foldings, as follows:
- VANDN(x,NOT(y)) -> AND(NOT(x),NOT(y)) -> NOT(OR(X,Y))
- VANDN(x, SplatVector(Imm)) -> AND(NOT(x), NOT(SplatVector(~Imm)))
Commit: cb63e99e58cbbb687575f2ab3139f9ba7b6e95bf
https://github.com/llvm/llvm-project/commit/cb63e99e58cbbb687575f2ab3139f9ba7b6e95bf
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
M llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
M llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-struct-return.ll
Log Message:
-----------
[VPlan] Include flags in VectorPointerRecipe::printRecipe (#169466)
The change is non-functional with respect to emitted IR.
Commit: 4b137e7446718973e209eb97402d9d06f90b8b0d
https://github.com/llvm/llvm-project/commit/4b137e7446718973e209eb97402d9d06f90b8b0d
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
Log Message:
-----------
[lldb][NFC] Remove code dupl in favour of a named variable in UnwindAssemblyInstEmulation (#169369)
Commit: bc4143b27afaeee1fcf3e8f0024774f3adc1eef9
https://github.com/llvm/llvm-project/commit/bc4143b27afaeee1fcf3e8f0024774f3adc1eef9
Author: Ravil Dorozhinskii <ravil.aviva.com at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[DAG] SDPatternMatch - add m_SpecificFP matcher (#167438)
This patch introduces SpecificFP matcher for SelectionDAG nodes.
This includes:
Adding SpecificFP_match() in SDPatternMatch.h.
Adding test coverage in SelectionDAGPatternMatchTest.cpp.
Closes #165566
Commit: e1b08731e5d81a0483a91da5eb89b1087876b9c2
https://github.com/llvm/llvm-project/commit/e1b08731e5d81a0483a91da5eb89b1087876b9c2
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
R llvm/test/CodeGen/AArch64/pr151592.mir
R llvm/test/CodeGen/AArch64/pr151888.mir
R llvm/test/CodeGen/AArch64/pr164181-reduced.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
R llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
M llvm/test/CodeGen/PowerPC/combine-fneg.ll
M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
M llvm/test/CodeGen/PowerPC/frem.ll
M llvm/test/CodeGen/PowerPC/froundeven-legalization.ll
M llvm/test/CodeGen/PowerPC/half.ll
M llvm/test/CodeGen/PowerPC/ldexp.ll
M llvm/test/CodeGen/PowerPC/llvm.modf.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
R llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
R llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
R llvm/test/CodeGen/X86/pr76416.ll
M llvm/test/CodeGen/X86/subreg-fail.mir
R llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
Log Message:
-----------
Revert "Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG""
This reverts commit bb78728826ff57f3df859e79bfd857b5a175bb6d.
Commit: 51dd3ec13c51b0e399cbceafb84698b7241ed731
https://github.com/llvm/llvm-project/commit/51dd3ec13c51b0e399cbceafb84698b7241ed731
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[MLIR][OpenMP] Bail early in sortMapIndices if indices are the same (#169474)
If we are given the same index in the comparator callback, simply return
false. Otherwise we will end up adding invalid items to
occludedChildren, causing extra items to get removed that should not be,
resulting in failures that manifest in different forms (assertions, asan
failures, ubsan failures, etc.).
Commit: 68c2a8140f7b8a487b7a9d9a53c6568b7336ee62
https://github.com/llvm/llvm-project/commit/68c2a8140f7b8a487b7a9d9a53c6568b7336ee62
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/test/extensions/libcxx/odr_signature.exceptions.sh.cpp
M libcxx/test/extensions/libcxx/odr_signature.hardening.sh.cpp
Log Message:
-----------
[libc++][C++03] Fix ODR tests (#169349)
We don't really need to include `<__config>`. We just need to include a
public C++ header.
Commit: 105900ced185558633e2ca8aa812c8c6c39ef59b
https://github.com/llvm/llvm-project/commit/105900ced185558633e2ca8aa812c8c6c39ef59b
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/__config
M libcxx/include/__configuration/platform.h
M libcxx/include/__random/binomial_distribution.h
M libcxx/src/filesystem/operations.cpp
Log Message:
-----------
[libc++] Always define _LIBCPP_GLIBC_PREREQ (#169405)
Always defining the macro allows us to simplify the few places where
it's used.
Commit: d748c81218bee39dafb9cc0c00ed7831a3ed44c3
https://github.com/llvm/llvm-project/commit/d748c81218bee39dafb9cc0c00ed7831a3ed44c3
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/add_i1.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-entry.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/cse-convergent.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub_i1.ll
M llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
Log Message:
-----------
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
The 16-bit immediate operand of s_waitcnt_depctr / s_wait_alu has some
unused bits. Previously codegen would set these bits to 1, but setting
them to 0 matches the SP3 assembler behaviour better, which in turn
means that we can print them using the human readable SP3 syntax:
s_wait_alu 0xfffd ; unused bits set to 1
s_wait_alu 0xff9d ; unused bits set to 0
s_wait_alu depctr_va_vcc(0) ; unused bits set to 0, human readable
Note that the set of unused bits changed between GFX10.1 and GFX10.3.
Commit: 17b19c50349053ed7721357f806233d633696bf0
https://github.com/llvm/llvm-project/commit/17b19c50349053ed7721357f806233d633696bf0
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/LoopUnrolling.cpp
M clang/test/Analysis/loop-unrolling.cpp
Log Message:
-----------
[analyzer] Unroll loops of compile-time upper-bounded loops (#169400)
Previously, only literal upper-bounded loops were recognized. This patch
relaxes this matching to accept any compile-time deducible constant
expression.
It would be better to rely on the SVals (values from the symbolic
domain), as those could potentially have more accurate answers, but this
one is much simpler.
Note that at the time we calculate this value, we have not evaluated the
sub-exprs of the condition, consequently, we can't just query the
Environment for the folded SVal.
Because of this, the next best tool in our toolbox is comp-time
evaluating the Expr.
rdar://165363923
Commit: 4e37526fdb37bb6e778a5445b05cb1be539fbda7
https://github.com/llvm/llvm-project/commit/4e37526fdb37bb6e778a5445b05cb1be539fbda7
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
Log Message:
-----------
[AMDGPU] Fix test after #169378
Commit: af3af8ea5a4a0102bfd3998d1898eef6d735b2e4
https://github.com/llvm/llvm-project/commit/af3af8ea5a4a0102bfd3998d1898eef6d735b2e4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/X86/setcc-wide-types.ll
Log Message:
-----------
[X86] setcc-wide-types.ll - cleanup check prefixes NFC (#169488)
Match typical prefixes used in x86 SSE/AVX tests
Commit: e06c148af7ed118ef2ff0774c8ad00838638bb2a
https://github.com/llvm/llvm-project/commit/e06c148af7ed118ef2ff0774c8ad00838638bb2a
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Analysis/IVDescriptors.cpp
Log Message:
-----------
[IVDesc] Use SCEVPatternMatch to improve code (NFC) (#168397)
Commit: 07ad928d92eac995e8d2fc48b0aafde511e9f3a0
https://github.com/llvm/llvm-project/commit/07ad928d92eac995e8d2fc48b0aafde511e9f3a0
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/fill_n.h
A libcxx/include/__algorithm/specialized_algorithms.h
M libcxx/include/__bit_reference
M libcxx/include/module.modulemap.in
Log Message:
-----------
[libc++] Introduce __specialized_algorithms (#167295)
Commit: 262716b35be1fc2c8de511b32d65f54448e0e204
https://github.com/llvm/llvm-project/commit/262716b35be1fc2c8de511b32d65f54448e0e204
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 07ad928d92ea
Commit: 4bc654d6497430c1dd5e4e25aaa84b3dec3e1113
https://github.com/llvm/llvm-project/commit/4bc654d6497430c1dd5e4e25aaa84b3dec3e1113
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
R cmake/Modules/GetToolchainDirs.cmake
M flang-rt/CMakeLists.txt
M flang-rt/cmake/modules/AddFlangRT.cmake
M flang-rt/cmake/modules/AddFlangRTOffload.cmake
R flang-rt/cmake/modules/FlangRTIntrospection.cmake
A flang-rt/cmake/modules/GetToolchainDirs.cmake
M flang-rt/lib/runtime/CMakeLists.txt
R flang-rt/lib/runtime/__cuda_builtins.f90
R flang-rt/lib/runtime/__cuda_device.f90
R flang-rt/lib/runtime/__fortran_builtins.f90
R flang-rt/lib/runtime/__fortran_ieee_exceptions.f90
R flang-rt/lib/runtime/__fortran_type_info.f90
R flang-rt/lib/runtime/__ppc_intrinsics.f90
R flang-rt/lib/runtime/__ppc_types.f90
R flang-rt/lib/runtime/cooperative_groups.f90
R flang-rt/lib/runtime/cudadevice.f90
R flang-rt/lib/runtime/ieee_arithmetic.f90
R flang-rt/lib/runtime/ieee_exceptions.f90
R flang-rt/lib/runtime/ieee_features.f90
R flang-rt/lib/runtime/iso_c_binding.f90
R flang-rt/lib/runtime/iso_fortran_env.f90
R flang-rt/lib/runtime/iso_fortran_env_impl.f90
R flang-rt/lib/runtime/mma.f90
M flang-rt/test/lit.site.cfg.py.in
M flang-rt/unittests/CMakeLists.txt
M flang/CMakeLists.txt
M flang/include/flang/Frontend/CompilerInvocation.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Semantics/semantics.cpp
A flang/module/.clang-format
A flang/module/__cuda_builtins.f90
A flang/module/__cuda_device.f90
A flang/module/__fortran_builtins.f90
A flang/module/__fortran_ieee_exceptions.f90
A flang/module/__fortran_type_info.f90
A flang/module/__ppc_intrinsics.f90
A flang/module/__ppc_types.f90
A flang/module/cooperative_groups.f90
A flang/module/cudadevice.f90
A flang/module/ieee_arithmetic.f90
A flang/module/ieee_exceptions.f90
A flang/module/ieee_features.f90
A flang/module/iso_c_binding.f90
A flang/module/iso_fortran_env.f90
A flang/module/iso_fortran_env_impl.f90
A flang/module/mma.f90
M flang/test/CMakeLists.txt
M flang/test/Driver/Inputs/ieee_arithmetic.mod
M flang/test/Driver/Inputs/iso_fortran_env.mod
R flang/test/Driver/intrinsic-module-path.F90
A flang/test/Driver/intrinsic-module-path.f90
M flang/test/Driver/lto-fatlto.f90
M flang/test/Driver/pp-fixed-form.f90
M flang/test/Lower/HLFIR/type-bound-call-mismatch.f90
M flang/test/Lower/OpenMP/simd_aarch64.f90
M flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90
M flang/test/Preprocessing/fixed-free.f
M flang/test/Preprocessing/no-pp-if.f90
M flang/test/Semantics/bug163242.f90
M flang/test/Semantics/bug164303.f90
M flang/test/lit.cfg.py
M flang/test/lit.site.cfg.py.in
M flang/tools/CMakeLists.txt
M flang/tools/bbc/bbc.cpp
A flang/tools/f18/CMakeLists.txt
A flang/tools/f18/dump.cpp
M llvm/runtimes/CMakeLists.txt
M openmp/CMakeLists.txt
M openmp/runtime/CMakeLists.txt
A openmp/runtime/cmake/LibompCheckFortranFlag.cmake
M openmp/runtime/cmake/LibompHandleFlags.cmake
M openmp/runtime/cmake/config-ix.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/test/lit.cfg
M openmp/runtime/test/lit.site.cfg.in
M runtimes/CMakeLists.txt
Log Message:
-----------
Revert "[Flang] Move builtin .mod generation into runtimes" (#169489)
Reverts llvm/llvm-project#137828
Buildbot error in
https://lab.llvm.org/staging/#/builders/105/builds/37275
Commit: 9e53ef3d8c18648517c7afb06bc0cd01ebbbdfa9
https://github.com/llvm/llvm-project/commit/9e53ef3d8c18648517c7afb06bc0cd01ebbbdfa9
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
A mlir/test/Target/LLVMIR/nvvm/mbar_arrive.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_arrive_drop.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_complete_tx.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_expect_tx.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_init.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_invalid.mlir
R mlir/test/Target/LLVMIR/nvvm/mbarriers.mlir
Log Message:
-----------
[MLIR][NVVM] Update mbarrier.arrive.* Op (#168758)
This patch updates the mbarrier.arrive.* family of Ops to include
all features added up-to Blackwell.
* Update the `mbarrier.arrive` Op to include shared_cluster
memory space, cta/cluster scope and an option to lower using
relaxed semantics.
* An `arrive_drop` variant is added for both the `arrive` and
`arrive.nocomplete` operations.
* Updates for expect_tx and complete_tx operations.
* Verifier checks are added wherever appropriate.
* lit tests are added to verify the lowering to the intrinsics.
TODO:
* Updates for the remaining mbarrier family will be done in
subsequent PRs. (mainly, arrive.expect-tx, test_wait and try_waits)
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 6bf3249fe9771c5732d993304ecee11f55927f9f
https://github.com/llvm/llvm-project/commit/6bf3249fe9771c5732d993304ecee11f55927f9f
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Sema/SemaARM.h
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
A clang/test/Sema/AArch64/builtin_vectorelements.c
Log Message:
-----------
[Clang][Sema] Emit diagnostic for __builtin_vectorelements(<SVEType>) when SVE is not available. (#168097)
As is done for other targets, I've moved the target type checking code
into SemaARM and migrated existing uses.
Fixes https://github.com/llvm/llvm-project/issues/155736
Commit: f0e0a2215827facf1f480753a96833f60ccbcb62
https://github.com/llvm/llvm-project/commit/f0e0a2215827facf1f480753a96833f60ccbcb62
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
Log Message:
-----------
[bazel] Delete redundant visibility (#169493)
default_visibility is already public.
Commit: 1919cd63223fdd6acd8a2c2d515f190160275226
https://github.com/llvm/llvm-project/commit/1919cd63223fdd6acd8a2c2d515f190160275226
Author: Colin Kinloch <colin at kinlo.ch>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/CheckerHelpers.cpp
A clang/test/Analysis/std-c-library-functions-eof-2-rad.c
Log Message:
-----------
[analyzer] Fix non decimal macro values in tryExpandAsInteger (#168632)
Values were parsed into an unsigned APInt with just enough of a bit
width to hold the number then interpreted as signed values. This
resulted in hex, octal and binary literals from being interpreted as
negative when the most significant bit is 1.
For example the `-0b11` would have a bit width of 2, would be
interpreted as -1, then negated to become 1.
Commit: 4e9b76e23b29a0576c0b950e06daa2f2a84c1b65
https://github.com/llvm/llvm-project/commit/4e9b76e23b29a0576c0b950e06daa2f2a84c1b65
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/lib/CIR/CodeGen/CIRGenOpenACCHelpers.h
M clang/test/CIR/CodeGenOpenACC/declare-create.cpp
M clang/test/CIR/CodeGenOpenACC/openacc-not-implemented-global.cpp
R clang/test/CIR/CodeGenOpenACC/openacc-not-implemented.cpp
Log Message:
-----------
[OpenACC][CIR] 'declare' lowering for globals/ns/struct-scopes (+create) (#169409)
This patch does the lowering for a 'declare' construct that is not a
function-local-scope. It also does the lowering for 'create', which has
an entry-op of create and exit-op of delete.
Global/NS/Struct scope 'declare's emit a single 'acc_ctor' and
'acc_dtor' (except in the case of 'link') per variable referenced. The
ctor is the entry op followed by a declare_enter. The dtor is a
get_device_ptr, followed by a declare_exit, followed by a delete(exit
op). This DOES include any necessary bounds.
This patch implements all of the above. We use a separate 'visitor' for
the clauses here since it is particularly different from the other uses,
AND there are only 4 valid clauses. Additionally, we had to split the
modifier conversion into its own 'helpers' file, which will hopefully
get some additional use in the future.
Commit: d54168013aa49876c21d53b9a4a39eec23953096
https://github.com/llvm/llvm-project/commit/d54168013aa49876c21d53b9a4a39eec23953096
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/Transforms/Utils/FunctionComparator.h
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
Log Message:
-----------
[LLVM] Use "syncscope" instead of "synchscope" in comments. NFC. (#134615)
This matches the spelling of the keyword in LLVM IR.
Commit: d615c14c22003522c16f7b82646542eb8e2dddca
https://github.com/llvm/llvm-project/commit/d615c14c22003522c16f7b82646542eb8e2dddca
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
Log Message:
-----------
[RISCV] Update SpacemiT-X60 vector floating-point instructions latencies (#150618)
This PR adds hardware-measured latencies for all instructions defined in
Section 13 of the RVV specification: "Vector Floating-Point
Instructions" to the SpacemiT-X60 scheduling model.
Commit: a7e715a1419ec977ff7d82f028a0449f9d20bf1c
https://github.com/llvm/llvm-project/commit/a7e715a1419ec977ff7d82f028a0449f9d20bf1c
Author: Paul Osmialowski <pawel.osmialowski at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/docs/Vectorizers.rst
Log Message:
-----------
[llvm][docs] Correct the list of the available -fveclib= options to match with the reality (#168205)
The command line reality is this:
$ clang -c prog.c -fveclib=accelerate
error: invalid value 'accelerate' in '-fveclib=accelerate'
$ clang -c prog.c -fveclib=Accelerate
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=libmvec
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=LIBMVEC
error: invalid value 'LIBMVEC' in '-fveclib=LIBMVEC'
$ clang -c prog.c -fveclib=massv
error: invalid value 'massv' in '-fveclib=massv'
$ clang -c prog.c -fveclib=MASSV
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=sleef
error: invalid value 'sleef' in '-fveclib=sleef'
$ clang -c prog.c -fveclib=sleefgnuabi
error: invalid value 'sleefgnuabi' in '-fveclib=sleefgnuabi'
$ clang -c prog.c -fveclib=SLEEF
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=darwin_libsystem_m
error: invalid value 'darwin' in '-fveclib=darwin_libsystem_m'
$ clang -c prog.c -fveclib=Darwin_libsystem_m
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=armpl
error: invalid value 'armpl' in '-fveclib=armpl'
$ clang -c prog.c -fveclib=ARMPL
error: invalid value 'ARMPL' in '-fveclib=ARMPL'
$ clang -c prog.c -fveclib=ArmPL
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=amdlibm
error: invalid value 'amdlibm' in '-fveclib=amdlibm'
$ clang -c prog.c -fveclib=AMDLIBM
clang: error: unsupported option 'AMDLIBM' for target 'aarch64'
Commit: b37b307715fd1c449698aabad1fcfd188b265f2c
https://github.com/llvm/llvm-project/commit/b37b307715fd1c449698aabad1fcfd188b265f2c
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/__functional/bind.h
M libcxx/include/__functional/bind_back.h
M libcxx/include/__functional/bind_front.h
M libcxx/include/__functional/function.h
M libcxx/include/__functional/mem_fn.h
M libcxx/include/__functional/reference_wrapper.h
M libcxx/test/libcxx/diagnostics/functional.nodiscard.verify.cpp
M libcxx/test/std/utilities/function.objects/refwrap/refwrap.invoke/robust_against_adl.pass.cpp
Log Message:
-----------
[libc++] Applied `[[nodiscard]]` to some general utilities (#169322)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
The following functions/classes have been annotated in this patch:
- [x] `bind_back`, `bind_front`, `bind`
- [x] `function`, `mem_fn`
- [x] `reference_wrapper`
Commit: 077a280cf586b29c6aa37a17637bcb6b91dc121c
https://github.com/llvm/llvm-project/commit/077a280cf586b29c6aa37a17637bcb6b91dc121c
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
A flang/test/Lower/OpenACC/acc-reduction-remapping.f90
Log Message:
-----------
[flang][acc] remap symbol appearing in reduction clause (#168876)
This patch is a follow-up of #162306 for the reduction clause.
Inside the compute region that carries the reduction clause, a new
hlfir.declare is generated for symbol appearing in the reduction clause.
The input of this hlfir.declare is the acc.reduction result. The related
semantics::Symbol is remapped to the hlfir.declare result so that any
reference to the symbol inside the compute region will use this SSA
value as the starting point instead of the SSA value for the host
address.
Commit: 5818435c437c654c8c17c7ba8b7eb8833b7c3229
https://github.com/llvm/llvm-project/commit/5818435c437c654c8c17c7ba8b7eb8833b7c3229
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/basic.ll
Log Message:
-----------
RuntimeLibcalls: Add a few libm entries from TargetLibraryInfo (#167049)
These are floating-point functions recorded in TargetLibraryInfo,
but missing from RuntimeLibcalls.
Commit: 7f8c43a24949e2aa33e5f03f75ac865bb2f11ad8
https://github.com/llvm/llvm-project/commit/7f8c43a24949e2aa33e5f03f75ac865bb2f11ad8
Author: GrumpyPigSkin <130710602+GrumpyPigSkin at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
A llvm/test/CodeGen/X86/GlobalISel/fp-bitcast.ll
Log Message:
-----------
[X86][GISel] Fix crash on bitcasting i16 <-> half with gisel enabled. (#168456)
Added missing checks for casting half to/from i16 with global-isel
enabled.
Fixes #166557
Commit: d8ae4d503ada5509fb526a782816540eb4d15012
https://github.com/llvm/llvm-project/commit/d8ae4d503ada5509fb526a782816540eb4d15012
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/basic.ll
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/ps.ll
Log Message:
-----------
RuntimeLibcalls: Add __memcpy_chk, __memmove_chk, __memset_chk (#167053)
These were in TargetLibraryInfo, but missing from RuntimeLibcalls.
This only adds the cases that already have the non-chk variants
already. Copies the enabled-by-default logic from TargetLibraryInfo,
which is probably overly permissive. Only isPS opts-out.
Commit: 25c95ebfa82e2f6a20cf1282aaef09d1cc598ee7
https://github.com/llvm/llvm-project/commit/25c95ebfa82e2f6a20cf1282aaef09d1cc598ee7
Author: Ming Yan <ming.yan at terapines.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/test/Fir/FirToSCF/do-loop.fir
Log Message:
-----------
[flang][fir] Convert `fir.do_loop` with the unordered attribute to `scf.parallel`. (#168510)
Refines the existing conversion to allow `fir.do_loop` annotated with
`unordered` to be lowered to `scf.parallel`, while other loops retain
their original lowering.
Commit: a51e2ef0fe73dd9ab6e608304ddf2b489c350cf4
https://github.com/llvm/llvm-project/commit/a51e2ef0fe73dd9ab6e608304ddf2b489c350cf4
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
Log Message:
-----------
[VPlan] Treat VPVector(End)PointerRecipe as single-scalar, if ops are. (#169249)
VPVector(End)PointerRecipes are single-scalar if all their operands are.
This should be effectively NFC currently, but it should re-enable cost
checking for some more VPWidenMemoryRecipe after
https://github.com/llvm/llvm-project/pull/157387 as discovered by
John Brawn.
Commit: eb5297e0ade96fe8a6297763f28219be97dfac76
https://github.com/llvm/llvm-project/commit/eb5297e0ade96fe8a6297763f28219be97dfac76
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/merge_attributes.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sincos_stret.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sleef.ll
Log Message:
-----------
RuntimeLibcalls: Add mustprogress to common function attributes (#167080)
Commit: be2dfce6472c65270900dce1754f5352a83c2e98
https://github.com/llvm/llvm-project/commit/be2dfce6472c65270900dce1754f5352a83c2e98
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copyin.cpp
Log Message:
-----------
[OpenACC][CIR] Global declare 'copyin' clause lowering (#169498)
JUST like the 'create' clause, except the entry op is copyin instead of
create. Most of this is the test.
Commit: 9007b36b4250dff51e1a22f0b1f4084d5ab4fd4a
https://github.com/llvm/llvm-project/commit/9007b36b4250dff51e1a22f0b1f4084d5ab4fd4a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
Log Message:
-----------
[RISCV] Add a InstRW to COPY in RISCVSchedSpacemitX60.td. (#169423)
This prevents the scheduler from thinking copy instructions are free. In
#167008, we saw cases where the scheduler moved ABI copies past other
instructions creating high register pressure that caused the register
allocator to run out of registers. They can't be spilled because the
physical register lifetime was increased, not the virtual register.
Ideally, we would detect what register class the COPY is for, but for now
I've just treated it as a scalar integer copy.
Commit: 4f5fb36ddba6f538ff859d494fe15f19691b88f1
https://github.com/llvm/llvm-project/commit/4f5fb36ddba6f538ff859d494fe15f19691b88f1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Use an enum class for AVL state ins RISCVInsertVSETVLI. NFC (#169455)
Commit: 3564870a9fbfe49b11b47136127b6f972fbac43b
https://github.com/llvm/llvm-project/commit/3564870a9fbfe49b11b47136127b6f972fbac43b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Initialize AltFmt and TWiden in the VSETVLIInfo default constructor. (#169457)
Commit: b3b83ac1e80e4a3f3e4241b2ae0ceabef369a5bf
https://github.com/llvm/llvm-project/commit/b3b83ac1e80e4a3f3e4241b2ae0ceabef369a5bf
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M offload/test/offloading/shared_lib_fp_mapping.c
M offload/test/offloading/static_linking.c
Log Message:
-----------
[offload][lit] Fix compilation of two offload tests (#169399)
These are C tests, not C++, so no function parameters means unspecified
number of parameters, not `void`.
These compile fine on the current tested offload targets because an
error is only
[thrown](https://github.com/llvm/llvm-project/blob/main/clang/lib/Sema/SemaDecl.cpp#L10695)
if the calling convention doesn't support variadic arguments, which they
happen to.
When compiling this test for other targets that do not support variadic
arguments, we get an error, which does not seem intentional.
Just add `void` to the parameter list.
---------
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 031d99836de51f2d6dfeb4f539e2d1af85f4f263
https://github.com/llvm/llvm-project/commit/031d99836de51f2d6dfeb4f539e2d1af85f4f263
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
A llvm/test/CodeGen/SPIRV/function/vararg.ll
Log Message:
-----------
[SPIRV] Error in backend for vararg functions (#169111)
SPIR-V doesn't support variadic functions, though we make an exception
for `printf`.
If we don't error, we generate invalid SPIR-V because the backend has no
idea how to codegen vararg functions as it is not described in the spec.
We get asm like this:
```
%27 = OpFunction %6 None %7
%28 = OpFunctionParameter %4
; -- End function
```
The above asm is totally invalid, there's no `OpFunctionEnd` and it
causes crashes in downstream tools like `spirv-as` and `spirv-link`.
We already have many `printf` tests locking down that this doesn't break
`printf`, it was already handled elsewhere at the time the error check
runs.
Note the SPIR-V Translator does the same thing, see
[here](https://github.com/KhronosGroup/SPIRV-LLVM-Translator/pull/2703).
---------
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: ccbd0d1a69eb71268bfa7066a962bbd37c9893b1
https://github.com/llvm/llvm-project/commit/ccbd0d1a69eb71268bfa7066a962bbd37c9893b1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Add assertions to VSETVLIInfo accessors. NFC (#169462)
Commit: 177e38286cd61a7b5a968636e1f147f128dd25a2
https://github.com/llvm/llvm-project/commit/177e38286cd61a7b5a968636e1f147f128dd25a2
Author: Sayan Saha <sayans at mathworks.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/Utils/QuantUtils.h
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Utils/QuantUtils.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/quant-test.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Get quantized element type with sign info. (#169387)
As mentioned in
https://github.com/llvm/llvm-project/blob/a27bb38ee6f5762e715803d8eb6ffc5a8dd09575/mlir/include/mlir/Dialect/Quant/IR/QuantTypes.h#L109
`QuantType::getStorageType` doesn't capture the sign information. This
lead to the following IR to fail during verification:
```
func.func @clamp(%arg0:tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>) -> (tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>) {
%0 = tosa.clamp %arg0 {max_val = 255 : ui8, min_val = 0 : ui8} : (tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>) -> tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>
return %0 : tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>
}
```
with `'tosa.clamp' op min/max attributes types are incompatible with
input/output element types` error
since `getStorageType` was returning signed integer but the clamp
attributes were unsigned.
This PR updates the usage of `getStorageType` in tosa codebase to
correctly use the signed info for the quantized type.
Commit: 1c3b10f2e2d8f9600fedd5e579aef69d7d31fadc
https://github.com/llvm/llvm-project/commit/1c3b10f2e2d8f9600fedd5e579aef69d7d31fadc
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)
Since #142598 isKernelLDS has been a pointless wrapper around isKernel.
Commit: 02c9e8987a22753417c721eba5e5848f3fe33a24
https://github.com/llvm/llvm-project/commit/02c9e8987a22753417c721eba5e5848f3fe33a24
Author: Marco Elver <elver at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll
Log Message:
-----------
[InstCombine][MemProf] Preserve all metadata (#169242)
When rewriting operator new calls to their hot/cold variants for PGHO,
`!alloc_token` metadata was being dropped. This metadata is required by
the AllocToken pass to correctly instrument the optimized allocation.
Fix it by preserving all metadata.
Commit: b8ef25aa643761233dc5b74d9fb7c38a2064d9c7
https://github.com/llvm/llvm-project/commit/b8ef25aa643761233dc5b74d9fb7c38a2064d9c7
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Transforms/Utils/LoopUtils.cpp
A llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
M llvm/test/Verifier/llvm.loop.estimated_trip_count.ll
M llvm/unittests/Transforms/Utils/LoopUtilsTest.cpp
Log Message:
-----------
[PGO] Fix zeroed estimated trip count (#167792)
Before PR #152775, `llvm::getLoopEstimatedTripCount` never returned 0.
If `llvm::setLoopEstimatedTripCount` were called with 0, it would zero
branch weights, causing `llvm::getLoopEstimatedTripCount` to return
`std::nullopt`.
PR #152775 changed that behavior: if `llvm::setLoopEstimatedTripCount`
is called with 0, it sets `llvm.loop.estimated_trip_count` to 0, causing
`llvm::getLoopEstimatedTripCount` to return 0. However, it kept
documentation saying `llvm::getLoopEstimatedTripCount` returns a
positive count.
Some passes continue to assume `llvm::getLoopEstimatedTripCount` never
returns 0 and crash if it does, as reported in issue #164254. To restore
the behavior they expect, this patch changes
`llvm::getLoopEstimatedTripCount` to return `std::nullopt` when
`llvm.loop.estimated_trip_count` is 0.
Commit: c582688b6912c615da1d08630c178dd3d0072aeb
https://github.com/llvm/llvm-project/commit/c582688b6912c615da1d08630c178dd3d0072aeb
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
Log Message:
-----------
[MLIR][tensor] Simplify ExtractSliceOp::inferResultType (nfc) (#169313)
The `offsets` and `strides` arguments are neither used nor required -
removed them and simplify this hook.
Commit: 6d21ce8797317814ad6f2372d98d21c9900f0579
https://github.com/llvm/llvm-project/commit/6d21ce8797317814ad6f2372d98d21c9900f0579
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceresident.cpp
Log Message:
-----------
[OpenACC][CIR] device_resident lowering for NS/global/struct declare (#169507)
This is the same as create/copyin, except it uses
declare_device_resident for the entry op.
Commit: 7b5163d3001613e9c449f7603f4a0f7f521e79a1
https://github.com/llvm/llvm-project/commit/7b5163d3001613e9c449f7603f4a0f7f521e79a1
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
Log Message:
-----------
[lldb][NFC] use llvm::StringRef in `ExtractContextAndIdentifer` function (#169506)
this avoids allocation when checking if a method contains a path.
Commit: e04cca8561c65b9820f2c284eea164ab9fb7cdce
https://github.com/llvm/llvm-project/commit/e04cca8561c65b9820f2c284eea164ab9fb7cdce
Author: Marco Elver <elver at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A clang/test/CodeGen/memprof-pgho.cpp
Log Message:
-----------
[Clang][MemProf] Add end-to-end test for PGHO rewriting (#169243)
Add an end-to-end (non-LTO) test verifying that the optimization
pipeline is set up correctly for Profile Guided Heap Optimization (PGHO)
transforms. Ensure that both PGHO and AllocToken can stack, and the
AllocToken pass does not interfere with PGHO and vice versa.
Commit: 1a036732d210c2b78404067a1aa0b3a3bba3eaf8
https://github.com/llvm/llvm-project/commit/1a036732d210c2b78404067a1aa0b3a3bba3eaf8
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
A clang/test/Driver/hip-spirv-backend-bindings.c
A clang/test/Driver/hip-spirv-backend-opt.c
A clang/test/Driver/hip-spirv-backend-phases.c
Log Message:
-----------
[clang][Driver] Support for the SPIR-V backend when compiling HIP (#167543)
For HIP, the SPIR-V backend can be optionally activated with the -use-spirv-backend flag. This option uses the SPIR-V BE instead of the SPIR-V translator. These changes also ensure that -use-spirv-backend does not require external dependencies, such as spirv-as and spirv-link
Commit: 17852deda7fb9dabb41023e2673025c630b9369d
https://github.com/llvm/llvm-project/commit/17852deda7fb9dabb41023e2673025c630b9369d
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
M llvm/lib/Target/NVPTX/NVPTXTagInvariantLoads.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
M llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
A llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
A llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
A llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
Log Message:
-----------
[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)
This backend support will allow the LoadStoreVectorizer, in certain
cases, to fill in gaps when creating load/store vectors and generate
LLVM masked load/stores
(https://llvm.org/docs/LangRef.html#llvm-masked-store-intrinsics). To
accomplish this, changes are separated into two parts. This first part
has the backend lowering and TTI changes, and a follow up PR will have
the LSV generate these intrinsics:
https://github.com/llvm/llvm-project/pull/159388.
In this backend change, Masked Loads get lowered to PTX with `#pragma
"used_bytes_mask" [mask];`
(https://docs.nvidia.com/cuda/parallel-thread-execution/#pragma-strings-used-bytes-mask).
And Masked Stores get lowered to PTX using the new sink symbol syntax
(https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-st).
# TTI Changes
TTI changes are needed because NVPTX only supports masked loads/stores
with _constant_ masks. `ScalarizeMaskedMemIntrin.cpp` is adjusted to
check that the mask is constant and pass that result into the TTI check.
Behavior shouldn't change for non-NVPTX targets, which do not care
whether the mask is variable or constant when determining legality, but
all TTI files that implement these API need to be updated.
# Masked store lowering implementation details
If the masked stores make it to the NVPTX backend without being
scalarized, they are handled by the following:
* `NVPTXISelLowering.cpp` - Sets up a custom operation action and
handles it in lowerMSTORE. Similar handling to normal store vectors,
except we read the mask and place a sentinel register `$noreg` in each
position where the mask reads as false.
For example,
```
t10: v8i1 = BUILD_VECTOR Constant:i1<-1>, Constant:i1<0>, Constant:i1<0>, Constant:i1<-1>, Constant:i1<-1>, Constant:i1<0>, Constant:i1<0>, Constant:i1<-1>
t11: ch = masked_store<(store unknown-size into %ir.lsr.iv28, align 32, addrspace 1)> t5:1, t5, t7, undef:i64, t10
->
STV_i32_v8 killed %13:int32regs, $noreg, $noreg, killed %16:int32regs, killed %17:int32regs, $noreg, $noreg, killed %20:int32regs, 0, 0, 1, 8, 0, 32, %4:int64regs, 0, debug-location !18 :: (store unknown-size into %ir.lsr.iv28, align 32, addrspace 1);
```
* `NVPTXInstInfo.td` - changes the definition of store vectors to allow
for a mix of sink symbols and registers.
* `NVPXInstPrinter.h/.cpp` - Handles the `$noreg` case by printing "_".
# Masked load lowering implementation details
Masked loads are routed to normal PTX loads, with one difference: a
`#pragma "used_bytes_mask"` is emitted before the load instruction
(https://docs.nvidia.com/cuda/parallel-thread-execution/#pragma-strings-used-bytes-mask).
To accomplish this, a new operand is added to every NVPTXISD Load type
representing this mask.
* `NVPTXISelLowering.h/.cpp` - Masked loads are converted into normal
NVPTXISD loads with a mask operand in two ways. 1) In type legalization
through replaceLoadVector, which is the normal path, and 2) through
LowerMLOAD, to handle the legal vector types
(v2f16/v2bf16/v2i16/v4i8/v2f32) that will not be type legalized. Both
share the same convertMLOADToLoadWithUsedBytesMask helper. Both default
this operand to UINT32_MAX, representing all bytes on. For the latter,
we need a new `NVPTXISD::MLoadV1` type to represent that edge case
because we cannot put the used bytes mask operand on a generic
LoadSDNode.
* `NVPTXISelDAGToDAG.cpp` - Extract used bytes mask from loads, add them
to created machine instructions.
* `NVPTXInstPrinter.h/.cpp` - Print the pragma when the used bytes mask
isn't all ones.
* `NVPTXForwardParams.cpp`, `NVPTXReplaceImageHandles.cpp` - Update
manual indexing of load operands to account for new operand.
* `NVPTXInsrtInfo.td`, `NVPTXIntrinsics.td` - Add the used bytes mask to
the MI definitions.
* `NVPTXTagInvariantLoads.cpp` - Ensure that masked loads also get
tagged as invariant.
Some generic changes that are needed:
* `LegalizeVectorTypes.cpp` - Ensure flags are preserved when splitting
masked loads.
* `SelectionDAGBuilder.cpp` - Preserve `MD_invariant_load` on masked
load SDNode creation
Commit: 6a395fec1f7663e02c6607e8e10791838c949389
https://github.com/llvm/llvm-project/commit/6a395fec1f7663e02c6607e8e10791838c949389
Author: Guy David <guyda96 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
Log Message:
-----------
[AArch64] Mark FMOVvXfY_ns as rematerializable, cheap (#169186)
Commit: b93bb69dfad5f94565d90575a92203a1a2f3395b
https://github.com/llvm/llvm-project/commit/b93bb69dfad5f94565d90575a92203a1a2f3395b
Author: Samira Bakon <bazuzi at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
Log Message:
-----------
[clang][dataflow] Use containers with deterministic iteration order. (#169512)
Commit: eb1ff56e26fdb48728642f7d26e47b337b7235ea
https://github.com/llvm/llvm-project/commit/eb1ff56e26fdb48728642f7d26e47b337b7235ea
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll
Log Message:
-----------
[SLP][NFC]Add a test for copyable operands, used multiple times, NFC
Commit: d69e70149636efa0293310303878fbf9a5f31433
https://github.com/llvm/llvm-project/commit/d69e70149636efa0293310303878fbf9a5f31433
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
Log Message:
-----------
[PGO] Add missing target datalayout in test (#169520)
The test was added by b8ef25aa643761233dc5b74d9fb7c38a2064d9c7. It
failed on at least the following bots, but the failure did not reproduce
on my test machines or in pre-commit CI:
- https://lab.llvm.org/buildbot/#/builders/190/builds/31638
- https://lab.llvm.org/buildbot/#/builders/190/builds/31638
This fix hopefully addresses at least the warnings there.
Commit: 5999cc8ceef3acef128e1baf8fcefd7164acc677
https://github.com/llvm/llvm-project/commit/5999cc8ceef3acef128e1baf8fcefd7164acc677
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/stack
M libcxx/test/libcxx/diagnostics/stack.nodiscard.verify.cpp
Log Message:
-----------
[libc++][stack] Applied `[[nodiscard]]` (#169468)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 1c5b1501ca50e039ae39075465972761449013e9
https://github.com/llvm/llvm-project/commit/1c5b1501ca50e039ae39075465972761449013e9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/lib/CodeGen/LibcallLoweringInfo.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.h
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/Mips/Mips16ISelLowering.h
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.h
Log Message:
-----------
CodeGen: Move libcall lowering configuration to subtarget (#168621)
Previously libcall lowering decisions were made directly
in the TargetLowering constructor. Pull these into the subtarget
to facilitate turning LibcallLoweringInfo into a separate analysis
in the future.
Commit: 5017370a1ce5009aed2855b645194bc141f72a2d
https://github.com/llvm/llvm-project/commit/5017370a1ce5009aed2855b645194bc141f72a2d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/gws_agpr.ll
Log Message:
-----------
AMDGPU: Add baseline test for gws handling with AGPR inputs (#169372)
Commit: a860c8378f91d9b7713171888e76962b2747fe4e
https://github.com/llvm/llvm-project/commit/a860c8378f91d9b7713171888e76962b2747fe4e
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
R clang/test/Driver/hip-spirv-backend-bindings.c
R clang/test/Driver/hip-spirv-backend-opt.c
R clang/test/Driver/hip-spirv-backend-phases.c
Log Message:
-----------
Revert "[clang][Driver] Support for the SPIR-V backend when compiling HIP (#167543)" (#169528)
This reverts commit 1a036732d210c2b78404067a1aa0b3a3bba3eaf8.
Reverted due to a failure in hip-spirv-backend-opt.c for
fuchsia-x86_64-linux.
Commit: 53e5cfdf8b13e2427797ca6eeda1860f8aa190ef
https://github.com/llvm/llvm-project/commit/53e5cfdf8b13e2427797ca6eeda1860f8aa190ef
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/combined-copy.c
M clang/test/CIR/CodeGenOpenACC/compute-copy.c
M clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceptr.cpp
M clang/test/CIR/CodeGenOpenACC/declare-link.cpp
M clang/test/CIR/CodeGenOpenACC/declare-present.cpp
Log Message:
-----------
[OpenACC][CIR] link clause lowering for global declare (#169524)
The 'link' clause is like the rest of the global clauses (copyin,
create, device_resident), except it only has an entry op(thus no
dtor).
This patch also removes a bunch of now stales TODOs from the tests.
Commit: 8380a48aa0b62be28b653ba6b3d38198680b2bd9
https://github.com/llvm/llvm-project/commit/8380a48aa0b62be28b653ba6b3d38198680b2bd9
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
Log Message:
-----------
[PGO] Add REQUIRES to test (#169531)
The test was added by b8ef25aa643761233dc5b74d9fb7c38a2064d9c7. It
failed on at least the following bots, but the failure did not reproduce
on my test machines or in pre-commit CI:
- https://lab.llvm.org/buildbot/#/builders/190/builds/31643
- https://lab.llvm.org/buildbot/#/builders/65/builds/25949
- https://lab.llvm.org/buildbot/#/builders/154/builds/24417
d69e70149636efa0293310303878fbf9a5f31433 did not fix the failure.
Hopefully this will.
Commit: 1441f0458545243f9278cf87a35c4cb4e1cd62bd
https://github.com/llvm/llvm-project/commit/1441f0458545243f9278cf87a35c4cb4e1cd62bd
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/Address.h
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
A clang/test/CIR/CodeGen/placement-new.cpp
Log Message:
-----------
[CIR] Upstream reserved placement new handling (#169436)
This upstreams the code to support reserved placement new calls.
Commit: 45336992453c83d083ccadf62ae56626dfb0f761
https://github.com/llvm/llvm-project/commit/45336992453c83d083ccadf62ae56626dfb0f761
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
Log Message:
-----------
[BOLT][BTI] Add MCPlusBuilder::isBTILandingPad (#167306)
- takes both implicit and explicit BTIs into account
- fix related comment in
llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
Commit: 83d9c636b753ab37842a25606d95d800dce90398
https://github.com/llvm/llvm-project/commit/83d9c636b753ab37842a25606d95d800dce90398
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M utils/bazel/third_party_build/zlib-ng.BUILD
Log Message:
-----------
[bazel] Add alias for zlib-ng for WORKSPACE compat (#169530)
The consumer of zlib in third-party/BUILD.bazel expects zlib-ng from the
BCR, if you still load this version from your WORKSPACE / MODULE.bazel
you need to use this name instead.
Commit: 012721d3200ceed635495394fe96b17bbaa8653e
https://github.com/llvm/llvm-project/commit/012721d3200ceed635495394fe96b17bbaa8653e
Author: Benjamin Chetioui <3920784+bchetioui at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/test/python/ir/operation.py
Log Message:
-----------
[mlir][python] Propagate error diagnostics when an op couldn't be created. (#169499)
Commit: 4877c593a873657cd18a1ee0bd4a13f4b84c4d3b
https://github.com/llvm/llvm-project/commit/4877c593a873657cd18a1ee0bd4a13f4b84c4d3b
Author: Kaitlin Peng <kaitlinpeng at microsoft.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCombine.td
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h
A llvm/test/CodeGen/SPIRV/GlobalISel/InstCombine/prelegalizercombiner-select-to-faceforward.mir
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/faceforward.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward.ll
Log Message:
-----------
[SPIRV] Add PreLegalizer pattern matching for `faceforward` (#139959)
Tasks completed:
- Pattern match`select(fcmp(dot(p2, p3), 0), p1, -p1)` to
`faceforward(p1, p2, p3)`
- Add pattern matching tests to
`prelegalizercombiner-select-to-faceforward.mir` and `faceforward.ll`
- Add CL extension error test
`llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll`
- Add CL extension test for no pattern matching in
`llvm/test/CodeGen/SPIRV/opencl/faceforward.ll`
Closes #137255.
Commit: d125cab13f08eee4d02d02e46223d14285bb2353
https://github.com/llvm/llvm-project/commit/d125cab13f08eee4d02d02e46223d14285bb2353
Author: Valeriy Savchenko <vsavchenko at apple.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/Transforms/InstCombine/cast-mul-select.ll
M llvm/test/Transforms/InstCombine/cast.ll
M llvm/test/Transforms/InstCombine/catchswitch-phi.ll
M llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
M llvm/test/Transforms/InstCombine/known-bits-lerp-pattern.ll
M llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
M llvm/test/Transforms/InstCombine/logical-select.ll
Log Message:
-----------
[InstCombine] Support multi-use values in cast elimination transforms (#165877)
`canEvaluateTruncated` and `canEvaluateSExtd` previously rejected
multi-use values to avoid duplication. This was overly conservative, if
all users of a multi-use value are part of the transform, we can
evaluate it in a different type without duplication.
This change tracks visited values and defers decisions on multi-use
values until we verify all their users were visited.
`EvaluateInDifferentType` now memoizes multi-use values to avoid
creating duplicates.
Applied to truncation and sext. Zext unchanged due to its dual-return
nature.
Commit: 84df446af980f33f8014578856f8b1f8037888ee
https://github.com/llvm/llvm-project/commit/84df446af980f33f8014578856f8b1f8037888ee
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
Log Message:
-----------
AMDGPU: Remove DummyCGSCC use after buffer lowering passes (#169519)
The fixme the comment refers to was removed.
Commit: 44cffbe5d8de5947780288ca3c366bbd52650314
https://github.com/llvm/llvm-project/commit/44cffbe5d8de5947780288ca3c366bbd52650314
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/fma-combine.ll
Log Message:
-----------
[RISCV] Propagate SDNode flags when combining `(fmul (fneg X), ...)` (#169460)
In #157388, we turned `(fmul (fneg X), Y)` into `(fneg (fmul X, Y))`.
However, we forgot to propagate SDNode flags, specifically fast math
flags, from the original FMUL to the new one. This hinders some of the
subsequent (FMA) DAG combiner patterns that relied on the contraction
flag and as a consequence, missed some of the opportunities to generate
negation FMA instructions like `fnmadd`.
This patch fixes this issue by propagating the flags.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 6a6b99aa8010f16f4e74f78bca1f3c6ca9e94b9f
https://github.com/llvm/llvm-project/commit/6a6b99aa8010f16f4e74f78bca1f3c6ca9e94b9f
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCRecipeBufferization.cpp
M flang/test/Fir/OpenACC/recipe-bufferization.mlir
M flang/test/Lower/OpenACC/acc-firstprivate-derived-allocatable-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-pointer-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-user-assign.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction-remapping.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenACC/do-loops-to-acc-loops.f90
M flang/test/Transforms/OpenACC/acc-implicit-copy-reduction.fir
M flang/test/Transforms/OpenACC/acc-implicit-data-fortran.F90
M flang/test/Transforms/OpenACC/acc-implicit-data.fir
M flang/test/Transforms/OpenACC/acc-implicit-firstprivate.fir
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/test/Dialect/OpenACC/acc-implicit-data-reduction.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
M mlir/test/Dialect/OpenACC/invalid.mlir
M mlir/test/Dialect/OpenACC/legalize-data.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
Log Message:
-----------
[acc][flang][cir] Add recipes to data entry operations (#149210)
This patch refactors the OpenACC dialect to attach recipe symbols
directly to data operations (acc.private, acc.firstprivate,
acc.reduction)
rather than to compute constructs (acc.parallel, acc.serial, acc.loop).
Motivation:
The previous design required compute constructs to carry both the recipe
symbol and the variable reference, leading to complexity. Additionally,
recipes were required even when they could be generated automatically
through MappableType interfaces.
Changes:
- Data operations (acc.private, acc.firstprivate, acc.reduction) now
require a 'recipe' attribute referencing their respective recipe
operations
- Verifier enforces recipe attribute presence for non-MappableType
operands; MappableType operands can generate recipes on demand
- Compute constructs (acc.parallel, acc.serial, acc.loop) no longer
carry recipe symbols in their operands
- Updated flang lowering to attach recipes to data operations instead
of passing them to compute constructs
Format Migration:
Old format:
```
acc.parallel private(@recipe -> %var : !fir.ref<i32>) { ... }
```
New format:
```
%private = acc.private varPtr(%var : !fir.ref<i32>)
recipe(@recipe) -> !fir.ref<i32>
acc.parallel private(%private : !fir.ref<i32>) { ... }
```
Test Updates:
- Updated all CIR and Flang OpenACC tests to new format
- Fixed CHECK lines to verify recipe attributes on data operations
Commit: d5aa686636e0824f2d39ac333537d19bb4f8fc34
https://github.com/llvm/llvm-project/commit/d5aa686636e0824f2d39ac333537d19bb4f8fc34
Author: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
[GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`. (#166204)
`convert-vector-to-llvm` pass applies a set of vector transformation
patterns that are not included in the standard `convert-to-llvm` pass
interface. These additional transformations are required to properly
lower MLIR vector operations. Since not all vector ops have direct
`llvm` dialect lowering, many of them must first be progressively
rewritten into simpler or more canonical vector ops, which are then
lowered to `llvm`. Therefore, running `convert-vector-to-llvm` is
necessary to ensure a complete and correct lowering of vector operations
to the `llvm` dialect.
Commit: 4822f4986fae9bb212e2f35e29839bbd9fb26bea
https://github.com/llvm/llvm-project/commit/4822f4986fae9bb212e2f35e29839bbd9fb26bea
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Analysis/CFG.cpp
M clang/test/Analysis/lifetime-cfg-output.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/unittests/Analysis/FlowSensitive/LoggerTest.cpp
Log Message:
-----------
[LifetimeSafety] Add parameter lifetime tracking in CFG (#169320)
This PR enhances the CFG builder to properly handle function parameters
in lifetime analysis:
1. Added code to include parameters in the initial scope during CFG
construction for both `FunctionDecl` and `BlockDecl` types
2. Added a special case to skip reference parameters, as they don't need
automatic destruction
3. Fixed several test cases that were previously marked as "FIXME" due
to missing parameter lifetime tracking
Previously, Clang's lifetime analysis was not properly tracking the
lifetime of function parameters, causing it to miss important
use-after-return bugs when parameter values were returned by reference
or address. This change ensures that parameters are properly tracked in
the CFG, allowing the analyzer to correctly identify when stack memory
associated with parameters is returned.
Fixes https://github.com/llvm/llvm-project/issues/169014
Commit: f545c2cec12f77f1fb61ccf07393f434d456ad94
https://github.com/llvm/llvm-project/commit/f545c2cec12f77f1fb61ccf07393f434d456ad94
Author: David Stone <davidfromonline at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaDeclCXX.cpp
Log Message:
-----------
[clang][NFC] Don't copy into a vector just to iterate in `IsInitListMemberExprInitialized` (#169385)
Commit: 0c9c62adf165ebf4128bcfe9863fa0c524b46b7b
https://github.com/llvm/llvm-project/commit/0c9c62adf165ebf4128bcfe9863fa0c524b46b7b
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
Log Message:
-----------
[PowerPC ]convert `(setcc (and X, 1), 0, eq)` to `XORI (and X, 1), 1` (#168384)
Convert `(setcc (and X, 1), 0, eq)` to `XORI (and X, 1), 1` , it will save one instruction.
Commit: d7dcc108fc3ada2330277424495b676d52de1765
https://github.com/llvm/llvm-project/commit/d7dcc108fc3ada2330277424495b676d52de1765
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/docs/DeveloperPolicy.rst
M llvm/utils/git/github-automation.py
Log Message:
-----------
[GitHub] Add review instructions for commit access requests (#168971)
As discussed in
https://discourse.llvm.org/t/clarification-on-how-to-accept-commit-access-requests/88728,
clarify reviewer instructions for how to accept commit access requests.
Commit: 1d30ae6e402a28018a5574b7c68d71aac14acd63
https://github.com/llvm/llvm-project/commit/1d30ae6e402a28018a5574b7c68d71aac14acd63
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
AMDGPU: Stop forcing RequiresCodeGenSCCOrder (#169522)
This hasn't been strictly necessary since c897c13dde.
Practically this makes little difference; we still enable IPRA
by default which implies this option. By removing this explicit
force, -enable-ipra=0 has the expected change in the pass pipeline
to remove the DummyCGSCC runs.
Commit: 8f1bb92bbfa45d49103953dad0d0a5dcfd388959
https://github.com/llvm/llvm-project/commit/8f1bb92bbfa45d49103953dad0d0a5dcfd388959
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
M llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
M llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
Log Message:
-----------
[NVPTX] Fix lit test issues from masked load/store implementation (#169535)
>From this commit:
https://github.com/llvm/llvm-project/commit/17852deda7fb9dabb41023e2673025c630b9369d,
Build was broken here:
https://lab.llvm.org/buildbot/#/builders/155/builds/15135/steps/7/logs/stdio.
I think this should fix things.
Commit: 6c8ff4f2bbae6fe29b0ef67edb70e6d73b47beb3
https://github.com/llvm/llvm-project/commit/6c8ff4f2bbae6fe29b0ef67edb70e6d73b47beb3
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Log Message:
-----------
[NVPTX] Fix maybe unused variable in 17852ded (#169542)
Commit: dce95b2ea41e8585cd1e3e2ce07f5d692a970949
https://github.com/llvm/llvm-project/commit/dce95b2ea41e8585cd1e3e2ce07f5d692a970949
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACCLoop.cpp
Log Message:
-----------
[OpenACC][CIR][NFC] Remove 'NYI' diagnostics, since we're done with t… (#169543)
…hese
We've finished all of the clauses/etc that we're going to use this
visitor for, so we can remove the SourceLocation we used just for that,
and replace all NYI with unreachables.
Commit: a8e0afe98853418e1367274e6f04f7ba255de199
https://github.com/llvm/llvm-project/commit/a8e0afe98853418e1367274e6f04f7ba255de199
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/test/CIR/CodeGen/vector-ext-element.cpp
Log Message:
-----------
[CIR] ArraySubscriptExpr on ExtVectorElementExpr (#169158)
Implement ArraySubscriptExpr support for ExtVectorElementExpr
Commit: 2d78b1409eeab558cfc1b64ab39211af00c5f35f
https://github.com/llvm/llvm-project/commit/2d78b1409eeab558cfc1b64ab39211af00c5f35f
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/OpenMPKinds.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/lib/Parse/ParseOpenMP.cpp
A clang/test/OpenMP/need_device_ptr_kind_ast_print.cpp
A clang/test/OpenMP/need_device_ptr_kind_messages.cpp
Log Message:
-----------
[OpenMP][Clang] Parsing/Sema support for `need_device_ptr(fb_nullify/fb_preserve)`. (#168905)
This patch adds parsing, semantic handling, and diagnostics for the
`OpenMP 6.1 fb_nullify` and` fb_preserve` fallback modifiers used with
the `need_device_ptr` map modifier.
Commit: 622dbb372bfefc135c3cdf967ae6f3b55ffa4a16
https://github.com/llvm/llvm-project/commit/622dbb372bfefc135c3cdf967ae6f3b55ffa4a16
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
Log Message:
-----------
AMDGPU: Add more tests for 32-bit constant address space (#168976)
The sub-dword cases just assert now, so comment those out.
Commit: 20ca85b69fc06feb75f67414d54f3830748bb456
https://github.com/llvm/llvm-project/commit/20ca85b69fc06feb75f67414d54f3830748bb456
Author: Jez Ng <me at jezng.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/InputFiles.cpp
M lld/test/MachO/x86-64-relocs.s
Log Message:
-----------
[lld] macho: Support section branch relocations, including the 1-byte form (#169062)
I noticed that we had a hardcoded value of 4 for the pcrel section
relocations, which seems like an issue given that we recently added
support for 1-byte branch relocations in
https://github.com/llvm/llvm-project/pull/164439. The code included an
assert that the relevant relocation had the BYTE4 attribute, but that is
actually not enough to use a hardcoded value of 4: we need to assert
that the *other* `BYTE<n>` attributes are not set either.
However, since we did not support local branch relocations, that doesn't
seem to have mattered in practice. That said, local branch relocations
can be emitted by compilers, and ld64 does handle the 4-byte version of
them, so I've added support for it here.
ld64 actually seems to reject 1-byte section relocations, so the
questionable code is actually probably fine (minus the incorrect
assert). So we have two options: add an equivalent check in LLD, or just
support 1-byte local branch relocations. Supporting it actually requires
less code, so I've gone with that option here.
Commit: 2ee12f191a005363259e3a95ccdf459d9044eadf
https://github.com/llvm/llvm-project/commit/2ee12f191a005363259e3a95ccdf459d9044eadf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/gws_agpr.ll
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
A llvm/test/MC/AMDGPU/ds_gws_sgpr_err.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
Log Message:
-----------
AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)
On targets that require even aligned 64-bit VGPRs, GWS operands
require even alignment of a 32-bit operand. Previously we had a hacky
post-processing which added an implicit operand to try to manage
the constraint. This would require special casing in other passes
to avoid breaking the operand constraint. This moves the handling
into the instruction definition, so other passes no longer need
to consider this edge case. MC still does need to special case this,
to print/parse as a 32-bit register. This also still ends up net
less work than introducing even aligned 32-bit register classes.
This also should be applied to the image special case.
Commit: 3a27fc48117ba7e062c3cfa0006badb64446ed69
https://github.com/llvm/llvm-project/commit/3a27fc48117ba7e062c3cfa0006badb64446ed69
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Omit VTYPE in VSETVLIInfo::print() when state is uninit or unknown. (#169459)
Commit: eab23e199aef18c2052c08171129633233ab98f5
https://github.com/llvm/llvm-project/commit/eab23e199aef18c2052c08171129633233ab98f5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Log Message:
-----------
[RISCV] Don't add Zilsd pairing hints if other part of the pair is reserved. (#169538)
Commit: ebe40066545fd0ad2e88c5e48b7751195d9a9eca
https://github.com/llvm/llvm-project/commit/ebe40066545fd0ad2e88c5e48b7751195d9a9eca
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/CMakeLists.txt
Log Message:
-----------
[mlir] Fix build failure with BUILD_SHARED_LIBS=ON
/usr/bin/ld: tools/mlir/lib/Dialect/GPU/Pipelines/CMakeFiles/obj.MLIRGP
UPipelines.dir/GPUToXeVMPipeline.cpp.o: in function `mlir::gpu::buildLo
werToXeVMPassPipeline(mlir::OpPassManager&, mlir::gpu::GPUToXeVMPipelin
eOptions const&)':
GPUToXeVMPipeline.cpp:(.text._ZN4mlir3gpu28buildLowerToXeVMPassPipeline
ERNS_13OpPassManagerERKNS0_24GPUToXeVMPipelineOptionsE+0x1293): undefin
ed reference to `mlir::createConvertVectorToLLVMPass()'
Commit: 6c48fbc1dcfbd44a47f126f21e575340b67aac06
https://github.com/llvm/llvm-project/commit/6c48fbc1dcfbd44a47f126f21e575340b67aac06
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/test/X86/lit.local.cfg
M bolt/test/lit.local.cfg
Log Message:
-----------
[BOLT][Tests] Use AT&T assembler syntax only for X86 tests (#169541)
Enabling AT&T syntax for all tests is broken when X86 target is not
enabled as reported in #167225.
Commit: 0917a38c694bd2558b79c2b6d51fee2308dd94dd
https://github.com/llvm/llvm-project/commit/0917a38c694bd2558b79c2b6d51fee2308dd94dd
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[PowerPC] Fix a warning
This patch fixes:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15676:17: error: unused
variable 'CC' [-Werror,-Wunused-variable]
Commit: af0fcf85c812867c1d03f390d5afbbbc5b7f1584
https://github.com/llvm/llvm-project/commit/af0fcf85c812867c1d03f390d5afbbbc5b7f1584
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/include/mlir/TableGen/Pattern.h
M mlir/lib/TableGen/Pattern.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
Log Message:
-----------
[mlir][tblgen] Don't echo absolute paths into rewrite pattern source (#168984)
Currently, the declarative pattern rewrite generator will always print
the [source]:[line](s) from which a pattern came. This is a useful
debugging hint, but it causes problem when absolute paths are used as
arguments to mlir-tblgen (which LLVM's build rules automatically do).
Specifially, it causes the source to be tied to the build location,
harning reproducability and our collective ability to get ccache hits
from, say, separate worktrees.
This commit resolves the issue by replacing absolute paths in thes
"Generated from:" comments with their filenames. (The alternative would
have been to implement an entire file-prefix-map the way the C compilers
do, but since this is an isolated incident, I chose to resolve it
locally.)
Commit: 36947982106686570383945c2bbf367f447d9edc
https://github.com/llvm/llvm-project/commit/36947982106686570383945c2bbf367f447d9edc
Author: Sergei Druzhkov <serzhdruzhok at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
Log Message:
-----------
[lldb-dap] Add format support for evaluate request (#169132)
This patch adds support for format option in the `evaluate` request
according to
[DAP](https://microsoft.github.io/debug-adapter-protocol/specification#Requests_Evaluate)
specification. Also, fixed typo in `LLDB_DAP_INVALID_VARRERF` constant.
Commit: 0f941f6866910e55e0e7cff30c48740477be0cd8
https://github.com/llvm/llvm-project/commit/0f941f6866910e55e0e7cff30c48740477be0cd8
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
Log Message:
-----------
[flang][cuda] Add support to allocate scalar character types (#169550)
Add support for character declared like:
```
subroutine sub1()
character*4, device :: b
end subroutine
```
Commit: ad3d9fb3cab7f2e9a7337ca3c1bd0018ff6c6158
https://github.com/llvm/llvm-project/commit/ad3d9fb3cab7f2e9a7337ca3c1bd0018ff6c6158
Author: Petr Penzin <ppenzin at tenstorrent.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
Log Message:
-----------
[RISCV] tt-ascalon-d8 vector scheduling (#167066)
Add the vector scheduling model for tt-ascalon-d8 and corresponding
llvm-mca tests.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 8d920725ca56930d301df1c7e090905423645a49
https://github.com/llvm/llvm-project/commit/8d920725ca56930d301df1c7e090905423645a49
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
Log Message:
-----------
[RISCV] Use FMV.D for moving GPRPairs on RV32_Zdinx (#169556)
This is noted by the specification, and should save a dynamic
instruction.
Code size should be no worse than before, as the pairs of moves can
usually be turned into two 16-bit moves, but `fmv.d` is always a 32-bit
instruction.
LLVM can look through a `FSGNJ_D_IN32X`, in
`RISCVInstrInfo::isCopyInstrImpl` which helps copy propagation.
Commit: dbcf5688cca37543ea3304be68516b3ac476eef3
https://github.com/llvm/llvm-project/commit/dbcf5688cca37543ea3304be68516b3ac476eef3
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
[AMDGPU] Simplify VT comparisons. NFC. (#169526)
Automated with `sed -i 's/\.Value//g' lib/Target/AMDGPU/*.td` plus a
tiny bit of manual reformatting.
Commit: 1c9368e01e6ed45e7dbc523d3bddfd900bb6e504
https://github.com/llvm/llvm-project/commit/1c9368e01e6ed45e7dbc523d3bddfd900bb6e504
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
A clang/test/CIR/CodeGen/copy-constructor.cpp
Log Message:
-----------
[CIR] Upstream non-record array init handling (#169429)
This upstreams the code to handle member initialization for non-record
arrays.
Commit: c475f8e5d809e2109a67c8523472eb28cd7bbb2a
https://github.com/llvm/llvm-project/commit/c475f8e5d809e2109a67c8523472eb28cd7bbb2a
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
A clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
Log Message:
-----------
[HLSL] Update vector swizzle elements individually (#169090)
When individual elements of a vector are updated via vector swizzle, it needs to be handled as separate store operations to the individual vector elements.
Clang treats vectors as one unit, so if a part of a vector needs to be updated, the whole vector is loaded, some elements modified, and then the whole vector is stored.
In HLSL vector elements are handled separately. We need to avoid this load/modify/store sequence to prevent overwriting other vector elements that might be getting updated in parallel.
Fixes #152815
Commit: 091aece72b0149bda6d465301fe3934ca570a592
https://github.com/llvm/llvm-project/commit/091aece72b0149bda6d465301fe3934ca570a592
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[VPlan] Remove redundant transferFlags call from replicateByVF (NFC).
Flags are now passed on construction/cloning. Remove unnecessary
transferFlags call, and make code independent of VPRecipeWithIRFlags, to
support additional recipes in the future.
Commit: 00ffc70ba154b8670fc37d1398ce4473bca3a516
https://github.com/llvm/llvm-project/commit/00ffc70ba154b8670fc37d1398ce4473bca3a516
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
Log Message:
-----------
[SLP][NFC]Add a test with commutative instruction with non-commutative op, NFC
Commit: 074d17e9c8cbc6f22e65ba1211787453ea629ccb
https://github.com/llvm/llvm-project/commit/074d17e9c8cbc6f22e65ba1211787453ea629ccb
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/tsd_shared.h
Log Message:
-----------
[scudo] Lock/unlock MutexTSDs in disable/enable. (#169440)
It is possible that a fork could occur while MutexTSDs is being held and
then cause a deadlock in a forked process when something attempts to
lock it again. Instead add it to the enable/disable list of mutexes.
Commit: e894654532a74b669b0b0830007cc6c979b35d56
https://github.com/llvm/llvm-project/commit/e894654532a74b669b0b0830007cc6c979b35d56
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/addrec-may-wrap-udiv-canonicalize.ll
Log Message:
-----------
[SCEV] Add tests for UDiv canonicalization of AddRecs that may wrap.
Add test cases for canonicalizing AddRecs that may wrap.
Commit: 9bf78ab8dd17ecbbecd4157c67e8fb4d95528194
https://github.com/llvm/llvm-project/commit/9bf78ab8dd17ecbbecd4157c67e8fb4d95528194
Author: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
Revert "[GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`." (#169570)
Reverts llvm/llvm-project#166204
There was a build issue due to a missing dependency.
Commit: 49828c23b59959ca9f2c0dc83aeb9ce7f84b5c31
https://github.com/llvm/llvm-project/commit/49828c23b59959ca9f2c0dc83aeb9ce7f84b5c31
Author: Haowei <haowei at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/cmake/caches/Fuchsia.cmake
Log Message:
-----------
[Fuchsia] Bump minimal OS X target to 11.0 (#169568)
libcxx requires minimal macOS 11 to build. This patch bumps the minimal
OS X target in Fuchsia's cmake cache file to 11.0 to satisfy this
requirement.
Commit: 4f39a4ff0ada92870ca1c2dccad382ea04947da8
https://github.com/llvm/llvm-project/commit/4f39a4ff0ada92870ca1c2dccad382ea04947da8
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCOpsInterfacesTest.cpp
Log Message:
-----------
[acc][flang] Add getInitRegion() to GlobalVariableOpInterface (#169569)
Some globals (e.g., fir.global) have initialization regions that may
transitively reference other globals or type descriptors. Add
getInitRegion() to GlobalVariableOpInterface to retrieve these regions,
returning Region* (nullptr if the global uses attributes for
initialization, as with memref.global).
Commit: 5f777b2c8faca3fe28079fc81a7aefbca1edb803
https://github.com/llvm/llvm-project/commit/5f777b2c8faca3fe28079fc81a7aefbca1edb803
Author: daniilavdeev <daniilavdeev237 at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCSymbol.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/MC/MCSymbol.cpp
A llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
Log Message:
-----------
[dwarf] make dwarf fission compatible with RISCV relaxations 1/2 (#166597)
Currently, -gsplit-dwarf and -mrelax are incompatible options in Clang.
The issue is that .dwo files should not contain any relocations, as they
are not processed by the linker. However, relaxable code emits
relocations in DWARF for debug ranges that reside in the .dwo file when
DWARF fission is enabled.
This patch makes DWARF fission compatible with RISC-V relaxations. It
uses the StartxEndx DWARF forms in .debug_rnglists.dwo, which allow
referencing addresses from .debug_addr instead of using absolute
addresses. This approach eliminates relocations from .dwo files.
Commit: 97023fba5546f9d0e762ccbca89cbb8324a9131a
https://github.com/llvm/llvm-project/commit/97023fba5546f9d0e762ccbca89cbb8324a9131a
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/test/CIR/CodeGen/coro-task.cpp
Log Message:
-----------
[CIR] Emit ready and suspend branches for cir.await (#168814)
This PR adds codegen for `cir.await` ready and suspend. One notable
difference from the classic codegen is that, in the suspend branch, it
emits an `AwaitSuspendWrapper`(`.__await_suspend_wrapper__init`)
function that is always inlined. This function wraps the suspend logic
inside an internal wrapper that gets inlined. Example here:
https://godbolt.org/z/rWYGcaaG4
Commit: ebf5d9ef7de29b55fd9e9d504f83689b4013e0de
https://github.com/llvm/llvm-project/commit/ebf5d9ef7de29b55fd9e9d504f83689b4013e0de
Author: Alan Li <me at alanli.org>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-i8-gep.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-var-delta.ll
R llvm/test/Transforms/StraightLineStrengthReduce/path-compression.ll
R llvm/test/Transforms/StraightLineStrengthReduce/pick-candidate.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll
Log Message:
-----------
Revert "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169546)
This reverts commit f67409c3ec7cd45c55656c8159bc42b3918f1116.
cc @fiigii
Including us, several separate groups are experiencing regressions with
this change. This is the smallest reproducer pasted by @akuegel :
https://github.com/llvm/llvm-project/pull/162930#issuecomment-3574307330
Commit: 9534ed9f30043318798a9544461bc174e273e1f3
https://github.com/llvm/llvm-project/commit/9534ed9f30043318798a9544461bc174e273e1f3
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M orc-rt/include/orc-rt/Error.h
M orc-rt/unittests/ErrorTest.cpp
Log Message:
-----------
[orc-rt] Add ErrorAsOutParameter convenience constructor. (#169467)
Allows construction of ErrorAsOutParameters from Error references.
Commit: fd22706e937f7d2563cfa0e433dd735cc5284599
https://github.com/llvm/llvm-project/commit/fd22706e937f7d2563cfa0e433dd735cc5284599
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
A flang/test/Lower/OpenMP/compiler-directives-loop.f90
Log Message:
-----------
[flang][OpenMP] Skip compiler directives in getCollapsedLoopEval (#169565)
Use `getNestedDoConstruct` from Utils to get the nested DoConstructs.
Fixes https://github.com/llvm/llvm-project/issues/169532
Commit: f7a9fcad99e155fed32d98a2d41d1e3bfdeebf48
https://github.com/llvm/llvm-project/commit/f7a9fcad99e155fed32d98a2d41d1e3bfdeebf48
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/test/Lower/CUDA/cuda-atomicadd.cuf
Log Message:
-----------
[flang][cuda] Use PTX instruction for atomicAdd with 4xf32 (#169581)
Implementation similar to the clang one in
`clang/lib/Headers/__clang_cuda_intrinsics.h`
Commit: 1c034a372403d539700292cd564773ef3531a423
https://github.com/llvm/llvm-project/commit/1c034a372403d539700292cd564773ef3531a423
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
Log Message:
-----------
[compiler-rt] [UBsan] precommit test (#169579)
Commit: 9c414c428d8464c829d551d0d91029339e746842
https://github.com/llvm/llvm-project/commit/9c414c428d8464c829d551d0d91029339e746842
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/CMakeLists.txt
M clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
M clang-tools-extra/clangd/test/index-tools.test
M clang-tools-extra/clangd/test/system-include-extractor.test
Log Message:
-----------
[clangd] Make lit tests work with the internal shell
This makes all of the clangd tests work with the internal shell.
Modifications needed for each test are as follows:
1. system-include-extractor.test was using variable expansion which is
not supported in the internal shell. This patch rewrites it to use
the readfile mechanism along with python. This isn't super pretty but
is readily understandable and there are only two tests across the
monorepo that use this construction, so making it prettier is hard to
justify.
2. include-cleaner-batch-fix.test - Was using $'' construction to create
new lines in a string. Simply replace it with multiple echo commands
to be canonical with the rest of the repository.
3. index-tools.test - Just add IndexBenchmark to the clangd test
depends, so the test now just works unconditionally. This should
significantly increase test coverage at little cost.
Reviewers: ilovepi, HighCommander4, petrhosek, kadircet
Reviewed By: ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/169539
Commit: c51c382c8752e7ba5049ed3662fefb9ffe9283c3
https://github.com/llvm/llvm-project/commit/c51c382c8752e7ba5049ed3662fefb9ffe9283c3
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/lit.cfg.py
Log Message:
-----------
[clangd] Enable lit internal shell by default
Enable it now that all of the tests pass under the internal shell. The
internal shell is slightly faster (10-15%) and also provides a better
debugging experience.
Reviewers: petrhosek, ilovepi, kadircet, HighCommander4
Reviewed By: ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/169540
Commit: 4cfbc44ebe26692c209655c37aeb0b6cbf1d479b
https://github.com/llvm/llvm-project/commit/4cfbc44ebe26692c209655c37aeb0b6cbf1d479b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/lit.cfg.py
Log Message:
-----------
Revert "[clangd] Enable lit internal shell by default"
This reverts commit c51c382c8752e7ba5049ed3662fefb9ffe9283c3.
This breaks at least one buildbot:
1. https://lab.llvm.org/buildbot/#/builders/134/builds/30460
Commit: bd04ef6df50e8e6e5212762fc798ea9fbdcfc897
https://github.com/llvm/llvm-project/commit/bd04ef6df50e8e6e5212762fc798ea9fbdcfc897
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/CMakeLists.txt
M clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
M clang-tools-extra/clangd/test/index-tools.test
M clang-tools-extra/clangd/test/system-include-extractor.test
Log Message:
-----------
Revert "[clangd] Make lit tests work with the internal shell"
This reverts commit 9c414c428d8464c829d551d0d91029339e746842.
This one is causing buildbot failures too at CMake configure time:
1. https://lab.llvm.org/buildbot/#/builders/193/builds/12452
Commit: 3f22ed1152c4c00e95381368ec7d88878f2fd9f9
https://github.com/llvm/llvm-project/commit/3f22ed1152c4c00e95381368ec7d88878f2fd9f9
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M offload/include/OpenMP/InteropAPI.h
M offload/include/PerThreadTable.h
Log Message:
-----------
[OFFLOAD] Add support for indexed per-thread containers (#164263)
Split from #158900 it adds a PerThreadContainer that can use STL-like
indexed containers based on a slightly refactored PerThreadTable.
---------
Co-authored-by: Joseph Huber <huberjn at outlook.com>
Commit: 5d38cddc3b00b428f848fdeddc8334c4560db36a
https://github.com/llvm/llvm-project/commit/5d38cddc3b00b428f848fdeddc8334c4560db36a
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/AST/Expr.cpp
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/CodeGen/scoped-atomic-ops.c
M clang/test/Sema/scoped-atomic-ops.c
Log Message:
-----------
[Clang] Add __scoped_atomic_uinc_wrap and __scoped_atomic_udec_wrap builtins (#168666)
This PR extends __scoped_atomic builtins with inc and dec functions.
They map to LLVM IR `atomicrmw uinc_wrap` and `atomicrmw udec_wrap`.
These enable implementation of OpenCL-style atomic_inc / atomic_dec with
wrap semantics on targets supporting scoped atomics (e.g. GPUs).
---------
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: d889b97f2b1cd7264a5a225edd7daf18c3709bfa
https://github.com/llvm/llvm-project/commit/d889b97f2b1cd7264a5a225edd7daf18c3709bfa
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
Log Message:
-----------
[RISCV][llvm] Support BUILD_VECTOR codegen for P extension (#169083)
Commit: 44c8a011764ae5fb9178d938fc3f1f1bf76bfe49
https://github.com/llvm/llvm-project/commit/44c8a011764ae5fb9178d938fc3f1f1bf76bfe49
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
Log Message:
-----------
[compiler-rt] [UBSan] remove unneeded test cases (#169594)
the target handling will be done in the driver, so removing codegen
tests.
Commit: 175168c620d6a62ab7360693c6415cc1ab1eeb4b
https://github.com/llvm/llvm-project/commit/175168c620d6a62ab7360693c6415cc1ab1eeb4b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Analysis/ThreadSafety.cpp
A clang/test/SemaCXX/no-warn-thread-safety-analysis.cpp
Log Message:
-----------
[Analysis] Make ThreadSafety correctly handle base class destructors (#169593)
Commit: 40f21a7b2f3e7d034cac4a981b09c1a0049df427
https://github.com/llvm/llvm-project/commit/40f21a7b2f3e7d034cac4a981b09c1a0049df427
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
Log Message:
-----------
[llvm][RISCV] Support P Extension CodeGen (#167895)
This patch supports: PSLLI_B, PSLLI_H, PSLLI_W, PSSLAI_H and PSSLAI_W
Commit: 1ea4aa1b91553847ab155f7ed6c22d392d06b38e
https://github.com/llvm/llvm-project/commit/1ea4aa1b91553847ab155f7ed6c22d392d06b38e
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M libclc/clc/lib/generic/atomic/clc_atomic_dec.cl
M libclc/clc/lib/generic/atomic/clc_atomic_def.inc
M libclc/clc/lib/generic/atomic/clc_atomic_inc.cl
Log Message:
-----------
[libclc] Use __scoped_atomic_udec/uinc_wrap to implement _clc_atomic_dec/inc (#168327)
Commit: 222ba6f5ce96d3612b7f62aeacd1d5599fbb8141
https://github.com/llvm/llvm-project/commit/222ba6f5ce96d3612b7f62aeacd1d5599fbb8141
Author: Jan Voung <jvoung at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][dataflow] Handle more glvalue cases of the ConditionalOperator transfer (#168994)
In the dataflow framework, the builtin transfer function currently only
handles the GLValue result case of ConditionalOperator when the
true and false expression StorageLocations are exactly the same.
Ideally / we have wanted to introduce alias sets to handle when the Locs
are different. However, that is a larger change to the framework
(and we may need to introduce weak updates).
For now, do something simpler to at least handle when the GLValue is
immediately cast to an RValue, by making up a distinct StorageLocation
that holds the join of the true and false expression values (when not a
record). This seems like the most common case, so seems worth covering.
The case when an LValue is needed and can be updated later (and
thus needs a link to the original storage locations) seems more rare,
and we currently do not handle such updates either, so this intermediate
step is no different (for that case).
Commit: bfc732efbda2dc1caa78de89600834c083bedd83
https://github.com/llvm/llvm-project/commit/bfc732efbda2dc1caa78de89600834c083bedd83
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M orc-rt/include/orc-rt/Session.h
M orc-rt/lib/executor/Session.cpp
M orc-rt/unittests/SessionTest.cpp
Log Message:
-----------
[orc-rt] Add ControllerAccess interface. (#169598)
ControllerAccess provides an abstract interface for bidirectional RPC
between the executor (running JIT'd code) and the controller (containing
the llvm::orc::ExecutionSession). ControllerAccess implementations are
expected to implement IPC / RPC using a concrete communication method
(shared memory, pipes, sockets, native system IPC, etc).
Calls from executor to controller are made via callController, with
"handler tags" (addresses in the executor) specifying the target handler
in the controller. A handler must be associated in the controller with
the given tag for the call to succeed. This ensures that only registered
entry points in the controller can be used, and avoids leaking
controller addresses into the executor.
Calls in both directions are to "wrapper functions" that take a buffer
of bytes as input and return a buffer of bytes as output. In the ORC
runtime these must be `orc_rt_WrapperFunction`s (see
Session::handleWrapperCall). The interpretation of the byte buffers is
up to the wrapper functions: the ORC runtime imposes no restrictions on
how the bytes are to be interpreted.
ControllerAccess objects may be detached from the Session prior to
Session shutdown, in which case no further calls may be made in either
direction, and any pending results (from calls made that haven't
returned yet) should return errors. If the ControllerAccess class is
still attached at Session shutdown time it will be detached as part of
the shutdown process. The ControllerAccess::disconnect method must
support concurrent entry on multiple threads, and all callers must block
until they can guarantee that no further calls will be received or
accepted.
Commit: e81a564cb0031e93d34a941224b14ec73c69bf65
https://github.com/llvm/llvm-project/commit/e81a564cb0031e93d34a941224b14ec73c69bf65
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/tools/opt/invalid-target.ll
M llvm/tools/opt/optdriver.cpp
Log Message:
-----------
opt: Stop creating TargetMachine to infer the datalayout (#169585)
The Triple directly has the datalayout string in it, so just
use that.
The logical flow here is kind of a mess. We were constructing
a temporary target machine in the asm parser to infer the datalayout,
throwing it away, and then creating another target machine for the
actual compilation. The flow of the Triple construction is still
convoluted, but we can at least drop the TargetMachine.
Commit: 76ec25f729fcc7ae576caf21293cc393e68e7cf7
https://github.com/llvm/llvm-project/commit/76ec25f729fcc7ae576caf21293cc393e68e7cf7
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
Log Message:
-----------
[ORC] Pass FailedSNs by const-ref. NFCI. (#169600)
Avoids a vector copy.
Commit: 4e7c65e85f47443ab3af729e5cf8e693081abb87
https://github.com/llvm/llvm-project/commit/4e7c65e85f47443ab3af729e5cf8e693081abb87
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Log Message:
-----------
[RISCV] Don't add duplicate Zilsd hints. (#169554)
This matches what ARM does. I'm not sure if there are any bad effects
from the duplicate hints. I have seen the duplicates hints in the debug
output and confirmed this removes them.
Commit: a7f9a4db895561b7bf4a1b91fe306b29fd61af6c
https://github.com/llvm/llvm-project/commit/a7f9a4db895561b7bf4a1b91fe306b29fd61af6c
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
Log Message:
-----------
[AMDGPU] Update strict floating point tests to be more comprehensive (#169578)
Commit: a57fe84af0679871d914e0d5fc3f449069f22a19
https://github.com/llvm/llvm-project/commit/a57fe84af0679871d914e0d5fc3f449069f22a19
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/TextNodeDumper.cpp
A clang/test/AST/ast-dump-APValue-addrlabeldiff.c
Log Message:
-----------
[clang] Implement dump() for AddrLabelDiff APValues (#169505)
Commit: 8396d4c10e98fedba5d8f6861087078b2de49674
https://github.com/llvm/llvm-project/commit/8396d4c10e98fedba5d8f6861087078b2de49674
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
Log Message:
-----------
[clang][bytecode][NFC] Clean up Integral::from() functions (#169513)
Commit: 6459f39c377dc8b7d5d81ef365553c8625fb4def
https://github.com/llvm/llvm-project/commit/6459f39c377dc8b7d5d81ef365553c8625fb4def
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/BitcastBuffer.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode] Add some convenience API to BitcastBuffer (#169516)
So we check the offsets before using them.
Commit: 00aca530b1e49281f461965a304a8a36cb41142d
https://github.com/llvm/llvm-project/commit/00aca530b1e49281f461965a304a8a36cb41142d
Author: Dominik Adamski <dominik.adamski at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M flang-rt/cmake/modules/HandleLibs.cmake
Log Message:
-----------
[Flang-rt] Remove COMPILE_ONLY from flang-rt CMake file. (#169534)
COMPILE_ONLY was introduced in cmake 3.27.0. We cannot use this feature,
because LLVM supports cmake 3.20.0.
Commit: e04c01bcc91226d632f81bd3290c180deb0b6db8
https://github.com/llvm/llvm-project/commit/e04c01bcc91226d632f81bd3290c180deb0b6db8
Author: Fangrui Song <i at maskray.me>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCMachOStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCWasmStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp
Log Message:
-----------
MC: Remove unneeded parameter `MCAsmBackend *`. NFC
Commit: 97732ddb5d921a7d5cd6ffc2a23438b607c0d3f6
https://github.com/llvm/llvm-project/commit/97732ddb5d921a7d5cd6ffc2a23438b607c0d3f6
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Program.h
Log Message:
-----------
[clang][bytecode][NFC] Make Program::getNativePointer() const (#169502)
Commit: e493e90a890d92cb13090710d74bb16b3e1075f8
https://github.com/llvm/llvm-project/commit/e493e90a890d92cb13090710d74bb16b3e1075f8
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
Log Message:
-----------
[lldb][NFC] Fix incorrect comments in TestArm64InstEmulation
Commit: 93f2deb1d0a886672683e1e6df9797d11cddf7c5
https://github.com/llvm/llvm-project/commit/93f2deb1d0a886672683e1e6df9797d11cddf7c5
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vle.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/addcarry.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/allow-check.ll
M llvm/test/CodeGen/RISCV/arith-with-overflow.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bitreverse-shift.ll
M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
M llvm/test/CodeGen/RISCV/bswap-shift.ll
M llvm/test/CodeGen/RISCV/clear-cache.ll
M llvm/test/CodeGen/RISCV/copy-frameindex.mir
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-zfa.ll
M llvm/test/CodeGen/RISCV/double_reduct.ll
M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
M llvm/test/CodeGen/RISCV/fixed-csr.ll
M llvm/test/CodeGen/RISCV/float-arith-strict.ll
M llvm/test/CodeGen/RISCV/float-arith.ll
M llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-convert-strict.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/float-select-verify.ll
M llvm/test/CodeGen/RISCV/float-zfa.ll
M llvm/test/CodeGen/RISCV/flt-rounds.ll
M llvm/test/CodeGen/RISCV/fmax-fmin.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/fpenv.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/frm-dependency.ll
M llvm/test/CodeGen/RISCV/get-register-invalid.ll
M llvm/test/CodeGen/RISCV/get-register-noreserve.ll
M llvm/test/CodeGen/RISCV/get-register-reserve.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/half-zfa.ll
M llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
M llvm/test/CodeGen/RISCV/i64-icmp.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll
M llvm/test/CodeGen/RISCV/intrinsics/trap.ll
M llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/machine-combiner.ll
M llvm/test/CodeGen/RISCV/machine-cse.ll
M llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll
M llvm/test/CodeGen/RISCV/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/memset-inline.ll
M llvm/test/CodeGen/RISCV/min-max.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/module-target-abi3.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsic-optimizations.ll
M llvm/test/CodeGen/RISCV/pei-crash.ll
M llvm/test/CodeGen/RISCV/pr135206.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/pr92193.ll
M llvm/test/CodeGen/RISCV/prefetch.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/readcyclecounter.ll
M llvm/test/CodeGen/RISCV/readsteadycounter.ll
M llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/replace-with-veclib-sleef-scalable.ll
M llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbkx-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
M llvm/test/CodeGen/RISCV/rv64-float-convert.ll
M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-args.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-frame-setup.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
M llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbkx-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
M llvm/test/CodeGen/RISCV/rvv/commutable.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-negative.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvw.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll
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M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vp-fsub-and-vp-fmul.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
M llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/fshr-fshl.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/llround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/lround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/marith-vp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int-e64.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int-e64.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-crash-zvl32b.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mixed-float-bf16-arith.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/pr63459.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
M llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
M llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfwmacc_4x4x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
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M llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
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M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
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M llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll
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M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
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M llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
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M llvm/test/CodeGen/RISCV/rvv/vcpopv.ll
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M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-bf.ll
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M llvm/test/CodeGen/RISCV/rvv/vmfle-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu.ll
M llvm/test/CodeGen/RISCV/rvv/vmnand.ll
M llvm/test/CodeGen/RISCV/rvv/vmnor.ll
M llvm/test/CodeGen/RISCV/rvv/vmor.ll
M llvm/test/CodeGen/RISCV/rvv/vmorn.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmset.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsif.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vmsof.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul.ll
M llvm/test/CodeGen/RISCV/rvv/vmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.x.s.ll
M llvm/test/CodeGen/RISCV/rvv/vmxnor.ll
M llvm/test/CodeGen/RISCV/rvv/vmxor.ll
M llvm/test/CodeGen/RISCV/rvv/vnclip.ll
M llvm/test/CodeGen/RISCV/rvv/vnclipu.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vor.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vqdot.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotsu.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotu.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotus.ll
M llvm/test/CodeGen/RISCV/rvv/vredand.ll
M llvm/test/CodeGen/RISCV/rvv/vredmax.ll
M llvm/test/CodeGen/RISCV/rvv/vredmaxu.ll
M llvm/test/CodeGen/RISCV/rvv/vredmin.ll
M llvm/test/CodeGen/RISCV/rvv/vredminu.ll
M llvm/test/CodeGen/RISCV/rvv/vredor.ll
M llvm/test/CodeGen/RISCV/rvv/vredsum.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vredxor.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu.ll
M llvm/test/CodeGen/RISCV/rvv/vrev8.ll
M llvm/test/CodeGen/RISCV/rvv/vrgather.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll
M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrol.ll
M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vror.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
M llvm/test/CodeGen/RISCV/rvv/vse.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-valid-elen-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvlmax-ext.ll
M llvm/test/CodeGen/RISCV/rvv/vsext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsext.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
M llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1down-constant-vl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1up-constant-vl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/vslidedown.ll
M llvm/test/CodeGen/RISCV/rvv/vslideup.ll
M llvm/test/CodeGen/RISCV/rvv/vsll.ll
M llvm/test/CodeGen/RISCV/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/rvv/vsm3c.ll
M llvm/test/CodeGen/RISCV/rvv/vsm3me.ll
M llvm/test/CodeGen/RISCV/rvv/vsm4k.ll
M llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
M llvm/test/CodeGen/RISCV/rvv/vsmul.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsra.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssub.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccus.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/vwredsum.ll
M llvm/test/CodeGen/RISCV/rvv/vwredsumu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vxor.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vzext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vzext.ll
M llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xv.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvv.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvw.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqa.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqasu.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqau.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqaus.ll
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
M llvm/test/CodeGen/RISCV/sadd_sat.ll
M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/saverestore.ll
M llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/simplify-condbr.ll
M llvm/test/CodeGen/RISCV/ssub_sat.ll
M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/thread-pointer.ll
M llvm/test/CodeGen/RISCV/uadd_sat.ll
M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/RISCV/usub_sat.ll
M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
M llvm/test/CodeGen/RISCV/vlenb.ll
M llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xcvalu.ll
M llvm/test/CodeGen/RISCV/xcvbitmanip.ll
M llvm/test/CodeGen/RISCV/xcvmac.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
M llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll
Log Message:
-----------
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
As @mshockwave mentioned in
https://github.com/llvm/llvm-project/pull/156415, we don't need to
declare intrinsics in tests now, this pr removes them.
Commit: de674fb6c250608197a70ae3fdef5519597054f6
https://github.com/llvm/llvm-project/commit/de674fb6c250608197a70ae3fdef5519597054f6
Author: David Green <david.green at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/addtruncshift.ll
Log Message:
-----------
[AArch64] Add vector tests for add(trunc(shift))
Commit: 19655231718929362f338fb73a6d4ae587ad927e
https://github.com/llvm/llvm-project/commit/19655231718929362f338fb73a6d4ae587ad927e
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir][tensor] Add new builders for insert_slice/extract_slice Ops (nfc) (#169533)
Adds new builders for `tensor.insert_slice` and `tensor.extract_slice`
Ops for which the _offsets_ and the _strides_ are all 0s and 1s,
respecitvely. This allows us to write:
```cpp
// No offsets and no strides - implicitly set to 0s and 1s,
// respectively.
tensor::InsertSliceOp::create(rewriter, loc, src, dest, writeSizes);
```
instead of:
```cpp
// Strides are initialised explicitly to 1s
Attribute oneIdxAttr = rewriter.getIndexAttr(1);
SmallVector<OpFoldResult> writeStrides(destRank, oneIdxAttr);
// Offsets are initialised explicitly to 0s
Attribute zeroIdxAttr = rewriter.getIndexAttr(0);
SmallVector<OpFoldResult> writeOffsets(destRank, zeroIdxAttr);
tensor::InsertSliceOp::create(rewriter, loc, src, dest, writeOffsets,
writeSizes, writeStrides);
```
Commit: 76079ecc891e2781168d9a92a4ff024aaffa77db
https://github.com/llvm/llvm-project/commit/76079ecc891e2781168d9a92a4ff024aaffa77db
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaExprCXX.cpp
A clang/test/Sema/AArch64/sve-vector-conditional-op.cpp
Log Message:
-----------
[clang][Sema] Merge Check[Sizeless]VectorConditionalTypes implementations (#169165)
These two functions are almost identical, except for the handling
different vector types, so merging them eliminates some duplication.
This also fixes some bugs, as "sizeless" vector code was missing checks
for several cases.
This meant type checking would crash if:
- The LHS or RHS type was void
- The LHS or RHS type was a fixed-length vector type
- There was not a scalable vector type for the result element count/size
These are fixed with this patch and tested in
Sema/AArch64/sve-vector-conditional-op.cpp.
Fixes #169025
Commit: 63e4b8c64105ea429f0d35f82b8492d6526b8c54
https://github.com/llvm/llvm-project/commit/63e4b8c64105ea429f0d35f82b8492d6526b8c54
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
Log Message:
-----------
[clang][bytecode][NFC] Remove unused Integral range functions (#169508)
Commit: f481f5bef90d0dd10a9d885b2e4bbfd015e6606d
https://github.com/llvm/llvm-project/commit/f481f5bef90d0dd10a9d885b2e4bbfd015e6606d
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
M flang/test/Lower/OpenMP/delayed-privatization-reduction-byref.f90
M flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array-lb.f90
M flang/test/Lower/OpenMP/parallel-reduction-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array2.f90
M flang/test/Lower/OpenMP/parallel-reduction-pointer-array.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/reduction-array-intrinsic.f90
M flang/test/Lower/OpenMP/sections-array-reduction.f90
M flang/test/Lower/OpenMP/taskgroup-task-array-reduction.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-lb.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-lb2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-multiple-clauses.f90
M flang/test/Lower/OpenMP/wsloop-reduction-pointer.f90
M flang/test/Lower/do_concurrent_reduce_allocatable.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/allocatable_gpu_reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-block-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-reduction.mlir
Log Message:
-----------
[OpenMP][flang] Add initial support for by-ref reductions on the GPU (#165714)
Adds initial support for GPU by-ref reductions. The main problem for
reduction by reference is that, prior to this PR, we were shuffling
(from remote lanes within the same warp or across different warps within
the block) pointers/references to the private reduction values rather
than the private reduction values themselves.
In particular, this diff adds support for reductions on scalar
allocatables where reductions happen on loops nested in `target`
regions. For example:
```fortran
integer :: i
real, allocatable :: scalar_alloc
allocate(scalar_alloc)
scalar_alloc = 0
!$omp target map(tofrom: scalar_alloc)
!$omp parallel do reduction(+: scalar_alloc)
do i = 1, 1000000
scalar_alloc = scalar_alloc + 1
end do
!$omp end target
```
This PR supports by-ref reductions on the intra- and inter-warp levels.
So far, there are still steps to be takens for full support of by-ref
reductions, for example:
* Support inter-block value combination is still not supported.
Therefore, `target teams distribute parallel do` is still not supported.
* Support for dynamically-sized arrays still needs to be added.
* Support for more than one allocatable/array on the same `reduction`
clause.
Commit: c43ac96331bc309c2a92ae20a7ae5fadfecbd073
https://github.com/llvm/llvm-project/commit/c43ac96331bc309c2a92ae20a7ae5fadfecbd073
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaAttr.cpp
Log Message:
-----------
[LifetimeSafety] Move GSL pointer/owner type detection to LifetimeAnnotations (#169620)
Refactored GSL pointer and owner type detection functions to improve code organization and reusability.
Commit: 3036de77239f0b29b3619ff6e468ccf5845c7e91
https://github.com/llvm/llvm-project/commit/3036de77239f0b29b3619ff6e468ccf5845c7e91
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
A llvm/test/Analysis/LoopCacheAnalysis/crash-after-pr164798.ll
Log Message:
-----------
[LoopCacheAnalysis] Fix crash after #164798 (#169486)
Fix the assertion failure after #164798. The issue is that the
comparison `Sizes.back() == ElementSize` can fail when their types are
different. We should cast them to the wider type before the comparison.
Commit: c0a7b15d0158a79786a38f5e94fa8315d4c9f0fe
https://github.com/llvm/llvm-project/commit/c0a7b15d0158a79786a38f5e94fa8315d4c9f0fe
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/pr39160.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-uniform-load.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/nsw-crash.ll
M llvm/test/Transforms/LoopVectorize/scev-exitlim-crash.ll
M llvm/test/Transforms/LoopVectorize/value-ptr-bug.ll
M llvm/test/Transforms/LoopVectorize/vector-to-scalar-cast.ll
M llvm/test/Transforms/LoopVectorize/version-mem-access.ll
Log Message:
-----------
[LV][NFC] Remove remaining uses of undef in tests (#169357)
Split off from PR #163525, this standalone patch replaces almost all the
remaining cases where undef is used as value in loop vectoriser tests.
This will reduce the likelihood of contributors hitting the `undef
deprecator` warning in github.
NOTE: The remaining use of undef in iv_outside_user.ll will be fixed in
a separate PR.
I've removed the test stride_undef from version-mem-access.ll, since
there is already a stride_poison test.
Commit: 04bddda08ab2126f74c902f6630c133382170001
https://github.com/llvm/llvm-project/commit/04bddda08ab2126f74c902f6630c133382170001
Author: Steven Perron <stevenperron at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-array.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-simple.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-struct.ll
Log Message:
-----------
[SPIRV] Improve Logical SPIR-V Pointer Access and GEP Legalization (#169076)
This commit improves the handling of GetElementPtr (GEP) instructions
for
Logical SPIR-V. It includes:
- Rewriting of GEPs that are not allowed in Logical SPIR-V
(specifically,
handling non-zero first indices by rebuilding access chains or adjusting
types).
- Better deduction of element types for pointer casting.
- Updates to instruction selection to ensure GEPs are correctly lowered
to
OpAccessChain or OpInBoundsAccessChain only when valid (e.g. first index
0).
- Support for standard HLSL cbuffer layouts in tests.
Commit: 2d4a8dadba88889ca19adee4fbf907d8c5a40282
https://github.com/llvm/llvm-project/commit/2d4a8dadba88889ca19adee4fbf907d8c5a40282
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilogue-vectorization-fix-scalar-resume-values.ll
M llvm/test/Transforms/LoopVectorize/AArch64/f128-fmuladd-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/licm-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr151664-cost-hoisted-vector-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-fixed-width-inorder-core.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-multi-block.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-unroll.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-loop-backedge-elimination-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/LoongArch/defaults.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
M llvm/test/Transforms/LoopVectorize/X86/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-step.ll
M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
M llvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll
M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
M llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/pr23997.ll
M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
M llvm/test/Transforms/LoopVectorize/X86/pr47437.ll
M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/X86/widened-value-used-as-scalar-and-first-lane.ll
M llvm/test/Transforms/LoopVectorize/assume.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/cse-casts.ll
M llvm/test/Transforms/LoopVectorize/cse-gep-source-element-type.ll
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
M llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
M llvm/test/Transforms/LoopVectorize/expand-scev-after-invoke.ll
M llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
M llvm/test/Transforms/LoopVectorize/if-reduction.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleave-with-i65-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-nested-loop.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/minimumnum-maximumnum-reductions.ll
M llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/noalias-scope-decl.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/pr37248.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-odd-interleave-counts.ll
M llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/reverse-induction-gep-nowrap-flags.ll
M llvm/test/Transforms/LoopVectorize/reverse_induction.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
M llvm/test/Transforms/LoopVectorize/select-cmp.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-hint.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
M llvm/test/Transforms/LoopVectorize/struct-return-replicate.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-outside-iv-users.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll
A llvm/test/Transforms/LoopVectorize/vector-pointer-gep-idxty-addrspace.ll
Log Message:
-----------
[VPlan] Use DL index type consistently for GEPs (#169396)
In preparation to strip VPUnrollPartAccessor and unroll recipes
directly, strip unnecessary complication in getGEPIndexTy, as the unroll
part will no longer be available in follow-ups (see #168886 for
instance). The patch also helps by doing a mass test update up-front.
Narrowing the GEP index type conditionally does not yield any benefit,
and the change is non-functional in terms of emitted assembly. While at
it, avoid hard-coding address-space 0, and use the pointer operand's
address space to get the GEP index type.
Commit: 800da10a3a697922042303daa4fe3e06aea34729
https://github.com/llvm/llvm-project/commit/800da10a3a697922042303daa4fe3e06aea34729
Author: J. Ryan Stinnett <jryans at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DebugOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/DebugInfo/Generic/dbg-info-all-calls-described.c
M clang/test/Driver/debug-options.c
Log Message:
-----------
[clang][DebugInfo] Add call site debug info flag (#169574)
This adds a default enabled flag to control attachment of call site
debug info. `-gno-call-site-info` can be used to disable this feature
when needed.
This should help those concerned about debug info size in
https://github.com/llvm/llvm-project/issues/168851.
Commit: d090311aa7df7cbd93412c31685893aefc4ad341
https://github.com/llvm/llvm-project/commit/d090311aa7df7cbd93412c31685893aefc4ad341
Author: Naveen Seth Hanig <naveen.hanig at outlook.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/Compiler.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/CommonArgs.h
A clang/include/clang/Driver/CreateASTUnitFromArgs.h
A clang/include/clang/Driver/CreateInvocationFromArgs.h
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Frontend/CompilerInvocation.h
A clang/include/clang/Frontend/StandaloneDiagnostic.h
M clang/include/clang/Frontend/Utils.h
M clang/include/clang/Options/OptionUtils.h
M clang/lib/CrossTU/CMakeLists.txt
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Driver/CMakeLists.txt
A clang/lib/Driver/CreateASTUnitFromArgs.cpp
A clang/lib/Driver/CreateInvocationFromArgs.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CMakeLists.txt
M clang/lib/Frontend/CompilerInvocation.cpp
R clang/lib/Frontend/CreateInvocationFromCommandLine.cpp
A clang/lib/Frontend/StandaloneDiagnostic.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Options/OptionUtils.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/tools/c-index-test/CMakeLists.txt
M clang/tools/c-index-test/core_main.cpp
M clang/tools/diagtool/CMakeLists.txt
M clang/tools/diagtool/ShowEnabledWarnings.cpp
M clang/tools/driver/cc1_main.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexer.cpp
M clang/tools/libclang/CMakeLists.txt
M clang/tools/libclang/Indexing.cpp
M clang/unittests/Driver/DXCModeTest.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M clang/unittests/Frontend/UtilsTest.cpp
M clang/unittests/Sema/CMakeLists.txt
M clang/unittests/Sema/SemaNoloadLookupTest.cpp
M clang/unittests/Serialization/ForceCheckFileInputTest.cpp
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Serialization/NoCommentsTest.cpp
M clang/unittests/Serialization/PreambleInNamedModulesTest.cpp
M clang/unittests/Serialization/VarDeclConstantInitTest.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
M clang/unittests/Tooling/Syntax/TreeTestBase.cpp
M flang/lib/Frontend/CMakeLists.txt
M flang/lib/Frontend/CompilerInvocation.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangHost.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/unittests/Expression/ClangParserTest.cpp
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
Reland "[clang] Refactor to remove clangDriver dependency from clangFrontend and flangFrontend" (#169599)
This relands #165277 by reverting #169397.
This also relands the corresponding Bazel port by reverting #169410.
The original revert was due to a report of a broken build, which was
later resolved by fully clearing the build directory.
Commit: cc1c41724ddab0112937e30e1eaa984595b7f48e
https://github.com/llvm/llvm-project/commit/cc1c41724ddab0112937e30e1eaa984595b7f48e
Author: daniilavdeev <daniilavdeev237 at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
Log Message:
-----------
[dwarf] make dwarf fission compatible with RISCV relaxations 2/2 (#164813)
This patch makes DWARF fission compatible with RISC-V relaxations by
using indirect addressing for the DW_AT_high_pc attribute. This
eliminates the remaining relocations in .dwo files.
Commit: bbbe511ea2f8d6e4f3977ef1bb28a4fb30323f9a
https://github.com/llvm/llvm-project/commit/bbbe511ea2f8d6e4f3977ef1bb28a4fb30323f9a
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
A clang/test/Driver/hip-spirv-backend-bindings.c
A clang/test/Driver/hip-spirv-backend-opt.c
A clang/test/Driver/hip-spirv-backend-phases.c
Log Message:
-----------
Reland "[clang][Driver] Support for the SPIR-V backend when compiling HIP" (#169637)
This relands "[clang][Driver] Support for the SPIR-V backend when compiling HIP" #167543. The only new change is a small fix for the multicall driver.
For HIP, the SPIR-V backend can be optionally activated with the -use-spirv-backend flag. This option uses the SPIR-V BE instead of the SPIR-V translator. These changes also ensure that -use-spirv-backend does not require external dependencies, such as spirv-as and spirv-link
Commit: 2b8d363ac1a8cca21c32afc039cb28f0f1608300
https://github.com/llvm/llvm-project/commit/2b8d363ac1a8cca21c32afc039cb28f0f1608300
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/Delinearization.h
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/lib/Analysis/Delinearization.cpp
Log Message:
-----------
[Delinearization] Remove tryDelinearizeFixedSizeImpl (#169046)
`tryDelinearizeFixedSizeImpl` is a heuristic function relying on GEP's
type information. Using these information to drive an optimization
heuristic is not allowed, so this function should be removed. As #161822
and #164798 have eliminated all calls to this, this patch removes the
function itself.
Commit: 23f90304507612fde6d4afb79e58dd4283b7be49
https://github.com/llvm/llvm-project/commit/23f90304507612fde6d4afb79e58dd4283b7be49
Author: Md Abdullah Shahneous Bari <md.abdullah.shahneous.bari at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
Reland: [GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`. (#169573)
`convert-vector-to-llvm` pass applies a set of vector transformation
patterns that are not included in the standard `convert-to-llvm` pass
interface. These additional transformations are required to properly
lower MLIR vector operations. Since not all vector ops have direct
`llvm` dialect lowering, many of them must first be progressively
rewritten into simpler or more canonical vector ops, which are then
lowered to `llvm`. Therefore, running `convert-vector-to-llvm` is
necessary to ensure a complete and correct lowering of vector operations
to the `llvm` dialect.
Original PR: https://github.com/llvm/llvm-project/pull/166204 +
post-commit failure fixes.
Commit: 0a35f44f58f322dece584265e252e21b3ca03530
https://github.com/llvm/llvm-project/commit/0a35f44f58f322dece584265e252e21b3ca03530
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaExpr.cpp
M clang/test/SemaHIP/amdgpu-gfx950-load-to-lds.hip
Log Message:
-----------
[HIP] Perform implicit pointer cast when compiling HIP, not when -fcuda-is-device (#165387)
When compiling HIP device code, we add implicit casts for the pointer arguments passed to built-in calls.
When compiling for the host, apply the same casts, since the device side of the source (device functions and kernels) should still pass type checks.
Commit: e3de8ff548a84645141fe16fad156525604c12ca
https://github.com/llvm/llvm-project/commit/e3de8ff548a84645141fe16fad156525604c12ca
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
Log Message:
-----------
[gn build] Port d090311aa7df
Commit: 4cc8cc81e3aa10e01ce6d54321cbddbc64f1bd15
https://github.com/llvm/llvm-project/commit/4cc8cc81e3aa10e01ce6d54321cbddbc64f1bd15
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads.ll
Log Message:
-----------
[VPlan] Hoist predicated loads with complementary masks. (#168373)
This patch adds a new VPlan transformation to hoist predicated loads, if
we can prove they execute unconditionally, i.e. there are 2 predicated
loads to the same address with complementary masks. Then we are
guaranteed to execute one of them on each iteration, allowing us to
remove the mask.
The transform groups masked replicating loads by their address SCEV,
then checks if there are 2 loads with complementary mask. If that is the
case, we check if there are any writes that may alias the load address
in the blocks between the first and last load with the same address.
The transforms operates after linearizing the CFG, but before
introducing replicate regions, which means this is just checking a chain
of consecutive blocks.
Currently this only uses noalias metadata to check for no-alias (using
the helpers added in https://github.com/llvm/llvm-project/pull/166247).
Then we create an unpredicated VPReplicateRecipe at the position of the
first load, then replace all users of the grouped loads with it.
Small Alive2 proof for hoisting with complementary masks:
https://alive2.llvm.org/ce/z/kUx742
PR: https://github.com/llvm/llvm-project/pull/168373
Commit: 637f206241756e769c5cf84da27aacc217549a52
https://github.com/llvm/llvm-project/commit/637f206241756e769c5cf84da27aacc217549a52
Author: Marco Elver <elver at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
M llvm/include/llvm/Support/AllocToken.h
M llvm/lib/Support/AllocToken.cpp
Log Message:
-----------
[Support] Add getAllocTokenModeAsString() helper (#169650)
Add a helper function getAllocTokenModeAsString() to convert
AllocTokenMode values to their string representation.
NFC.
Commit: b20d35c4a2b01090e54b8732a3a9d5b69de3e10c
https://github.com/llvm/llvm-project/commit/b20d35c4a2b01090e54b8732a3a9d5b69de3e10c
Author: David Green <david.green at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/addtruncshift.ll
Log Message:
-----------
[AArch64] Combine vector add(trunc(shift)) (#169523)
This adds a combine for
add(trunc(ashr(A, C)), trunc(lshr(A, BW-1))), with C >= BW
->
X = trunc(ashr(A, C)); add(x, lshr(X, BW-1)
The original converts into ashr+lshr+xtn+xtn+add. The second becomes
ashr+xtn+usra. The first form has less total latency due to more
parallelism,
but more micro-ops and seems to be slower in practice.
Commit: cd1ad5a9e08800043f03f73348b56372a983afa2
https://github.com/llvm/llvm-project/commit/cd1ad5a9e08800043f03f73348b56372a983afa2
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
Log Message:
-----------
[CIR] Add missing switch cases for AO__scoped_atomic_uinc/udec_wrap in emitAtomicOp (#169610)
Fix build error: enumeration values 'AO__scoped_atomic_udec_wrap' and
'AO__scoped_atomic_uinc_wrap' not handled in switch [-Werror,-Wswitch]
The two builtins were added in 5d38cddc3b00.
Commit: de4e12849bae65699f705bbf10110366ab36dfc4
https://github.com/llvm/llvm-project/commit/de4e12849bae65699f705bbf10110366ab36dfc4
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
[BOLT] Fix assertion test (#169635)
The AArch64_BTI MCPlusBuilder unittest was failing in no assertion
builds. Add `#ifndef NDEBUG` to exclude the assertion test from
no assertion builds.
Commit: 75ae0e882d923fd08360380e010935dd3e960a1b
https://github.com/llvm/llvm-project/commit/75ae0e882d923fd08360380e010935dd3e960a1b
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[OpenMP] Add docs for fb_nullify/fb_preserve (#169558)
Adding documentation following the merge of
https://github.com/llvm/llvm-project/pull/168905.
Commit: ff0c347d003098db82db312d5da8ac925c0002dd
https://github.com/llvm/llvm-project/commit/ff0c347d003098db82db312d5da8ac925c0002dd
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
A llvm/test/tools/opt/infer-data-layout-target-abi.ll
M llvm/tools/opt/optdriver.cpp
Log Message:
-----------
opt: Try to respect target-abi command line option (#169604)
Mips seems kind of broken with these options. n32 seems to
override the 64-bit arch with 32-bit pointers, and trying
to use any 32-bit mips triple also just errors with any
options.
Commit: 35dfeb7b4d720f16e9ded25527a0631d63736d78
https://github.com/llvm/llvm-project/commit/35dfeb7b4d720f16e9ded25527a0631d63736d78
Author: Steven Perron <stevenperron at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/SPIRV/OpVariable_order.ll
M llvm/test/CodeGen/SPIRV/SpecConstants/restore-spec-type.ll
M llvm/test/CodeGen/SPIRV/basic_float_types.ll
M llvm/test/CodeGen/SPIRV/basic_int_types.ll
M llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll
M llvm/test/CodeGen/SPIRV/builtin_intrinsics_32.ll
M llvm/test/CodeGen/SPIRV/builtin_intrinsics_64.ll
M llvm/test/CodeGen/SPIRV/builtin_vars-decorate.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
M llvm/test/CodeGen/SPIRV/event-zero-const.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/decoration.ll
M llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
M llvm/test/CodeGen/SPIRV/freeze.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/AddUint64.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll
M llvm/test/CodeGen/SPIRV/instructions/insertvalue-undef-ptr.ll
M llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll
R llvm/test/CodeGen/SPIRV/keep-tracked-const.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/bitreverse_small_type.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/lifetime.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/uadd.with.overflow.ll
M llvm/test/CodeGen/SPIRV/logical-access-chain.ll
M llvm/test/CodeGen/SPIRV/logical-struct-access.ll
M llvm/test/CodeGen/SPIRV/phi-insert-point.ll
M llvm/test/CodeGen/SPIRV/phi-ptrcast-dominate.ll
M llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll
M llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll
M llvm/test/CodeGen/SPIRV/pointers/gep-types-1.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll
M llvm/test/CodeGen/SPIRV/pointers/global-addrspacecast.ll
M llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll
M llvm/test/CodeGen/SPIRV/pointers/phi-chain-types.ll
M llvm/test/CodeGen/SPIRV/pointers/pointer-addrspacecast.ll
M llvm/test/CodeGen/SPIRV/pointers/ptr-eq-types.ll
M llvm/test/CodeGen/SPIRV/pointers/resource-vector-load-store.ll
M llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll
A llvm/test/CodeGen/SPIRV/remove-dead-type-intrinsics.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse-subbyte.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpGenericCastToPtr.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpPtrCastToGeneric.ll
M llvm/test/CodeGen/SPIRV/transcoding/fcmp.ll
M llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll
M llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
Log Message:
-----------
[SPIRV] Enable DCE in instruction selection and update tests (#168428)
The instruction selection pass for SPIR-V now performs dead code
elimination (DCE).
This change removes unused instructions, leading to more optimized
SPIR-V output.
As a consequence of this, several tests were updated to ensure their
continued
correctness and to prevent previously tested code from being optimized
away.
Specifically:
- Many tests now store computed values into global variables to ensure
they are
not eliminated by DCE, allowing their code generation to be verified.
- The test `keep-tracked-const.ll` was removed because it no longer
tested
its original intent. The check statements in this test were for
constants
generated when expanding a G_TRUNC instruction, which is now removed by
DCE
instead of being expanded.
- A new test, `remove-dead-type-intrinsics.ll`, was added to confirm
that dead
struct types are correctly removed by the compiler.
These updates improve the SPIR-V backends optimization capabilities and
maintain the robustness of the test suite.
---------
Co-authored-by: Nathan Gauër <github at keenuts.net>
Commit: 0c2701fe7fa002e1befc5f86c268a7964f96d286
https://github.com/llvm/llvm-project/commit/0c2701fe7fa002e1befc5f86c268a7964f96d286
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AMDGPU/R600.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/ARM/ARM.td
M llvm/lib/Target/AVR/AVR.td
M llvm/lib/Target/BPF/BPF.td
M llvm/lib/Target/CSKY/CSKY.td
M llvm/lib/Target/DirectX/DirectX.td
M llvm/lib/Target/Hexagon/Hexagon.td
M llvm/lib/Target/Lanai/Lanai.td
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/M68k/M68k.td
M llvm/lib/Target/MSP430/MSP430.td
M llvm/lib/Target/Mips/Mips.td
M llvm/lib/Target/NVPTX/NVPTX.td
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/SPIRV/SPIRV.td
M llvm/lib/Target/Sparc/Sparc.td
M llvm/lib/Target/SystemZ/SystemZ.td
M llvm/lib/Target/VE/VE.td
M llvm/lib/Target/WebAssembly/WebAssembly.td
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/XCore/XCore.td
M llvm/lib/Target/Xtensa/Xtensa.td
Log Message:
-----------
CodeGen: Make all targets override pseudos with pointers (#159881)
This eliminates the need to have PointerLikeRegClass handling in
codegen.
Commit: 6e983e3876afe5e502d96cef3d4b0fbb7cd068ed
https://github.com/llvm/llvm-project/commit/6e983e3876afe5e502d96cef3d4b0fbb7cd068ed
Author: Steven Perron <stevenperron at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVIRMapping.h
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-peeled-array-minimal.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-peeled-array.ll
Log Message:
-----------
[SPIRV] Support Peeled Array Layouts for HLSL CBuffers (#169078)
This commit adds support for 'peeled arrays' in HLSL constant buffers.
HLSL CBuffers may have padding between array elements but not after the
last element. This is represented in LLVM IR as {[N-1 x {T, pad}], T}.
Changes include:
- Recognition of the peeled array pattern.
- Logic to reconstitute these into SPIR-V compatible arrays.
- Support for spirv.Padding type in GlobalRegistry and Builtins.
- Updates to SPIRVCBufferAccess to correctly calculate member offsets
in these padded structures.
Depends on https://github.com/llvm/llvm-project/pull/169076
Commit: e7bcd80e5bbc9c4c287d835a1df46742ba0fc3e9
https://github.com/llvm/llvm-project/commit/e7bcd80e5bbc9c4c287d835a1df46742ba0fc3e9
Author: Steven Perron <stevenperron at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/logical-memcpy.ll
Log Message:
-----------
[SPIRV] Use OpCopyMemory for logical SPIRV memcpy (#169348)
This commit modifies the SPIRV instruction selector to emit
`OpCopyMemory`
instead of `OpCopyMemorySized` when generating SPIRV for logical
addressing.
Previously, `G_MEMCPY` was translated to `OpCopyMemorySized`, which
requires an
explicit size operand. However, for logical SPIRV, the size of the
pointee type
is implicitly known. This change ensures that `OpCopyMemory` is used,
which is
more appropriate for logical SPIRV and aligns with the SPIR-V
specification for
logical addressing.
Commit: 7bf459bce34280273942e4a75ce9eab4d4b4e496
https://github.com/llvm/llvm-project/commit/7bf459bce34280273942e4a75ce9eab4d4b4e496
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/TableGen/DuplicateFieldValues.td
M llvm/test/TableGen/RegClassByHwMode.td
M llvm/test/TableGen/def-multiple-operands.td
M llvm/test/TableGen/get-named-operand-idx.td
M llvm/test/TableGen/get-operand-type-no-expand.td
M llvm/test/TableGen/get-operand-type.td
M llvm/test/TableGen/target-specialized-pseudos.td
M llvm/utils/TableGen/InstrInfoEmitter.cpp
Log Message:
-----------
CodeGen: Make target overrides of PointerLikeRegClass mandatory (#159882)
Most targets should now use the convenience multiclass to fixup
the operand definitions of pointer-using pseudoinstructions:
defm : RemapAllTargetPseudoPointerOperands<target_ptr_regclass>;
Commit: 9b88cd9945c5077f0d07f04cd9c9e8e146c48a1b
https://github.com/llvm/llvm-project/commit/9b88cd9945c5077f0d07f04cd9c9e8e146c48a1b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCInstrDesc.h
M llvm/include/llvm/Target/Target.td
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/InstructionEncoding.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/InstrInfoEmitter.cpp
Log Message:
-----------
CodeGen: Remove PointerLikeRegClass handling from codegen (#159883)
All uses have been migrated to RegClassByHwMode. This is now
an implementation detail of InstrInfoEmitter for pseudoinstructions.
Commit: 43e69b18920ecabcf7c6c5fb898f9b18120200f2
https://github.com/llvm/llvm-project/commit/43e69b18920ecabcf7c6c5fb898f9b18120200f2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/basic.ll
Log Message:
-----------
RuntimeLibcalls: Add malloc and free entries (#167081)
Calloc was already here, but not the others. Also add
manual type information.
Commit: 59b3d1814afca973d1417ed2f1d5dac4af3de636
https://github.com/llvm/llvm-project/commit/59b3d1814afca973d1417ed2f1d5dac4af3de636
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
Log Message:
-----------
RuntimeLibcalls: Add more function entries from TargetLibraryInfo (#167082)
Script scraped dump of most functions in TargetLibraryInfo.def,
with existing entries and a few special cases removed. This only
adds the definitions, and doesn't add them to any system yet.
Adding them in the correct places is the hard part, since it's
all written as opt-out with manually written exemptions in
TargetLibraryInfo.
Commit: 9e1d3cac8562fab0a62c1ab19228da5ff6fb26c5
https://github.com/llvm/llvm-project/commit/9e1d3cac8562fab0a62c1ab19228da5ff6fb26c5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/darwin.ll
Log Message:
-----------
RuntimeLibcalls: Add memset_pattern* calls to darwin systems (#167083)
This is one of the easier cases to comprehend in TargetLibraryInfo's
setup.
Commit: e8b9d4217046727845d107c6d4e4ff275e6ee1b4
https://github.com/llvm/llvm-project/commit/e8b9d4217046727845d107c6d4e4ff275e6ee1b4
Author: anoopkg6 <anoop.kumar6 at ibm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Linux.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/tysan/tysan_platform.h
Log Message:
-----------
[tysan] Type Sanitizer support for SystemZ (#162396)
Type Sanitizer support for SystemZ.
Co-authored-by: anoopkg6 <anoopkg6 at github.com>
Commit: 44c9d3a6f5d155ce7d934244dd673b7a8cd5296b
https://github.com/llvm/llvm-project/commit/44c9d3a6f5d155ce7d934244dd673b7a8cd5296b
Author: anoopkg6 <anoop.kumar6 at ibm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Linux.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
Log Message:
-----------
[scudo] Add scudo_standalone support for SystemZ (#166187)
Add Support for scudo_standalone for SystemZ without enabling gwp_asan.
Co-authored-by: anoopkg6 <anoopkg6 at github.com>
Commit: c333f7dab9f89734777f7d19bc7b68c86f393216
https://github.com/llvm/llvm-project/commit/c333f7dab9f89734777f7d19bc7b68c86f393216
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
Log Message:
-----------
[mlir][xegpu] Add layout based SIMT distribution support for `vector.extract/insert_strided_slice` (#168626)
This PR adds general SIMT distribution support for
`vector.extract/insert_strided_slice`. Currently vector distribution
already have support for these operations but have restrictions to avoid
requiring layouts during distribution logic. For example,
`extract_stride_slice` require that distributed dimension is fully
extracted. However, more complex cases may require extracting partially
from distributed dimension (eg. 8x16xf16 extraction from 8x32xf16).
These types of cases need the layouts to reason about how the data is
spread across SIMT lanes.
Currently, we don't have layout access in vector distribution so these
new patterns are place in XeGPU side. They have higher pattern benefit
so that they will be tried first before trying regular vector
distribution based patterns.
Commit: 96cbbebc20dc62e6a780952e3745f67aaefcdf13
https://github.com/llvm/llvm-project/commit/96cbbebc20dc62e6a780952e3745f67aaefcdf13
Author: Shaoce SUN <sunshaoce at outlook.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
Log Message:
-----------
[MC][RISCV] Add missing Predicates for NDS_FMV_BF16_X (#169662)
run
```shell
build/bin/llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-index=-1
```
error:
```
---
mode: latency
key:
instructions:
- 'NDS_FMV_BF16_X F2_H X11'
- 'NDS_FMV_X_BF16 X26 F2_H'
config: ''
register_initial_values:
- 'X11=0x0'
cpu_name: generic
llvm_triple: riscv64-unknown-linux-gnu
min_instructions: 10000
measurements: []
error: actual measurements skipped.
info: Repeating two instructions
assembled_snippet: 41116AE48145538105F0530D01E0538105F0530D01E0538105F0530D01E0538105F0530D01E0226D41018280
...
LLVM ERROR: Attempting to emit FMV_H_X instruction but the Feature_HasHalfFPLoadStoreMove predicate(s) are not met
```
Commit: 071d1fb8beda4c0ec9ede0acab12a382f34758fe
https://github.com/llvm/llvm-project/commit/071d1fb8beda4c0ec9ede0acab12a382f34758fe
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[LV] Use VPReductionRecipe for partial reductions (#147513)
Partial reductions can easily be represented by the VPReductionRecipe
class by setting their scale factor to something greater than 1. This PR
merges the two together and gives VPReductionRecipe a VFScaleFactor so
that it can choose to generate the partial reduction intrinsic at
execute time.
Stacked PRs:
1. https://github.com/llvm/llvm-project/pull/147026
2. https://github.com/llvm/llvm-project/pull/147255
3. https://github.com/llvm/llvm-project/pull/156976
4. https://github.com/llvm/llvm-project/pull/160154
5. https://github.com/llvm/llvm-project/pull/147302
6. https://github.com/llvm/llvm-project/pull/162503
7. -> https://github.com/llvm/llvm-project/pull/147513
Replaces https://github.com/llvm/llvm-project/pull/146073 .
Commit: 7c3c8dabd6ddcbf153ff2c7024ba1164524e5423
https://github.com/llvm/llvm-project/commit/7c3c8dabd6ddcbf153ff2c7024ba1164524e5423
Author: daniilavdeev <daniilavdeev237 at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/test/Driver/riscv-features.c
Log Message:
-----------
Revert [Driver] Error for -gsplit-dwarf with RISC-V linker relaxation (#169653)
This patch reverts 80a4e6fd31a06143b83947785ea3bd5c04344ea6
After the relevant patches clang now supports dwarf fission with RISC-V
linker relaxations, so we can remove the related driver error.
Commit: 9bd30e2f272536e82730b115720fa807d7be9be9
https://github.com/llvm/llvm-project/commit/9bd30e2f272536e82730b115720fa807d7be9be9
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fully-unrolled-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll
Log Message:
-----------
[AArch64] Enable maximising scalable vector bandwidth (#166748)
This PR enables maximising scalable vector bandwidth for all AArch64
cores other than the V1 and N2. Those two have shown small regressions
that we'll investigate, fix and then enable.
Commit: e99029ef0f0f0bacd8b734058e9cf2be971f16de
https://github.com/llvm/llvm-project/commit/e99029ef0f0f0bacd8b734058e9cf2be971f16de
Author: Kaitlin Peng <kaitlinpeng at microsoft.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h
M clang/test/CodeGenHLSL/builtins/faceforward.hlsl
Log Message:
-----------
[HLSL] Remove `faceforward` SPIRV fast path (#169547)
Commit: cca66a21c20537171712b3adf35b4b82de5f2ad5
https://github.com/llvm/llvm-project/commit/cca66a21c20537171712b3adf35b4b82de5f2ad5
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][BTI] Add MCPlusBuilder::updateBTIVariant (#167308)
Checks if an instruction is BTI, and updates the immediate value to the
newly requested variant.
This can be used in situations when the compiler already inserted a BTI
landing pad to a location, but BOLT needs to update it to a different
variant.
Example: br x0 to a location with a BTI c.
Commit: b78b5ba225c121fb4463791bcbdd78be19e49213
https://github.com/llvm/llvm-project/commit/b78b5ba225c121fb4463791bcbdd78be19e49213
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
R llvm/test/MC/PowerPC/ppc64-encoding-ISA31-errors.s
M llvm/test/MC/PowerPC/ppc64-errors.s
Log Message:
-----------
[NFC][PowerPC] Merge ppc64 encoding error tests (#169669)
Based on the RUN lines, there is actually no need for different versions
of these error files since no cpu specific
option needed. Combine to reduce confusion and maintenance as these are
not huge files.
Commit: 356479191ca001df47136c89cc9a761c64a6323c
https://github.com/llvm/llvm-project/commit/356479191ca001df47136c89cc9a761c64a6323c
Author: Lucie Choi <clucie at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
A llvm/test/Transforms/IndVarSimplify/skip-predication-convergence.ll
A llvm/test/Transforms/IndVarSimplify/skip-predication-nested-convergence.ll
Log Message:
-----------
[IndVarSimplify] Fix `IndVarSimplify` to skip unfolding predicates when the loop contains control convergence operations. (#165643)
Skip constant folding the loop predicates if the loop contains control
convergence tokens referenced outside the loop.
Fixes https://github.com/llvm/llvm-project/issues/164496.
Verified
[loop_peeling.test](https://github.com/llvm/offload-test-suite/pull/473)
passes with the fix.
Similar control convergence issues are found on other passes.
https://github.com/llvm/llvm-project/issues/165642
HLSL used for tests:
```hlsl
RWStructuredBuffer<uint> Out : register(u0);
[numthreads(8,1,1)]
void main(uint3 TID : SV_GroupThreadID) {
for (uint i = 0; i < 8; i++) {
if (i == TID.x) {
Out[TID.x] = WaveActiveMax(TID.x);
break;
}
}
}
```
With nested loop:
```hlsl
RWStructuredBuffer<uint> Out : register(u0);
[numthreads(8,8,1)]
void main(uint3 TID : SV_GroupThreadID) {
for (uint i = 0; i < 8; i++) {
for (uint j = 0; j < 8; j++) {
if (i == TID.x && j == TID.y) {
uint index = TID.x * 8 + TID.y;
Out[index] = WaveActiveMax(index);
break;
}
}
}
}
```
Commit: 84d511df8dcdd6da00be41b250312d84b5de41a7
https://github.com/llvm/llvm-project/commit/84d511df8dcdd6da00be41b250312d84b5de41a7
Author: Jason-VanBeusekom <jason.van-beusekom at hpe.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M offload/include/omptarget.h
M offload/libomptarget/PluginManager.cpp
M offload/libomptarget/device.cpp
A offload/test/api/omp_indirect_call_table_manual.c
Log Message:
-----------
[OpenMP][clang] Register vtables on device for indirect calls runtime (#167011)
This is a branch off of
https://github.com/llvm/llvm-project/pull/159856, in which consists of
the runtime portion of the changes required to support indirect function
and virtual function calls on an `omp target device` when the virtual
class / indirect function is mapped to the device from the host.
Key Changes
- Introduced a new flag OMP_DECLARE_TARGET_INDIRECT_VTABLE to mark
VTable registrations
- Modified setupIndirectCallTable to support both VTable entries and
indirect function pointers
Details:
The setupIndirectCallTable implementation was modified to support this
registration type by retrieving the first address of the VTable and
inferring the remaining data needed to build the indirect call table.
Since the Vtables / Classes registered as indirect can be larger than 8
bytes, and the vtables may not be at the first address we either need to
pass the size to __llvm_omp_indirect_call_lookup and have a check at
each step of the binary search, or add multiple entries to the indirect
table for each address registered. The latter was chosen.
Commit: a00def3f20e166d4fb9328e6f0bc0742cd0afa31 is not a part of this
PR and is handled / reviewed in:
https://github.com/llvm/llvm-project/pull/159856,
This is PR (2/3)
Register Vtable PR (1/3):
https://github.com/llvm/llvm-project/pull/159856,
Codegen / _llvm_omp_indirect_call_lookup PR (3/3):
https://github.com/llvm/llvm-project/pull/159857
Commit: 954fa0f9bae73a2214d1d5079d6c3c028dca42ce
https://github.com/llvm/llvm-project/commit/954fa0f9bae73a2214d1d5079d6c3c028dca42ce
Author: Moritz Zielke <moritz.zielke at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
Log Message:
-----------
[Clang] Allow AVX/AVX512 subvector shuffles in constexpr (#168700)
Resolves #160514
Enables usage of the following x86 intrinsics in `constexpr`:
```
_mm256_shuffle_i64x2 _mm256_mask_shuffle_i64x2 _mm256_maskz_shuffle_i64x2
_mm256_shuffle_f64x2 _mm256_mask_shuffle_f64x2 _mm256_maskz_shuffle_f64x2
_mm512_shuffle_i64x2 _mm512_mask_shuffle_i64x2 _mm512_maskz_shuffle_i64x2
_mm512_shuffle_f64x2 _mm512_mask_shuffle_f64x2 _mm512_maskz_shuffle_f64x2
_mm256_shuffle_i32x4 _mm256_mask_shuffle_i32x4 _mm256_maskz_shuffle_i32x4
_mm256_shuffle_f32x4 _mm256_mask_shuffle_f32x4 _mm256_maskz_shuffle_f32x4
_mm512_shuffle_i32x4 _mm512_mask_shuffle_i32x4 _mm512_maskz_shuffle_i32x4
_mm512_shuffle_f32x4 _mm512_mask_shuffle_f32x4 _mm512_maskz_shuffle_f32x4
```
Commit: 411a53e16fbc9bfe23fd887c918c3ec5d74fa2bc
https://github.com/llvm/llvm-project/commit/411a53e16fbc9bfe23fd887c918c3ec5d74fa2bc
Author: Letu Ren <fantasquex at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/builtins-floating-point.c
Log Message:
-----------
[CIR] Upstream Builtin Exp2Op (#169152)
Add the cir::exp2 operation and handling for the related builtins.
Commit: 0940f686dc332557f0368290ebc3d9aff1f36714
https://github.com/llvm/llvm-project/commit/0940f686dc332557f0368290ebc3d9aff1f36714
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/unittests/Support/JobserverTest.cpp
Log Message:
-----------
Move static test variable into the #if that uses it (#169695)
Fixes -Wunused-variable when compiling without LLVM_ENABLE_THREADS
Commit: c98e867822d8e741159ff0be09ccc2a5c7841a28
https://github.com/llvm/llvm-project/commit/c98e867822d8e741159ff0be09ccc2a5c7841a28
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaType.cpp
M clang/test/SemaCXX/return.cpp
Log Message:
-----------
[Clang] Fix false positive -Wignored-qualifiers (#169664)
A deduced return type can be an object type, in which case `const` can
have an effect.
Delay the diagnostic to the point at which the type is deduced.
Add tests for lambdas.
Fixes #43054
Note that there is a discussion in #43054 about adding a separate
warning for "const return types are weird" for the class type cases, but
it would have to be a separate warning - warning which currently exists
in clang-tidy as `readability-const-return-type`.
Commit: 18805b6ce9a4887ea6a19ce7e4f8fc943a716ec5
https://github.com/llvm/llvm-project/commit/18805b6ce9a4887ea6a19ce7e4f8fc943a716ec5
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/test/CIR/CodeGen/count-of.c
Log Message:
-----------
[CIR] CountOf VLA with Array element type (#169404)
Implement CountOf on VariableArrayType with IntegerConstant SizeExpr
Commit: 587e279a880add8017bdc9484c3bf9030fdcec8f
https://github.com/llvm/llvm-project/commit/587e279a880add8017bdc9484c3bf9030fdcec8f
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
Log Message:
-----------
[CIR][NFC] Cleanup builtin helper function interfaces (#169586)
A couple of builtin helper functions were taking a clang::Expr argument
but only using it to build an MLIR location. This change updates these
functions to take a location directly.
Commit: 5ab3375b2cf461ab02704d129a1f4d5ba1a1e275
https://github.com/llvm/llvm-project/commit/5ab3375b2cf461ab02704d129a1f4d5ba1a1e275
Author: Janet Yang <qxy11 at meta.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lldb/include/lldb/API/SBTarget.h
M lldb/include/lldb/Target/Target.h
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/source/API/SBTarget.cpp
M lldb/source/Target/Target.cpp
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
M lldb/test/API/tools/lldb-dap/startDebugging/TestDAP_startDebugging.py
M lldb/tools/lldb-dap/CMakeLists.txt
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPForward.h
A lldb/tools/lldb-dap/DAPSessionManager.cpp
A lldb/tools/lldb-dap/DAPSessionManager.h
M lldb/tools/lldb-dap/EventHelper.cpp
M lldb/tools/lldb-dap/EventHelper.h
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/LaunchRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/package.json
M lldb/tools/lldb-dap/tool/lldb-dap.cpp
M lldb/unittests/DAP/CMakeLists.txt
A lldb/unittests/DAP/DAPSessionManagerTest.cpp
M llvm/utils/gn/secondary/lldb/tools/lldb-dap/BUILD.gn
Log Message:
-----------
[lldb-dap] Add multi-session support with shared debugger instances (#163653)
## Summary:
This change introduces a `DAPSessionManager` to enable multiple DAP
sessions to share debugger instances when needed, for things like child
process debugging and some scripting hooks that create dynamically new
targets.
Changes include:
- Add `DAPSessionManager` singleton to track and coordinate all active DAP
sessions
- Support attaching to an existing target via its globally unique target
ID (targetId parameter)
- Share debugger instances across sessions when new targets are created
dynamically
- Refactor event thread management to allow sharing event threads
between sessions and move event thread and event thread handlers to `EventHelpers`
- Add `eBroadcastBitNewTargetCreated` event to notify when new targets are
created
- Extract session names from target creation events
- Defer debugger initialization from 'initialize' request to
'launch'/'attach' requests. The only time the debugger is used currently
in between its creation in `InitializeRequestHandler` and the `Launch`
or `Attach` requests is during the `TelemetryDispatcher` destruction
call at the end of the `DAP::HandleObject` call, so this is safe.
This enables scenarios when new targets are created dynamically so that
the debug adapter can automatically start a new debug session for the
spawned target while sharing the debugger instance.
## Tests:
The refactoring maintains backward compatibility. All existing DAP test
cases pass.
Also added a few basic unit tests for DAPSessionManager
```
>> ninja DAPTests
>> ./tools/lldb/unittests/DAP/DAPTests
>>./bin/llvm-lit -v ../llvm-project/lldb/test/API/tools/lldb-dap/
```
Commit: bf43b95025124017b37aa8fd0ee7dc94ac4d670e
https://github.com/llvm/llvm-project/commit/bf43b95025124017b37aa8fd0ee7dc94ac4d670e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.h
Log Message:
-----------
[flang][OpenMP] Remove unused #include "dump-parse-tree.h", NFC (#169708)
Commit: a059afafde068773693c1fab4d89c208b1437f76
https://github.com/llvm/llvm-project/commit/a059afafde068773693c1fab4d89c208b1437f76
Author: Igor Kudrin <ikudrin at accesssoftek.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lldb/source/Target/Process.cpp
M lldb/source/Target/Target.cpp
M lldb/unittests/Target/MemoryTest.cpp
Log Message:
-----------
[lldb] Fix reading 32-bit signed integers (#169150)
Both `Target::ReadSignedIntegerFromMemory()` and
`Process::ReadSignedIntegerFromMemory()` internally created an unsigned
scalar, so extending the value later did not duplicate the sign bit.
Commit: 66e18b86b8b1e98eeb71d7ab57cb09a26dff6b96
https://github.com/llvm/llvm-project/commit/66e18b86b8b1e98eeb71d7ab57cb09a26dff6b96
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/user-with-multi-copyable-ops.ll
Log Message:
-----------
[SLP][NFC]Add a test with single op inst, used in many nodes, NFC.
Commit: d09644a294c8393eb7a2cc586762a8d3f60b5aeb
https://github.com/llvm/llvm-project/commit/d09644a294c8393eb7a2cc586762a8d3f60b5aeb
Author: Ravil Dorozhinskii <ravil.aviva.com at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[ROCDL] Added missing `cluster.load.async.to.lds` op (gfx1250) (#169042)
* Added missing cluster.load ops with different sizes. Extended all
rocdl tests
Commit: 72e51d389f66d9cc6b55fd74b56fbbd087672a43
https://github.com/llvm/llvm-project/commit/72e51d389f66d9cc6b55fd74b56fbbd087672a43
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
Log Message:
-----------
Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)"
This reverts commit a6edeedbfa308876d6f2b1648729d52970bb07e6.
The following fixes have landed, addressing issues causing the original
revert:
* https://github.com/llvm/llvm-project/pull/169298
* https://github.com/llvm/llvm-project/pull/167897
* https://github.com/llvm/llvm-project/pull/168949
Original message:
Building on top of https://github.com/llvm/llvm-project/pull/148817,
introduce a new abstract LastActiveLane opcode that gets lowered to
Not(Mask) → FirstActiveLane(NotMask) → Sub(result, 1).
When folding the tail, update all extracts for uses outside the loop the
extract the value of the last actice lane.
See also https://github.com/llvm/llvm-project/issues/148603
PR: https://github.com/llvm/llvm-project/pull/149042
Commit: 684f64c0baca15c84e222c0f7c7455e8c505e575
https://github.com/llvm/llvm-project/commit/684f64c0baca15c84e222c0f7c7455e8c505e575
Author: n2h9 <13541181+n2h9 at users.noreply.github.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/builders/darwin.py
Log Message:
-----------
[lldb] [test-suite] fix typo in variable in darwin builder (#169254)
While taking a look at the code of lldb test-suite packages, I have
noticed that in `get_triple_str` in `darwin.py` env is added inside a
`components` list, which is probably supposed to be `component` (defined
on the line 61).
Signed-off-by: Nikita B <n2h9z4 at gmail.com>
Commit: a4d42775b9af0d961f71934e38342a9384534022
https://github.com/llvm/llvm-project/commit/a4d42775b9af0d961f71934e38342a9384534022
Author: n2h9 <13541181+n2h9 at users.noreply.github.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lldb/bindings/interface/SBTargetExtensions.i
M lldb/examples/python/templates/scripted_process.py
M lldb/include/lldb/API/SBTarget.h
M lldb/source/API/SBTarget.cpp
M lldb/test/API/python_api/target/TestTargetAPI.py
Log Message:
-----------
[lldb] [scripting bridge] 167388 chore: add api to return arch name for target (#168273)
This pr fixes #167388 .
## Description
This pr adds new method `GetArchName` to `SBTarget` so that no need to
parse triple to get arch name in client code.
## Testing
### All from `TestTargetAPI.py`
run test with
```
./build/bin/lldb-dotest -v -p TestTargetAPI.py
```
<details>
<summary>existing tests (without newly added)</summary>
<img width="1425" height="804" alt="image"
src="https://github.com/user-attachments/assets/617e4c69-5c6b-44c4-9aeb-b751a47e253c"
/>
</details>
<details>
<summary>existing tests (with newly added)</summary>
<img width="1422" height="778" alt="image"
src="https://github.com/user-attachments/assets/746990a1-df88-4348-a090-224963d3c640"
/>
</details>
### Only `test_get_arch_name`
run test with
```
./build/bin/lldb-dotest -v -p TestTargetAPI.py -f test_get_arch_name_dwarf -f test_get_arch_name_dwo -f test_get_arch_name_dsym lldb/test/API/python_api/target
```
<details>
<summary>only newly added</summary>
<img width="1422" height="778" alt="image"
src="https://github.com/user-attachments/assets/fcaafa5d-2622-4171-acee-e104ecee0652"
/>
</details>
---------
Signed-off-by: Nikita B <n2h9z4 at gmail.com>
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: d58ebe339c920e1a90f4fd87b0873a119e5f9d05
https://github.com/llvm/llvm-project/commit/d58ebe339c920e1a90f4fd87b0873a119e5f9d05
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
Log Message:
-----------
Revert "Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)""
This reverts commit 72e51d389f66d9cc6b55fd74b56fbbd087672a43.
Missed some test updates.
Commit: 9af00e62ecc33960ada5366bffc369a647699fe9
https://github.com/llvm/llvm-project/commit/9af00e62ecc33960ada5366bffc369a647699fe9
Author: Erick Ochoa Lopez <erick.ochoalopez at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/test/Dialect/AMDGPU/ops.mlir
Log Message:
-----------
[mlir][amdgpu] Add make_dma_base operation (#169086)
Commit: cabcb5ae55f117d15f41aed8f064dc528ddc9e8f
https://github.com/llvm/llvm-project/commit/cabcb5ae55f117d15f41aed8f064dc528ddc9e8f
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
Log Message:
-----------
[CIR][NFC] Fix build problem inside an assert (#169715)
A recent change introduced a failure in debug builds due to an incorrect
level of indirection inside an assert. This fixes that.
Commit: f8eca64a2820553ffc22c58ac39c2e5c14888e61
https://github.com/llvm/llvm-project/commit/f8eca64a2820553ffc22c58ac39c2e5c14888e61
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
Log Message:
-----------
Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)"
This reverts commit a6edeedbfa308876d6f2b1648729d52970bb07e6.
The following fixes have landed, addressing issues causing the original
revert:
* https://github.com/llvm/llvm-project/pull/169298
* https://github.com/llvm/llvm-project/pull/167897
* https://github.com/llvm/llvm-project/pull/168949
Original message:
Building on top of https://github.com/llvm/llvm-project/pull/148817,
introduce a new abstract LastActiveLane opcode that gets lowered to
Not(Mask) → FirstActiveLane(NotMask) → Sub(result, 1).
When folding the tail, update all extracts for uses outside the loop the
extract the value of the last actice lane.
See also https://github.com/llvm/llvm-project/issues/148603
PR: https://github.com/llvm/llvm-project/pull/149042
Commit: cec837e3e09f7751e668c89aed894d547d542ae6
https://github.com/llvm/llvm-project/commit/cec837e3e09f7751e668c89aed894d547d542ae6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/CodeGen/X86/addcarry.ll
Log Message:
-----------
[X86] addcarry.ll - add test coverage for #169691 (#169716)
Commit: bbb8f7aaf8c2cc7f68b59ed0d5abed068c581682
https://github.com/llvm/llvm-project/commit/bbb8f7aaf8c2cc7f68b59ed0d5abed068c581682
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M libcxx/include/__flat_map/flat_map.h
M libcxx/include/__flat_map/utils.h
M libcxx/test/libcxx/diagnostics/flat_map.nodiscard.verify.cpp
M libcxx/test/std/containers/container.adaptors/flat.map/flat.map.access/index_transparent.pass.cpp
Log Message:
-----------
[libc++][flat_map] Applied `[[nodiscard]]` (#169453)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 8706d82bd420fdfb95e207df6d56f73274ec7d20
https://github.com/llvm/llvm-project/commit/8706d82bd420fdfb95e207df6d56f73274ec7d20
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M libcxx/include/__compare/is_eq.h
M libcxx/include/__coroutine/coroutine_handle.h
M libcxx/include/__coroutine/noop_coroutine_handle.h
M libcxx/include/__utility/cmp.h
M libcxx/include/initializer_list
M libcxx/test/libcxx/diagnostics/utility.nodiscard.verify.cpp
A libcxx/test/libcxx/language.support/nodiscard.verify.cpp
Log Message:
-----------
[libc++] Applied `[[nodiscard]]` to Language Support (partially) (#169611)
https://wg21.link/#support
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
The following was implemented in this patch:
- [x] `<compare>`
- [x] `<corotine>`
- [x] `<initializer_list>`
- [x] Integer comparisons
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Co-authored-by: A. Jiang <de34 at live.cn>
Commit: 3a25a4a68705d7861c5b0312667f3bc43359da41
https://github.com/llvm/llvm-project/commit/3a25a4a68705d7861c5b0312667f3bc43359da41
Author: Björn Schäpers <bjoern at hazardy.de>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/Format.cpp
M clang/lib/Format/IntegerLiteralSeparatorFixer.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/IntegerLiteralSeparatorTest.cpp
Log Message:
-----------
[clang-format] Add xxxMaxDigitsNoSeparator (#164286)
This basically adds a Leave option for a specific range of literals.
Commit: c378bb135455787a5d8b1f4da5d3522a3e6a60b9
https://github.com/llvm/llvm-project/commit/c378bb135455787a5d8b1f4da5d3522a3e6a60b9
Author: Peter Collingbourne <pcc at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
A llvm/test/CodeGen/AArch64/ptrauth-irelative.ll
M llvm/test/CodeGen/AArch64/ptrauth-type-info-vptr-discr.ll
Log Message:
-----------
CodeGen: Optionally emit PAuth relocations as IRELATIVE relocations.
This supports the following use cases:
- ConstantPtrAuth expressions that are unrepresentable using standard PAuth
relocations such as expressions involving an integer operand or
deactivation symbols.
- libc implementations that do not support PAuth relocations.
For more information see the RFC:
https://discourse.llvm.org/t/rfc-structure-protection-a-family-of-uaf-mitigation-techniques/85555
Reviewers: MaskRay, fmayer, smithp35, kovdan01
Reviewed By: fmayer
Pull Request: https://github.com/llvm/llvm-project/pull/133533
Commit: 6227eb90da2a417125477b27799ae2e8f43b9e49
https://github.com/llvm/llvm-project/commit/6227eb90da2a417125477b27799ae2e8f43b9e49
Author: Peter Collingbourne <pcc at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/CodeGen/MachineInstrBuilder.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/LLVMContext.h
M llvm/include/llvm/Target/Target.td
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/LLVMContext.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Bitcode/operand-bundles-bc-analyzer.ll
A llvm/test/CodeGen/AArch64/deactivation-symbols.ll
A llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
M llvm/test/Transforms/InstCombine/ptrauth-intrinsics.ll
M llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
Log Message:
-----------
Add IR and codegen support for deactivation symbols.
Deactivation symbols are a mechanism for allowing object files to disable
specific instructions in other object files at link time. The initial use
case is for pointer field protection.
For more information, see the RFC:
https://discourse.llvm.org/t/rfc-deactivation-symbols/85556
Reviewers: ojhunt, nikic, fmayer, arsenm, ahmedbougacha
Reviewed By: fmayer
Pull Request: https://github.com/llvm/llvm-project/pull/133536
Commit: d2379effe9db15765e4fd1f7a0589af5f9269f96
https://github.com/llvm/llvm-project/commit/d2379effe9db15765e4fd1f7a0589af5f9269f96
Author: Peter Collingbourne <pcc at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGPointerAuth.cpp
M llvm/docs/LangRef.rst
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/Constants.h
M llvm/include/llvm/SandboxIR/Constant.h
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/ConstantsContext.h
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/SandboxIR/Constant.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Utils/ValueMapper.cpp
A llvm/test/Assembler/invalid-ptrauth-const6.ll
M llvm/test/Bitcode/compatibility.ll
M llvm/test/CodeGen/AArch64/ptrauth-irelative.ll
M llvm/test/Transforms/InstCombine/ptrauth-intrinsics.ll
A llvm/test/Verifier/ptrauth-constant.ll
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/Transforms/Utils/ValueMapperTest.cpp
Log Message:
-----------
Add deactivation symbol operand to ConstantPtrAuth.
Deactivation symbol operands are supported in the code generator by
building on the previously added support for IRELATIVE relocations.
Reviewers: ojhunt, fmayer, ahmedbougacha, nikic, efriedma-quic
Reviewed By: fmayer
Pull Request: https://github.com/llvm/llvm-project/pull/133537
Commit: a33fd4437216fff3d092e5056a78c4f430b2f9da
https://github.com/llvm/llvm-project/commit/a33fd4437216fff3d092e5056a78c4f430b2f9da
Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Linux.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/tysan/tysan_platform.h
Log Message:
-----------
Revert "[tysan] Type Sanitizer support for SystemZ" (#169726)
Reverts llvm/llvm-project#162396
Commit: 75ca83563de13ebbf381a0e9e9d97dfbf98ea0f5
https://github.com/llvm/llvm-project/commit/75ca83563de13ebbf381a0e9e9d97dfbf98ea0f5
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Fix build after #169086 (#169725)
Just required wiring up some additional AMDGPU table generated files.
Commit: 8e4208f83a9bb7a4cd550e90e70f3b77499c623e
https://github.com/llvm/llvm-project/commit/8e4208f83a9bb7a4cd550e90e70f3b77499c623e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M flang-rt/lib/cuda/allocator.cpp
M flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
M flang/include/flang/Runtime/CUDA/allocator.h
Log Message:
-----------
[flang][cuda][rt] Add entry point to get the allocation stream (#169608)
Commit: 47efff777d907fcabda59d925dfed3040c7308be
https://github.com/llvm/llvm-project/commit/47efff777d907fcabda59d925dfed3040c7308be
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
A llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll
Log Message:
-----------
[SystemZ] Emit optional argument area length field (#169679)
The Language Environment (LE) reserves 128 byte for the argument area
when the optional field is not present. If the argument area is larger,
then the field must be present to guarantee that the space is reserved
on stack extension. Creating this field when alloca() is used may reduce
the needed stack space in case alloca() causes a stack extension.
Commit: 48454241cde713c450e2369983b8c98b7ab16f19
https://github.com/llvm/llvm-project/commit/48454241cde713c450e2369983b8c98b7ab16f19
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
Log Message:
-----------
[SPIRV] Fix a warning
This patch fixes:
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp:245:25: error: unused
variable 'TII' [-Werror,-Wunused-variable]
Commit: 9871d7089890f357308804987ceae1e98c5c42a3
https://github.com/llvm/llvm-project/commit/9871d7089890f357308804987ceae1e98c5c42a3
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
A mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitDeclare.cpp
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
A mlir/test/Dialect/OpenACC/acc-implicit-declare.mlir
Log Message:
-----------
[mlir][acc] Introduce ACCImplicitDeclare pass for globals handling (#169720)
This commit introduces the ACCImplicitDeclare pass to the OpenACC
dialect, complementing ACCImplicitData by handling global variables
referenced in OpenACC compute regions and routines.
Overview:
---------
The pass applies implicit `acc declare` actions to global variables
referenced in OpenACC regions. While the OpenACC spec focuses on
implicit data mapping (handled by ACCImplicitData), implicit declare is
advantageous and required for specific cases:
1. Globals referenced in implicit `acc routine` - Since data mapping
only applies to compute regions, globals in routines must use `acc
declare`.
2. Compiler-generated globals - Type descriptors, runtime names, and
error reporting strings introduced during compilation that wouldn't be
visible for user-provided `acc declare` directives.
3. Constant globals - Constants like filename strings or initialization
values benefit from being marked with `acc declare` rather than being
mapped repeatedly (e.g., 1000 kernel launches shouldn't map the same
constant 1000 times).
Implementation:
---------------
The pass performs this in two phases:
1. Hoisting: Non-constant globals in compute regions have their
address-of operations hoisted out of the region when possible, allowing
implicit data mapping instead of declare marking.
2. Declaration: Remaining that must be device available (constants,
globals in routines, globals in recipe operations) are marked with the
acc.declare attribute.
The pass processes:
- OpenACC compute constructs (parallel, kernels, serial)
- Functions marked with acc routine
- Private, firstprivate, and reduction recipes (when used)
- Initialization regions of existing declared globals
Requirements:
-------------
The pass requires operations to implement:
- acc::AddressOfGlobalOpInterface (for address-of ops)
- acc::GlobalVariableOpInterface (for global definitions)
- acc::IndirectGlobalAccessOpInterface (for indirect access)
Commit: 3d596ad09234c92067012b33a81be8dc48aa2e47
https://github.com/llvm/llvm-project/commit/3d596ad09234c92067012b33a81be8dc48aa2e47
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/test/Driver/hip-spirv-backend-opt.c
Log Message:
-----------
[clang][Driver] Use -no-canonical-prefixes in hip-spirv-backend-opt test (#169717)
Otherwise the test can fail in weirder setups (like ours downstream
where the actual binary path only contains the hash of the object). This
makes the test more resilient, more consistent with other driver tests,
and allows us to assert that the binary is named clang rather than
clang-<some suffix>.
Commit: d5778a7ff55688de0d6c87204fdd8d32ac1bdc99
https://github.com/llvm/llvm-project/commit/d5778a7ff55688de0d6c87204fdd8d32ac1bdc99
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libcxx/include/__condition_variable/condition_variable.h
M libcxx/include/__mutex/mutex.h
M libcxx/include/__thread/thread.h
M libcxx/include/barrier
M libcxx/include/latch
M libcxx/include/mutex
M libcxx/include/semaphore
A libcxx/test/libcxx/thread/nodiscard.verify.cpp
R libcxx/test/std/thread/thread.jthread/nodiscard.verify.cpp
Log Message:
-----------
[libc++] Applied `[[nodiscard]]` to concurrency (partially) (#169463)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
The following utilities have been annotated in this patch:
- [x] `<barrier>`
- [x] `<condition_variable>`
- [x] `<latch>`
- [x] `<mutex>`
- [x] `<semaphore>`
- [x] `<thread>`
N.B. Some classes don't provide all specified methods, which were not
annotated.
Commit: 216b9fa2275eb11fdb0133870ac81c8da7ff8fcf
https://github.com/llvm/llvm-project/commit/216b9fa2275eb11fdb0133870ac81c8da7ff8fcf
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/multi-node-user-with-copyable-ops.ll
Log Message:
-----------
[SLP][NFC]Add another test with the user with multiple copyable operands, NFC
Commit: 20d95c807092755114fdc8cc3dba49e3f6820eb2
https://github.com/llvm/llvm-project/commit/20d95c807092755114fdc8cc3dba49e3f6820eb2
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/lambda.cpp
Log Message:
-----------
[CIR] Add undef handling to enable global lambdas (#169721)
This change adds undef handling that was needed to enable global
lambdas. There was no lambda-specific code needed, but the global lambda
handling needed to initialize a global with an undef value.
[CIR] Handle undef init of struct
This adds handling for a case where Clang initializes a struct to undef
with a constant copy. This required adding support for undef constants
and lowering undef attributes to LLVM IR.
Commit: dab44135df10d9e29a38f25e112a847020ee2831
https://github.com/llvm/llvm-project/commit/dab44135df10d9e29a38f25e112a847020ee2831
Author: Peter Collingbourne <pcc at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
Log Message:
-----------
Fix sanitizer failure introduced by #133537
Commit: 2bef14c1a9dc939598ef12999f05527a662e42fa
https://github.com/llvm/llvm-project/commit/2bef14c1a9dc939598ef12999f05527a662e42fa
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
R clang/test/CIR/CodeGen/X86/avx-builtins.c
R clang/test/CIR/CodeGen/X86/avx10_2_512bf16-builtins.c
R clang/test/CIR/CodeGen/X86/avx10_2bf16-builtins.c
R clang/test/CIR/CodeGen/X86/avx512bw-builtins.c
R clang/test/CIR/CodeGen/X86/avx512f-builtins.c
R clang/test/CIR/CodeGen/X86/avx512fp16-builtins.c
R clang/test/CIR/CodeGen/X86/bmi-builtins.c
R clang/test/CIR/CodeGen/X86/lzcnt-builtins.c
R clang/test/CIR/CodeGen/X86/sse-builtins.c
R clang/test/CIR/CodeGen/X86/sse2-builtins.c
R clang/test/CIR/CodeGen/builtin-fcmp-sse.c
R clang/test/CIR/CodeGen/builtin-isfpclass.c
R clang/test/CIR/CodeGen/builtin_bit.cpp
R clang/test/CIR/CodeGen/builtin_call.cpp
R clang/test/CIR/CodeGen/builtin_inline.c
R clang/test/CIR/CodeGen/builtin_new_delete.cpp
R clang/test/CIR/CodeGen/builtin_prefetch.c
R clang/test/CIR/CodeGen/builtin_printf.cpp
R clang/test/CIR/CodeGen/builtins-elementwise.c
R clang/test/CIR/CodeGen/builtins-floating-point.c
R clang/test/CIR/CodeGen/builtins-overflow.cpp
R clang/test/CIR/CodeGen/builtins.cpp
A clang/test/CIR/CodeGenBuiltins/X86/avx-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/avx512bw-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/bmi-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/lzcnt-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/sse-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/sse2-builtins.c
A clang/test/CIR/CodeGenBuiltins/builtin-fcmp-sse.c
A clang/test/CIR/CodeGenBuiltins/builtin-isfpclass.c
A clang/test/CIR/CodeGenBuiltins/builtin_bit.cpp
A clang/test/CIR/CodeGenBuiltins/builtin_call.cpp
A clang/test/CIR/CodeGenBuiltins/builtin_inline.c
A clang/test/CIR/CodeGenBuiltins/builtin_new_delete.cpp
A clang/test/CIR/CodeGenBuiltins/builtin_prefetch.c
A clang/test/CIR/CodeGenBuiltins/builtin_printf.cpp
A clang/test/CIR/CodeGenBuiltins/builtins-elementwise.c
A clang/test/CIR/CodeGenBuiltins/builtins-floating-point.c
A clang/test/CIR/CodeGenBuiltins/builtins-overflow.cpp
A clang/test/CIR/CodeGenBuiltins/builtins.cpp
Log Message:
-----------
[CIR][NFC] Move builtin tests to their own directory (#169737)
This moves all builtin-related CodeGen tests to a new directory,
separate from the main clang/test/CIR/CodeGen directory. This will make
it easier to run the basic CodeGen tests without running the builtin
tests. This is specifically intended to move those tests which include
`immintrin.h` or any of its variants, which take a very long time to
compile with a debug build.
Commit: 36bed4d0cd3e0e3871ad2360a7524da245e289d0
https://github.com/llvm/llvm-project/commit/36bed4d0cd3e0e3871ad2360a7524da245e289d0
Author: John Holdsworth <github at johnholdsworth.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lld/MachO/Driver.cpp
M lld/MachO/InputFiles.cpp
M lld/test/MachO/read-workers.s
M llvm/lib/Object/Archive.cpp
Log Message:
-----------
[lld][MachO] Follow-up to use madvise() for threaded file page-in. (#157917)
Further to
https://github.com/llvm/llvm-project/pull/147134#discussion_r2337246489,
switch to use the madvise() api to page in mmap'd files and
1) All new code compiled in #if LLVM_ENABLE_THREADS is set so it can be
seen where the changes were from this PR.
2) The new PR moves to use madvise() instead of the ad-hoc page
referencing code I wrote which should avoid SIGSEGVs if the buffer is
deallocated.
3) A new property SerialBackgroundQueue().stopAllWork to be used to stop
background workers when there is no further call for them. Usually the
background "page-in" threads have completed first but it seems with this
troublesome test this is not always the case and buffers stored in the
static input file cache are being deallocated while being referenced.
---------
Co-authored-by: James Henderson <James.Henderson at sony.com>
Commit: 2f71e606c96c6b1a534b829fc10ff2d3ef497688
https://github.com/llvm/llvm-project/commit/2f71e606c96c6b1a534b829fc10ff2d3ef497688
Author: Ryan Mast <3969255+nightlark at users.noreply.github.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
A llvm/utils/git/requirements_upload_release.txt
A llvm/utils/git/requirements_upload_release.txt.in
M llvm/utils/release/github-upload-release.py
Log Message:
-----------
github-upload-release.py: add requirements and lock files for installing dependencies (#169461)
Adds requirements.txt and lock files for installing dependencies for
github-upload-release.py script.
Signed-off-by: Ryan Mast <mast.ryan at gmail.com>
Commit: 49516ba0e3a64bafc523c5f03594f607a0cf24ca
https://github.com/llvm/llvm-project/commit/49516ba0e3a64bafc523c5f03594f607a0cf24ca
Author: gulfemsavrun <gulfem at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/tools/llvm-objdump/SourcePrinter.cpp
M llvm/tools/llvm-objdump/SourcePrinter.h
M llvm/tools/llvm-objdump/llvm-objdump.cpp
Log Message:
-----------
[llvm-objdump] Optimize live element tracking (#158763)
This patch significantly optimizes the LiveElementPrinter
by replacing a slow linear search with efficient hash map
lookups. It refactors the code to use a map-based system
for tracking live element addresses and managing column
assignments, leading to a major performance improvement
for large binaries.
Commit: 8cc02597f119674b7592e4db5dabf476c97ac8fa
https://github.com/llvm/llvm-project/commit/8cc02597f119674b7592e4db5dabf476c97ac8fa
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
M llvm/unittests/ExecutionEngine/Orc/WaitingOnGraphTest.cpp
Log Message:
-----------
[ORC] Clear stale ElemToPendingSN entries in WaitingOnGraph. (#169747)
WaitingOnGraph::processReadyOrFailed was not clearing stale entries from
the ElemToPendingSN map. If symbols were removed from the
ExecutionSession and then re-added this could lead to dependencies on
the stale entries, triggering a use-after-free bug.
https://github.com/llvm/llvm-project/issues/169135
Commit: b7eb9883dc9014a392f6435ba9b4058c8f8efd3f
https://github.com/llvm/llvm-project/commit/b7eb9883dc9014a392f6435ba9b4058c8f8efd3f
Author: Matej Košík <m4tej.kosik at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lldb/source/Utility/RegisterValue.cpp
Log Message:
-----------
[lldb] Use InlHostByteOrder in RegisterValue::SetValueFromData (#169624)
An existing code can be further simplified.
---------
Co-authored-by: Matej Košík <matej.kosik at codasip.com>
Commit: e2a29eca56bf92c8f3c5b5c88259211579b66182
https://github.com/llvm/llvm-project/commit/e2a29eca56bf92c8f3c5b5c88259211579b66182
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
M clang/test/Driver/fsanitize.c
M compiler-rt/test/ubsan_minimal/TestCases/override-callback.c
M llvm/include/llvm/Transforms/Instrumentation/BoundsChecking.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
M llvm/test/Instrumentation/BoundsChecking/runtimes.ll
Log Message:
-----------
[UBSan] Use -fsanitize-handler-preserve-all-regs in codegen
Pull Request: https://github.com/llvm/llvm-project/pull/168645
Commit: 48a9b07264e0b7d515806295272771af69186801
https://github.com/llvm/llvm-project/commit/48a9b07264e0b7d515806295272771af69186801
Author: Jim Lin <jim at andestech.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
Log Message:
-----------
[AMDGPU] Remove unused functions isSigned. NFC (#169750)
These have been unused since
https://github.com/llvm/llvm-project/pull/145483.
Commit: 1ff5c89176f9171bd50b1f005cbf019a5d72e0b6
https://github.com/llvm/llvm-project/commit/1ff5c89176f9171bd50b1f005cbf019a5d72e0b6
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/test/Analysis/DataFlow/test-liveness-analysis.mlir
M mlir/test/lib/Analysis/DataFlow/TestLivenessAnalysis.cpp
Log Message:
-----------
[mlir][dataflow] Add arguemnt print for test-liveness-analysis (#169625)
Add arguemnt print for test-liveness-analysis to better debug
remove-dead-values pass.
---------
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
Commit: ceba82f862b61396c2321613f544f925aefce015
https://github.com/llvm/llvm-project/commit/ceba82f862b61396c2321613f544f925aefce015
Author: Gang Chen <gangc at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll
Log Message:
-----------
[LoadStoreVectorizer] Fix one-element vector handling (#169671)
This is the followup of https://github.com/llvm/llvm-project/pull/168135
Commit: b028dacc60929995997ba1795f460d6ff0f2c302
https://github.com/llvm/llvm-project/commit/b028dacc60929995997ba1795f460d6ff0f2c302
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libcxx/include/queue
M libcxx/test/libcxx/diagnostics/queue.nodiscard.verify.cpp
Log Message:
-----------
[libc++][queue] Applied `[[nodiscard]]` (#169469)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: bd643bc1410eefced91384f816177b8189ffb981
https://github.com/llvm/llvm-project/commit/bd643bc1410eefced91384f816177b8189ffb981
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
Log Message:
-----------
[flang] Use default constructor for FIRToSCF pass (#169741)
Commit: 504b50789602813b88a482c39072822cbaa16b37
https://github.com/llvm/llvm-project/commit/504b50789602813b88a482c39072822cbaa16b37
Author: Matthias Springer <me at m-sp.org>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Transforms/Utils/DialectConversion.cpp
A mlir/test/Transforms/test-legalizer-no-rollback.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Add support for `replaceUsesWithIf` (#169606)
This commit adds support for `replaceUsesWithIf` (and variants such as
`replaceAllUsesExcept`) to the `ConversionPatternRewriter`. This API is
supported only in no-rollback mode. An assertion is triggered in
rollback mode. (This missing assertion has been confusing for users
because it seemed that the API supported, while it was actually not
working properly.)
This commit brings us a bit closer towards removing
[this](https://github.com/llvm/llvm-project/blob/76ec25f729fcc7ae576caf21293cc393e68e7cf7/mlir/lib/Transforms/Utils/DialectConversion.cpp#L1214)
workaround.
Additional changes are needed to support this API in rollback mode. In
particular, no entries should be added to the `ConversionValueMapping`
for conditional replacements. It's unclear at this point if this API can
be supported in rollback mode, so this is deferred to later.
This commit turns `replaceUsesWithIf` into a virtual function, so that
the `ConversionPatternRewriter` can override it. All other API functions
for conditional value replacements call that function.
Note for LLVM integration: If you are seeing failed assertions due to
this change, you are using unsupported API in your dialect conversion.
You have 3 options: (1) Migrate to the no-rollback driver. (2) Rewrite
your patterns without the unsupported API. (3) Last resort: bypass the
rewriter and call `replaceUsesWithIf` etc. directly on the `Value`
object.
Commit: bacca2337156edd28fc5bb0237371dc01bdc19e0
https://github.com/llvm/llvm-project/commit/bacca2337156edd28fc5bb0237371dc01bdc19e0
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libcxx/include/__mdspan/extents.h
M libcxx/include/__mdspan/mdspan.h
M libcxx/test/libcxx/containers/views/mdspan/extents/assert.obs.pass.cpp
A libcxx/test/libcxx/containers/views/mdspan/nodiscard.verify.cpp
Log Message:
-----------
[libc++][mdspan] Applied `[[nodiscard]]` (#169326)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: fb18f75343738570b9f34b89973ef2ae4ada7a85
https://github.com/llvm/llvm-project/commit/fb18f75343738570b9f34b89973ef2ae4ada7a85
Author: Janet Yang <qxy11 at meta.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/DAP.py
Log Message:
-----------
[lldb-dap] Add breakpoints after debugger initialization in DExTer (#169744)
# Summary
This is a forward fix for test errors from
https://github.com/llvm/llvm-project/pull/163653.
The PR moved debugger initialization outside of
InitializeRequestHandler, and into Launch/AttachRequestHandlers to
support DAP sessions sharing debugger instances for dynamically created
targets. However, DExTer's DAP class seemed to set breakpoints before
the debugger was initialized, which caused the tests to hang waiting for
a breakpoint to hit due to none of the breakpoints getting resolved.
# Tests
```
bin/llvm-lit -v /home/qxy11/llvm/llvm-project/cross-project-tests/debuginfo-tests/dexter-tests/
```
Commit: b3428bb966f1de8aa48375ffee0eba04ede133b7
https://github.com/llvm/llvm-project/commit/b3428bb966f1de8aa48375ffee0eba04ede133b7
Author: Peter Collingbourne <pcc at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/IR/LLVMContextImpl.cpp
Log Message:
-----------
Add missing freeConstants() call for ConstantPtrAuths.
Fixes memory leak uncovered by #133533.
Commit: e7dec231fe4da28c76ecb212360b155beec40cc9
https://github.com/llvm/llvm-project/commit/e7dec231fe4da28c76ecb212360b155beec40cc9
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/IR/ReplaceConstant.cpp
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-constexpr.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr.ll
A llvm/test/CodeGen/AMDGPU/same-lds-variable-multiple-use-in-one-phi-node.ll
Log Message:
-----------
[ReplaceConstant] Don't create instructions for the same constant multiple times in the same basic block (#169141)
Fixes #167500.
Commit: 601f79622af6f042379483573fc913c8686fabb6
https://github.com/llvm/llvm-project/commit/601f79622af6f042379483573fc913c8686fabb6
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Dialect/LLVMIR/nvvm/invalid-convert-stochastic-rounding.mlir
A mlir/test/Target/LLVMIR/nvvm/convert_fp16x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_stochastic_rounding.mlir
A mlir/test/Target/LLVMIR/nvvm/invalid_convert_fp16x2.mlir
Log Message:
-----------
[MLIR][NVVM] Add missing rounding modes in fp16x2 conversions (#169005)
This change adds the `RN` and `RZ` rounding modes to the
`convert.f32x2.to.f16x2` and `convert.f32x2.to.bf16x2` Ops.
Tests are added in `convert_fp16x2.mlir` and
`invalid_convert_fp16x2.mlir`.
Tests with these Ops in `convert_stochastic_rounding.mlir` and
`invalid-convert-stochastic-rounding.mlir` have been removed or
modified.
PTX spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt
Commit: 1748e2330e230cfea3c8c09547af257f2f82b002
https://github.com/llvm/llvm-project/commit/1748e2330e230cfea3c8c09547af257f2f82b002
Author: Rajat Bajpai <rbajpai at nvidia.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
Log Message:
-----------
[MLIR][Intrinsics] Add new MLIR API to automatically resolve overload types (#168188)
Add createIntrinsicCall overload that accepts return type and arguments,
automatically resolve overload types rather than requiring manual
computation. Simplifies NVVM_PrefetchOp by removing conditional overload
logic.
Commit: 40991215f4aba37fd43b65d96ad0a445dcd041b2
https://github.com/llvm/llvm-project/commit/40991215f4aba37fd43b65d96ad0a445dcd041b2
Author: Eric Li <li.zhe.hua at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/Tooling/Transformer/SourceCode.cpp
M clang/unittests/Tooling/SourceCodeTest.cpp
Log Message:
-----------
[clang][Tooling] Fix `getFileRange` returning a range spanning across macro arguments (#169757)
When the start and end token are both spelled in macro arguments, we
still want to reject the range if they come from two separate macro
arguments, as the original specified range is not precisely spelled in a
single sequence of characters in source.
Commit: fede9471c48d91cae6ee94f247797ba3d30bfa80
https://github.com/llvm/llvm-project/commit/fede9471c48d91cae6ee94f247797ba3d30bfa80
Author: Men-cotton <mencotton0410 at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
A mlir/test/Dialect/LLVMIR/invalid-cg-profile.mlir
Log Message:
-----------
[mlir][LLVMIR] Handle missing functions in CGProfile module flags (#169517)
This commit extends the CGProfile module flags export with support for missing function references. Previously, this caused a crash and now it's properly exported to `null` values in the metadata node.
Fixes: https://github.com/llvm/llvm-project/issues/160717
Commit: 6696e0c8f8605e8ebef4a786e244baf3d6a09816
https://github.com/llvm/llvm-project/commit/6696e0c8f8605e8ebef4a786e244baf3d6a09816
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
Log Message:
-----------
[clang][bytecode] Remove double diagnostic emission (#169658)
We emit this diagnostic from CheckPointerToIntegralCast() already, so
remove the emission from CastPointerIntegral().
Commit: f6712b6ea3d59b019e26f8716020d4ca654c043c
https://github.com/llvm/llvm-project/commit/f6712b6ea3d59b019e26f8716020d4ca654c043c
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/U.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/const_T.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/const_optional_U.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/copy.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/ctor.verify.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/deduct.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/deduct.verify.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/default.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/empty_in_place_t_does_not_clobber.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/explicit_const_optional_U.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/explicit_optional_U.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/in_place_t.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/initializer_list.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/move.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/nullopt_t.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/optional_U.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/rvalue_T.pass.cpp
Log Message:
-----------
[libc++] Reformat `optional` constructor tests (#169231)
- Mass-reformat tests in
`std/utilities/optional/optional.object/optional.object.ctor` and
rearrange header `#include`s
- No functional changes
- Prelude for #169203
Commit: a9cc7fe3caf6e14ae755689df8ccde2edc4c8a43
https://github.com/llvm/llvm-project/commit/a9cc7fe3caf6e14ae755689df8ccde2edc4c8a43
Author: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProf.h
Log Message:
-----------
[NFC][SampleFDO] Use const& to avoid copies (#164584)
Use const& in range-based for loop to avoid unnecessary copies
Commit: 326a1a4badcd13ad8e722ac542cff19eed7bb03a
https://github.com/llvm/llvm-project/commit/326a1a4badcd13ad8e722ac542cff19eed7bb03a
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
Log Message:
-----------
[MLIR][XeGPU] Add anchor_layout and update propagation to honor user-specified layouts (#169267)
Introduce anchor layout for XeGPU anchor ops: load_nd, store_nd,
prefetch_nd, dpas, load, store, prefetch, load_matrix, store_matrix, and
atomic_rmw. Anchor layout is permanent, and is guaranteed to be honored
by XeGPU distribution and lowerinngs once specified.
1. Add anchor_layout for XeGPU anchor OPs: load_nd, store_nd,
prefetch_nd, dpas, load, store, prefetch, load_matrix, store_matrix, and
atomic_rmw.
2. rename layout attributes to anchor_layout for these ops: load, store,
load_matrix, store_matrix
3. update layout propagation pass: Only when user doesn't specify anchor
layout, the pass computes a default layout and set to anchor op's
permant layout and use that for propagation. if user specified anchor
layout, the pass takes user-specified anchor layout. permant layout and
use that for propagation. if user specified anchor layout, the pass
takes user-specified anchor layout.
Commit: f1ddb2f4120645b56802859e26e2006e6db72597
https://github.com/llvm/llvm-project/commit/f1ddb2f4120645b56802859e26e2006e6db72597
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
A llvm/test/CodeGen/LoongArch/lasx/rotl-rotr.ll
A llvm/test/CodeGen/LoongArch/lsx/rotl-rotr.ll
Log Message:
-----------
[LoongArch][NFC] Pre-commit tests for vector rotl/rotr (#161115)
Commit: bb9449d5bbd72441d8f95052ddfd29e2d29297d7
https://github.com/llvm/llvm-project/commit/bb9449d5bbd72441d8f95052ddfd29e2d29297d7
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
A llvm/test/Transforms/InstCombine/get_vector_length.ll
Log Message:
-----------
[InstCombine] Fold @llvm.experimental.get.vector.length when cnt <= max_lanes (#169293)
On RISC-V, some loops that the loop vectorizer vectorizes pre-LTO may
turn out to have the exact trip count exposed after LTO, see #164762.
If the trip count is small enough we can fold away the
@llvm.experimental.get.vector.length intrinsic based on this corollary
from the LangRef:
> If %cnt is less than or equal to %max_lanes, the return value is equal
to %cnt.
This on its own doesn't remove the @llvm.experimental.get.vector.length
in #164762 since we also need to teach computeKnownBits about
@llvm.experimental.get.vector.length and the sub recurrence, but this PR
is a starting point.
I've added this in InstCombine rather than InstSimplify since we may
need to insert a truncation (@llvm.experimental.get.vector.length can
take an i64 %cnt argument, the result is always i32).
Note that there was something similar done in VPlan in #167647 for when
the loop vectorizer knows the trip count.
Commit: 6abbbca32472537389a4fd9961f680251a57e82b
https://github.com/llvm/llvm-project/commit/6abbbca32472537389a4fd9961f680251a57e82b
Author: David Green <david.green at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
A llvm/test/Transforms/AggressiveInstCombine/umulh_carry.ll
A llvm/test/Transforms/AggressiveInstCombine/umulh_carry4.ll
A llvm/test/Transforms/AggressiveInstCombine/umulh_ladder.ll
A llvm/test/Transforms/AggressiveInstCombine/umulh_ladder4.ll
Log Message:
-----------
[AggressiveInstCombine] Match long high-half multiply (#168396)
This patch adds recognition of high-half multiply by parts into a single
larger multiply.
Considering a multiply made up of high and low parts, we can split the
multiply into:
x * y == (xh*T + xl) * (yh*T + yl)
where `xh == x>>32` and `xl == x & 0xffffffff`. `T = 2^32`.
This expands to
xh*yh*T*T + xh*yl*T + xl*yh*T + xl*yl
which I find it helpful to be drawn as
[ xh*yh ]
[ xh*yl ]
[ xl*yh ]
[ xl*yl ]
We are looking for the "high" half, which is xh*yh + xh*yl>>32 + xl*yh>>32 +
carrys. The carry makes this difficult and there are multiple ways of
representing it. The ones we attempt to support here are:
Carry: xh*yh + carry + lowsum
carry = lowsum < xh*yl ? 0x1000000 : 0
lowsum = xh*yl + xl*yh + (xl*yl>>32)
Ladder: xh*yh + c2>>32 + c3>>32
c2 = xh*yl + (xl*yl >> 32); c3 = c2&0xffffffff + xl*yh
Carry4: xh*yh + carry + crosssum>>32 + (xl*yl + crosssum&0xffffffff) >> 32
crosssum = xh*yl + xl*yh
carry = crosssum < xh*yl ? 0x1000000 : 0
Ladder4: xh*yh + (xl*yh)>>32 + (xh*yl)>>32 + low>>32;
low = (xl*yl)>>32 + (xl*yh)&0xffffffff + (xh*yl)&0xfffffff
They all start by matching `xh*yh` + 2 or 3 other operands. The bottom of the
tree is `xh*yh`, `xh*yl`, `xl*yh` and `xl*yl`.
Based on #156879 by @c-rhodes
Commit: 1c7ec06b16dc59b5b52cff95bde7d5330ffa0293
https://github.com/llvm/llvm-project/commit/1c7ec06b16dc59b5b52cff95bde7d5330ffa0293
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
Log Message:
-----------
[VPlan] Optimize LastActiveLane to EVL - 1 (#169766)
With EVL tail folding, the LastActiveLane can be computed with EVL - 1.
This removes the need for a header mask and vfirst.m for loops with live
outs on RISC-V:
# %bb.5: # %for.cond.cleanup7
- vsetvli zero, zero, e32, m2, ta, ma
- vmv.v.x v8, s1
- vmsleu.vv v10, v8, v22
- vfirst.m a0, v10
- srli a1, a0, 63
- czero.nez a0, a0, a1
- czero.eqz a1, s8, a1
- or a0, a0, a1
- addi a0, a0, -1
- vsetvli zero, zero, e64, m4, ta, ma
- vslidedown.vx v8, v12, a0
+ addi s1, s1, -1
+ vslidedown.vx v8, v12, s1
Commit: 9cb9b16fd63365fe452947ffdfbccd3ac7e6a08c
https://github.com/llvm/llvm-project/commit/9cb9b16fd63365fe452947ffdfbccd3ac7e6a08c
Author: Vadim Curcă <80581374+VadimCurca at users.noreply.github.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/test/Target/LLVMIR/Import/metadata-profiling.ll
Log Message:
-----------
[mlir][llvm] Fix import of branch weights with "expected" field (#169776)
This commit fixes the import of `branch_weights` metadata from LLVM IR
to the LLVM dialect. Previously, `branch_weights` metadata containing
the `!"expected"` field were rejected because the importer expected
integer weights at operand 1, but found a string.
Commit: dc8311f207f4facf88a8c939b4132afdaab08470
https://github.com/llvm/llvm-project/commit/dc8311f207f4facf88a8c939b4132afdaab08470
Author: David Green <david.green at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir
Log Message:
-----------
[ARM] Remove IR from mve vpt mir tests. NFC
As far as I can tell the llvm.arm.mve.vminnm.m intrinsic used in these tests
was the pre-upstream name of llvm.arm.mve.min.predicated. The tests should not
need IR sections, so remove them just relying on the MIR portions.
Commit: c28c99f51101d5130eeb9df061dcd10a1750d97b
https://github.com/llvm/llvm-project/commit/c28c99f51101d5130eeb9df061dcd10a1750d97b
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/test/SemaHIP/amdgpu-gfx950-load-to-lds.hip
Log Message:
-----------
[NFC][HIP] Add __builtin_*_load_lds type check test cases (#165388)
This tests show how type-checking is performed for
`__builtin_amdgcn_load_to_lds`,
but not for `__builtin_amdgcn_raw_ptr_buffer_load_lds`,
`__builtin_amdgcn_struct_ptr_buffer_load_lds` and
`__builtin_amdgcn_global_load_lds` since they are declared with the 't'
attribute.
Stacked on top of: https://github.com/llvm/llvm-project/pull/165387
Commit: 650eeb867fa95435b7c123e6630eb98934ac5bf3
https://github.com/llvm/llvm-project/commit/650eeb867fa95435b7c123e6630eb98934ac5bf3
Author: Nathan Corbyn <n_corbyn at apple.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
Log Message:
-----------
[ShrinkWrap] Modify shrink wrapping to accommodate functions terminated by no-return blocks (#167548)
At present, the shrink wrapping pass misses opportunities to shrink wrap
in the presence of machine basic blocks which exit the function without
returning. Such cases arise from C++ functions like the following:
```cxx
int foo(int err, void* ptr) {
if (err == -1) {
if (ptr == nullptr) {
throw MyException("Received `nullptr`!", __FILE__, __LINE__);
}
handle(ptr);
}
return STATUS_OK;
}
```
In particular, assuming `MyException`'s constructor is not marked
`noexcept`, the above code will generate a trivial EH landing pad
calling `__cxa_free_exception()` and rethrowing the unhandled internal
exception, exiting the function without returning. As such, the shrink
wrapping pass refuses to touch the above function, spilling to the stack
on every call, even though no CSRs are clobbered on the hot path. This
patch tweaks the shrink wrapping logic to enable the pass to fire in
this and similar cases.
Commit: c3c3d16773f8db2188145378500070658afeb30f
https://github.com/llvm/llvm-project/commit/c3c3d16773f8db2188145378500070658afeb30f
Author: NagaChaitanya Vellanki <pnagato at protonmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/avx512vbmiintrin.h
M clang/lib/Headers/avx512vbmivlintrin.h
M clang/test/CodeGen/X86/avx512vbmi-builtins.c
M clang/test/CodeGen/X86/avx512vbmivl-builtin.c
Log Message:
-----------
[Clang] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - Allow AVX512 VPMULTISHIFTQB intrinsics to be used in constexpr (#168995)
Resolves #167477
Commit: 0b1651260a36b38a65bb4f14ad8c9c5551ab5a34
https://github.com/llvm/llvm-project/commit/0b1651260a36b38a65bb4f14ad8c9c5551ab5a34
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/utils/TableGen/README.md
Log Message:
-----------
[llvm][Tablegen] Link to tutorial before programmer's reference
The natural assumption is that there's some sort of order here
and having people read the reference manual before the basic
tutorial does not make sense to me.
Commit: 8401a8d0be7671fb5089f850a34dc92ad4a2eb12
https://github.com/llvm/llvm-project/commit/8401a8d0be7671fb5089f850a34dc92ad4a2eb12
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
A llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll
A llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll.bc
Log Message:
-----------
[NFC][LLVM] Add bitcode tests for llvm.aarch64.sve.rev
Commit: 0dbedd195c94e89b43660e67aa56dd139a81fa40
https://github.com/llvm/llvm-project/commit/0dbedd195c94e89b43660e67aa56dd139a81fa40
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/lib/Headers/avx10_2_512bf16intrin.h
M clang/lib/Headers/avx10_2bf16intrin.h
M clang/lib/Headers/avx512vlfp16intrin.h
M clang/lib/Headers/avxintrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/xmmintrin.h
M clang/test/CodeGen/X86/sse-builtins-constrained.c
M clang/test/CodeGen/X86/sse-builtins.c
M clang/test/CodeGen/X86/sse2-builtins-constrained.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/builtins-x86.c
Log Message:
-----------
[Clang] Replace some x86 sqrt builtins with the generic __builtin_elementwise_sqrt versions (#165682)
Commit: bec726f6a6d37bdfb90d1330d4b5e947ce017046
https://github.com/llvm/llvm-project/commit/bec726f6a6d37bdfb90d1330d4b5e947ce017046
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
A llvm/test/CodeGen/X86/haddsubsat.ll
Log Message:
-----------
[X86] optimize ssse3 horizontal saturating add/sub (#169591)
Currently LLVM fails to recognize a manual implementation of `phadd`
https://godbolt.org/z/zozrssaWb
```llvm
declare <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
define <8 x i16> @phaddsw_v8i16_intrinsic(<8 x i16> %a, <8 x i16> %b) {
entry:
%res = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
define <8 x i16> @phaddsw_v8i16_generic(<8 x i16> %a, <8 x i16> %b) {
entry:
%even = shufflevector <8 x i16> %a, <8 x i16> %b,
<8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%odd = shufflevector <8 x i16> %a, <8 x i16> %b,
<8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%sum = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %even, <8 x i16> %odd)
ret <8 x i16> %sum
}
```
```asm
phaddsw_v8i16_intrinsic: # @phaddsw_v8i16_intrinsic
phaddsw xmm0, xmm1
ret
phaddsw_v8i16_generic: # @phaddsw_v8i16_generic
movdqa xmm2, xmmword ptr [rip + .LCPI1_0] # xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
movdqa xmm3, xmm1
pshufb xmm3, xmm2
movdqa xmm4, xmm0
pshufb xmm4, xmm2
punpcklqdq xmm4, xmm3 # xmm4 = xmm4[0],xmm3[0]
psrad xmm1, 16
psrad xmm0, 16
packssdw xmm0, xmm1
paddsw xmm0, xmm4
ret
```
This PR does recognize the pattern.
Commit: d6be9fc115459ce154f8aa062b05645adb150469
https://github.com/llvm/llvm-project/commit/d6be9fc115459ce154f8aa062b05645adb150469
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libcxx/include/deque
M libcxx/test/libcxx/diagnostics/deque.nodiscard.verify.cpp
Log Message:
-----------
[libc++][deque] Applied `[[nodiscard]]` (#169745)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: bd95a74a2c548867c004ec991defe276f9cbbf40
https://github.com/llvm/llvm-project/commit/bd95a74a2c548867c004ec991defe276f9cbbf40
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/invalid.cpp
Log Message:
-----------
[clang][bytecode] Check for invalid record decls in IntPointer::atOffset (#169786)
We can't access the RecordLayout of an invalid decl, so return failure
if that happens.
Fixes https://github.com/llvm/llvm-project/issues/167076
Commit: 682f292d2caec5b71f8ce6c641114fee446ba49f
https://github.com/llvm/llvm-project/commit/682f292d2caec5b71f8ce6c641114fee446ba49f
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
Log Message:
-----------
[LV] Test more combinations of scalar stores using last lane of IV.
Extends test coverage to include different start and step values, as
well as interleaving.
Commit: df8061272ad6d3770ddc17498eff70f700a020ad
https://github.com/llvm/llvm-project/commit/df8061272ad6d3770ddc17498eff70f700a020ad
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libcxx/include/__flat_set/flat_set.h
M libcxx/test/libcxx/diagnostics/flat_map.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/flat_set.nodiscard.verify.cpp
Log Message:
-----------
[libc++][flat_set] Applied `[[nodiscard]]` (#169739)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 7b813c3d8095ba49a8f1e935a9b14c23490e3bb0
https://github.com/llvm/llvm-project/commit/7b813c3d8095ba49a8f1e935a9b14c23490e3bb0
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/test/AST/ByteCode/invalid.cpp
Log Message:
-----------
[clang][bytecode][test] Specify triple for Invalid.cpp
This should unbreak that test on 32bit builders, e.g.
https://lab.llvm.org/buildbot/#/builders/154/builds/24509
Commit: eee09ca98470b880fdd54bd3ff7ea05ae276314a
https://github.com/llvm/llvm-project/commit/eee09ca98470b880fdd54bd3ff7ea05ae276314a
Author: Eric Xu <60671484+ericxu233 at users.noreply.github.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/test/CodeGen/X86/f16c-builtins.c
Log Message:
-----------
[X86][Clang] Allow constexpr evaluation of F16C CVTPS2PH intrinsics (#162295)
Fixes #160312
Commit: fca41f4aa105f30af75d88d993539d043ac66460
https://github.com/llvm/llvm-project/commit/fca41f4aa105f30af75d88d993539d043ac66460
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/lib/Headers/avx512bf16intrin.h
M clang/lib/Headers/avx512vlbf16intrin.h
M clang/test/CodeGen/X86/avx512bf16-builtins.c
M clang/test/CodeGen/X86/avx512vlbf16-builtins.c
Log Message:
-----------
[X86] Replace BF16 to F32 conversions with generic conversions (#169781)
Let standard casting / builtin_convertvector handle the conversions from BF16 to F32
My only query is how to best implement _mm_cvtpbh_ps - I went for the
v8bf16 -> v8f32 conversion followed by subvector extraction in the end,
but could just as easily extract a v4bf16 first - makes no difference to
final optimized codegen.
First part of #154911
Commit: ea1e62d1a00bf3d40b7a1fd926d2a573c997188d
https://github.com/llvm/llvm-project/commit/ea1e62d1a00bf3d40b7a1fd926d2a573c997188d
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/Target/Target.td
M llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
M llvm/utils/TableGen/Basic/VTEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
Log Message:
-----------
[CodeGenTypes] Remove explicit VT numbers from ValueTypes.td (#169670)
Remove explicit VT numbers from ValueTypes.td so that patches that add a
new VT do not have to renumber the entire file.
In TableGen VTs are now identified by ValueType.LLVMName instead of
ValueType.Value. This is important for target-defined types (typically
based on PtrValueType) which are not mentioned in ValueTypes.td itself.
Commit: 66ca3f1367bb59915bd9f832a9cd3dfe56304538
https://github.com/llvm/llvm-project/commit/66ca3f1367bb59915bd9f832a9cd3dfe56304538
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
A llvm/test/CodeGen/SystemZ/zos-target-flags.ll
Log Message:
-----------
[SystemZ] Serialize ada entry flags (#169395)
Adding support for serializing the ada entry flags helps with mir based
test cases. Without this change, the flags are simple displayed as being
"unkmown".
Commit: 1d7d83d0bf8f376b977f25cec75633dceb91b8f1
https://github.com/llvm/llvm-project/commit/1d7d83d0bf8f376b977f25cec75633dceb91b8f1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/darwin.ll
Log Message:
-----------
RuntimeLibcalls: Add macos unlocked IO functions to systems (#167084)
Commit: 514dbab474c71326c1080f3129a26f0ffdd71d51
https://github.com/llvm/llvm-project/commit/514dbab474c71326c1080f3129a26f0ffdd71d51
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/docs/ClangStaticAnalyzer.rst
M clang/docs/analyzer/user-docs.rst
M clang/docs/analyzer/user-docs/CommandLineUsage.rst
M clang/docs/analyzer/user-docs/Installation.rst
Log Message:
-----------
[NFC][analyzer] Clean up obsolete installation instructions (#166193)
The documentation file `Installation.rst` contained very obsolete
instructions for installing the clang static analyzer. This commit
replaces it with sentence which explains that the analyzer is part of
clang and links to the releases page of LLVM (for downloading clang).
This sentence is primarily added to the top-level page of the analyzer
documentation; but it also appears in a stubbed Installation.rst (for
users who followed a direct external link to this installation page).
This stubbed section is removed from the table of contents, but I kept
it as an orphaned page (to avoid breaking links).
Fixes #165571
Commit: d128d90e71146cf099a31a967fdeb2591d30514d
https://github.com/llvm/llvm-project/commit/d128d90e71146cf099a31a967fdeb2591d30514d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/emscripten.ll
Log Message:
-----------
RuntimeLibcalls: Add small_printf functions to emscripten (#167087)
Commit: 97aa4f3abbba2ce4460c0d8e5364bd333aaa8079
https://github.com/llvm/llvm-project/commit/97aa4f3abbba2ce4460c0d8e5364bd333aaa8079
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/xcore.ll
Log Message:
-----------
XCore: Add iprintf to RuntimeLibcalls system library (#167088)
Commit: 6412184891526690cff804f87f986b1fa039f011
https://github.com/llvm/llvm-project/commit/6412184891526690cff804f87f986b1fa039f011
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/docs/Dialects/NVVMDialect.md
Log Message:
-----------
[MLIR][NVVM][Docs] Update docs (#169694)
This patch updates the NVVM Dialect docs to:
* include information on the type of pointers for the memory spaces.
* include high-level information on mbarrier objects.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 4394aa685c4b01ad3782a137fcfebeadc4941df1
https://github.com/llvm/llvm-project/commit/4394aa685c4b01ad3782a137fcfebeadc4941df1
Author: Jason-VanBeusekom <jason.van-beusekom at hpe.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/docs/HIPSupport.rst
M clang/lib/CodeGen/CodeGenModule.cpp
A clang/test/CodeGenCUDA/cuda_weak_alias.cu
A clang/test/CodeGenHIP/hip_weak_alias.cpp
A clang/test/OpenMP/amdgcn_weak_alias.c
A clang/test/OpenMP/amdgcn_weak_alias.cpp
A clang/test/OpenMP/nvptx_weak_alias.c
Log Message:
-----------
[OpenMP][clang][HIP][CUDA] fix weak alias emit on device compilation (#164326)
This PR adds checks for when emitting weak aliases in: `void
CodeGenModule::EmitGlobal(GlobalDecl GD)`, before for device compilation
for OpenMP, HIP and Cuda, clang would look for the aliasee even if it
was never marked for device compilation.
For OpenMP the following case now works:
> Failed before when compiling with device, ie: `clang -fopenmp
-fopenmp-targets=amdgcn-amd-amdhsa`
> ```
> int __Two(void) { return 2; }
> int Two(void) __attribute__ ((weak, alias("__Two")));
> ```
For HIP / Cuda:
>
> ```
> int __HostFunc(void) { return 42; }
> int HostFunc(void) __attribute__ ((weak, alias("__HostFunc")));
> ```
For HIP:
>Failed before on HIP, Cuda fails due to: `NVPTX aliasee must not be
'.weak'` error
> ```
> __device__ int __One(void) { return 2; }
> __device__ int One(void) __attribute__ ((weak, alias("__One")));
> ```
Included are Codegen LIT tests for the above cases, and also cases for
weak alias cases that currently work in clang.
Fixes https://github.com/llvm/llvm-project/issues/117369
Commit: 0e5633fcd984b54acc071c2c982c1ff4691aa10f
https://github.com/llvm/llvm-project/commit/0e5633fcd984b54acc071c2c982c1ff4691aa10f
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/test/OpenMP/cancel_codegen.cpp
M clang/test/OpenMP/critical_codegen.cpp
M clang/test/OpenMP/critical_codegen_attr.cpp
M clang/test/OpenMP/irbuilder_nested_parallel_for.c
M clang/test/OpenMP/masked_codegen.cpp
M clang/test/OpenMP/master_codegen.cpp
M clang/test/OpenMP/nested_loop_codegen.cpp
M clang/test/OpenMP/ordered_codegen.cpp
M clang/test/OpenMP/parallel_codegen.cpp
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/test/Transforms/OpenMP/parallel_region_merging.ll
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-barrier-cancel.mlir
M mlir/test/Target/LLVMIR/openmp-cancel.mlir
M mlir/test/Target/LLVMIR/openmp-cancellation-point.mlir
M mlir/test/Target/LLVMIR/openmp-outline-infinite-loop.mlir
M mlir/test/Target/LLVMIR/openmp-parallel-reduction-multiblock.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-array-sections.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-init-arg.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-sections.mlir
Log Message:
-----------
[OMPIRBuilder] always leave PARALLEL via the same barrier (#164586)
A barrier will pause execution until all threads reach it. If some go to
a different barrier then we deadlock. This manifests in that the
finalization callback must only be run once. Fix by ensuring we always
go through the same finalization block whether the thread in cancelled
or not and no matter which cancellation point causes the cancellation.
The old callback only affected PARALLEL, so it has been moved into the
code generating PARALLEL. For this reason, we don't need similar changes
for other cancellable constructs. We need to create the barrier on the
shared exit from the outlined function instead of only on the cancelled
branch to make sure that threads exiting normally (without cancellation)
meet the same barriers as those which were cancelled. For example,
previously we might have generated code like
```
...
%ret = call i32 @__kmpc_cancel(...)
%cond = icmp eq i32 %ret, 0
br i1 %cond, label %continue, label %cancel
continue:
// do the rest of the callback, eventually branching to %fini
br label %fini
cancel:
// Populated by the callback:
// unsafe: if any thread makes it to the end without being cancelled
// it won't reach this barrier and then the program will deadlock
%unused = call i32 @__kmpc_cancel_barrier(...)
br label %fini
fini:
// run destructors etc
ret
```
In the new version the barrier is moved into fini. I generate it *after*
the destructors because the standard describes the barrier as occurring
after the end of the parallel region.
```
...
%ret = call i32 @__kmpc_cancel(...)
%cond = icmp eq i32 %ret, 0
br i1 %cond, label %continue, label %cancel
continue:
// do the rest of the callback, eventually branching to %fini
br label %fini
cancel:
br label %fini
fini:
// run destructors etc
// safe so long as every exit from the function happens via this block:
%unused = call i32 @__kmpc_cancel_barrier(...)
ret
```
To achieve this, the barrier is now generated alongside the finalization
code instead of in the callback. This is the reason for the changes to
the unit test.
I'm unsure if I should keep the incorrect barrier generation callback
only on the cancellation branch in clang with the OMPIRBuilder backend
because that would match clang's ordinary codegen. Right now I have
opted to remove it entirely because it is a deadlock waiting to happen.
Commit: 47ae3eaa29f2195429f2ca19cc171a9ebd83c242
https://github.com/llvm/llvm-project/commit/47ae3eaa29f2195429f2ca19cc171a9ebd83c242
Author: Jack Styles <jack.styles at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M flang/docs/OpenMPSupport.md
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir
A mlir/test/Target/LLVMIR/openmp-dist_schedule.mlir
A mlir/test/Target/LLVMIR/openmp-dist_schedule_with_wsloop.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[MLIR][OpenMP] Add MLIR Lowering Support for dist_schedule (#152736)
`dist_schedule` was previously supported in Flang/Clang but was not
implemented in MLIR, instead a user would get a "not yet implemented"
error. This patch adds support for the `dist_schedule` clause to be
lowered to LLVM IR when used in an `omp.distribute` or `omp.wsloop`
section.
There has needed to be some rework required to ensure that MLIR/LLVM
emits the correct Schedule Type for the clause, as it uses a different
schedule type to other OpenMP directives/clauses in the runtime library.
This patch also ensures that when using dist_schedule or a chunked
schedule clause, the correct llvm loop parallel accesses details are
added.
Commit: e3044cd552ca0300dbb4c1051dccd038382bd4af
https://github.com/llvm/llvm-project/commit/e3044cd552ca0300dbb4c1051dccd038382bd4af
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[X86] Sync multiversion features with libgcc and refactor internal feature tables (#168750)
Compiler-rt internal feature table is synced with the one in libgcc
(common/config/i386/i386-cpuinfo.h).
LLVM internal feature table is refactored to include a field ABI_VALUE,
so we won't be relying on ordering to keep the values correct. The table
is also synced to the one in compiler-rt.
Commit: c0d81bf55f3dc3b38a1d403ee07e547016f46842
https://github.com/llvm/llvm-project/commit/c0d81bf55f3dc3b38a1d403ee07e547016f46842
Author: David Green <david.green at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.h
M llvm/lib/Target/ARM/ARMMCInstLower.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
Log Message:
-----------
[ARM] Remove Subtarget from ARMAsmPrinter (#168264)
Remove Subtarget uses from ARMAsmPrinter, making use of TargetMachine
where applicable and getting the Subtarget from the MF where not. Some
of the `if() llvm_unreachable` have been replaced by `asserts`.
Commit: adcc557ef176ee36a1e5df12b60789b6fa2fe73c
https://github.com/llvm/llvm-project/commit/adcc557ef176ee36a1e5df12b60789b6fa2fe73c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/test/CodeGen/X86/srem-vector-lkk.ll
M llvm/test/CodeGen/X86/urem-vector-lkk.ll
Log Message:
-----------
[X86] rem-vector-lkk.ll - improve CPU coverage to cover all x86-64 levels (#169805)
SSE2/SSE42/AVX1/AVX2 + x86-64-v4 (AVX512)
Commit: 920a091da216521cbef4203ad69c63aaa2ea2154
https://github.com/llvm/llvm-project/commit/920a091da216521cbef4203ad69c63aaa2ea2154
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libcxx/test/libcxx-03/algorithms/half_positive.pass.cpp
M libcxx/test/libcxx-03/algorithms/robust_against_copying_comparators.pass.cpp
M libcxx/test/libcxx-03/algorithms/robust_against_cpp20_hostile_iterators.compile.pass.cpp
M libcxx/test/libcxx-03/containers/sequences/vector/asan.pass.cpp
M libcxx/test/libcxx-03/containers/sequences/vector/asan_throw.pass.cpp
M libcxx/test/libcxx-03/depr/depr.default.allocator/allocator.members/construct.cxx20.pass.cpp
M libcxx/test/libcxx-03/input.output/string.streams/stringbuf/const_sso_buffer.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/arithmetic.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/comparison.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/pointer_traits.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/types.compile.pass.cpp
M libcxx/test/libcxx-03/iterators/contiguous_iterators.conv.compile.pass.cpp
M libcxx/test/libcxx-03/iterators/contiguous_iterators.pass.cpp
M libcxx/test/libcxx-03/iterators/predef.iterators/insert.iterators/back.insert.iter.ops/get_container.pass.cpp
M libcxx/test/libcxx-03/iterators/unwrap_iter.pass.cpp
M libcxx/test/libcxx-03/language.support/support.dynamic/libcpp_deallocate.sh.cpp
M libcxx/test/libcxx-03/libcpp_alignof.pass.cpp
M libcxx/test/libcxx-03/memory/allocation_guard.pass.cpp
M libcxx/test/libcxx-03/memory/swap_allocator.pass.cpp
M libcxx/test/libcxx-03/numerics/bit.ops.pass.cpp
M libcxx/test/libcxx-03/strings/basic.string/string.capacity/max_size.pass.cpp
M libcxx/test/libcxx-03/strings/basic.string/string.cons/copy_shrunk_long.pass.cpp
M libcxx/test/libcxx-03/strings/c.strings/constexpr_memmove.pass.cpp
M libcxx/test/libcxx-03/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/bullet_1_2_3.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/bullet_4_5_6.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/bullet_7.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/invoke.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/invoke_helpers.h
M libcxx/test/libcxx-03/utilities/is_pointer_in_range.pass.cpp
M libcxx/test/libcxx-03/utilities/is_valid_range.pass.cpp
M libcxx/test/libcxx-03/utilities/memory/pointer.conversion/to_address.pass.cpp
M libcxx/test/libcxx-03/utilities/memory/pointer.conversion/to_address_std_iterators.pass.cpp
M libcxx/test/libcxx-03/utilities/meta/is_referenceable.compile.pass.cpp
M libcxx/test/libcxx-03/utilities/no_destroy.pass.cpp
M libcxx/test/libcxx-03/utilities/utility/pairs/pairs.pair/abi.non_trivial_copy_move.pass.cpp
M libcxx/test/libcxx-03/utilities/utility/pairs/pairs.pair/abi.trivial_copy_move.pass.cpp
M libcxx/test/libcxx-03/utilities/utility/pairs/pairs.pair/abi.trivially_copyable.compile.pass.cpp
Log Message:
-----------
[libc++][C++03] Remove code in the C++03-specific tests that is guarded on the language version (#169354)
This is dead code, since `test/libcxx-03` is only ever executed with
`-std=c++03`.
Commit: 634f6e9ff357050ab28de150f35bf293cd31b332
https://github.com/llvm/llvm-project/commit/634f6e9ff357050ab28de150f35bf293cd31b332
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libcxx/include/__algorithm/copy_n.h
M libcxx/include/__algorithm/iterator_operations.h
M libcxx/include/__algorithm/ranges_copy_n.h
M libcxx/include/__vector/vector.h
Log Message:
-----------
[libc++] Merge the implementations of ranges::copy_n and std::copy_n and fix vector::insert to assign (#157444)
This reduces the amount of code we have to maintain a bit.
This also simplifies `vector` by using the internal API instead of
`#if`s to switch based on language dialect.
Commit: f8e77168c89a142b6e2bdb9ea8322c42c0808fae
https://github.com/llvm/llvm-project/commit/f8e77168c89a142b6e2bdb9ea8322c42c0808fae
Author: NagaChaitanya Vellanki <pnagato at protonmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/avx2intrin.h
M clang/lib/Headers/avx512bwintrin.h
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avx512vlintrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/mmintrin.h
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[Clang] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - Allow PSLL/PSRA/PSRL var intrinsics to be used in constexpr (#169276)
Resolves #169176
Commit: b64150963733d04e524f501cdd736963a7a3ba6d
https://github.com/llvm/llvm-project/commit/b64150963733d04e524f501cdd736963a7a3ba6d
Author: Julian Nagele <j.nagele at apple.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/test/Transforms/LoopUnroll/partial-unroll-reductions.ll
M llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
Log Message:
-----------
[LoopUnroll] Introduce parallel accumulators when unrolling FP reductions. (#166630)
This is building on top of
https://github.com/llvm/llvm-project/pull/149470, also introducing
parallel accumulator PHIs when the reduction is for floating points,
provided we have the reassoc flag. See also
https://github.com/llvm/llvm-project/pull/166353, which aims to
introduce parallel accumulators for reductions with vector instructions.
Commit: 8871e9e2e2c0941b04b22f719906a588fe523be2
https://github.com/llvm/llvm-project/commit/8871e9e2e2c0941b04b22f719906a588fe523be2
Author: Jacob Lambert <jacob.lambert at amd.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
Log Message:
-----------
[clang][Driver] Handle ROCm installation layout of lib/llvm/bin/clang (#138928)
Committing on behalf of @stellaraccident
Commit: 7f1423e58ac894e7225625f34d90806ce5f052b3
https://github.com/llvm/llvm-project/commit/7f1423e58ac894e7225625f34d90806ce5f052b3
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/Delinearization.h
M llvm/lib/Analysis/Delinearization.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/Delinearization/a.ll
M llvm/test/Analysis/Delinearization/constant_functions_multi_dim.ll
M llvm/test/Analysis/Delinearization/divide_by_one.ll
M llvm/test/Analysis/Delinearization/fixed_size_array.ll
M llvm/test/Analysis/Delinearization/himeno_1.ll
M llvm/test/Analysis/Delinearization/himeno_2.ll
M llvm/test/Analysis/Delinearization/iv_times_constant_in_subscript.ll
M llvm/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_3d.ll
M llvm/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_nts_3d.ll
M llvm/test/Analysis/Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll
M llvm/test/Analysis/Delinearization/multidim_only_ivs_2d.ll
M llvm/test/Analysis/Delinearization/multidim_only_ivs_3d.ll
M llvm/test/Analysis/Delinearization/multidim_only_ivs_3d_cast.ll
M llvm/test/Analysis/Delinearization/multidim_two_accesses_different_delinearization.ll
M llvm/test/Analysis/Delinearization/parameter_addrec_product.ll
M llvm/test/Analysis/Delinearization/terms_with_identity_factor.ll
Log Message:
-----------
[DA][Delinearization] Move validation logic into Delinearization (#169047)
This patch moves the validation logic of delinearization results from DA
to Delinearization. Also call it in `printDelinearization` to test its
behavior. The motivation is as follows:
- Almost the same code exists in `tryDelinearizeFixedSize` and
`tryDelinearizeParametricSize`. Consolidating it in Delinearization
avoids code duplication.
- Currently this validation logic is not well tested. Moving it to
Delinearization allows us to write regression tests easily.
This patch changes the test outputs and debug messages, but otherwise
NFCI.
Commit: 90e8889a6394e29843ba903eff45ca03f877a6dd
https://github.com/llvm/llvm-project/commit/90e8889a6394e29843ba903eff45ca03f877a6dd
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
Log Message:
-----------
[lldb] Fix CxxMethodName Parser on return type (#169652)
The simplified parser incorrectly assumes if there is a context, there
is no return type.
Fixed the case where functions have both a context and a return type.
For example,
`int foo::bar::func()`
`Type<int> foo::bar::func()`
Also fixed the case where there is no space between the context and
return.
`std::vector<int>foo::bar()`
Commit: e0c0075819f4fe30c1522a1972b683641e66507a
https://github.com/llvm/llvm-project/commit/e0c0075819f4fe30c1522a1972b683641e66507a
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/disabled-on-amd.ll
Log Message:
-----------
[SPIRV][AMD] Disable SPV_KHR_float_control2 for AMD flavored SPIRV (#169659)
AMD uses the translator to recover LLVM-IR from SPIRV.
Currently, the translator doesn't implement the
`SPV_KHR_float_controls2` extension (I'm working on it).
If this extension is used by the SPIRV module, we cannot translate it
back to LLVM-IR.
I'm working on the extension, but in the meantime, lets just disable it
when the target triple's vendor is `amd`.
Commit: 48e34d95987aec19585672b2363eda1a99338751
https://github.com/llvm/llvm-project/commit/48e34d95987aec19585672b2363eda1a99338751
Author: Ingo Müller <ingomueller at google.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir:bazel] Fix build broken by #169670. (#169804)
This PR adds a dependency to the `BUILD` files overlay silently added by
#169670.
Signed-off-by: Ingo Müller <ingomueller at google.com>
Commit: 25d027b8ab3acd65b58fce278f4173b431326934
https://github.com/llvm/llvm-project/commit/25d027b8ab3acd65b58fce278f4173b431326934
Author: Ming Yan <ming.yan at terapines.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/UpliftWhileToFor.cpp
M mlir/test/Dialect/SCF/uplift-while.mlir
Log Message:
-----------
[MLIR][SCF] Sink scf.if from scf.while before region into after region in scf-uplift-while-to-for (#165216)
When a `scf.if` directly precedes an `scf.condition` in the before
region of an `scf.while` and both share the same condition, move the if
into the after region of the loop. This helps simplify the control flow
to enable uplifting `scf.while` to `scf.for`.
Commit: 5d6d74359d69d3aada6a46c7cf51d84eb0848b70
https://github.com/llvm/llvm-project/commit/5d6d74359d69d3aada6a46c7cf51d84eb0848b70
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M bolt/lib/Passes/Inliner.cpp
A bolt/test/AArch64/inline-bti.s
Log Message:
-----------
[BOLT][BTI] Skip inlining BasicBlocks containing indirect tailcalls (#168403)
In the Inliner pass, tailcalls are converted to calls in the inlined
BasicBlock. If the tailcall is indirect, the `BR` is converted to `BLR`.
These instructions require different BTI landing pads at their targets.
As the targets of indirect tailcalls are unknown, inlining such blocks
is unsound for BTI: they should be skipped instead.
Commit: 39f5ff056bc459c7db4d01c348fe78925da8c558
https://github.com/llvm/llvm-project/commit/39f5ff056bc459c7db4d01c348fe78925da8c558
Author: Vitalii Shutov <vitalii.shutov at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/Transforms/Passes.td
M mlir/lib/Dialect/Tosa/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Tosa/Transforms/TosaArithConstantToConst.cpp
A mlir/test/Dialect/Tosa/tosa-arith-const-to-tosa-const.mlir
Log Message:
-----------
[mlir][tosa] Introduce arith.constant -> tosa.const normalization pass (#168370)
Add a standalone pass that rewrites tensor-valued `arith.constant` ops
into `tosa.const`, normalize the TOSA backend contract.
Signed-off-by: Vitalii Shutov <vitalii.shutov at arm.com>
Co-authored-by: Shubham <shubham at arm.com>
Commit: fb94261d88eb679ba227281ccae88165172a68cb
https://github.com/llvm/llvm-project/commit/fb94261d88eb679ba227281ccae88165172a68cb
Author: Shreeyash Pandey <shreeyash335 at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/include/sys/syscall.h.def
Log Message:
-----------
[libc][darwin] add syscall numbers from macos sdk (#166354)
This PR adds support to include syscall.h from MacOS sdk by explicitly including the path to the sdk via `xcrun`.
Commit: 58fa7e4ccd533e5547868a9211d4da16bc80ac20
https://github.com/llvm/llvm-project/commit/58fa7e4ccd533e5547868a9211d4da16bc80ac20
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/test/OpenMP/cancel_codegen.cpp
M clang/test/OpenMP/critical_codegen.cpp
M clang/test/OpenMP/critical_codegen_attr.cpp
M clang/test/OpenMP/irbuilder_nested_parallel_for.c
M clang/test/OpenMP/masked_codegen.cpp
M clang/test/OpenMP/master_codegen.cpp
M clang/test/OpenMP/nested_loop_codegen.cpp
M clang/test/OpenMP/ordered_codegen.cpp
M clang/test/OpenMP/parallel_codegen.cpp
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/test/Transforms/OpenMP/parallel_region_merging.ll
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-barrier-cancel.mlir
M mlir/test/Target/LLVMIR/openmp-cancel.mlir
M mlir/test/Target/LLVMIR/openmp-cancellation-point.mlir
M mlir/test/Target/LLVMIR/openmp-outline-infinite-loop.mlir
M mlir/test/Target/LLVMIR/openmp-parallel-reduction-multiblock.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-array-sections.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-init-arg.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-sections.mlir
Log Message:
-----------
Revert "[OMPIRBuilder] always leave PARALLEL via the same barrier" (#169829)
Reverts llvm/llvm-project#164586
Reverting due to buildbot failure:
https://lab.llvm.org/buildbot/#/builders/169/builds/17519
Commit: 620f1f1efb45bf918db494f6779ed1f46d2da456
https://github.com/llvm/llvm-project/commit/620f1f1efb45bf918db494f6779ed1f46d2da456
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
Log Message:
-----------
[AMDGPU] Remove odd syntax in some RUN lines. NFC. (#169831)
Commit: e3a28c060dc99cc41952d56445e1e4c26ddae685
https://github.com/llvm/llvm-project/commit/e3a28c060dc99cc41952d56445e1e4c26ddae685
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M flang-rt/lib/cuda/allocator.cpp
M flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
M flang/include/flang/Runtime/CUDA/allocator.h
Log Message:
-----------
[flang][cuda][NFC] Fix naming of CUFGetAssociatedStream (#169838)
Commit: a1ca69098d6c02c5d7f5a54f84a54636522b38be
https://github.com/llvm/llvm-project/commit/a1ca69098d6c02c5d7f5a54f84a54636522b38be
Author: Philip Ginsbach-Chen <philip.ginsbach at cantab.net>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64PerfectShuffle.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/insert-subvector.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
Log Message:
-----------
[AArch64] recognise zip1/zip2 with flipped operands (#167235)
Currently, the following two snippets get treated very differently from
each other (https://godbolt.org/z/rYGj9TGz6):
```LLVM
define <8 x i8> @foo(<8 x i8> %x, <8 x i8> %y) local_unnamed_addr #0 {
entry:
%0 = shufflevector <8 x i8> %x, <8 x i8> %y, <8 x i32>
<i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
ret <8 x i8> %0
}
define <8 x i8> @bar(<8 x i8> %x, <8 x i8> %y) local_unnamed_addr #0 {
entry:
%0 = shufflevector <8 x i8> %x, <8 x i8> %y, <8 x i32>
<i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3>
ret <8 x i8> %0
}
```
```
foo: // @foo
zip1 v0.8b, v0.8b, v1.8b
ret
.LCPI1_0:
.byte 8 // 0x8
.byte 0 // 0x0
.byte 9 // 0x9
.byte 1 // 0x1
.byte 10 // 0xa
.byte 2 // 0x2
.byte 11 // 0xb
.byte 3 // 0x3
bar: // @bar
adrp x8, .LCPI1_0
mov v0.d[1], v1.d[0]
ldr d1, [x8, :lo12:.LCPI1_0]
tbl v0.8b, { v0.16b }, v1.8b
ret
```
The reason is that `isZIPMask` does not recognise the pattern when the
operands are flipped.
This PR fixes `isZIPMask` so that both `foo` and `bar` get compiled as
expected:
```
foo: // @foo
zip1 v0.8b, v0.8b, v1.8b
ret
bar: // @bar
zip1 v0.8b, v1.8b, v0.8b
ret
```
I intend to open a similar follow-up PR for `isTRNMask`, which seems to
have the same problem.
I noticed this while working on
https://github.com/llvm/llvm-project/issues/137447, though the change
does not on itself fix that issue.
Commit: 8397945f6d1406bc659f1ee10575f42a8c1846b6
https://github.com/llvm/llvm-project/commit/8397945f6d1406bc659f1ee10575f42a8c1846b6
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
Log Message:
-----------
[clang][CIR] Fix build after builtins removal. NFC
Commit: 75e4438b57eb7ac2e1cdd1bcba3368bddd81d0c4
https://github.com/llvm/llvm-project/commit/75e4438b57eb7ac2e1cdd1bcba3368bddd81d0c4
Author: Thurston Dang <thurston at google.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/CodeGen/SanitizerHandler.h
M clang/test/DebugInfo/Generic/ubsan-trap-reason-type-mismatch.c
Log Message:
-----------
[ubsan] Change "Type mismatch in operation" trap reason to "Alignment, null, or object-size error" (#169752)
I originally proposed this rewording when trap reasons were introduced
in
https://github.com/llvm/llvm-project/pull/145967#discussion_r2196212344.
This was not adopted because there was a counter-proposal to split the
enum; however, that work appears to have stalled
(https://github.com/llvm/llvm-project/pull/151243). In the meantime,
there has been an additional datapoint that the current wording is
confusing to users. Thus, let's reword it now to prevent further
confusion.
Commit: db85babddd9e96e862ba09df6d25dfac1d15fb31
https://github.com/llvm/llvm-project/commit/db85babddd9e96e862ba09df6d25dfac1d15fb31
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[VPlan] Use m_Intrinsic to match assumes/noalias_scope_decl (NFC).
Use pattern matching to check for intrinsics to slightly simplify code.
Commit: 03c86242929c1b05f417aa5ddd016b7664e22d4e
https://github.com/llvm/llvm-project/commit/03c86242929c1b05f417aa5ddd016b7664e22d4e
Author: Ingo Müller <ingomueller at google.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
[clang:ast] Avoid warning for unused var without assertions. (NFC) (#169822)
This PR avoids a compiler warning, which turns into an error with
`-Werror`, for a variable introduced in #169276 and only used in an
assertion (which is, thus, unused if compiled without assertions).
Signed-off-by: Ingo Müller <ingomueller at google.com>
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: fd19a20a1ac55775333c2630e53b9fdf7c8dc831
https://github.com/llvm/llvm-project/commit/fd19a20a1ac55775333c2630e53b9fdf7c8dc831
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
Log Message:
-----------
Revert "[ShrinkWrap] Modify shrink wrapping to accommodate functions terminated by no-return blocks" (#169852)
Reverts llvm/llvm-project#167548
As commented at
https://github.com/llvm/llvm-project/pull/167548#issuecomment-3587008602
this is causing miscompiles in two-stage RISC-V Clang/LLVM builds that
result in test failures on the builders.
Commit: 1b7ae0b673638062fc99a6605df6212b6d35eb06
https://github.com/llvm/llvm-project/commit/1b7ae0b673638062fc99a6605df6212b6d35eb06
Author: clf <53817093+clingfei at users.noreply.github.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/aarch64-isel-umin.ll
M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
Log Message:
-----------
[AArch64] Use umin for x != 0 when +cssc is enabled (#169159)
Closes https://github.com/llvm/llvm-project/issues/161584
Commit: ee45ba2ff49db3cc5d31f2600a3e7fad81d70cb1
https://github.com/llvm/llvm-project/commit/ee45ba2ff49db3cc5d31f2600a3e7fad81d70cb1
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/fixed-length-bf16-arith.ll
M llvm/test/CodeGen/AArch64/sve-indexed-arithmetic.ll
Log Message:
-----------
[AArch64] Use SVE for fixed-length bf16 operations with +sve-b16b16 (#169329)
This can avoid the promotion bf16 -> f32 -> bf16 round trip (or costly
expansions).
Commit: 965c3d760de35753d97d41c6b69582cecff8819d
https://github.com/llvm/llvm-project/commit/965c3d760de35753d97d41c6b69582cecff8819d
Author: Lukas Döllerer <contact at lukas-doellerer.de>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
A lld/test/wasm/wrap_import.s
M lld/wasm/Driver.cpp
M lld/wasm/SyntheticSections.cpp
Log Message:
-----------
[lld][WebAssembly] Fix SEGFAULT when importing wrapped symbol (#169656)
When wrapping a symbol `foo` via `-wrap=foo`, we create the symbol
`__wrap_foo` that replaces all mentions of `foo`. This feature was
implemented for wasm-ld in commit a5ca34e.
So far, no valid signature has been attached to the undefined symbol,
leading to a nullptr dereference in the logic for creating the import
section. This change adds the correct signature to the wrapped symbol,
enabling the generation of an import for it.
Commit: a1f30c24ea2cf7d3acdd0f6eed19f737ae26b0d2
https://github.com/llvm/llvm-project/commit/a1f30c24ea2cf7d3acdd0f6eed19f737ae26b0d2
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/test/CodeGen/DirectX/CBufferAccess/gep-ce-two-uses.ll
Log Message:
-----------
[NFC] [DirectX] Update DirectX codegen test `CBufferAccess/gep-ce-two-uses.ll` due to changes to ReplaceConstant (#169848)
Fixes an LLVM DirectX codegen test after it broke due to #169141
The CBuffer loads and GEPs are no longer duplicated when there are two
or more accesses within the same basic block.
This PR removes the duplicate check for CBuffer load and GEP from the
original test function `@f` and adds a new test function `@g` which
places duplicate CBuffer loads into separate basic blocks.
Commit: d39f5243f8df23392e1c493f7d607cd0074222b9
https://github.com/llvm/llvm-project/commit/d39f5243f8df23392e1c493f7d607cd0074222b9
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
M llvm/test/MC/PowerPC/ppc64-errors.s
Log Message:
-----------
[PowerPC] Implement paddis (#161572)
Commit: ad605bdad7bb36bc74b9fa5f8b3786081dac4ec6
https://github.com/llvm/llvm-project/commit/ad605bdad7bb36bc74b9fa5f8b3786081dac4ec6
Author: Alexey Moksyakov <moksyakov.alexey at huawei.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Passes/Instrumentation.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/runtime/instr.cpp
M bolt/runtime/sys_aarch64.h
M bolt/test/runtime/AArch64/instrumentation-ind-call.c
Log Message:
-----------
[bolt][aarch64] Change indirect call instrumentation snippet
Indirect call instrumentation snippet uses x16 register in exit
handler to go to destination target
__bolt_instr_ind_call_handler_func:
msr nzcv, x1
ldp x0, x1, [sp], llvm#16
ldr x16, [sp], llvm#16
ldp x0, x1, [sp], llvm#16
br x16 <-----
This patch adds the instrumentation snippet by calling instrumentation
runtime library through indirect call instruction and adding the wrapper
to store/load target value and the register for original indirect instruction.
Example:
mov x16, foo
infirectCall:
adrp x8, Label
add x8, x8, #:lo12:Label
blr x8
Before:
Instrumented indirect call:
stp x0, x1, [sp, #-16]!
mov x0, x8
movk x1, #0x0, lsl llvm#48
movk x1, #0x0, lsl llvm#32
movk x1, #0x0, lsl llvm#16
movk x1, #0x0
stp x0, x1, [sp, #-16]!
adrp x0, __bolt_instr_ind_call_handler_func
add x0, x0, #:lo12:__bolt_instr_ind_call_handler_func
blr x0
__bolt_instr_ind_call_handler: (exit snippet)
msr nzcv, x1
ldp x0, x1, [sp], llvm#16
ldr x16, [sp], llvm#16
ldp x0, x1, [sp], llvm#16
br x16 <- overwrites the original value in X16
__bolt_instr_ind_call_handler_func: (entry snippet)
stp x0, x1, [sp, #-16]!
mrs x1, nzcv
adrp x0, __bolt_instr_ind_call_handler
add x0, x0, x0, #:lo12:__bolt_instr_ind_call_handler
ldr x0, [x0]
cmp x0, #0x0
b.eq __bolt_instr_ind_call_handler
str x30, [sp, #-16]!
blr x0 <--- runtime lib store/load all regs
ldr x30, [sp], llvm#16
b __bolt_instr_ind_call_handler
_________________________________________________________________________
After:
mov x16, foo
infirectCall:
adrp x8, Label
add x8, x8, #:lo12:Label
blr x8
Instrumented indirect call:
stp x0, x1, [sp, #-16]!
mov x0, x8
movk x1, #0x0, lsl llvm#48
movk x1, #0x0, lsl llvm#32
movk x1, #0x0, lsl llvm#16
movk x1, #0x0
stp x0, x30, [sp, #-16]!
adrp x8, __bolt_instr_ind_call_handler_func
add x8, x8, #:lo12:__bolt_instr_ind_call_handler_func
blr x8 <--- call trampoline instr lib
ldp x0, x30, [sp], llvm#16
mov x8, x0 <---- restore original target
ldp x0, x1, [sp], llvm#16
blr x8 <--- original indirect call instruction
// don't touch regs besides x0, x1
__bolt_instr_ind_call_handler: (exit snippet)
ret <---- return to original function with indirect call
__bolt_instr_ind_call_handler_func: (entry snippet)
adrp x0, __bolt_instr_ind_call_handler
add x0, x0, #:lo12:__bolt_instr_ind_call_handler
ldr x0, [x0]
cmp x0, #0x0
b.eq __bolt_instr_ind_call_handler
str x30, [sp, #-16]!
blr x0 <--- runtime lib store/load all regs
ldr x30, [sp], llvm#16
b __bolt_instr_ind_call_handler
Commit: 2e655c23deec6076f0198fafbe5c2b1deb6d5b98
https://github.com/llvm/llvm-project/commit/2e655c23deec6076f0198fafbe5c2b1deb6d5b98
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
A clang/test/CIR/IR/try-call.cir
Log Message:
-----------
[CIR] Upstream TryCallOp (#165303)
Upstream TryCall Op as a prerequisite for Try Catch work
Issue https://github.com/llvm/llvm-project/issues/154992
Commit: 8f36135aea5dfbb5f090ca9ad055094c9913f735
https://github.com/llvm/llvm-project/commit/8f36135aea5dfbb5f090ca9ad055094c9913f735
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
Log Message:
-----------
[VPlan] Add m_Intrinsic matcher that takes a variable intrinsic ID (NFC)
Add a variant of m_Intrinsic that matches a variable runtime ID.
Commit: 07d14cb6d3e0319b4f95bfaca1502c4a8dc02910
https://github.com/llvm/llvm-project/commit/07d14cb6d3e0319b4f95bfaca1502c4a8dc02910
Author: owenca <owenpiano at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Format/UnwrappedLineParser.h
Log Message:
-----------
[clang-format][NFC] Remove the parameter of parseRequires...() (#169773)
Commit: 8459508227dd30ce32f870fbc9109fe95d51f4db
https://github.com/llvm/llvm-project/commit/8459508227dd30ce32f870fbc9109fe95d51f4db
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
Log Message:
-----------
[VPlan] Handle scalar VPWidenPointerInd in convertToConcreteRecipes. (#169338)
In some case, VPWidenPointerInductions become only used by scalars after
legalizeAndOptimizationInducftions was already run, for example due to
some VPlan optimizations.
Move the code to scalarize VPWidenPointerInductions to a helper and use
it if needed.
This fixes a crash after #148274 in the added test case.
Fixes https://github.com/llvm/llvm-project/issues/169780
Commit: 06c8ee61ab80305be88380e6aa2f1b2fe32f859d
https://github.com/llvm/llvm-project/commit/06c8ee61ab80305be88380e6aa2f1b2fe32f859d
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/test/CodeGen/DirectX/CBufferAccess/gep-ce-two-uses.ll
Log Message:
-----------
[NFC] [DirectX] Make DirectX codegen test `CBufferAccess/gep-ce-two-uses.ll` more strict (#169855)
Continuation of PR #169848 to address PR comments.
This PR makes the test more strict by adding CHECKs to ensure the loads
are indeed using the same or different GEPs.
Commit: 583fba35247d8ffc87e0df9f9eb49ab02ea3bb8e
https://github.com/llvm/llvm-project/commit/583fba35247d8ffc87e0df9f9eb49ab02ea3bb8e
Author: actink <actink at 163.com>
Date: 2025-11-28 (Fri, 28 Nov 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp-select.ll
Log Message:
-----------
[InstCombine] fold icmp of select with invertible shl (#147182)
Proof: https://alive2.llvm.org/ce/z/a5fzlJ
Closes https://github.com/llvm/llvm-project/issues/146642
---------
Co-authored-by: Yingwei Zheng <dtcxzyw at qq.com>
Commit: aa2a7f4eb1b130e9e41d9a87bffcaa47876a97fc
https://github.com/llvm/llvm-project/commit/aa2a7f4eb1b130e9e41d9a87bffcaa47876a97fc
Author: Mr. Walls <reactive-firewall at users.noreply.github.com>
Date: 2025-11-28 (Fri, 28 Nov 2025)
Changed paths:
M libcxx/include/__locale_dir/support/linux.h
Log Message:
-----------
[libc++] Fix the locale base API on Linux with musl (#167980)
This pull request addresses an issue encountered when building
**libcxx** with certain configurations (`-D_LIBCPP_HAS_MUSL_LIBC` &
`-D__linux__`) that lack the `_GNU_SOURCE` definition. Specifically,
this issue arises if the system **musl libc** is built with
`_BSD_SOURCE` instead of `_GNU_SOURCE`. The resultant configuration
leads to problems with the "Strtonum functions" in the file
[libcxx/include/__locale_dir/support/linux.h](https://github.com/llvm/llvm-project/tree/master/libcxx/include/__locale_dir/support/linux.h),
affecting the following functions:
- `__strtof`
- `__strtod`
- `__strtold`
**Error messages displayed include**:
```console
error: no member named 'strtof_l' in the global namespace
```
```console
error: no member named 'strtod_l' in the global namespace
```
```console
error: no member named 'strtold_l' in the global namespace
```
For more insight, relevant code can be accessed
[here](https://github.com/llvm/llvm-project/blob/79cd1b7a25cdbf42c7234999ae9bc51db30af1f0/libcxx/include/__locale_dir/support/linux.h#L85-L95).
Commit: 6f7ea34933649d16845b1635d1e97f9ccb35ffea
https://github.com/llvm/llvm-project/commit/6f7ea34933649d16845b1635d1e97f9ccb35ffea
Author: Zaky Hermawan <44158147+ZakyHermawan at users.noreply.github.com>
Date: 2025-11-28 (Fri, 28 Nov 2025)
Changed paths:
M llvm/docs/GettingInvolved.rst
M llvm/docs/QualGroup.rst
Log Message:
-----------
[QualGroup][docs] Update meeting schedule and link for slides (#169458)
Summary
======
This PR update the schedule for online sync-up and update link for past
meeting slides.
Changes
======
* Remove the wednesday schedule, since we did not have the meeting for
Americas-friendly timezones.
* Use a single folder for past meeting slides instead of individual
links.
Related Links
=========
* [Meeting materials for Qualification Working
Group](https://llvm.org/docs/QualGroup.html#meeting-materials)
* [Online
Sync-Ups](https://llvm.org/docs/GettingInvolved.html#online-sync-ups)
---------
Signed-off-by: ZakyHermawan <zaky.hermawan9615 at gmail.com>
Commit: b14291238a987675b1fb39938efc938afcab8446
https://github.com/llvm/llvm-project/commit/b14291238a987675b1fb39938efc938afcab8446
Author: Matthias Springer <me at m-sp.org>
Date: 2025-11-28 (Fri, 28 Nov 2025)
Changed paths:
M mlir/include/mlir/Conversion/LLVMCommon/VectorPattern.h
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/LLVMCommon/VectorPattern.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
Log Message:
-----------
[mlir][arith] Fix `arith.cmpf` lowering with unsupported FP types (#166684)
The `arith.cmpf` lowering pattern used to generate invalid IR when an
unsupported floating-point type was used.
Commit: 0c6d7a40187e5e6cbdff1cf5dbdb6fe91054bef4
https://github.com/llvm/llvm-project/commit/0c6d7a40187e5e6cbdff1cf5dbdb6fe91054bef4
Author: Owen Anderson <resistor at mac.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M lld/ELF/Arch/RISCV.cpp
A lld/ELF/Arch/RISCVInternalRelocations.h
M lld/ELF/Target.cpp
M lld/test/ELF/riscv-vendor-relocations.s
Log Message:
-----------
[LLD] Add support for statically resolved vendor-specific RISCV relocations. (#169273)
This is achieved by using some of the bits of RelType to tag vendor namespaces. This change also adds a relocation iterator for RISCV that folds vendor namespaces into the RelType of the following relocation.
This patch is extracted from the implementation of RISCV vendor-specific relocations in the CHERIoT LLVM downstream: https://github.com/CHERIoT-Platform/llvm-project/commit/3d6d6f7d9480b590731cbcf4b4817e1fa3049854
Commit: f40c69471331e18176c01d08161f2e51ab7367cb
https://github.com/llvm/llvm-project/commit/f40c69471331e18176c01d08161f2e51ab7367cb
Author: Shih-Po Hung <shihpo.hung at sifive.com>
Date: 2025-11-28 (Fri, 28 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Log Message:
-----------
[TTI] Use MemIntrinsicCostAttributes for getExpandCompressMemoryOpCost (#168677)
- Following #168029. This is a step toward a unified interface for
masked/gather-scatter/strided/expand-compress cost modeling.
- Replace the ad-hoc parameter list with a single attributes object.
API change:
```
- InstructionCost getExpandCompressMemoryOpCost(Opcode, DataTy,
- VariableMask, Alignment,
- CostKind, Inst);
+ InstructionCost getExpandCompressMemoryOpCost(MemIntrinsicCostAttributes,
+ CostKind);
```
Notes:
- NFCI intended: callers populate MemIntrinsicCostAttributes with same
information as before.
Commit: b9bdec302124bc1c40c0f0c02d096b541b013518
https://github.com/llvm/llvm-project/commit/b9bdec302124bc1c40c0f0c02d096b541b013518
Author: Shih-Po Hung <shihpo.hung at sifive.com>
Date: 2025-11-28 (Fri, 28 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[TTI][Vectorize] Migrate masked/gather-scatter/strided/expand-compress costing (NFCI) (#165532)
In #160470, there is a discussion about the possibility to explored a
general approach for handling memory intrinsics.
API changes:
- Remove getMaskedMemoryOpCost, getGatherScatterOpCost,
getExpandCompressMemoryOpCost, getStridedMemoryOpCost from
Analysis/TargetTransformInfo.
- Add getMemIntrinsicInstrCost.
In BasicTTIImpl, map intrinsic IDs to existing target implementation
until the legacy TTI hooks are retired.
- masked_load/store → getMaskedMemoryOpCost
- masked_/vp_gather/scatter → getGatherScatterOpCost
- masked_expandload/compressstore → getExpandCompressMemoryOpCost
- experimental_vp_strided_{load,store} → getStridedMemoryOpCost
TODO: add support for vp_load_ff.
No functional change intended; costs continue to route to the same
target-specific hooks.
Commit: f18d72f65f2030c7044a39bff804b44abaa3bb52
https://github.com/llvm/llvm-project/commit/f18d72f65f2030c7044a39bff804b44abaa3bb52
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-11-28 (Fri, 28 Nov 2025)
Changed paths:
M .ci/premerge_advisor_explain.py
M .git-blame-ignore-revs
M .gitattributes
M .github/CODEOWNERS
M .github/workflows/bazel-checks.yml
M .github/workflows/build-ci-container-tooling.yml
M .github/workflows/build-ci-container-windows.yml
M .github/workflows/build-ci-container.yml
M .github/workflows/build-metrics-container.yml
M .github/workflows/check-ci.yml
M .github/workflows/ci-post-commit-analyzer.yml
M .github/workflows/commit-access-greeter.yml
M .github/workflows/commit-access-review.py
M .github/workflows/commit-access-review.yml
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
M .github/workflows/docs.yml
M .github/workflows/email-check.yaml
M .github/workflows/gha-codeql.yml
M .github/workflows/hlsl-test-all.yaml
M .github/workflows/issue-release-workflow.yml
M .github/workflows/issue-subscriber.yml
M .github/workflows/issue-write.yml
M .github/workflows/libc-fullbuild-tests.yml
M .github/workflows/libc-overlay-tests.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/libclang-python-tests.yml
M .github/workflows/libcxx-build-and-test.yaml
M .github/workflows/libcxx-build-containers.yml
M .github/workflows/libcxx-check-generated-files.yml
M .github/workflows/libcxx-run-benchmarks.yml
M .github/workflows/llvm-abi-tests.yml
M .github/workflows/merged-prs.yml
M .github/workflows/mlir-spirv-tests.yml
M .github/workflows/new-prs.yml
M .github/workflows/pr-code-format.yml
M .github/workflows/pr-code-lint.yml
M .github/workflows/pr-request-release-note.yml
M .github/workflows/pr-subscriber.yml
M .github/workflows/premerge.yaml
M .github/workflows/release-asset-audit.yml
M .github/workflows/release-binaries.yml
M .github/workflows/release-documentation.yml
M .github/workflows/release-doxygen.yml
M .github/workflows/release-lit.yml
M .github/workflows/release-sources.yml
M .github/workflows/release-tasks.yml
M .github/workflows/scorecard.yml
M .github/workflows/spirv-tests.yml
M .github/workflows/test-unprivileged-download-artifact.yml
M .github/workflows/version-check.yml
M .gitignore
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Passes/Inliner.cpp
M bolt/lib/Passes/Instrumentation.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/runtime/instr.cpp
M bolt/runtime/sys_aarch64.h
A bolt/test/AArch64/inline-armv8.3-returns.s
A bolt/test/AArch64/inline-armv8.3-tailcall.s
A bolt/test/AArch64/inline-bti.s
A bolt/test/AArch64/inline-pauth-lr.s
M bolt/test/X86/lit.local.cfg
M bolt/test/lit.local.cfg
M bolt/test/runtime/AArch64/instrumentation-ind-call.c
M bolt/unittests/Core/MCPlusBuilder.cpp
M clang-tools-extra/clang-doc/BitcodeReader.cpp
M clang-tools-extra/clang-doc/BitcodeReader.h
M clang-tools-extra/clang-doc/BitcodeWriter.h
M clang-tools-extra/clang-doc/ClangDoc.cpp
M clang-tools-extra/clang-doc/ClangDoc.h
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/Generators.h
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/HTMLMustacheGenerator.cpp
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-doc/Mapper.h
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clang-doc/Serialize.h
M clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-doc/assets/class-template.mustache
M clang-tools-extra/clang-doc/assets/comment-template.mustache
M clang-tools-extra/clang-doc/assets/function-template.mustache
M clang-tools-extra/clang-doc/assets/namespace-template.mustache
M clang-tools-extra/clang-doc/support/File.h
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
M clang-tools-extra/clang-tidy/.clang-format
M clang-tools-extra/clang-tidy/.clang-tidy
M clang-tools-extra/clang-tidy/ClangTidy.cpp
M clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
M clang-tools-extra/clang-tidy/altera/KernelNameRestrictionCheck.cpp
M clang-tools-extra/clang-tidy/boost/UseRangesCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/BranchCloneCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/ComparePointerToMemberVirtualFunctionCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/DanglingHandleCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/IncDecInConditionsCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/MacroParenthesesCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/NondeterministicPointerIterationOrderCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/OptionalValueConversionCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SpuriouslyWakeUpFunctionsCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SuspiciousMemsetUsageCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SuspiciousStringviewDataUsageCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/TaggedUnionMemberCountCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/ProBoundsAvoidUncheckedContainerAccessCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeMemberInitCheck.cpp
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M clang/test/AST/ast-dump-expr-json.cpp
A clang/test/AST/ast-dump-lambda-json.cpp
M clang/test/ASTMerge/struct/test.c
M clang/test/Analysis/block-in-critical-section.cpp
M clang/test/Analysis/lifetime-cfg-output.cpp
M clang/test/Analysis/loop-unrolling.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
M clang/test/Analysis/stackaddrleak.c
A clang/test/Analysis/std-c-library-functions-eof-2-rad.c
M clang/test/Analysis/suppression-attr.cpp
R clang/test/CIR/CodeGen/X86/sse-builtins.c
R clang/test/CIR/CodeGen/X86/sse2-builtins.c
M clang/test/CIR/CodeGen/atomic.c
R clang/test/CIR/CodeGen/builtin-fcmp-sse.c
R clang/test/CIR/CodeGen/builtin_bit.cpp
R clang/test/CIR/CodeGen/builtin_call.cpp
R clang/test/CIR/CodeGen/builtin_inline.c
R clang/test/CIR/CodeGen/builtin_prefetch.c
R clang/test/CIR/CodeGen/builtin_printf.cpp
R clang/test/CIR/CodeGen/builtins-elementwise.c
R clang/test/CIR/CodeGen/builtins-floating-point.c
R clang/test/CIR/CodeGen/builtins.cpp
M clang/test/CIR/CodeGen/call.c
A clang/test/CIR/CodeGen/copy-constructor.cpp
M clang/test/CIR/CodeGen/coro-task.cpp
A clang/test/CIR/CodeGen/count-of.c
M clang/test/CIR/CodeGen/ctor-null-init.cpp
A clang/test/CIR/CodeGen/cxx-special-member-attr.cpp
M clang/test/CIR/CodeGen/defaultarg.cpp
A clang/test/CIR/CodeGen/global-array-dtor.cpp
M clang/test/CIR/CodeGen/global-init.cpp
M clang/test/CIR/CodeGen/lambda.cpp
A clang/test/CIR/CodeGen/placement-new.cpp
A clang/test/CIR/CodeGen/static-members.cpp
M clang/test/CIR/CodeGen/ternary-throw.cpp
M clang/test/CIR/CodeGen/vector-ext-element.cpp
A clang/test/CIR/CodeGenBuiltins/X86/avx-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/avx512bw-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/bmi-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/lzcnt-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/sse-builtins.c
A clang/test/CIR/CodeGenBuiltins/X86/sse2-builtins.c
A clang/test/CIR/CodeGenBuiltins/builtin-fcmp-sse.c
A clang/test/CIR/CodeGenBuiltins/builtin-isfpclass.c
A clang/test/CIR/CodeGenBuiltins/builtin_bit.cpp
A clang/test/CIR/CodeGenBuiltins/builtin_call.cpp
A clang/test/CIR/CodeGenBuiltins/builtin_inline.c
A clang/test/CIR/CodeGenBuiltins/builtin_new_delete.cpp
A clang/test/CIR/CodeGenBuiltins/builtin_prefetch.c
A clang/test/CIR/CodeGenBuiltins/builtin_printf.cpp
A clang/test/CIR/CodeGenBuiltins/builtins-elementwise.c
A clang/test/CIR/CodeGenBuiltins/builtins-floating-point.c
A clang/test/CIR/CodeGenBuiltins/builtins-overflow.cpp
A clang/test/CIR/CodeGenBuiltins/builtins.cpp
A clang/test/CIR/CodeGenOpenACC/atomic-capture.cpp
M clang/test/CIR/CodeGenOpenACC/combined-copy.c
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-copy.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.cpp
A clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
A clang/test/CIR/CodeGenOpenACC/declare-copyin.cpp
A clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
A clang/test/CIR/CodeGenOpenACC/declare-create.cpp
A clang/test/CIR/CodeGenOpenACC/declare-deviceptr.cpp
A clang/test/CIR/CodeGenOpenACC/declare-deviceresident.cpp
A clang/test/CIR/CodeGenOpenACC/declare-link.cpp
A clang/test/CIR/CodeGenOpenACC/declare-present.cpp
M clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/openacc-not-implemented-global.cpp
R clang/test/CIR/CodeGenOpenACC/openacc-not-implemented.cpp
A clang/test/CIR/IR/await.cir
A clang/test/CIR/IR/eh-inflight.cir
M clang/test/CIR/IR/func.cir
A clang/test/CIR/IR/invalid-await.cir
A clang/test/CIR/IR/try-call.cir
A clang/test/CIR/Lowering/eh-inflight.cir
M clang/test/CXX/drs/cwg6xx.cpp
A clang/test/ClangScanDeps/modules-current-modulemap-file-dep.c
M clang/test/ClangScanDeps/modules-fmodule-name-no-module-built.m
M clang/test/ClangScanDeps/modules-header-sharing.m
M clang/test/ClangScanDeps/modules-implementation-module-map.c
M clang/test/ClangScanDeps/modules-implementation-private.m
M clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
M clang/test/CodeGen/LoongArch/lasx/builtin.c
M clang/test/CodeGen/X86/avx-builtins.c
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/avx512bf16-builtins.c
M clang/test/CodeGen/X86/avx512bitalg-builtins.c
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512dq-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vbmi-builtins.c
M clang/test/CodeGen/X86/avx512vbmivl-builtin.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/X86/avx512vlbf16-builtins.c
M clang/test/CodeGen/X86/avx512vlbitalg-builtins.c
M clang/test/CodeGen/X86/avx512vlbw-builtins.c
M clang/test/CodeGen/X86/avx512vldq-builtins.c
M clang/test/CodeGen/X86/f16c-builtins.c
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse-builtins-constrained.c
M clang/test/CodeGen/X86/sse-builtins.c
M clang/test/CodeGen/X86/sse2-builtins-constrained.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
M clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
M clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
A clang/test/CodeGen/arm64ec-varargs.c
M clang/test/CodeGen/attr-target-clones.c
M clang/test/CodeGen/builtins-x86.c
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
A clang/test/CodeGen/complex-compound-assign-bitfield.c
A clang/test/CodeGen/memprof-pgho.cpp
M clang/test/CodeGen/promoted-complex-div.c
A clang/test/CodeGen/sanitize-type-outlined.cpp
M clang/test/CodeGen/scoped-atomic-ops.c
A clang/test/CodeGenCUDA/cuda_weak_alias.cu
M clang/test/CodeGenCXX/alloc-token.cpp
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
M clang/test/CodeGenCXX/dllexport.cpp
M clang/test/CodeGenCXX/microsoft-abi-extern-template.cpp
M clang/test/CodeGenCXX/microsoft-abi-structors.cpp
M clang/test/CodeGenCXX/microsoft-abi-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-vftables.cpp
M clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-multiple-nonvirtual-inheritance-vdtors.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-return-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-single-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-virtual-inheritance-vtordisps.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-virtual-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-no-rtti-data.cpp
R clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
M clang/test/CodeGenCXX/vtable-consteval.cpp
A clang/test/CodeGenHIP/hip_weak_alias.cpp
M clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
A clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
M clang/test/CodeGenHLSL/builtins/faceforward.hlsl
A clang/test/CodeGenHLSL/builtins/fwidth.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-methods-lib.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-methods-ps.hlsl
M clang/test/CodeGenHLSL/resources/TypedBuffers-methods.hlsl
M clang/test/CodeGenHLSL/semantics/SV_Position.ps.hlsl
A clang/test/CodeGenHLSL/semantics/SV_Position.vs.hlsl
A clang/test/CodeGenHLSL/semantics/semantic-struct-2-output.hlsl
A clang/test/CodeGenHLSL/semantics/semantic.array.output.hlsl
A clang/test/CodeGenHLSL/semantics/semantic.struct.output.hlsl
M clang/test/CodeGenHLSL/sret_output.hlsl
A clang/test/CodeGenOpenCL/__bf16.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
A clang/test/CodeGenSPIRV/Builtins/fwidth.c
M clang/test/DebugInfo/CXX/simple-template-names.cpp
M clang/test/DebugInfo/CXX/windows-dtor.cpp
M clang/test/DebugInfo/Generic/dbg-info-all-calls-described.c
M clang/test/DebugInfo/Generic/ubsan-trap-reason-type-mismatch.c
M clang/test/Driver/crash-ir-repro.cpp
M clang/test/Driver/debug-options.c
M clang/test/Driver/fsanitize-coverage.c
M clang/test/Driver/fsanitize.c
A clang/test/Driver/hip-spirv-backend-bindings.c
A clang/test/Driver/hip-spirv-backend-opt.c
A clang/test/Driver/hip-spirv-backend-phases.c
M clang/test/Driver/linker-wrapper-hip-no-rdc.c
M clang/test/Driver/riscv-features.c
M clang/test/Headers/opencl-c-header.cl
M clang/test/Index/print-type.c
M clang/test/Layout/ms-x86-alias-avoidance-padding.cpp
A clang/test/Misc/opencl-c-3.0.incorrect_define.cl
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
R clang/test/Modules/Inputs/msvc-vector-deleting-dtors/module.modulemap
R clang/test/Modules/Inputs/msvc-vector-deleting-dtors/msvc-vector-deleting-dtors.h
M clang/test/Modules/compare-record.c
R clang/test/Modules/msvc-vector-deleting-destructors.cpp
A clang/test/Modules/reference-tu-local-var.cppm
M clang/test/Modules/vtable-windows.cppm
A clang/test/OpenMP/amdgcn_weak_alias.c
A clang/test/OpenMP/amdgcn_weak_alias.cpp
A clang/test/OpenMP/need_device_ptr_kind_ast_print.cpp
A clang/test/OpenMP/need_device_ptr_kind_messages.cpp
R clang/test/OpenMP/nvptx_target_exceptions_messages.cpp
A clang/test/OpenMP/nvptx_weak_alias.c
A clang/test/OpenMP/parallel_default_variableCategory_codegen.cpp
M clang/test/OpenMP/spirv_target_codegen_basic.cpp
A clang/test/OpenMP/spirv_target_codegen_noexceptions.cpp
A clang/test/OpenMP/target_exceptions_messages.cpp
R clang/test/PCH/Inputs/msvc-vector-deleting-dtors.h
R clang/test/PCH/msvc-vector-deleting-destructors.cpp
M clang/test/Preprocessor/init-loongarch.c
M clang/test/Profile/cxx-abc-deleting-dtor.cpp
A clang/test/Sema/AArch64/builtin_vectorelements.c
A clang/test/Sema/AArch64/sve-vector-conditional-op.cpp
A clang/test/Sema/attr-malloc_span.c
M clang/test/Sema/attr-target-clones.c
M clang/test/Sema/scoped-atomic-ops.c
A clang/test/Sema/warn-enum-compare-typo.c
M clang/test/Sema/warn-fortify-source.c
M clang/test/Sema/warn-lifetime-safety-dataflow.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/test/SemaCXX/alloc-token.cpp
A clang/test/SemaCXX/attr-malloc_span.cpp
M clang/test/SemaCXX/cxx2a-consteval.cpp
R clang/test/SemaCXX/gh134265.cpp
A clang/test/SemaCXX/no-warn-thread-safety-analysis.cpp
M clang/test/SemaCXX/return.cpp
M clang/test/SemaCXX/wmissing-noreturn-suggestion.cpp
M clang/test/SemaHIP/amdgpu-gfx950-load-to-lds.hip
M clang/test/SemaHLSL/Availability/attr-availability-compute.hlsl
M clang/test/SemaHLSL/Availability/attr-availability-mesh.hlsl
M clang/test/SemaHLSL/Availability/attr-availability-pixel.hlsl
M clang/test/SemaHLSL/Availability/avail-diag-default-compute.hlsl
M clang/test/SemaHLSL/Availability/avail-diag-default-lib.hlsl
M clang/test/SemaHLSL/Availability/avail-diag-relaxed-compute.hlsl
M clang/test/SemaHLSL/Availability/avail-diag-relaxed-lib.hlsl
M clang/test/SemaHLSL/Availability/avail-diag-strict-compute.hlsl
M clang/test/SemaHLSL/Availability/avail-diag-strict-lib.hlsl
M clang/test/SemaHLSL/BuiltIns/buffer_update_counter-errors.hlsl
A clang/test/SemaHLSL/Semantics/missing-vs.hlsl
M clang/test/SemaHLSL/Semantics/position.ps.hlsl
M clang/test/SemaHLSL/Semantics/position.ps.struct.hlsl
M clang/test/SemaHLSL/Semantics/position.ps.struct.reuse.hlsl
R clang/test/SemaHLSL/Semantics/position.vs.hlsl
M clang/test/SemaHLSL/WaveBuiltinAvailability.hlsl
M clang/test/SemaHLSL/num_threads.hlsl
M clang/test/SemaHLSL/shader_type_attr.hlsl
M clang/test/SemaObjCXX/arc-0x.mm
M clang/test/SemaOpenACC/declare-construct-ast.cpp
M clang/test/SemaOpenACC/declare-construct.cpp
M clang/test/SemaOpenCL/extension-version.cl
M clang/test/SemaOpenCL/features.cl
A clang/test/SemaSPIRV/BuiltIns/fwidth-errors.c
M clang/test/SemaSYCL/bf16.cpp
M clang/tools/c-index-test/CMakeLists.txt
M clang/tools/c-index-test/core_main.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-repl/ClangRepl.cpp
M clang/tools/diagtool/CMakeLists.txt
M clang/tools/diagtool/ShowEnabledWarnings.cpp
M clang/tools/driver/cc1_main.cpp
M clang/tools/driver/cc1as_main.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexer.cpp
M clang/tools/libclang/CMakeLists.txt
M clang/tools/libclang/Indexing.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/AST/TypePrinterTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
M clang/unittests/Analysis/FlowSensitive/LoggerTest.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
M clang/unittests/Driver/DXCModeTest.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/IntegerLiteralSeparatorTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M clang/unittests/Frontend/UtilsTest.cpp
M clang/unittests/Sema/CMakeLists.txt
M clang/unittests/Sema/SemaNoloadLookupTest.cpp
M clang/unittests/Serialization/ForceCheckFileInputTest.cpp
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Serialization/NoCommentsTest.cpp
M clang/unittests/Serialization/PreambleInNamedModulesTest.cpp
M clang/unittests/Serialization/VarDeclConstantInitTest.cpp
M clang/unittests/Tooling/DependencyScanning/DependencyScanningFilesystemTest.cpp
M clang/unittests/Tooling/RangeSelectorTest.cpp
M clang/unittests/Tooling/SourceCodeTest.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
M clang/unittests/Tooling/Syntax/TreeTestBase.cpp
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
M clang/utils/TableGen/MveEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/cmake/builtin-config-ix.cmake
M compiler-rt/include/sanitizer/common_interface_defs.h
M compiler-rt/lib/asan/CMakeLists.txt
A compiler-rt/lib/asan/asan_aix.cpp
M compiler-rt/lib/asan/asan_errors.cpp
M compiler-rt/lib/asan/asan_posix.cpp
M compiler-rt/lib/asan/scripts/asan_symbolize.py
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/lib/builtins/cpu_model/x86.c
M compiler-rt/lib/sanitizer_common/symbolizer/CMakeLists.txt
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/memtag.h
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/memtag_test.cpp
M compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
M compiler-rt/lib/scudo/standalone/tests/quarantine_test.cpp
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
M compiler-rt/lib/scudo/standalone/tests/size_class_map_test.cpp
M compiler-rt/lib/scudo/standalone/tsd_shared.h
M compiler-rt/lib/tsan/rtl/tsan_platform_mac.cpp
M compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
A compiler-rt/test/asan/TestCases/Darwin/Inputs/check-syslog.sh
M compiler-rt/test/asan/TestCases/Darwin/duplicate_os_log_reports.cpp
M compiler-rt/test/asan/TestCases/Darwin/dyld_insert_libraries_reexec.cpp
M compiler-rt/test/asan/TestCases/Darwin/interface_symbols_darwin.cpp
M compiler-rt/test/asan/TestCases/Darwin/lit.local.cfg.py
A compiler-rt/test/asan/TestCases/disable_container_overflow_checks.cpp
A compiler-rt/test/asan/TestCases/stack_container_dynamic_lib.cpp
M compiler-rt/test/fuzzer/big-file-copy.test
M compiler-rt/test/fuzzer/merge-posix.test
M compiler-rt/test/lit.common.cfg.py
M compiler-rt/test/orc/TestCases/Darwin/x86-64/objc-imageinfo.S
R compiler-rt/test/profile/Linux/instrprof-debug-info-correlate-warnings.c
A compiler-rt/test/profile/Linux/instrprof-debug-info-correlate-warnings.ll
M compiler-rt/test/sanitizer_common/TestCases/Posix/posix_spawn.c
M compiler-rt/test/ubsan_minimal/TestCases/misalignment.cpp
M compiler-rt/test/ubsan_minimal/TestCases/null.cpp
M compiler-rt/test/ubsan_minimal/TestCases/override-callback.c
M compiler-rt/test/ubsan_minimal/TestCases/test-darwin-interface.c
A cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/Inputs/simplified_template_names.cpp
A cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/simplified_template_names-debug-types.test
R cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/simplified_template_names.cpp
A cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/simplified_template_names.test
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/DAP.py
M flang-rt/cmake/modules/HandleLibs.cmake
M flang-rt/include/flang-rt/runtime/environment.h
M flang-rt/lib/cuda/allocator.cpp
M flang-rt/lib/runtime/environment.cpp
M flang-rt/lib/runtime/type-code.cpp
M flang-rt/lib/runtime/unit.cpp
M flang-rt/unittests/Runtime/CMakeLists.txt
M flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
A flang-rt/unittests/Runtime/TypeCode.cpp
M flang/docs/Extensions.md
M flang/docs/OpenMPSupport.md
M flang/docs/RuntimeEnvironment.md
M flang/include/flang/Lower/Support/ReductionProcessor.h
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/include/flang/Optimizer/Builder/CUFCommon.h
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.td
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Parser/characters.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/openmp-utils.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Parser/preprocessor.h
M flang/include/flang/Runtime/CUDA/allocator.h
M flang/include/flang/Semantics/openmp-directive-sets.h
M flang/include/flang/Support/LangOptions.def
M flang/lib/Frontend/CMakeLists.txt
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Lower/Runtime.cpp
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/CUFCommon.cpp
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Character.cpp
M flang/lib/Optimizer/Builder/Runtime/Reduction.cpp
M flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenACC/Support/RegisterOpenACCExtensions.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCRecipeBufferization.cpp
M flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/lib/Optimizer/OpenMP/MarkDeclareTarget.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/lib/Optimizer/Transforms/SetRuntimeCallAttributes.cpp
M flang/lib/Parser/executable-parsers.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/openmp-utils.cpp
M flang/lib/Parser/parse-tree.cpp
M flang/lib/Parser/preprocessor.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/type-parsers.h
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/canonicalize-do.cpp
M flang/lib/Semantics/canonicalize-omp.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Semantics/rewrite-parse-tree.cpp
M flang/module/cooperative_groups.f90
M flang/test/Driver/fast-real-mod.f90
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/FirToSCF/do-loop.fir
M flang/test/Fir/OpenACC/recipe-bufferization.mlir
M flang/test/Fir/declare-codegen.fir
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
A flang/test/Integration/debug-module-equivalence.f90
M flang/test/Lower/CUDA/cuda-atomicadd.cuf
A flang/test/Lower/CUDA/cuda-cluster.cuf
M flang/test/Lower/HLFIR/allocatable-and-pointer-status-change.f90
M flang/test/Lower/HLFIR/issue80884.f90
M flang/test/Lower/HLFIR/proc-pointer-comp-nopass.f90
M flang/test/Lower/HLFIR/procedure-pointer.f90
M flang/test/Lower/Intrinsics/command_argument_count.f90
M flang/test/Lower/Intrinsics/fast-real-mod.f90
M flang/test/Lower/Intrinsics/modulo.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-allocatable-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-pointer-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-user-assign.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
A flang/test/Lower/OpenACC/acc-reduction-remapping.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenACC/do-loops-to-acc-loops.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-allocatable.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-teams-private-implicit-scalar-map.f90
M flang/test/Lower/OpenMP/Todo/omp-clause-indirect.f90
M flang/test/Lower/OpenMP/Todo/omp-declarative-allocate.f90
A flang/test/Lower/OpenMP/Todo/omp-declare-reduction-advanced-types.f90
R flang/test/Lower/OpenMP/Todo/omp-declare-reduction-initsub.f90
R flang/test/Lower/OpenMP/Todo/omp-declare-reduction.f90
M flang/test/Lower/OpenMP/Todo/omp-declare-simd.f90
M flang/test/Lower/OpenMP/allocatable-array-bounds.f90
M flang/test/Lower/OpenMP/allocatable-map.f90
M flang/test/Lower/OpenMP/array-bounds.f90
A flang/test/Lower/OpenMP/compiler-directives-loop.f90
M flang/test/Lower/OpenMP/cray-pointers01.f90
M flang/test/Lower/OpenMP/cray-pointers02.f90
M flang/test/Lower/OpenMP/declare-mapper.f90
A flang/test/Lower/OpenMP/declare-target-deferred-marking-reductions.f90
M flang/test/Lower/OpenMP/declare-target-link-tarop-cap.f90
M flang/test/Lower/OpenMP/defaultmap.f90
M flang/test/Lower/OpenMP/delayed-privatization-reduction-byref.f90
M flang/test/Lower/OpenMP/derived-type-allocatable-map.f90
M flang/test/Lower/OpenMP/derived-type-map.f90
M flang/test/Lower/OpenMP/map-character.f90
M flang/test/Lower/OpenMP/map-descriptor-deferral.f90
M flang/test/Lower/OpenMP/map-neg-alloca-derived-type-array.f90
M flang/test/Lower/OpenMP/nested-loop-transformation-construct02.f90
A flang/test/Lower/OpenMP/omp-declare-reduction-derivedtype.f90
A flang/test/Lower/OpenMP/omp-declare-reduction-initsub.f90
A flang/test/Lower/OpenMP/omp-declare-reduction.f90
M flang/test/Lower/OpenMP/optional-argument-map-2.f90
M flang/test/Lower/OpenMP/optional-argument-map-3.f90
M flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90
M flang/test/Lower/OpenMP/parallel-private-clause.f90
M flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array-lb.f90
M flang/test/Lower/OpenMP/parallel-reduction-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array2.f90
M flang/test/Lower/OpenMP/parallel-reduction-pointer-array.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/parallel-wsloop-reduction-byref.f90
M flang/test/Lower/OpenMP/parallel-wsloop-reduction.f90
M flang/test/Lower/OpenMP/reduction-array-intrinsic.f90
M flang/test/Lower/OpenMP/sections-array-reduction.f90
M flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/OpenMP/taskgroup-task-array-reduction.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-lb.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-lb2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-multiple-clauses.f90
M flang/test/Lower/OpenMP/wsloop-reduction-pointer.f90
M flang/test/Lower/assignment.f90
M flang/test/Lower/assumed-shape-callee.f90
M flang/test/Lower/assumed-shape-caller.f90
M flang/test/Lower/big-integer-parameter.f90
M flang/test/Lower/c-interoperability.f90
M flang/test/Lower/call-copy-in-out.f90
M flang/test/Lower/charconvert.f90
M flang/test/Lower/control-flow.f90
M flang/test/Lower/default-initialization.f90
M flang/test/Lower/derived-allocatable-components.f90
M flang/test/Lower/derived-type-descriptor.f90
M flang/test/Lower/derived-types.f90
M flang/test/Lower/dispatch.f90
M flang/test/Lower/do_concurrent_delayed_locality.f90
M flang/test/Lower/do_concurrent_reduce.f90
M flang/test/Lower/do_concurrent_reduce_allocatable.f90
M flang/test/Lower/do_loop.f90
M flang/test/Lower/dummy-argument-contiguous.f90
M flang/test/Lower/dummy-procedure-character.f90
M flang/test/Lower/dummy-procedure.f90
M flang/test/Lower/equivalence-1.f90
M flang/test/Lower/equivalence-2.f90
M flang/test/Lower/explicit-interface-results.f90
M flang/test/Lower/host-associated.f90
M flang/test/Lower/identical-block-merge-disable.f90
M flang/test/Lower/implicit-interface.f90
M flang/test/Lower/inline_directive.f90
M flang/test/Lower/io-statement-1.f90
M flang/test/Lower/io-write.f90
M flang/test/Lower/location.f90
M flang/test/Lower/module_definition.f90
M flang/test/Lower/module_use.f90
M flang/test/Lower/module_use_in_same_file.f90
M flang/test/Lower/namelist-common-block.f90
M flang/test/Lower/nested-where.f90
M flang/test/Lower/nullify-polymorphic.f90
M flang/test/Lower/pointer-association-polymorphic.f90
A flang/test/Lower/pointer-disassociate-character.f90
M flang/test/Lower/pointer-disassociate.f90
M flang/test/Lower/polymorphic-temp.f90
M flang/test/Lower/polymorphic-types.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/procedure-declarations.f90
M flang/test/Lower/read-write-buffer.f90
M flang/test/Lower/select-case-statement.f90
M flang/test/Lower/select-type.f90
M flang/test/Lower/statement-function.f90
M flang/test/Lower/variable.f90
M flang/test/Lower/volatile-allocatable.f90
M flang/test/Lower/volatile-openmp.f90
M flang/test/Lower/volatile-openmp1.f90
M flang/test/Lower/volatile3.f90
M flang/test/Lower/volatile4.f90
A flang/test/Parser/OpenMP/atomic-label-do.f90
A flang/test/Parser/OpenMP/cross-label-do.f90
M flang/test/Parser/OpenMP/fail-construct2.f90
A flang/test/Parser/OpenMP/fail-looprange.f90
A flang/test/Parser/OpenMP/fuse-looprange.f90
A flang/test/Parser/OpenMP/fuse01.f90
A flang/test/Parser/OpenMP/fuse02.f90
M flang/test/Parser/OpenMP/loop-transformation-construct01.f90
M flang/test/Parser/OpenMP/loop-transformation-construct02.f90
A flang/test/Parser/OpenMP/loop-transformation-construct04.f90
A flang/test/Parser/OpenMP/loop-transformation-construct05.f90
M flang/test/Parser/OpenMP/tile-fail.f90
A flang/test/Preprocessing/bug168077.F90
M flang/test/Semantics/OpenMP/clause-validity01.f90
A flang/test/Semantics/OpenMP/compiler-directives-loop.f90
M flang/test/Semantics/OpenMP/do21.f90
M flang/test/Semantics/OpenMP/loop-association.f90
A flang/test/Semantics/OpenMP/loop-transformation-clauses01.f90
M flang/test/Semantics/OpenMP/loop-transformation-construct01.f90
A flang/test/Semantics/OpenMP/loop-transformation-construct02.f90
A flang/test/Semantics/OpenMP/loop-transformation-construct03.f90
A flang/test/Semantics/OpenMP/loop-transformation-construct04.f90
A flang/test/Semantics/OpenMP/target-teams-nesting.f90
M flang/test/Semantics/OpenMP/tile02.f90
A flang/test/Semantics/bug168099.f90
M flang/test/Semantics/indirect01.f90
M flang/test/Semantics/indirect02.f90
M flang/test/Transforms/OpenACC/acc-implicit-copy-reduction.fir
M flang/test/Transforms/OpenACC/acc-implicit-data-fortran.F90
M flang/test/Transforms/OpenACC/acc-implicit-data.fir
M flang/test/Transforms/OpenACC/acc-implicit-firstprivate.fir
M flang/test/Transforms/debug-common-block.fir
M flang/test/Transforms/omp-map-info-finalization.fir
M flang/test/Transforms/set-runtime-call-attributes.fir
M libc/cmake/caches/armv6m-none-eabi.cmake
M libc/cmake/caches/armv7em-none-eabi.cmake
M libc/cmake/caches/armv7m-none-eabi.cmake
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/cmake/modules/LLVMLibCHeaderRules.cmake
M libc/docs/dev/header_generation.rst
M libc/include/CMakeLists.txt
M libc/include/sys/syscall.h.def
M libc/src/__support/math/CMakeLists.txt
M libc/src/__support/math/atanf.h
A libc/src/__support/math/atanf_float.h
M libc/test/src/math/atanf_test.cpp
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/atanf_float_test.cpp
R libc/utils/hdrgen/hdrgen/gpu_headers.py
M libc/utils/hdrgen/hdrgen/yaml_to_classes.py
A libclc/clc/include/clc/atomic/clc_atomic_flag_clear.h
A libclc/clc/include/clc/atomic/clc_atomic_flag_test_and_set.h
M libclc/clc/lib/generic/SOURCES
M libclc/clc/lib/generic/atomic/clc_atomic_dec.cl
M libclc/clc/lib/generic/atomic/clc_atomic_def.inc
A libclc/clc/lib/generic/atomic/clc_atomic_flag_clear.cl
A libclc/clc/lib/generic/atomic/clc_atomic_flag_test_and_set.cl
M libclc/clc/lib/generic/atomic/clc_atomic_inc.cl
A libclc/opencl/include/clc/opencl/atomic/atomic_flag_clear.h
A libclc/opencl/include/clc/opencl/atomic/atomic_flag_test_and_set.h
A libclc/opencl/include/clc/opencl/atomic/atomic_init.h
A libclc/opencl/include/clc/opencl/atomic/atomic_init.inc
A libclc/opencl/include/clc/opencl/types.h
A libclc/opencl/include/clc/opencl/utils.h
M libclc/opencl/lib/generic/SOURCES
A libclc/opencl/lib/generic/atomic/atomic_flag_clear.cl
A libclc/opencl/lib/generic/atomic/atomic_flag_test_and_set.cl
A libclc/opencl/lib/generic/atomic/atomic_init.cl
A libclc/opencl/lib/generic/atomic/atomic_init.inc
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/all_of.h
M libcxx/include/__algorithm/copy_n.h
M libcxx/include/__algorithm/fill_n.h
M libcxx/include/__algorithm/iterator_operations.h
M libcxx/include/__algorithm/none_of.h
M libcxx/include/__algorithm/ranges_copy_n.h
M libcxx/include/__algorithm/simd_utils.h
A libcxx/include/__algorithm/specialized_algorithms.h
M libcxx/include/__bit/has_single_bit.h
M libcxx/include/__bit_reference
M libcxx/include/__charconv/from_chars_integral.h
M libcxx/include/__charconv/to_chars_integral.h
M libcxx/include/__compare/is_eq.h
M libcxx/include/__condition_variable/condition_variable.h
M libcxx/include/__config
M libcxx/include/__configuration/platform.h
M libcxx/include/__coroutine/coroutine_handle.h
M libcxx/include/__coroutine/noop_coroutine_handle.h
M libcxx/include/__flat_map/flat_map.h
M libcxx/include/__flat_map/utils.h
M libcxx/include/__flat_set/flat_set.h
M libcxx/include/__functional/bind.h
M libcxx/include/__functional/bind_back.h
M libcxx/include/__functional/bind_front.h
M libcxx/include/__functional/function.h
M libcxx/include/__functional/mem_fn.h
M libcxx/include/__functional/reference_wrapper.h
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_fallbacks.h
M libcxx/include/__locale_dir/locale_base_api/ibm.h
R libcxx/include/__locale_dir/locale_base_api/musl.h
M libcxx/include/__locale_dir/num.h
M libcxx/include/__locale_dir/support/bsd_like.h
M libcxx/include/__locale_dir/support/fuchsia.h
M libcxx/include/__locale_dir/support/linux.h
M libcxx/include/__locale_dir/support/no_locale/strtonum.h
M libcxx/include/__locale_dir/support/windows.h
M libcxx/include/__mdspan/extents.h
M libcxx/include/__mdspan/mdspan.h
R libcxx/include/__memory/aligned_alloc.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/include/__mutex/mutex.h
M libcxx/include/__random/binomial_distribution.h
M libcxx/include/__ranges/iota_view.h
M libcxx/include/__support/xlocale/__strtonum_fallback.h
M libcxx/include/__thread/thread.h
M libcxx/include/__utility/cmp.h
M libcxx/include/__vector/vector.h
M libcxx/include/any
M libcxx/include/array
M libcxx/include/barrier
M libcxx/include/deque
M libcxx/include/forward_list
M libcxx/include/fstream
M libcxx/include/initializer_list
M libcxx/include/latch
M libcxx/include/limits
M libcxx/include/list
M libcxx/include/module.modulemap.in
M libcxx/include/mutex
M libcxx/include/queue
M libcxx/include/semaphore
M libcxx/include/stack
M libcxx/include/string
M libcxx/include/string_view
M libcxx/src/filesystem/operations.cpp
A libcxx/src/include/aligned_alloc.h
M libcxx/src/locale.cpp
M libcxx/src/new.cpp
M libcxx/src/thread.cpp
R libcxx/test/benchmarks/streams/fstream.bench.cpp
A libcxx/test/benchmarks/streams/ofstream.bench.cpp
M libcxx/test/extensions/libcxx/odr_signature.exceptions.sh.cpp
M libcxx/test/extensions/libcxx/odr_signature.hardening.sh.cpp
M libcxx/test/libcxx-03/algorithms/half_positive.pass.cpp
M libcxx/test/libcxx-03/algorithms/robust_against_copying_comparators.pass.cpp
M libcxx/test/libcxx-03/algorithms/robust_against_cpp20_hostile_iterators.compile.pass.cpp
M libcxx/test/libcxx-03/containers/sequences/vector/asan.pass.cpp
M libcxx/test/libcxx-03/containers/sequences/vector/asan_throw.pass.cpp
M libcxx/test/libcxx-03/depr/depr.default.allocator/allocator.members/construct.cxx20.pass.cpp
M libcxx/test/libcxx-03/input.output/string.streams/stringbuf/const_sso_buffer.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/arithmetic.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/comparison.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/pointer_traits.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/types.compile.pass.cpp
M libcxx/test/libcxx-03/iterators/contiguous_iterators.conv.compile.pass.cpp
M libcxx/test/libcxx-03/iterators/contiguous_iterators.pass.cpp
M libcxx/test/libcxx-03/iterators/predef.iterators/insert.iterators/back.insert.iter.ops/get_container.pass.cpp
M libcxx/test/libcxx-03/iterators/unwrap_iter.pass.cpp
M libcxx/test/libcxx-03/language.support/support.dynamic/libcpp_deallocate.sh.cpp
M libcxx/test/libcxx-03/libcpp_alignof.pass.cpp
M libcxx/test/libcxx-03/memory/allocation_guard.pass.cpp
M libcxx/test/libcxx-03/memory/swap_allocator.pass.cpp
M libcxx/test/libcxx-03/numerics/bit.ops.pass.cpp
M libcxx/test/libcxx-03/strings/basic.string/string.capacity/max_size.pass.cpp
M libcxx/test/libcxx-03/strings/basic.string/string.cons/copy_shrunk_long.pass.cpp
M libcxx/test/libcxx-03/strings/c.strings/constexpr_memmove.pass.cpp
M libcxx/test/libcxx-03/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/bullet_1_2_3.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/bullet_4_5_6.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/bullet_7.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/invoke.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/invoke_helpers.h
M libcxx/test/libcxx-03/utilities/is_pointer_in_range.pass.cpp
M libcxx/test/libcxx-03/utilities/is_valid_range.pass.cpp
M libcxx/test/libcxx-03/utilities/memory/pointer.conversion/to_address.pass.cpp
M libcxx/test/libcxx-03/utilities/memory/pointer.conversion/to_address_std_iterators.pass.cpp
M libcxx/test/libcxx-03/utilities/meta/is_referenceable.compile.pass.cpp
M libcxx/test/libcxx-03/utilities/no_destroy.pass.cpp
M libcxx/test/libcxx-03/utilities/utility/pairs/pairs.pair/abi.non_trivial_copy_move.pass.cpp
M libcxx/test/libcxx-03/utilities/utility/pairs/pairs.pair/abi.trivial_copy_move.pass.cpp
M libcxx/test/libcxx-03/utilities/utility/pairs/pairs.pair/abi.trivially_copyable.compile.pass.cpp
M libcxx/test/libcxx/containers/views/mdspan/extents/assert.obs.pass.cpp
A libcxx/test/libcxx/containers/views/mdspan/nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/array.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/deque.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/flat_map.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/flat_set.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/forward_list.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/functional.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/list.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/queue.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/stack.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/string.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/string_view.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/utility.nodiscard.verify.cpp
M libcxx/test/libcxx/input.output/file.streams/fstreams/filebuf/traits_mismatch.verify.cpp
M libcxx/test/libcxx/input.output/file.streams/fstreams/traits_mismatch.verify.cpp
A libcxx/test/libcxx/language.support/nodiscard.verify.cpp
M libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
M libcxx/test/libcxx/numerics/clamp_to_integral.pass.cpp
M libcxx/test/libcxx/strings/string.view/nonnull.verify.cpp
A libcxx/test/libcxx/thread/nodiscard.verify.cpp
A libcxx/test/libcxx/utilities/any/nodiscard.verify.cpp
M libcxx/test/libcxx/utilities/smartptr/nodiscard.verify.cpp
A libcxx/test/std/algorithms/robust_against_nonbool.compile.pass.cpp
M libcxx/test/std/containers/container.adaptors/flat.map/flat.map.access/index_transparent.pass.cpp
M libcxx/test/std/containers/sequences/array/array.creation/to_array.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/ccomplex.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/ciso646.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/cstdalign.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/cstdbool.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/ctgmath.verify.cpp
M libcxx/test/std/input.output/file.streams/c.files/gets-removed.verify.cpp
A libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/xsgetn.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/xsgetn.test.dat
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_long.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_int.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_long.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_long_long.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_short.pass.cpp
M libcxx/test/std/numerics/c.math/isnormal.pass.cpp
M libcxx/test/std/ranges/range.factories/range.iota.view/indices.pass.cpp
M libcxx/test/std/ranges/range.factories/range.iota.view/iterator/member_typedefs.compile.pass.cpp
R libcxx/test/std/thread/thread.jthread/nodiscard.verify.cpp
M libcxx/test/std/time/time.clock/time.clock.gps/types.compile.pass.cpp
M libcxx/test/std/time/time.clock/time.clock.tai/types.compile.pass.cpp
M libcxx/test/std/time/time.clock/time.clock.utc/types.compile.pass.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_pointer.pass.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_reference.pass.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_request_invalid_value_category.verify.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/const_correctness.verify.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/not_copy_constructible.verify.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/reference_types.verify.cpp
M libcxx/test/std/utilities/any/any.nonmembers/any.cast/void.verify.cpp
M libcxx/test/std/utilities/function.objects/refwrap/refwrap.invoke/robust_against_adl.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.obs/unique.deprecated_in_cxx17.verify.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/U.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/const_T.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/const_optional_U.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/copy.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/ctor.verify.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/deduct.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/deduct.verify.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/default.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/empty_in_place_t_does_not_clobber.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/explicit_const_optional_U.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/explicit_optional_U.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/in_place_t.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/initializer_list.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/move.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/nullopt_t.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/optional_U.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/rvalue_T.pass.cpp
M libcxx/test/std/utilities/utility/utility.intcmp/intcmp.cmp_greater/cmp_greater.pass.cpp
M libcxx/test/std/utilities/utility/utility.intcmp/intcmp.cmp_less/cmp_less.pass.cpp
M libcxx/test/std/utilities/utility/utility.intcmp/intcmp.cmp_less_equal/cmp_less_equal.pass.cpp
M libcxx/utils/libcxx/test/features/availability.py
M libcxxabi/src/fallback_malloc.cpp
M libcxxabi/src/stdlib_new_delete.cpp
A libsycl/Maintainers.md
M lld/COFF/DriverUtils.cpp
M lld/COFF/Options.td
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/Arch/RISCV.cpp
A lld/ELF/Arch/RISCVInternalRelocations.h
M lld/ELF/InputFiles.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/Symbols.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Target.cpp
M lld/ELF/Target.h
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/Driver.cpp
M lld/MachO/InputFiles.cpp
M lld/MachO/SymbolTable.cpp
M lld/MinGW/Driver.cpp
M lld/test/COFF/driver.test
A lld/test/ELF/aarch64-funcinit64-invalid.s
A lld/test/ELF/aarch64-funcinit64.s
M lld/test/ELF/linkerscript/version-script.s
M lld/test/ELF/riscv-vendor-relocations.s
M lld/test/ELF/version-script-extern-undefined.s
M lld/test/MachO/read-workers.s
A lld/test/MachO/weak-alias-override.s
M lld/test/MachO/x86-64-relocs.s
M lld/test/MinGW/driver.test
A lld/test/wasm/wrap_import.s
M lld/wasm/Driver.cpp
M lld/wasm/SyntheticSections.cpp
M lldb/bindings/interface/SBFrameExtensions.i
M lldb/bindings/interface/SBTargetExtensions.i
M lldb/bindings/lua/lua-typemaps.swig
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/docs/CMakeLists.txt
M lldb/docs/dil-expr-lang.ebnf
M lldb/examples/python/templates/scripted_process.py
M lldb/include/lldb/API/SBStructuredData.h
M lldb/include/lldb/API/SBTarget.h
M lldb/include/lldb/Core/Disassembler.h
M lldb/include/lldb/Core/SourceManager.h
M lldb/include/lldb/Expression/DiagnosticManager.h
A lldb/include/lldb/Host/common/DiagnosticsRendering.h
M lldb/include/lldb/Interpreter/CommandReturnObject.h
M lldb/include/lldb/Symbol/CompileUnit.h
M lldb/include/lldb/Symbol/Function.h
M lldb/include/lldb/Symbol/LineEntry.h
M lldb/include/lldb/Symbol/TypeSystem.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/Target/UnixSignals.h
R lldb/include/lldb/Utility/DiagnosticsRendering.h
M lldb/include/lldb/Utility/FileSpecList.h
A lldb/include/lldb/Utility/NonNullSharedPtr.h
M lldb/include/lldb/Utility/SupportFile.h
M lldb/include/lldb/ValueObject/DILAST.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/include/lldb/lldb-forward.h
M lldb/packages/Python/lldbsuite/test/builders/darwin.py
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/source/API/SBTarget.cpp
M lldb/source/Breakpoint/BreakpointResolverFileLine.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/CommandObjectExpression.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Core/Disassembler.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/Expression/REPL.cpp
M lldb/source/Host/CMakeLists.txt
A lldb/source/Host/common/DiagnosticsRendering.cpp
M lldb/source/Interpreter/CommandReturnObject.cpp
M lldb/source/Interpreter/Options.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangHost.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Plugins/Language/CPlusPlus/LibStdcpp.cpp
M lldb/source/Plugins/Language/ObjC/NSSet.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
M lldb/source/Symbol/CompileUnit.cpp
M lldb/source/Symbol/CompilerType.cpp
M lldb/source/Symbol/Function.cpp
M lldb/source/Symbol/LineTable.cpp
M lldb/source/Symbol/TypeSystem.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/ThreadPlanStepRange.cpp
M lldb/source/Target/UnixSignals.cpp
M lldb/source/Utility/CMakeLists.txt
R lldb/source/Utility/DiagnosticsRendering.cpp
M lldb/source/Utility/FileSpecList.cpp
M lldb/source/Utility/RegisterValue.cpp
M lldb/source/Utility/StringExtractorGDBRemote.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILParser.cpp
A lldb/test/API/commands/frame/var-dil/expr/Arithmetic/Makefile
A lldb/test/API/commands/frame/var-dil/expr/Arithmetic/TestFrameVarDILArithmetic.py
A lldb/test/API/commands/frame/var-dil/expr/Arithmetic/main.cpp
A lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/Makefile
A lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/TestFrameVarDILPointerArithmetic.py
A lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/main.cpp
M lldb/test/API/functionalities/breakpoint/hardware_breakpoints/simple_hw_breakpoints/TestSimpleHWBreakpoints.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/invalid-string/TestDataFormatterLibcxxInvalidString.py
M lldb/test/API/lang/cpp/libcxx-internals-recognizer/TestLibcxxInternalsRecognizer.py
M lldb/test/API/python_api/target/TestTargetAPI.py
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/test/API/tools/lldb-dap/startDebugging/TestDAP_startDebugging.py
M lldb/test/Shell/helper/toolchain.py
M lldb/tools/driver/Driver.cpp
M lldb/tools/lldb-dap/CMakeLists.txt
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPForward.h
A lldb/tools/lldb-dap/DAPSessionManager.cpp
A lldb/tools/lldb-dap/DAPSessionManager.h
M lldb/tools/lldb-dap/EventHelper.cpp
M lldb/tools/lldb-dap/EventHelper.h
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/LaunchRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/package.json
M lldb/tools/lldb-dap/tool/lldb-dap.cpp
M lldb/unittests/DAP/CMakeLists.txt
A lldb/unittests/DAP/DAPSessionManagerTest.cpp
M lldb/unittests/Editline/EditlineTest.cpp
M lldb/unittests/Expression/ClangParserTest.cpp
M lldb/unittests/Expression/DWARFExpressionTest.cpp
M lldb/unittests/Host/common/CMakeLists.txt
A lldb/unittests/Host/common/DiagnosticsRenderingTest.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
M lldb/unittests/Signals/UnixSignalsTest.cpp
M lldb/unittests/Symbol/LineTableTest.cpp
M lldb/unittests/Target/MemoryTest.cpp
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
M lldb/unittests/Utility/CMakeLists.txt
R lldb/unittests/Utility/DiagnosticsRenderingTest.cpp
M llvm/Maintainers.md
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/docs/DeveloperPolicy.rst
M llvm/docs/GettingInvolved.rst
M llvm/docs/GlobalISel/GenericOpcode.rst
M llvm/docs/LangRef.rst
M llvm/docs/QualGroup.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/SourceLevelDebugging.rst
M llvm/docs/Vectorizers.rst
M llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl02.rst
M llvm/include/llvm/ADT/DenseMap.h
M llvm/include/llvm/ADT/MapVector.h
M llvm/include/llvm/ADT/StringTable.h
A llvm/include/llvm/Analysis/CMakeLists.txt
M llvm/include/llvm/Analysis/Delinearization.h
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/Analysis/LoopCacheAnalysis.h
R llvm/include/llvm/Analysis/TargetLibraryInfo.def
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
A llvm/include/llvm/Analysis/TargetLibraryInfo.td
A llvm/include/llvm/Analysis/TargetLibraryInfoImpl.td
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/Bitcode/BitcodeConvenience.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CAS/OnDiskTrieRawHashMap.h
M llvm/include/llvm/CMakeLists.txt
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/CallBrPrepare.h
M llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/CodeGen/MachineInstrBuilder.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/DWARFLinker/Classic/DWARFLinker.h
M llvm/include/llvm/DWARFLinker/Classic/DWARFLinkerDeclContext.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFContext.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h
M llvm/include/llvm/Frontend/OpenACC/ACC.td
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/Constants.h
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfo.h
M llvm/include/llvm/IR/DebugProgramInstruction.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/LLVMContext.h
M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/MC/MCInstrDesc.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCParser/MCAsmParserExtension.h
M llvm/include/llvm/MC/MCSymbol.h
M llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
M llvm/include/llvm/MC/MCWin64EH.h
M llvm/include/llvm/MC/MCWinEH.h
M llvm/include/llvm/Object/OffloadBinary.h
M llvm/include/llvm/ProfileData/SampleProf.h
M llvm/include/llvm/SandboxIR/Constant.h
M llvm/include/llvm/Support/AllocToken.h
M llvm/include/llvm/Support/BranchProbability.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Support/JSON.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Support/ThreadPool.h
M llvm/include/llvm/TableGen/CodeGenHelpers.h
M llvm/include/llvm/TableGen/StringToOffsetTable.h
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/Target/Target.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/include/llvm/Transforms/Instrumentation/BoundsChecking.h
M llvm/include/llvm/Transforms/Utils/FunctionComparator.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/PrintInstructionCount.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/SeedCollector.h
M llvm/include/module.modulemap
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/CMakeLists.txt
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/Delinearization.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/InstructionPrecedenceTracking.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CAS/OnDiskCAS.cpp
M llvm/lib/CAS/OnDiskGraphDB.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/CFIInstrInserter.cpp
M llvm/lib/CodeGen/CallBrPrepare.cpp
M llvm/lib/CodeGen/CallingConvLower.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/LibcallLoweringInfo.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/RenameIndependentSubregs.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
M llvm/lib/DWARFLinker/Classic/DWARFLinkerDeclContext.cpp
M llvm/lib/DWP/DWP.cpp
M llvm/lib/DebugInfo/PDB/Native/NativeSession.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
M llvm/lib/Frontend/OpenMP/OMP.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/CMakeLists.txt
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/ConstantsContext.h
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugProgramInstruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/LLVMContext.cpp
M llvm/lib/IR/LLVMContextImpl.cpp
A llvm/lib/IR/NVVMIntrinsicUtils.cpp
M llvm/lib/IR/ReplaceConstant.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/LTO/LTOModule.cpp
M llvm/lib/LTO/UpdateCompilerUsed.cpp
M llvm/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCMachOStreamer.cpp
M llvm/lib/MC/MCNullStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/COFFAsmParser.cpp
M llvm/lib/MC/MCParser/COFFMasmParser.cpp
M llvm/lib/MC/MCParser/DarwinAsmParser.cpp
M llvm/lib/MC/MCParser/ELFAsmParser.cpp
M llvm/lib/MC/MCParser/GOFFAsmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCParser/WasmAsmParser.cpp
M llvm/lib/MC/MCParser/XCOFFAsmParser.cpp
M llvm/lib/MC/MCSymbol.cpp
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
M llvm/lib/MC/MCWasmStreamer.cpp
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/MC/MCWinEH.cpp
M llvm/lib/Object/Archive.cpp
M llvm/lib/Object/RecordStreamer.cpp
M llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp
M llvm/lib/ObjectYAML/MinidumpEmitter.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/ProfileData/InstrProfCorrelator.cpp
M llvm/lib/SandboxIR/Constant.cpp
M llvm/lib/Support/AllocToken.cpp
M llvm/lib/Support/BalancedPartitioning.cpp
M llvm/lib/Support/BranchProbability.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/SpecialCaseList.cpp
M llvm/lib/TableGen/StringToOffsetTable.cpp
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
M llvm/lib/Target/AArch64/AArch64PerfectShuffle.h
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
M llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp
M llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/R600.td
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/ARC/ARCISelLowering.cpp
M llvm/lib/Target/ARM/ARM.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/lib/Target/ARM/ARMMCInstLower.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp
M llvm/lib/Target/AVR/AVR.td
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/BPF/BPF.td
M llvm/lib/Target/BPF/BPFISelLowering.cpp
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/BPF/BPFSubtarget.cpp
M llvm/lib/Target/BPF/BPFSubtarget.h
M llvm/lib/Target/CSKY/CSKY.td
M llvm/lib/Target/CSKY/CSKYISelLowering.cpp
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DirectX.td
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/Hexagon/Hexagon.td
M llvm/lib/Target/Hexagon/HexagonCallingConv.td
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
M llvm/lib/Target/Hexagon/HexagonSubtarget.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/Lanai.td
M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
M llvm/lib/Target/LoongArch/CMakeLists.txt
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
A llvm/lib/Target/LoongArch/LoongArchSelectionDAGInfo.cpp
A llvm/lib/Target/LoongArch/LoongArchSelectionDAGInfo.h
M llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
M llvm/lib/Target/LoongArch/LoongArchSubtarget.h
M llvm/lib/Target/M68k/M68k.td
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430.td
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.h
M llvm/lib/Target/Mips/Mips.td
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/Mips/Mips16ISelLowering.h
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsInstrFPU.td
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTX.td
M llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXTagInvariantLoads.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/RISCV.h
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
A llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRV.td
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.cpp
M llvm/lib/Target/SPIRV/SPIRVCombine.td
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVIRMapping.h
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.h
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/Sparc/Sparc.td
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.h
M llvm/lib/Target/SystemZ/SystemZ.td
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/VE/VE.td
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssembly.td
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Target/XCore/XCore.td
M llvm/lib/Target/XCore/XCoreISelLowering.cpp
M llvm/lib/Target/Xtensa/Xtensa.td
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/TextAPI/InterfaceFile.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp
M llvm/lib/Transforms/Instrumentation/TypeSanitizer.cpp
M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
M llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/lib/Transforms/Utils/DebugSSAUpdater.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/ProfileVerify.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Utils/ValueMapper.cpp
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanSLP.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AMDGPU/shufflevector.ll
M llvm/test/Analysis/Delinearization/a.ll
M llvm/test/Analysis/Delinearization/constant_functions_multi_dim.ll
M llvm/test/Analysis/Delinearization/divide_by_one.ll
M llvm/test/Analysis/Delinearization/fixed_size_array.ll
M llvm/test/Analysis/Delinearization/himeno_1.ll
M llvm/test/Analysis/Delinearization/himeno_2.ll
M llvm/test/Analysis/Delinearization/iv_times_constant_in_subscript.ll
M llvm/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_3d.ll
M llvm/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_nts_3d.ll
M llvm/test/Analysis/Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll
M llvm/test/Analysis/Delinearization/multidim_only_ivs_2d.ll
M llvm/test/Analysis/Delinearization/multidim_only_ivs_3d.ll
M llvm/test/Analysis/Delinearization/multidim_only_ivs_3d_cast.ll
M llvm/test/Analysis/Delinearization/multidim_two_accesses_different_delinearization.ll
M llvm/test/Analysis/Delinearization/parameter_addrec_product.ll
M llvm/test/Analysis/Delinearization/terms_with_identity_factor.ll
M llvm/test/Analysis/DependenceAnalysis/Banerjee.ll
R llvm/test/Analysis/DependenceAnalysis/Coupled.ll
M llvm/test/Analysis/DependenceAnalysis/DifferentOffsets.ll
M llvm/test/Analysis/DependenceAnalysis/Invariant.ll
M llvm/test/Analysis/DependenceAnalysis/NonCanonicalizedSubscript.ll
M llvm/test/Analysis/DependenceAnalysis/PR51512.ll
M llvm/test/Analysis/DependenceAnalysis/Propagating.ll
M llvm/test/Analysis/DependenceAnalysis/SameSDLoops.ll
R llvm/test/Analysis/DependenceAnalysis/Separability.ll
M llvm/test/Analysis/DependenceAnalysis/StrongSIV.ll
M llvm/test/Analysis/DependenceAnalysis/SymbolicSIV.ll
M llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
M llvm/test/Analysis/DependenceAnalysis/run-specific-dependence-test.ll
A llvm/test/Analysis/LoopCacheAnalysis/crash-after-pr164798.ll
M llvm/test/Analysis/LoopCacheAnalysis/interchange-refcost-overflow.ll
A llvm/test/Analysis/ScalarEvolution/addrec-may-wrap-udiv-canonicalize.ll
A llvm/test/Assembler/dbg_declare_value.ll
A llvm/test/Assembler/invalid-ptrauth-const6.ll
A llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll
A llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll.bc
M llvm/test/Bitcode/compatibility.ll
M llvm/test/Bitcode/operand-bundles-bc-analyzer.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/AArch64/aarch64-isel-umin.ll
M llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
A llvm/test/CodeGen/AArch64/addtruncshift.ll
M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
M llvm/test/CodeGen/AArch64/arm64-trn.ll
M llvm/test/CodeGen/AArch64/arm64-vhadd.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/combine-sdiv.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
A llvm/test/CodeGen/AArch64/deactivation-symbols.ll
A llvm/test/CodeGen/AArch64/fixed-length-bf16-arith.ll
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/freeze.ll
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/insert-subvector.ll
M llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/machine-sink-kill-flags.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
A llvm/test/CodeGen/AArch64/ptrauth-irelative.ll
M llvm/test/CodeGen/AArch64/ptrauth-type-info-vptr-discr.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
M llvm/test/CodeGen/AArch64/rem-by-const.ll
A llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
M llvm/test/CodeGen/AArch64/sme-zt0-state.ll
M llvm/test/CodeGen/AArch64/srem-lkk.ll
M llvm/test/CodeGen/AArch64/sve-bf16-arith.ll
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-indexed-arithmetic.ll
M llvm/test/CodeGen/AArch64/sve-vector-compress.ll
M llvm/test/CodeGen/AArch64/trunc-avg-fold.ll
M llvm/test/CodeGen/AArch64/vldn_shuffle.ll
M llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/add_i1.ll
M llvm/test/CodeGen/AMDGPU/add_u64.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-entry.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/cse-convergent.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds_read2-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-av-classes.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
A llvm/test/CodeGen/AMDGPU/gws_agpr.ll
M llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
R llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
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M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
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A llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
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M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
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M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
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M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-constexpr.ll
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M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
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M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
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A llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
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M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
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M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
A llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
A llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-scale-to-agpr.mir
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
A llvm/test/CodeGen/AMDGPU/same-lds-variable-multiple-use-in-one-phi-node.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select-load-to-load-select-ptr-combine.ll
M llvm/test/CodeGen/AMDGPU/select-vectors.ll
M llvm/test/CodeGen/AMDGPU/select64.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
A llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
M llvm/test/CodeGen/AMDGPU/spillv16.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub_i1.ll
M llvm/test/CodeGen/AMDGPU/sub_u64.ll
M llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir
M llvm/test/CodeGen/AMDGPU/use-after-free-after-cleanup-failed-vreg.ll
M llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
M llvm/test/CodeGen/BPF/atomic-oversize.ll
A llvm/test/CodeGen/BPF/builtin_calls.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/CodeGen/BPF/struct_ret1.ll
M llvm/test/CodeGen/BPF/struct_ret2.ll
M llvm/test/CodeGen/DirectX/CBufferAccess/gep-ce-two-uses.ll
M llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll
M llvm/test/CodeGen/DirectX/ddx_coarse-errors.ll
M llvm/test/CodeGen/DirectX/ddy_coarse-errors.ll
M llvm/test/CodeGen/DirectX/scalarize-alloca.ll
M llvm/test/CodeGen/DirectX/scalarize-global.ll
A llvm/test/CodeGen/Hexagon/bfloat.ll
A llvm/test/CodeGen/Hexagon/bfloat_vec.ll
M llvm/test/CodeGen/Hexagon/swp-stages5.ll
M llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll
A llvm/test/CodeGen/LoongArch/lasx/rotl-rotr.ll
M llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll
A llvm/test/CodeGen/LoongArch/lsx/rotl-rotr.ll
A llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
A llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir
A llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-name-error.mir
A llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-mfi.ll
A llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-stack-type-error.mir
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
M llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
A llvm/test/CodeGen/Mips/fp-intrinsics.ll
A llvm/test/CodeGen/Mips/fp-strict-fcmp.ll
M llvm/test/CodeGen/NVPTX/atomics-b128.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/bswap.ll
M llvm/test/CodeGen/NVPTX/bug22246.ll
M llvm/test/CodeGen/NVPTX/fast-math.ll
M llvm/test/CodeGen/NVPTX/i1-select.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
M llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
A llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
A llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
A llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
A llvm/test/CodeGen/NVPTX/wmma-ptx88-sm120a.py
M llvm/test/CodeGen/NVPTX/wmma.py
M llvm/test/CodeGen/PowerPC/addition-vector-all-ones.ll
M llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll
M llvm/test/CodeGen/PowerPC/licm-xxsplti.ll
M llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
M llvm/test/CodeGen/PowerPC/sink-side-effect.ll
M llvm/test/CodeGen/PowerPC/sms-phi-1.ll
M llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vle.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/addcarry.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/allow-check.ll
M llvm/test/CodeGen/RISCV/arith-with-overflow.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bitreverse-shift.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
M llvm/test/CodeGen/RISCV/bswap-shift.ll
M llvm/test/CodeGen/RISCV/cfi-multiple-locations.mir
M llvm/test/CodeGen/RISCV/clear-cache.ll
M llvm/test/CodeGen/RISCV/copy-frameindex.mir
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/double-zfa.ll
M llvm/test/CodeGen/RISCV/double_reduct.ll
M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/fixed-csr.ll
M llvm/test/CodeGen/RISCV/float-arith-strict.ll
M llvm/test/CodeGen/RISCV/float-arith.ll
M llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-convert-strict.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/float-select-verify.ll
M llvm/test/CodeGen/RISCV/float-zfa.ll
M llvm/test/CodeGen/RISCV/flt-rounds.ll
A llvm/test/CodeGen/RISCV/fma-combine.ll
M llvm/test/CodeGen/RISCV/fmax-fmin.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/fpenv.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/frm-dependency.ll
M llvm/test/CodeGen/RISCV/get-register-invalid.ll
M llvm/test/CodeGen/RISCV/get-register-noreserve.ll
M llvm/test/CodeGen/RISCV/get-register-reserve.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/half-zfa.ll
M llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
M llvm/test/CodeGen/RISCV/i64-icmp.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll
M llvm/test/CodeGen/RISCV/intrinsics/trap.ll
M llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/machine-combiner.ll
M llvm/test/CodeGen/RISCV/machine-cse.ll
M llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll
M llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
M llvm/test/CodeGen/RISCV/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/memset-inline.ll
M llvm/test/CodeGen/RISCV/min-max.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/module-target-abi3.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsic-optimizations.ll
M llvm/test/CodeGen/RISCV/pei-crash.ll
M llvm/test/CodeGen/RISCV/pr135206.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/pr92193.ll
M llvm/test/CodeGen/RISCV/prefetch.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/readcyclecounter.ll
M llvm/test/CodeGen/RISCV/readsteadycounter.ll
M llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/remat.ll
M llvm/test/CodeGen/RISCV/replace-with-veclib-sleef-scalable.ll
M llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbkx-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
M llvm/test/CodeGen/RISCV/rv64-float-convert.ll
M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-args.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-frame-setup.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
M llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbkx-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
A llvm/test/CodeGen/RISCV/rvv/combine-vl-vw-macc.ll
M llvm/test/CodeGen/RISCV/rvv/commutable.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-negative.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vector-splice.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvw.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vp-fsub-and-vp-fmul.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
M llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
Log Message:
-----------
Merge branch 'main' into users/s.barannikov/decoder-operands-7-arm
Compare: https://github.com/llvm/llvm-project/compare/682f9f4debe6...f18d72f65f20
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