[all-commits] [llvm/llvm-project] bb9449: [InstCombine] Fold @llvm.experimental.get.vector.l...
Zhaoxin Yang via All-commits
all-commits at lists.llvm.org
Thu Nov 27 17:14:13 PST 2025
Branch: refs/heads/users/ylzsx/rotr-custom
Home: https://github.com/llvm/llvm-project
Commit: bb9449d5bbd72441d8f95052ddfd29e2d29297d7
https://github.com/llvm/llvm-project/commit/bb9449d5bbd72441d8f95052ddfd29e2d29297d7
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
A llvm/test/Transforms/InstCombine/get_vector_length.ll
Log Message:
-----------
[InstCombine] Fold @llvm.experimental.get.vector.length when cnt <= max_lanes (#169293)
On RISC-V, some loops that the loop vectorizer vectorizes pre-LTO may
turn out to have the exact trip count exposed after LTO, see #164762.
If the trip count is small enough we can fold away the
@llvm.experimental.get.vector.length intrinsic based on this corollary
from the LangRef:
> If %cnt is less than or equal to %max_lanes, the return value is equal
to %cnt.
This on its own doesn't remove the @llvm.experimental.get.vector.length
in #164762 since we also need to teach computeKnownBits about
@llvm.experimental.get.vector.length and the sub recurrence, but this PR
is a starting point.
I've added this in InstCombine rather than InstSimplify since we may
need to insert a truncation (@llvm.experimental.get.vector.length can
take an i64 %cnt argument, the result is always i32).
Note that there was something similar done in VPlan in #167647 for when
the loop vectorizer knows the trip count.
Commit: 6abbbca32472537389a4fd9961f680251a57e82b
https://github.com/llvm/llvm-project/commit/6abbbca32472537389a4fd9961f680251a57e82b
Author: David Green <david.green at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
A llvm/test/Transforms/AggressiveInstCombine/umulh_carry.ll
A llvm/test/Transforms/AggressiveInstCombine/umulh_carry4.ll
A llvm/test/Transforms/AggressiveInstCombine/umulh_ladder.ll
A llvm/test/Transforms/AggressiveInstCombine/umulh_ladder4.ll
Log Message:
-----------
[AggressiveInstCombine] Match long high-half multiply (#168396)
This patch adds recognition of high-half multiply by parts into a single
larger multiply.
Considering a multiply made up of high and low parts, we can split the
multiply into:
x * y == (xh*T + xl) * (yh*T + yl)
where `xh == x>>32` and `xl == x & 0xffffffff`. `T = 2^32`.
This expands to
xh*yh*T*T + xh*yl*T + xl*yh*T + xl*yl
which I find it helpful to be drawn as
[ xh*yh ]
[ xh*yl ]
[ xl*yh ]
[ xl*yl ]
We are looking for the "high" half, which is xh*yh + xh*yl>>32 + xl*yh>>32 +
carrys. The carry makes this difficult and there are multiple ways of
representing it. The ones we attempt to support here are:
Carry: xh*yh + carry + lowsum
carry = lowsum < xh*yl ? 0x1000000 : 0
lowsum = xh*yl + xl*yh + (xl*yl>>32)
Ladder: xh*yh + c2>>32 + c3>>32
c2 = xh*yl + (xl*yl >> 32); c3 = c2&0xffffffff + xl*yh
Carry4: xh*yh + carry + crosssum>>32 + (xl*yl + crosssum&0xffffffff) >> 32
crosssum = xh*yl + xl*yh
carry = crosssum < xh*yl ? 0x1000000 : 0
Ladder4: xh*yh + (xl*yh)>>32 + (xh*yl)>>32 + low>>32;
low = (xl*yl)>>32 + (xl*yh)&0xffffffff + (xh*yl)&0xfffffff
They all start by matching `xh*yh` + 2 or 3 other operands. The bottom of the
tree is `xh*yh`, `xh*yl`, `xl*yh` and `xl*yl`.
Based on #156879 by @c-rhodes
Commit: 1c7ec06b16dc59b5b52cff95bde7d5330ffa0293
https://github.com/llvm/llvm-project/commit/1c7ec06b16dc59b5b52cff95bde7d5330ffa0293
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
Log Message:
-----------
[VPlan] Optimize LastActiveLane to EVL - 1 (#169766)
With EVL tail folding, the LastActiveLane can be computed with EVL - 1.
This removes the need for a header mask and vfirst.m for loops with live
outs on RISC-V:
# %bb.5: # %for.cond.cleanup7
- vsetvli zero, zero, e32, m2, ta, ma
- vmv.v.x v8, s1
- vmsleu.vv v10, v8, v22
- vfirst.m a0, v10
- srli a1, a0, 63
- czero.nez a0, a0, a1
- czero.eqz a1, s8, a1
- or a0, a0, a1
- addi a0, a0, -1
- vsetvli zero, zero, e64, m4, ta, ma
- vslidedown.vx v8, v12, a0
+ addi s1, s1, -1
+ vslidedown.vx v8, v12, s1
Commit: 9cb9b16fd63365fe452947ffdfbccd3ac7e6a08c
https://github.com/llvm/llvm-project/commit/9cb9b16fd63365fe452947ffdfbccd3ac7e6a08c
Author: Vadim Curcă <80581374+VadimCurca at users.noreply.github.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/test/Target/LLVMIR/Import/metadata-profiling.ll
Log Message:
-----------
[mlir][llvm] Fix import of branch weights with "expected" field (#169776)
This commit fixes the import of `branch_weights` metadata from LLVM IR
to the LLVM dialect. Previously, `branch_weights` metadata containing
the `!"expected"` field were rejected because the importer expected
integer weights at operand 1, but found a string.
Commit: dc8311f207f4facf88a8c939b4132afdaab08470
https://github.com/llvm/llvm-project/commit/dc8311f207f4facf88a8c939b4132afdaab08470
Author: David Green <david.green at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir
Log Message:
-----------
[ARM] Remove IR from mve vpt mir tests. NFC
As far as I can tell the llvm.arm.mve.vminnm.m intrinsic used in these tests
was the pre-upstream name of llvm.arm.mve.min.predicated. The tests should not
need IR sections, so remove them just relying on the MIR portions.
Commit: c28c99f51101d5130eeb9df061dcd10a1750d97b
https://github.com/llvm/llvm-project/commit/c28c99f51101d5130eeb9df061dcd10a1750d97b
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/test/SemaHIP/amdgpu-gfx950-load-to-lds.hip
Log Message:
-----------
[NFC][HIP] Add __builtin_*_load_lds type check test cases (#165388)
This tests show how type-checking is performed for
`__builtin_amdgcn_load_to_lds`,
but not for `__builtin_amdgcn_raw_ptr_buffer_load_lds`,
`__builtin_amdgcn_struct_ptr_buffer_load_lds` and
`__builtin_amdgcn_global_load_lds` since they are declared with the 't'
attribute.
Stacked on top of: https://github.com/llvm/llvm-project/pull/165387
Commit: 650eeb867fa95435b7c123e6630eb98934ac5bf3
https://github.com/llvm/llvm-project/commit/650eeb867fa95435b7c123e6630eb98934ac5bf3
Author: Nathan Corbyn <n_corbyn at apple.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
Log Message:
-----------
[ShrinkWrap] Modify shrink wrapping to accommodate functions terminated by no-return blocks (#167548)
At present, the shrink wrapping pass misses opportunities to shrink wrap
in the presence of machine basic blocks which exit the function without
returning. Such cases arise from C++ functions like the following:
```cxx
int foo(int err, void* ptr) {
if (err == -1) {
if (ptr == nullptr) {
throw MyException("Received `nullptr`!", __FILE__, __LINE__);
}
handle(ptr);
}
return STATUS_OK;
}
```
In particular, assuming `MyException`'s constructor is not marked
`noexcept`, the above code will generate a trivial EH landing pad
calling `__cxa_free_exception()` and rethrowing the unhandled internal
exception, exiting the function without returning. As such, the shrink
wrapping pass refuses to touch the above function, spilling to the stack
on every call, even though no CSRs are clobbered on the hot path. This
patch tweaks the shrink wrapping logic to enable the pass to fire in
this and similar cases.
Commit: c3c3d16773f8db2188145378500070658afeb30f
https://github.com/llvm/llvm-project/commit/c3c3d16773f8db2188145378500070658afeb30f
Author: NagaChaitanya Vellanki <pnagato at protonmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/avx512vbmiintrin.h
M clang/lib/Headers/avx512vbmivlintrin.h
M clang/test/CodeGen/X86/avx512vbmi-builtins.c
M clang/test/CodeGen/X86/avx512vbmivl-builtin.c
Log Message:
-----------
[Clang] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - Allow AVX512 VPMULTISHIFTQB intrinsics to be used in constexpr (#168995)
Resolves #167477
Commit: 0b1651260a36b38a65bb4f14ad8c9c5551ab5a34
https://github.com/llvm/llvm-project/commit/0b1651260a36b38a65bb4f14ad8c9c5551ab5a34
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/utils/TableGen/README.md
Log Message:
-----------
[llvm][Tablegen] Link to tutorial before programmer's reference
The natural assumption is that there's some sort of order here
and having people read the reference manual before the basic
tutorial does not make sense to me.
Commit: 8401a8d0be7671fb5089f850a34dc92ad4a2eb12
https://github.com/llvm/llvm-project/commit/8401a8d0be7671fb5089f850a34dc92ad4a2eb12
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
A llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll
A llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll.bc
Log Message:
-----------
[NFC][LLVM] Add bitcode tests for llvm.aarch64.sve.rev
Commit: 0dbedd195c94e89b43660e67aa56dd139a81fa40
https://github.com/llvm/llvm-project/commit/0dbedd195c94e89b43660e67aa56dd139a81fa40
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/lib/Headers/avx10_2_512bf16intrin.h
M clang/lib/Headers/avx10_2bf16intrin.h
M clang/lib/Headers/avx512vlfp16intrin.h
M clang/lib/Headers/avxintrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/xmmintrin.h
M clang/test/CodeGen/X86/sse-builtins-constrained.c
M clang/test/CodeGen/X86/sse-builtins.c
M clang/test/CodeGen/X86/sse2-builtins-constrained.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/builtins-x86.c
Log Message:
-----------
[Clang] Replace some x86 sqrt builtins with the generic __builtin_elementwise_sqrt versions (#165682)
Commit: bec726f6a6d37bdfb90d1330d4b5e947ce017046
https://github.com/llvm/llvm-project/commit/bec726f6a6d37bdfb90d1330d4b5e947ce017046
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
A llvm/test/CodeGen/X86/haddsubsat.ll
Log Message:
-----------
[X86] optimize ssse3 horizontal saturating add/sub (#169591)
Currently LLVM fails to recognize a manual implementation of `phadd`
https://godbolt.org/z/zozrssaWb
```llvm
declare <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
define <8 x i16> @phaddsw_v8i16_intrinsic(<8 x i16> %a, <8 x i16> %b) {
entry:
%res = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
define <8 x i16> @phaddsw_v8i16_generic(<8 x i16> %a, <8 x i16> %b) {
entry:
%even = shufflevector <8 x i16> %a, <8 x i16> %b,
<8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%odd = shufflevector <8 x i16> %a, <8 x i16> %b,
<8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%sum = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %even, <8 x i16> %odd)
ret <8 x i16> %sum
}
```
```asm
phaddsw_v8i16_intrinsic: # @phaddsw_v8i16_intrinsic
phaddsw xmm0, xmm1
ret
phaddsw_v8i16_generic: # @phaddsw_v8i16_generic
movdqa xmm2, xmmword ptr [rip + .LCPI1_0] # xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
movdqa xmm3, xmm1
pshufb xmm3, xmm2
movdqa xmm4, xmm0
pshufb xmm4, xmm2
punpcklqdq xmm4, xmm3 # xmm4 = xmm4[0],xmm3[0]
psrad xmm1, 16
psrad xmm0, 16
packssdw xmm0, xmm1
paddsw xmm0, xmm4
ret
```
This PR does recognize the pattern.
Commit: d6be9fc115459ce154f8aa062b05645adb150469
https://github.com/llvm/llvm-project/commit/d6be9fc115459ce154f8aa062b05645adb150469
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libcxx/include/deque
M libcxx/test/libcxx/diagnostics/deque.nodiscard.verify.cpp
Log Message:
-----------
[libc++][deque] Applied `[[nodiscard]]` (#169745)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: bd95a74a2c548867c004ec991defe276f9cbbf40
https://github.com/llvm/llvm-project/commit/bd95a74a2c548867c004ec991defe276f9cbbf40
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/invalid.cpp
Log Message:
-----------
[clang][bytecode] Check for invalid record decls in IntPointer::atOffset (#169786)
We can't access the RecordLayout of an invalid decl, so return failure
if that happens.
Fixes https://github.com/llvm/llvm-project/issues/167076
Commit: 682f292d2caec5b71f8ce6c641114fee446ba49f
https://github.com/llvm/llvm-project/commit/682f292d2caec5b71f8ce6c641114fee446ba49f
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
Log Message:
-----------
[LV] Test more combinations of scalar stores using last lane of IV.
Extends test coverage to include different start and step values, as
well as interleaving.
Commit: df8061272ad6d3770ddc17498eff70f700a020ad
https://github.com/llvm/llvm-project/commit/df8061272ad6d3770ddc17498eff70f700a020ad
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libcxx/include/__flat_set/flat_set.h
M libcxx/test/libcxx/diagnostics/flat_map.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/flat_set.nodiscard.verify.cpp
Log Message:
-----------
[libc++][flat_set] Applied `[[nodiscard]]` (#169739)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 7b813c3d8095ba49a8f1e935a9b14c23490e3bb0
https://github.com/llvm/llvm-project/commit/7b813c3d8095ba49a8f1e935a9b14c23490e3bb0
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/test/AST/ByteCode/invalid.cpp
Log Message:
-----------
[clang][bytecode][test] Specify triple for Invalid.cpp
This should unbreak that test on 32bit builders, e.g.
https://lab.llvm.org/buildbot/#/builders/154/builds/24509
Commit: eee09ca98470b880fdd54bd3ff7ea05ae276314a
https://github.com/llvm/llvm-project/commit/eee09ca98470b880fdd54bd3ff7ea05ae276314a
Author: Eric Xu <60671484+ericxu233 at users.noreply.github.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/test/CodeGen/X86/f16c-builtins.c
Log Message:
-----------
[X86][Clang] Allow constexpr evaluation of F16C CVTPS2PH intrinsics (#162295)
Fixes #160312
Commit: fca41f4aa105f30af75d88d993539d043ac66460
https://github.com/llvm/llvm-project/commit/fca41f4aa105f30af75d88d993539d043ac66460
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/lib/Headers/avx512bf16intrin.h
M clang/lib/Headers/avx512vlbf16intrin.h
M clang/test/CodeGen/X86/avx512bf16-builtins.c
M clang/test/CodeGen/X86/avx512vlbf16-builtins.c
Log Message:
-----------
[X86] Replace BF16 to F32 conversions with generic conversions (#169781)
Let standard casting / builtin_convertvector handle the conversions from BF16 to F32
My only query is how to best implement _mm_cvtpbh_ps - I went for the
v8bf16 -> v8f32 conversion followed by subvector extraction in the end,
but could just as easily extract a v4bf16 first - makes no difference to
final optimized codegen.
First part of #154911
Commit: ea1e62d1a00bf3d40b7a1fd926d2a573c997188d
https://github.com/llvm/llvm-project/commit/ea1e62d1a00bf3d40b7a1fd926d2a573c997188d
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/Target/Target.td
M llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
M llvm/utils/TableGen/Basic/VTEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
Log Message:
-----------
[CodeGenTypes] Remove explicit VT numbers from ValueTypes.td (#169670)
Remove explicit VT numbers from ValueTypes.td so that patches that add a
new VT do not have to renumber the entire file.
In TableGen VTs are now identified by ValueType.LLVMName instead of
ValueType.Value. This is important for target-defined types (typically
based on PtrValueType) which are not mentioned in ValueTypes.td itself.
Commit: 66ca3f1367bb59915bd9f832a9cd3dfe56304538
https://github.com/llvm/llvm-project/commit/66ca3f1367bb59915bd9f832a9cd3dfe56304538
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
A llvm/test/CodeGen/SystemZ/zos-target-flags.ll
Log Message:
-----------
[SystemZ] Serialize ada entry flags (#169395)
Adding support for serializing the ada entry flags helps with mir based
test cases. Without this change, the flags are simple displayed as being
"unkmown".
Commit: 1d7d83d0bf8f376b977f25cec75633dceb91b8f1
https://github.com/llvm/llvm-project/commit/1d7d83d0bf8f376b977f25cec75633dceb91b8f1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/darwin.ll
Log Message:
-----------
RuntimeLibcalls: Add macos unlocked IO functions to systems (#167084)
Commit: 514dbab474c71326c1080f3129a26f0ffdd71d51
https://github.com/llvm/llvm-project/commit/514dbab474c71326c1080f3129a26f0ffdd71d51
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/docs/ClangStaticAnalyzer.rst
M clang/docs/analyzer/user-docs.rst
M clang/docs/analyzer/user-docs/CommandLineUsage.rst
M clang/docs/analyzer/user-docs/Installation.rst
Log Message:
-----------
[NFC][analyzer] Clean up obsolete installation instructions (#166193)
The documentation file `Installation.rst` contained very obsolete
instructions for installing the clang static analyzer. This commit
replaces it with sentence which explains that the analyzer is part of
clang and links to the releases page of LLVM (for downloading clang).
This sentence is primarily added to the top-level page of the analyzer
documentation; but it also appears in a stubbed Installation.rst (for
users who followed a direct external link to this installation page).
This stubbed section is removed from the table of contents, but I kept
it as an orphaned page (to avoid breaking links).
Fixes #165571
Commit: d128d90e71146cf099a31a967fdeb2591d30514d
https://github.com/llvm/llvm-project/commit/d128d90e71146cf099a31a967fdeb2591d30514d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/emscripten.ll
Log Message:
-----------
RuntimeLibcalls: Add small_printf functions to emscripten (#167087)
Commit: 97aa4f3abbba2ce4460c0d8e5364bd333aaa8079
https://github.com/llvm/llvm-project/commit/97aa4f3abbba2ce4460c0d8e5364bd333aaa8079
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/xcore.ll
Log Message:
-----------
XCore: Add iprintf to RuntimeLibcalls system library (#167088)
Commit: 6412184891526690cff804f87f986b1fa039f011
https://github.com/llvm/llvm-project/commit/6412184891526690cff804f87f986b1fa039f011
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/docs/Dialects/NVVMDialect.md
Log Message:
-----------
[MLIR][NVVM][Docs] Update docs (#169694)
This patch updates the NVVM Dialect docs to:
* include information on the type of pointers for the memory spaces.
* include high-level information on mbarrier objects.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 4394aa685c4b01ad3782a137fcfebeadc4941df1
https://github.com/llvm/llvm-project/commit/4394aa685c4b01ad3782a137fcfebeadc4941df1
Author: Jason-VanBeusekom <jason.van-beusekom at hpe.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/docs/HIPSupport.rst
M clang/lib/CodeGen/CodeGenModule.cpp
A clang/test/CodeGenCUDA/cuda_weak_alias.cu
A clang/test/CodeGenHIP/hip_weak_alias.cpp
A clang/test/OpenMP/amdgcn_weak_alias.c
A clang/test/OpenMP/amdgcn_weak_alias.cpp
A clang/test/OpenMP/nvptx_weak_alias.c
Log Message:
-----------
[OpenMP][clang][HIP][CUDA] fix weak alias emit on device compilation (#164326)
This PR adds checks for when emitting weak aliases in: `void
CodeGenModule::EmitGlobal(GlobalDecl GD)`, before for device compilation
for OpenMP, HIP and Cuda, clang would look for the aliasee even if it
was never marked for device compilation.
For OpenMP the following case now works:
> Failed before when compiling with device, ie: `clang -fopenmp
-fopenmp-targets=amdgcn-amd-amdhsa`
> ```
> int __Two(void) { return 2; }
> int Two(void) __attribute__ ((weak, alias("__Two")));
> ```
For HIP / Cuda:
>
> ```
> int __HostFunc(void) { return 42; }
> int HostFunc(void) __attribute__ ((weak, alias("__HostFunc")));
> ```
For HIP:
>Failed before on HIP, Cuda fails due to: `NVPTX aliasee must not be
'.weak'` error
> ```
> __device__ int __One(void) { return 2; }
> __device__ int One(void) __attribute__ ((weak, alias("__One")));
> ```
Included are Codegen LIT tests for the above cases, and also cases for
weak alias cases that currently work in clang.
Fixes https://github.com/llvm/llvm-project/issues/117369
Commit: 0e5633fcd984b54acc071c2c982c1ff4691aa10f
https://github.com/llvm/llvm-project/commit/0e5633fcd984b54acc071c2c982c1ff4691aa10f
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/test/OpenMP/cancel_codegen.cpp
M clang/test/OpenMP/critical_codegen.cpp
M clang/test/OpenMP/critical_codegen_attr.cpp
M clang/test/OpenMP/irbuilder_nested_parallel_for.c
M clang/test/OpenMP/masked_codegen.cpp
M clang/test/OpenMP/master_codegen.cpp
M clang/test/OpenMP/nested_loop_codegen.cpp
M clang/test/OpenMP/ordered_codegen.cpp
M clang/test/OpenMP/parallel_codegen.cpp
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/test/Transforms/OpenMP/parallel_region_merging.ll
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-barrier-cancel.mlir
M mlir/test/Target/LLVMIR/openmp-cancel.mlir
M mlir/test/Target/LLVMIR/openmp-cancellation-point.mlir
M mlir/test/Target/LLVMIR/openmp-outline-infinite-loop.mlir
M mlir/test/Target/LLVMIR/openmp-parallel-reduction-multiblock.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-array-sections.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-init-arg.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-sections.mlir
Log Message:
-----------
[OMPIRBuilder] always leave PARALLEL via the same barrier (#164586)
A barrier will pause execution until all threads reach it. If some go to
a different barrier then we deadlock. This manifests in that the
finalization callback must only be run once. Fix by ensuring we always
go through the same finalization block whether the thread in cancelled
or not and no matter which cancellation point causes the cancellation.
The old callback only affected PARALLEL, so it has been moved into the
code generating PARALLEL. For this reason, we don't need similar changes
for other cancellable constructs. We need to create the barrier on the
shared exit from the outlined function instead of only on the cancelled
branch to make sure that threads exiting normally (without cancellation)
meet the same barriers as those which were cancelled. For example,
previously we might have generated code like
```
...
%ret = call i32 @__kmpc_cancel(...)
%cond = icmp eq i32 %ret, 0
br i1 %cond, label %continue, label %cancel
continue:
// do the rest of the callback, eventually branching to %fini
br label %fini
cancel:
// Populated by the callback:
// unsafe: if any thread makes it to the end without being cancelled
// it won't reach this barrier and then the program will deadlock
%unused = call i32 @__kmpc_cancel_barrier(...)
br label %fini
fini:
// run destructors etc
ret
```
In the new version the barrier is moved into fini. I generate it *after*
the destructors because the standard describes the barrier as occurring
after the end of the parallel region.
```
...
%ret = call i32 @__kmpc_cancel(...)
%cond = icmp eq i32 %ret, 0
br i1 %cond, label %continue, label %cancel
continue:
// do the rest of the callback, eventually branching to %fini
br label %fini
cancel:
br label %fini
fini:
// run destructors etc
// safe so long as every exit from the function happens via this block:
%unused = call i32 @__kmpc_cancel_barrier(...)
ret
```
To achieve this, the barrier is now generated alongside the finalization
code instead of in the callback. This is the reason for the changes to
the unit test.
I'm unsure if I should keep the incorrect barrier generation callback
only on the cancellation branch in clang with the OMPIRBuilder backend
because that would match clang's ordinary codegen. Right now I have
opted to remove it entirely because it is a deadlock waiting to happen.
Commit: 47ae3eaa29f2195429f2ca19cc171a9ebd83c242
https://github.com/llvm/llvm-project/commit/47ae3eaa29f2195429f2ca19cc171a9ebd83c242
Author: Jack Styles <jack.styles at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M flang/docs/OpenMPSupport.md
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir
A mlir/test/Target/LLVMIR/openmp-dist_schedule.mlir
A mlir/test/Target/LLVMIR/openmp-dist_schedule_with_wsloop.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[MLIR][OpenMP] Add MLIR Lowering Support for dist_schedule (#152736)
`dist_schedule` was previously supported in Flang/Clang but was not
implemented in MLIR, instead a user would get a "not yet implemented"
error. This patch adds support for the `dist_schedule` clause to be
lowered to LLVM IR when used in an `omp.distribute` or `omp.wsloop`
section.
There has needed to be some rework required to ensure that MLIR/LLVM
emits the correct Schedule Type for the clause, as it uses a different
schedule type to other OpenMP directives/clauses in the runtime library.
This patch also ensures that when using dist_schedule or a chunked
schedule clause, the correct llvm loop parallel accesses details are
added.
Commit: e3044cd552ca0300dbb4c1051dccd038382bd4af
https://github.com/llvm/llvm-project/commit/e3044cd552ca0300dbb4c1051dccd038382bd4af
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[X86] Sync multiversion features with libgcc and refactor internal feature tables (#168750)
Compiler-rt internal feature table is synced with the one in libgcc
(common/config/i386/i386-cpuinfo.h).
LLVM internal feature table is refactored to include a field ABI_VALUE,
so we won't be relying on ordering to keep the values correct. The table
is also synced to the one in compiler-rt.
Commit: c0d81bf55f3dc3b38a1d403ee07e547016f46842
https://github.com/llvm/llvm-project/commit/c0d81bf55f3dc3b38a1d403ee07e547016f46842
Author: David Green <david.green at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.h
M llvm/lib/Target/ARM/ARMMCInstLower.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
Log Message:
-----------
[ARM] Remove Subtarget from ARMAsmPrinter (#168264)
Remove Subtarget uses from ARMAsmPrinter, making use of TargetMachine
where applicable and getting the Subtarget from the MF where not. Some
of the `if() llvm_unreachable` have been replaced by `asserts`.
Commit: adcc557ef176ee36a1e5df12b60789b6fa2fe73c
https://github.com/llvm/llvm-project/commit/adcc557ef176ee36a1e5df12b60789b6fa2fe73c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/test/CodeGen/X86/srem-vector-lkk.ll
M llvm/test/CodeGen/X86/urem-vector-lkk.ll
Log Message:
-----------
[X86] rem-vector-lkk.ll - improve CPU coverage to cover all x86-64 levels (#169805)
SSE2/SSE42/AVX1/AVX2 + x86-64-v4 (AVX512)
Commit: 920a091da216521cbef4203ad69c63aaa2ea2154
https://github.com/llvm/llvm-project/commit/920a091da216521cbef4203ad69c63aaa2ea2154
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libcxx/test/libcxx-03/algorithms/half_positive.pass.cpp
M libcxx/test/libcxx-03/algorithms/robust_against_copying_comparators.pass.cpp
M libcxx/test/libcxx-03/algorithms/robust_against_cpp20_hostile_iterators.compile.pass.cpp
M libcxx/test/libcxx-03/containers/sequences/vector/asan.pass.cpp
M libcxx/test/libcxx-03/containers/sequences/vector/asan_throw.pass.cpp
M libcxx/test/libcxx-03/depr/depr.default.allocator/allocator.members/construct.cxx20.pass.cpp
M libcxx/test/libcxx-03/input.output/string.streams/stringbuf/const_sso_buffer.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/arithmetic.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/comparison.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/pointer_traits.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/types.compile.pass.cpp
M libcxx/test/libcxx-03/iterators/contiguous_iterators.conv.compile.pass.cpp
M libcxx/test/libcxx-03/iterators/contiguous_iterators.pass.cpp
M libcxx/test/libcxx-03/iterators/predef.iterators/insert.iterators/back.insert.iter.ops/get_container.pass.cpp
M libcxx/test/libcxx-03/iterators/unwrap_iter.pass.cpp
M libcxx/test/libcxx-03/language.support/support.dynamic/libcpp_deallocate.sh.cpp
M libcxx/test/libcxx-03/libcpp_alignof.pass.cpp
M libcxx/test/libcxx-03/memory/allocation_guard.pass.cpp
M libcxx/test/libcxx-03/memory/swap_allocator.pass.cpp
M libcxx/test/libcxx-03/numerics/bit.ops.pass.cpp
M libcxx/test/libcxx-03/strings/basic.string/string.capacity/max_size.pass.cpp
M libcxx/test/libcxx-03/strings/basic.string/string.cons/copy_shrunk_long.pass.cpp
M libcxx/test/libcxx-03/strings/c.strings/constexpr_memmove.pass.cpp
M libcxx/test/libcxx-03/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/bullet_1_2_3.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/bullet_4_5_6.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/bullet_7.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/invoke.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/invoke_helpers.h
M libcxx/test/libcxx-03/utilities/is_pointer_in_range.pass.cpp
M libcxx/test/libcxx-03/utilities/is_valid_range.pass.cpp
M libcxx/test/libcxx-03/utilities/memory/pointer.conversion/to_address.pass.cpp
M libcxx/test/libcxx-03/utilities/memory/pointer.conversion/to_address_std_iterators.pass.cpp
M libcxx/test/libcxx-03/utilities/meta/is_referenceable.compile.pass.cpp
M libcxx/test/libcxx-03/utilities/no_destroy.pass.cpp
M libcxx/test/libcxx-03/utilities/utility/pairs/pairs.pair/abi.non_trivial_copy_move.pass.cpp
M libcxx/test/libcxx-03/utilities/utility/pairs/pairs.pair/abi.trivial_copy_move.pass.cpp
M libcxx/test/libcxx-03/utilities/utility/pairs/pairs.pair/abi.trivially_copyable.compile.pass.cpp
Log Message:
-----------
[libc++][C++03] Remove code in the C++03-specific tests that is guarded on the language version (#169354)
This is dead code, since `test/libcxx-03` is only ever executed with
`-std=c++03`.
Commit: 634f6e9ff357050ab28de150f35bf293cd31b332
https://github.com/llvm/llvm-project/commit/634f6e9ff357050ab28de150f35bf293cd31b332
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libcxx/include/__algorithm/copy_n.h
M libcxx/include/__algorithm/iterator_operations.h
M libcxx/include/__algorithm/ranges_copy_n.h
M libcxx/include/__vector/vector.h
Log Message:
-----------
[libc++] Merge the implementations of ranges::copy_n and std::copy_n and fix vector::insert to assign (#157444)
This reduces the amount of code we have to maintain a bit.
This also simplifies `vector` by using the internal API instead of
`#if`s to switch based on language dialect.
Commit: f8e77168c89a142b6e2bdb9ea8322c42c0808fae
https://github.com/llvm/llvm-project/commit/f8e77168c89a142b6e2bdb9ea8322c42c0808fae
Author: NagaChaitanya Vellanki <pnagato at protonmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/avx2intrin.h
M clang/lib/Headers/avx512bwintrin.h
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avx512vlintrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/mmintrin.h
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[Clang] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - Allow PSLL/PSRA/PSRL var intrinsics to be used in constexpr (#169276)
Resolves #169176
Commit: b64150963733d04e524f501cdd736963a7a3ba6d
https://github.com/llvm/llvm-project/commit/b64150963733d04e524f501cdd736963a7a3ba6d
Author: Julian Nagele <j.nagele at apple.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/test/Transforms/LoopUnroll/partial-unroll-reductions.ll
M llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
Log Message:
-----------
[LoopUnroll] Introduce parallel accumulators when unrolling FP reductions. (#166630)
This is building on top of
https://github.com/llvm/llvm-project/pull/149470, also introducing
parallel accumulator PHIs when the reduction is for floating points,
provided we have the reassoc flag. See also
https://github.com/llvm/llvm-project/pull/166353, which aims to
introduce parallel accumulators for reductions with vector instructions.
Commit: 8871e9e2e2c0941b04b22f719906a588fe523be2
https://github.com/llvm/llvm-project/commit/8871e9e2e2c0941b04b22f719906a588fe523be2
Author: Jacob Lambert <jacob.lambert at amd.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
Log Message:
-----------
[clang][Driver] Handle ROCm installation layout of lib/llvm/bin/clang (#138928)
Committing on behalf of @stellaraccident
Commit: 7f1423e58ac894e7225625f34d90806ce5f052b3
https://github.com/llvm/llvm-project/commit/7f1423e58ac894e7225625f34d90806ce5f052b3
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/Delinearization.h
M llvm/lib/Analysis/Delinearization.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/Delinearization/a.ll
M llvm/test/Analysis/Delinearization/constant_functions_multi_dim.ll
M llvm/test/Analysis/Delinearization/divide_by_one.ll
M llvm/test/Analysis/Delinearization/fixed_size_array.ll
M llvm/test/Analysis/Delinearization/himeno_1.ll
M llvm/test/Analysis/Delinearization/himeno_2.ll
M llvm/test/Analysis/Delinearization/iv_times_constant_in_subscript.ll
M llvm/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_3d.ll
M llvm/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_nts_3d.ll
M llvm/test/Analysis/Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll
M llvm/test/Analysis/Delinearization/multidim_only_ivs_2d.ll
M llvm/test/Analysis/Delinearization/multidim_only_ivs_3d.ll
M llvm/test/Analysis/Delinearization/multidim_only_ivs_3d_cast.ll
M llvm/test/Analysis/Delinearization/multidim_two_accesses_different_delinearization.ll
M llvm/test/Analysis/Delinearization/parameter_addrec_product.ll
M llvm/test/Analysis/Delinearization/terms_with_identity_factor.ll
Log Message:
-----------
[DA][Delinearization] Move validation logic into Delinearization (#169047)
This patch moves the validation logic of delinearization results from DA
to Delinearization. Also call it in `printDelinearization` to test its
behavior. The motivation is as follows:
- Almost the same code exists in `tryDelinearizeFixedSize` and
`tryDelinearizeParametricSize`. Consolidating it in Delinearization
avoids code duplication.
- Currently this validation logic is not well tested. Moving it to
Delinearization allows us to write regression tests easily.
This patch changes the test outputs and debug messages, but otherwise
NFCI.
Commit: 90e8889a6394e29843ba903eff45ca03f877a6dd
https://github.com/llvm/llvm-project/commit/90e8889a6394e29843ba903eff45ca03f877a6dd
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
Log Message:
-----------
[lldb] Fix CxxMethodName Parser on return type (#169652)
The simplified parser incorrectly assumes if there is a context, there
is no return type.
Fixed the case where functions have both a context and a return type.
For example,
`int foo::bar::func()`
`Type<int> foo::bar::func()`
Also fixed the case where there is no space between the context and
return.
`std::vector<int>foo::bar()`
Commit: e0c0075819f4fe30c1522a1972b683641e66507a
https://github.com/llvm/llvm-project/commit/e0c0075819f4fe30c1522a1972b683641e66507a
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/disabled-on-amd.ll
Log Message:
-----------
[SPIRV][AMD] Disable SPV_KHR_float_control2 for AMD flavored SPIRV (#169659)
AMD uses the translator to recover LLVM-IR from SPIRV.
Currently, the translator doesn't implement the
`SPV_KHR_float_controls2` extension (I'm working on it).
If this extension is used by the SPIRV module, we cannot translate it
back to LLVM-IR.
I'm working on the extension, but in the meantime, lets just disable it
when the target triple's vendor is `amd`.
Commit: 48e34d95987aec19585672b2363eda1a99338751
https://github.com/llvm/llvm-project/commit/48e34d95987aec19585672b2363eda1a99338751
Author: Ingo Müller <ingomueller at google.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir:bazel] Fix build broken by #169670. (#169804)
This PR adds a dependency to the `BUILD` files overlay silently added by
#169670.
Signed-off-by: Ingo Müller <ingomueller at google.com>
Commit: 25d027b8ab3acd65b58fce278f4173b431326934
https://github.com/llvm/llvm-project/commit/25d027b8ab3acd65b58fce278f4173b431326934
Author: Ming Yan <ming.yan at terapines.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/UpliftWhileToFor.cpp
M mlir/test/Dialect/SCF/uplift-while.mlir
Log Message:
-----------
[MLIR][SCF] Sink scf.if from scf.while before region into after region in scf-uplift-while-to-for (#165216)
When a `scf.if` directly precedes an `scf.condition` in the before
region of an `scf.while` and both share the same condition, move the if
into the after region of the loop. This helps simplify the control flow
to enable uplifting `scf.while` to `scf.for`.
Commit: 5d6d74359d69d3aada6a46c7cf51d84eb0848b70
https://github.com/llvm/llvm-project/commit/5d6d74359d69d3aada6a46c7cf51d84eb0848b70
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M bolt/lib/Passes/Inliner.cpp
A bolt/test/AArch64/inline-bti.s
Log Message:
-----------
[BOLT][BTI] Skip inlining BasicBlocks containing indirect tailcalls (#168403)
In the Inliner pass, tailcalls are converted to calls in the inlined
BasicBlock. If the tailcall is indirect, the `BR` is converted to `BLR`.
These instructions require different BTI landing pads at their targets.
As the targets of indirect tailcalls are unknown, inlining such blocks
is unsound for BTI: they should be skipped instead.
Commit: 39f5ff056bc459c7db4d01c348fe78925da8c558
https://github.com/llvm/llvm-project/commit/39f5ff056bc459c7db4d01c348fe78925da8c558
Author: Vitalii Shutov <vitalii.shutov at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/Transforms/Passes.td
M mlir/lib/Dialect/Tosa/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Tosa/Transforms/TosaArithConstantToConst.cpp
A mlir/test/Dialect/Tosa/tosa-arith-const-to-tosa-const.mlir
Log Message:
-----------
[mlir][tosa] Introduce arith.constant -> tosa.const normalization pass (#168370)
Add a standalone pass that rewrites tensor-valued `arith.constant` ops
into `tosa.const`, normalize the TOSA backend contract.
Signed-off-by: Vitalii Shutov <vitalii.shutov at arm.com>
Co-authored-by: Shubham <shubham at arm.com>
Commit: fb94261d88eb679ba227281ccae88165172a68cb
https://github.com/llvm/llvm-project/commit/fb94261d88eb679ba227281ccae88165172a68cb
Author: Shreeyash Pandey <shreeyash335 at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/include/sys/syscall.h.def
Log Message:
-----------
[libc][darwin] add syscall numbers from macos sdk (#166354)
This PR adds support to include syscall.h from MacOS sdk by explicitly including the path to the sdk via `xcrun`.
Commit: 58fa7e4ccd533e5547868a9211d4da16bc80ac20
https://github.com/llvm/llvm-project/commit/58fa7e4ccd533e5547868a9211d4da16bc80ac20
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/test/OpenMP/cancel_codegen.cpp
M clang/test/OpenMP/critical_codegen.cpp
M clang/test/OpenMP/critical_codegen_attr.cpp
M clang/test/OpenMP/irbuilder_nested_parallel_for.c
M clang/test/OpenMP/masked_codegen.cpp
M clang/test/OpenMP/master_codegen.cpp
M clang/test/OpenMP/nested_loop_codegen.cpp
M clang/test/OpenMP/ordered_codegen.cpp
M clang/test/OpenMP/parallel_codegen.cpp
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/test/Transforms/OpenMP/parallel_region_merging.ll
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-barrier-cancel.mlir
M mlir/test/Target/LLVMIR/openmp-cancel.mlir
M mlir/test/Target/LLVMIR/openmp-cancellation-point.mlir
M mlir/test/Target/LLVMIR/openmp-outline-infinite-loop.mlir
M mlir/test/Target/LLVMIR/openmp-parallel-reduction-multiblock.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-array-sections.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-init-arg.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-sections.mlir
Log Message:
-----------
Revert "[OMPIRBuilder] always leave PARALLEL via the same barrier" (#169829)
Reverts llvm/llvm-project#164586
Reverting due to buildbot failure:
https://lab.llvm.org/buildbot/#/builders/169/builds/17519
Commit: 620f1f1efb45bf918db494f6779ed1f46d2da456
https://github.com/llvm/llvm-project/commit/620f1f1efb45bf918db494f6779ed1f46d2da456
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
Log Message:
-----------
[AMDGPU] Remove odd syntax in some RUN lines. NFC. (#169831)
Commit: e3a28c060dc99cc41952d56445e1e4c26ddae685
https://github.com/llvm/llvm-project/commit/e3a28c060dc99cc41952d56445e1e4c26ddae685
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M flang-rt/lib/cuda/allocator.cpp
M flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
M flang/include/flang/Runtime/CUDA/allocator.h
Log Message:
-----------
[flang][cuda][NFC] Fix naming of CUFGetAssociatedStream (#169838)
Commit: a1ca69098d6c02c5d7f5a54f84a54636522b38be
https://github.com/llvm/llvm-project/commit/a1ca69098d6c02c5d7f5a54f84a54636522b38be
Author: Philip Ginsbach-Chen <philip.ginsbach at cantab.net>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64PerfectShuffle.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/insert-subvector.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
Log Message:
-----------
[AArch64] recognise zip1/zip2 with flipped operands (#167235)
Currently, the following two snippets get treated very differently from
each other (https://godbolt.org/z/rYGj9TGz6):
```LLVM
define <8 x i8> @foo(<8 x i8> %x, <8 x i8> %y) local_unnamed_addr #0 {
entry:
%0 = shufflevector <8 x i8> %x, <8 x i8> %y, <8 x i32>
<i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
ret <8 x i8> %0
}
define <8 x i8> @bar(<8 x i8> %x, <8 x i8> %y) local_unnamed_addr #0 {
entry:
%0 = shufflevector <8 x i8> %x, <8 x i8> %y, <8 x i32>
<i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3>
ret <8 x i8> %0
}
```
```
foo: // @foo
zip1 v0.8b, v0.8b, v1.8b
ret
.LCPI1_0:
.byte 8 // 0x8
.byte 0 // 0x0
.byte 9 // 0x9
.byte 1 // 0x1
.byte 10 // 0xa
.byte 2 // 0x2
.byte 11 // 0xb
.byte 3 // 0x3
bar: // @bar
adrp x8, .LCPI1_0
mov v0.d[1], v1.d[0]
ldr d1, [x8, :lo12:.LCPI1_0]
tbl v0.8b, { v0.16b }, v1.8b
ret
```
The reason is that `isZIPMask` does not recognise the pattern when the
operands are flipped.
This PR fixes `isZIPMask` so that both `foo` and `bar` get compiled as
expected:
```
foo: // @foo
zip1 v0.8b, v0.8b, v1.8b
ret
bar: // @bar
zip1 v0.8b, v1.8b, v0.8b
ret
```
I intend to open a similar follow-up PR for `isTRNMask`, which seems to
have the same problem.
I noticed this while working on
https://github.com/llvm/llvm-project/issues/137447, though the change
does not on itself fix that issue.
Commit: 8397945f6d1406bc659f1ee10575f42a8c1846b6
https://github.com/llvm/llvm-project/commit/8397945f6d1406bc659f1ee10575f42a8c1846b6
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
Log Message:
-----------
[clang][CIR] Fix build after builtins removal. NFC
Commit: 75e4438b57eb7ac2e1cdd1bcba3368bddd81d0c4
https://github.com/llvm/llvm-project/commit/75e4438b57eb7ac2e1cdd1bcba3368bddd81d0c4
Author: Thurston Dang <thurston at google.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/CodeGen/SanitizerHandler.h
M clang/test/DebugInfo/Generic/ubsan-trap-reason-type-mismatch.c
Log Message:
-----------
[ubsan] Change "Type mismatch in operation" trap reason to "Alignment, null, or object-size error" (#169752)
I originally proposed this rewording when trap reasons were introduced
in
https://github.com/llvm/llvm-project/pull/145967#discussion_r2196212344.
This was not adopted because there was a counter-proposal to split the
enum; however, that work appears to have stalled
(https://github.com/llvm/llvm-project/pull/151243). In the meantime,
there has been an additional datapoint that the current wording is
confusing to users. Thus, let's reword it now to prevent further
confusion.
Commit: db85babddd9e96e862ba09df6d25dfac1d15fb31
https://github.com/llvm/llvm-project/commit/db85babddd9e96e862ba09df6d25dfac1d15fb31
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[VPlan] Use m_Intrinsic to match assumes/noalias_scope_decl (NFC).
Use pattern matching to check for intrinsics to slightly simplify code.
Commit: 03c86242929c1b05f417aa5ddd016b7664e22d4e
https://github.com/llvm/llvm-project/commit/03c86242929c1b05f417aa5ddd016b7664e22d4e
Author: Ingo Müller <ingomueller at google.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
[clang:ast] Avoid warning for unused var without assertions. (NFC) (#169822)
This PR avoids a compiler warning, which turns into an error with
`-Werror`, for a variable introduced in #169276 and only used in an
assertion (which is, thus, unused if compiled without assertions).
Signed-off-by: Ingo Müller <ingomueller at google.com>
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: fd19a20a1ac55775333c2630e53b9fdf7c8dc831
https://github.com/llvm/llvm-project/commit/fd19a20a1ac55775333c2630e53b9fdf7c8dc831
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
Log Message:
-----------
Revert "[ShrinkWrap] Modify shrink wrapping to accommodate functions terminated by no-return blocks" (#169852)
Reverts llvm/llvm-project#167548
As commented at
https://github.com/llvm/llvm-project/pull/167548#issuecomment-3587008602
this is causing miscompiles in two-stage RISC-V Clang/LLVM builds that
result in test failures on the builders.
Commit: 1b7ae0b673638062fc99a6605df6212b6d35eb06
https://github.com/llvm/llvm-project/commit/1b7ae0b673638062fc99a6605df6212b6d35eb06
Author: clf <53817093+clingfei at users.noreply.github.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/aarch64-isel-umin.ll
M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
Log Message:
-----------
[AArch64] Use umin for x != 0 when +cssc is enabled (#169159)
Closes https://github.com/llvm/llvm-project/issues/161584
Commit: ee45ba2ff49db3cc5d31f2600a3e7fad81d70cb1
https://github.com/llvm/llvm-project/commit/ee45ba2ff49db3cc5d31f2600a3e7fad81d70cb1
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/fixed-length-bf16-arith.ll
M llvm/test/CodeGen/AArch64/sve-indexed-arithmetic.ll
Log Message:
-----------
[AArch64] Use SVE for fixed-length bf16 operations with +sve-b16b16 (#169329)
This can avoid the promotion bf16 -> f32 -> bf16 round trip (or costly
expansions).
Commit: 965c3d760de35753d97d41c6b69582cecff8819d
https://github.com/llvm/llvm-project/commit/965c3d760de35753d97d41c6b69582cecff8819d
Author: Lukas Döllerer <contact at lukas-doellerer.de>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
A lld/test/wasm/wrap_import.s
M lld/wasm/Driver.cpp
M lld/wasm/SyntheticSections.cpp
Log Message:
-----------
[lld][WebAssembly] Fix SEGFAULT when importing wrapped symbol (#169656)
When wrapping a symbol `foo` via `-wrap=foo`, we create the symbol
`__wrap_foo` that replaces all mentions of `foo`. This feature was
implemented for wasm-ld in commit a5ca34e.
So far, no valid signature has been attached to the undefined symbol,
leading to a nullptr dereference in the logic for creating the import
section. This change adds the correct signature to the wrapped symbol,
enabling the generation of an import for it.
Commit: a1f30c24ea2cf7d3acdd0f6eed19f737ae26b0d2
https://github.com/llvm/llvm-project/commit/a1f30c24ea2cf7d3acdd0f6eed19f737ae26b0d2
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/test/CodeGen/DirectX/CBufferAccess/gep-ce-two-uses.ll
Log Message:
-----------
[NFC] [DirectX] Update DirectX codegen test `CBufferAccess/gep-ce-two-uses.ll` due to changes to ReplaceConstant (#169848)
Fixes an LLVM DirectX codegen test after it broke due to #169141
The CBuffer loads and GEPs are no longer duplicated when there are two
or more accesses within the same basic block.
This PR removes the duplicate check for CBuffer load and GEP from the
original test function `@f` and adds a new test function `@g` which
places duplicate CBuffer loads into separate basic blocks.
Commit: d39f5243f8df23392e1c493f7d607cd0074222b9
https://github.com/llvm/llvm-project/commit/d39f5243f8df23392e1c493f7d607cd0074222b9
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
M llvm/test/MC/PowerPC/ppc64-errors.s
Log Message:
-----------
[PowerPC] Implement paddis (#161572)
Commit: ad605bdad7bb36bc74b9fa5f8b3786081dac4ec6
https://github.com/llvm/llvm-project/commit/ad605bdad7bb36bc74b9fa5f8b3786081dac4ec6
Author: Alexey Moksyakov <moksyakov.alexey at huawei.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Passes/Instrumentation.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/runtime/instr.cpp
M bolt/runtime/sys_aarch64.h
M bolt/test/runtime/AArch64/instrumentation-ind-call.c
Log Message:
-----------
[bolt][aarch64] Change indirect call instrumentation snippet
Indirect call instrumentation snippet uses x16 register in exit
handler to go to destination target
__bolt_instr_ind_call_handler_func:
msr nzcv, x1
ldp x0, x1, [sp], llvm#16
ldr x16, [sp], llvm#16
ldp x0, x1, [sp], llvm#16
br x16 <-----
This patch adds the instrumentation snippet by calling instrumentation
runtime library through indirect call instruction and adding the wrapper
to store/load target value and the register for original indirect instruction.
Example:
mov x16, foo
infirectCall:
adrp x8, Label
add x8, x8, #:lo12:Label
blr x8
Before:
Instrumented indirect call:
stp x0, x1, [sp, #-16]!
mov x0, x8
movk x1, #0x0, lsl llvm#48
movk x1, #0x0, lsl llvm#32
movk x1, #0x0, lsl llvm#16
movk x1, #0x0
stp x0, x1, [sp, #-16]!
adrp x0, __bolt_instr_ind_call_handler_func
add x0, x0, #:lo12:__bolt_instr_ind_call_handler_func
blr x0
__bolt_instr_ind_call_handler: (exit snippet)
msr nzcv, x1
ldp x0, x1, [sp], llvm#16
ldr x16, [sp], llvm#16
ldp x0, x1, [sp], llvm#16
br x16 <- overwrites the original value in X16
__bolt_instr_ind_call_handler_func: (entry snippet)
stp x0, x1, [sp, #-16]!
mrs x1, nzcv
adrp x0, __bolt_instr_ind_call_handler
add x0, x0, x0, #:lo12:__bolt_instr_ind_call_handler
ldr x0, [x0]
cmp x0, #0x0
b.eq __bolt_instr_ind_call_handler
str x30, [sp, #-16]!
blr x0 <--- runtime lib store/load all regs
ldr x30, [sp], llvm#16
b __bolt_instr_ind_call_handler
_________________________________________________________________________
After:
mov x16, foo
infirectCall:
adrp x8, Label
add x8, x8, #:lo12:Label
blr x8
Instrumented indirect call:
stp x0, x1, [sp, #-16]!
mov x0, x8
movk x1, #0x0, lsl llvm#48
movk x1, #0x0, lsl llvm#32
movk x1, #0x0, lsl llvm#16
movk x1, #0x0
stp x0, x30, [sp, #-16]!
adrp x8, __bolt_instr_ind_call_handler_func
add x8, x8, #:lo12:__bolt_instr_ind_call_handler_func
blr x8 <--- call trampoline instr lib
ldp x0, x30, [sp], llvm#16
mov x8, x0 <---- restore original target
ldp x0, x1, [sp], llvm#16
blr x8 <--- original indirect call instruction
// don't touch regs besides x0, x1
__bolt_instr_ind_call_handler: (exit snippet)
ret <---- return to original function with indirect call
__bolt_instr_ind_call_handler_func: (entry snippet)
adrp x0, __bolt_instr_ind_call_handler
add x0, x0, #:lo12:__bolt_instr_ind_call_handler
ldr x0, [x0]
cmp x0, #0x0
b.eq __bolt_instr_ind_call_handler
str x30, [sp, #-16]!
blr x0 <--- runtime lib store/load all regs
ldr x30, [sp], llvm#16
b __bolt_instr_ind_call_handler
Commit: 2e655c23deec6076f0198fafbe5c2b1deb6d5b98
https://github.com/llvm/llvm-project/commit/2e655c23deec6076f0198fafbe5c2b1deb6d5b98
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
A clang/test/CIR/IR/try-call.cir
Log Message:
-----------
[CIR] Upstream TryCallOp (#165303)
Upstream TryCall Op as a prerequisite for Try Catch work
Issue https://github.com/llvm/llvm-project/issues/154992
Commit: 8f36135aea5dfbb5f090ca9ad055094c9913f735
https://github.com/llvm/llvm-project/commit/8f36135aea5dfbb5f090ca9ad055094c9913f735
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
Log Message:
-----------
[VPlan] Add m_Intrinsic matcher that takes a variable intrinsic ID (NFC)
Add a variant of m_Intrinsic that matches a variable runtime ID.
Commit: 07d14cb6d3e0319b4f95bfaca1502c4a8dc02910
https://github.com/llvm/llvm-project/commit/07d14cb6d3e0319b4f95bfaca1502c4a8dc02910
Author: owenca <owenpiano at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Format/UnwrappedLineParser.h
Log Message:
-----------
[clang-format][NFC] Remove the parameter of parseRequires...() (#169773)
Commit: 8459508227dd30ce32f870fbc9109fe95d51f4db
https://github.com/llvm/llvm-project/commit/8459508227dd30ce32f870fbc9109fe95d51f4db
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
Log Message:
-----------
[VPlan] Handle scalar VPWidenPointerInd in convertToConcreteRecipes. (#169338)
In some case, VPWidenPointerInductions become only used by scalars after
legalizeAndOptimizationInducftions was already run, for example due to
some VPlan optimizations.
Move the code to scalarize VPWidenPointerInductions to a helper and use
it if needed.
This fixes a crash after #148274 in the added test case.
Fixes https://github.com/llvm/llvm-project/issues/169780
Commit: 06c8ee61ab80305be88380e6aa2f1b2fe32f859d
https://github.com/llvm/llvm-project/commit/06c8ee61ab80305be88380e6aa2f1b2fe32f859d
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/test/CodeGen/DirectX/CBufferAccess/gep-ce-two-uses.ll
Log Message:
-----------
[NFC] [DirectX] Make DirectX codegen test `CBufferAccess/gep-ce-two-uses.ll` more strict (#169855)
Continuation of PR #169848 to address PR comments.
This PR makes the test more strict by adding CHECKs to ensure the loads
are indeed using the same or different GEPs.
Commit: 583fba35247d8ffc87e0df9f9eb49ab02ea3bb8e
https://github.com/llvm/llvm-project/commit/583fba35247d8ffc87e0df9f9eb49ab02ea3bb8e
Author: actink <actink at 163.com>
Date: 2025-11-28 (Fri, 28 Nov 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp-select.ll
Log Message:
-----------
[InstCombine] fold icmp of select with invertible shl (#147182)
Proof: https://alive2.llvm.org/ce/z/a5fzlJ
Closes https://github.com/llvm/llvm-project/issues/146642
---------
Co-authored-by: Yingwei Zheng <dtcxzyw at qq.com>
Commit: 56c1063a59124f2024c8a2d1e45b8e1fe1b80772
https://github.com/llvm/llvm-project/commit/56c1063a59124f2024c8a2d1e45b8e1fe1b80772
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2025-11-28 (Fri, 28 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Passes/Inliner.cpp
M bolt/lib/Passes/Instrumentation.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/runtime/instr.cpp
M bolt/runtime/sys_aarch64.h
A bolt/test/AArch64/inline-bti.s
M bolt/test/runtime/AArch64/instrumentation-ind-call.c
M clang/docs/ClangStaticAnalyzer.rst
M clang/docs/HIPSupport.rst
M clang/docs/analyzer/user-docs.rst
M clang/docs/analyzer/user-docs/CommandLineUsage.rst
M clang/docs/analyzer/user-docs/Installation.rst
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/SanitizerHandler.h
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Format/UnwrappedLineParser.h
M clang/lib/Headers/avx10_2_512bf16intrin.h
M clang/lib/Headers/avx10_2bf16intrin.h
M clang/lib/Headers/avx2intrin.h
M clang/lib/Headers/avx512bf16intrin.h
M clang/lib/Headers/avx512bwintrin.h
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avx512vbmiintrin.h
M clang/lib/Headers/avx512vbmivlintrin.h
M clang/lib/Headers/avx512vlbf16intrin.h
M clang/lib/Headers/avx512vlfp16intrin.h
M clang/lib/Headers/avx512vlintrin.h
M clang/lib/Headers/avxintrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/mmintrin.h
M clang/lib/Headers/xmmintrin.h
M clang/test/AST/ByteCode/invalid.cpp
A clang/test/CIR/IR/try-call.cir
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/avx512bf16-builtins.c
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vbmi-builtins.c
M clang/test/CodeGen/X86/avx512vbmivl-builtin.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/X86/avx512vlbf16-builtins.c
M clang/test/CodeGen/X86/f16c-builtins.c
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse-builtins-constrained.c
M clang/test/CodeGen/X86/sse-builtins.c
M clang/test/CodeGen/X86/sse2-builtins-constrained.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/builtins-x86.c
A clang/test/CodeGenCUDA/cuda_weak_alias.cu
A clang/test/CodeGenHIP/hip_weak_alias.cpp
M clang/test/DebugInfo/Generic/ubsan-trap-reason-type-mismatch.c
A clang/test/OpenMP/amdgcn_weak_alias.c
A clang/test/OpenMP/amdgcn_weak_alias.cpp
A clang/test/OpenMP/nvptx_weak_alias.c
M clang/test/SemaHIP/amdgpu-gfx950-load-to-lds.hip
M compiler-rt/lib/builtins/cpu_model/x86.c
M flang-rt/lib/cuda/allocator.cpp
M flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
M flang/docs/OpenMPSupport.md
M flang/include/flang/Runtime/CUDA/allocator.h
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/include/sys/syscall.h.def
M libcxx/include/__algorithm/copy_n.h
M libcxx/include/__algorithm/iterator_operations.h
M libcxx/include/__algorithm/ranges_copy_n.h
M libcxx/include/__flat_set/flat_set.h
M libcxx/include/__vector/vector.h
M libcxx/include/deque
M libcxx/test/libcxx-03/algorithms/half_positive.pass.cpp
M libcxx/test/libcxx-03/algorithms/robust_against_copying_comparators.pass.cpp
M libcxx/test/libcxx-03/algorithms/robust_against_cpp20_hostile_iterators.compile.pass.cpp
M libcxx/test/libcxx-03/containers/sequences/vector/asan.pass.cpp
M libcxx/test/libcxx-03/containers/sequences/vector/asan_throw.pass.cpp
M libcxx/test/libcxx-03/depr/depr.default.allocator/allocator.members/construct.cxx20.pass.cpp
M libcxx/test/libcxx-03/input.output/string.streams/stringbuf/const_sso_buffer.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/arithmetic.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/comparison.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/pointer_traits.pass.cpp
M libcxx/test/libcxx-03/iterators/bounded_iter/types.compile.pass.cpp
M libcxx/test/libcxx-03/iterators/contiguous_iterators.conv.compile.pass.cpp
M libcxx/test/libcxx-03/iterators/contiguous_iterators.pass.cpp
M libcxx/test/libcxx-03/iterators/predef.iterators/insert.iterators/back.insert.iter.ops/get_container.pass.cpp
M libcxx/test/libcxx-03/iterators/unwrap_iter.pass.cpp
M libcxx/test/libcxx-03/language.support/support.dynamic/libcpp_deallocate.sh.cpp
M libcxx/test/libcxx-03/libcpp_alignof.pass.cpp
M libcxx/test/libcxx-03/memory/allocation_guard.pass.cpp
M libcxx/test/libcxx-03/memory/swap_allocator.pass.cpp
M libcxx/test/libcxx-03/numerics/bit.ops.pass.cpp
M libcxx/test/libcxx-03/strings/basic.string/string.capacity/max_size.pass.cpp
M libcxx/test/libcxx-03/strings/basic.string/string.cons/copy_shrunk_long.pass.cpp
M libcxx/test/libcxx-03/strings/c.strings/constexpr_memmove.pass.cpp
M libcxx/test/libcxx-03/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/bullet_1_2_3.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/bullet_4_5_6.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/bullet_7.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/invoke.pass.cpp
M libcxx/test/libcxx-03/utilities/function.objects/func.require/invoke_helpers.h
M libcxx/test/libcxx-03/utilities/is_pointer_in_range.pass.cpp
M libcxx/test/libcxx-03/utilities/is_valid_range.pass.cpp
M libcxx/test/libcxx-03/utilities/memory/pointer.conversion/to_address.pass.cpp
M libcxx/test/libcxx-03/utilities/memory/pointer.conversion/to_address_std_iterators.pass.cpp
M libcxx/test/libcxx-03/utilities/meta/is_referenceable.compile.pass.cpp
M libcxx/test/libcxx-03/utilities/no_destroy.pass.cpp
M libcxx/test/libcxx-03/utilities/utility/pairs/pairs.pair/abi.non_trivial_copy_move.pass.cpp
M libcxx/test/libcxx-03/utilities/utility/pairs/pairs.pair/abi.trivial_copy_move.pass.cpp
M libcxx/test/libcxx-03/utilities/utility/pairs/pairs.pair/abi.trivially_copyable.compile.pass.cpp
M libcxx/test/libcxx/diagnostics/deque.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/flat_map.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/flat_set.nodiscard.verify.cpp
A lld/test/wasm/wrap_import.s
M lld/wasm/Driver.cpp
M lld/wasm/SyntheticSections.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
M llvm/include/llvm/Analysis/Delinearization.h
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/Target/Target.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/lib/Analysis/Delinearization.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64PerfectShuffle.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.h
M llvm/lib/Target/ARM/ARMMCInstLower.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/Analysis/Delinearization/a.ll
M llvm/test/Analysis/Delinearization/constant_functions_multi_dim.ll
M llvm/test/Analysis/Delinearization/divide_by_one.ll
M llvm/test/Analysis/Delinearization/fixed_size_array.ll
M llvm/test/Analysis/Delinearization/himeno_1.ll
M llvm/test/Analysis/Delinearization/himeno_2.ll
M llvm/test/Analysis/Delinearization/iv_times_constant_in_subscript.ll
M llvm/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_3d.ll
M llvm/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_nts_3d.ll
M llvm/test/Analysis/Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll
M llvm/test/Analysis/Delinearization/multidim_only_ivs_2d.ll
M llvm/test/Analysis/Delinearization/multidim_only_ivs_3d.ll
M llvm/test/Analysis/Delinearization/multidim_only_ivs_3d_cast.ll
M llvm/test/Analysis/Delinearization/multidim_two_accesses_different_delinearization.ll
M llvm/test/Analysis/Delinearization/parameter_addrec_product.ll
M llvm/test/Analysis/Delinearization/terms_with_identity_factor.ll
A llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll
A llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll.bc
A llvm/test/CodeGen/AArch64/aarch64-isel-umin.ll
M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
A llvm/test/CodeGen/AArch64/fixed-length-bf16-arith.ll
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/insert-subvector.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-indexed-arithmetic.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
M llvm/test/CodeGen/DirectX/CBufferAccess/gep-ce-two-uses.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/disabled-on-amd.ll
A llvm/test/CodeGen/SystemZ/zos-target-flags.ll
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir
A llvm/test/CodeGen/X86/haddsubsat.ll
M llvm/test/CodeGen/X86/srem-vector-lkk.ll
M llvm/test/CodeGen/X86/urem-vector-lkk.ll
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
M llvm/test/MC/PowerPC/ppc64-errors.s
A llvm/test/Transforms/AggressiveInstCombine/umulh_carry.ll
A llvm/test/Transforms/AggressiveInstCombine/umulh_carry4.ll
A llvm/test/Transforms/AggressiveInstCombine/umulh_ladder.ll
A llvm/test/Transforms/AggressiveInstCombine/umulh_ladder4.ll
A llvm/test/Transforms/InstCombine/get_vector_length.ll
M llvm/test/Transforms/InstCombine/icmp-select.ll
M llvm/test/Transforms/LoopUnroll/partial-unroll-reductions.ll
M llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/darwin.ll
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/emscripten.ll
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/xcore.ll
M llvm/utils/TableGen/Basic/VTEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/README.md
M mlir/docs/Dialects/NVVMDialect.md
M mlir/include/mlir/Dialect/Tosa/Transforms/Passes.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SCF/Transforms/UpliftWhileToFor.cpp
M mlir/lib/Dialect/Tosa/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Tosa/Transforms/TosaArithConstantToConst.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir
M mlir/test/Dialect/SCF/uplift-while.mlir
A mlir/test/Dialect/Tosa/tosa-arith-const-to-tosa-const.mlir
M mlir/test/Target/LLVMIR/Import/metadata-profiling.ll
A mlir/test/Target/LLVMIR/openmp-dist_schedule.mlir
A mlir/test/Target/LLVMIR/openmp-dist_schedule_with_wsloop.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/ylzsx/rotr-custom
Compare: https://github.com/llvm/llvm-project/compare/aa61f21602a9...56c1063a5912
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