[all-commits] [llvm/llvm-project] c6f433: [bazel][libc] Remove target compatibility restrict...
Peter Collingbourne via All-commits
all-commits at lists.llvm.org
Wed Nov 26 12:37:20 PST 2025
Branch: refs/heads/users/pcc/spr/add-ir-and-codegen-support-for-deactivation-symbols
Home: https://github.com/llvm/llvm-project
Commit: c6f433e880a01a29325f4d7d2b98c84feecf2297
https://github.com/llvm/llvm-project/commit/c6f433e880a01a29325f4d7d2b98c84feecf2297
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel][libc] Remove target compatibility restrictions for float128 (#169292)
The restrictions here aren't nearly as much about the OS as the compiler
and architecture, but the Bazel restriction was OS-based. Everything
seems to work well on even Arm64 macOS, and I would expect most BSDs and
other OSes to work well with Clang's support on x86-64.
The source code here already handles detecting when there is compiler
support for the type. And the users of this don't `select` or do
anything else to conditionally include the header, so it seems better to
not restrict access to the header from the build system, and instead
continue making the source code compatible or a no-op on relevant
configurations.
Commit: 26362c68579dd4375198aae4651b4d5f8a36c715
https://github.com/llvm/llvm-project/commit/26362c68579dd4375198aae4651b4d5f8a36c715
Author: Petr Penzin <ppenzin at tenstorrent.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add segmented tunes to tt-ascalon-d8 (#168800)
Add TuneOptimizedNFnSegmentedLoadStore tune flags to tt-ascalon-d8
processor definition.
Commit: b1111356e697a7f5c436846f97adf18a353766dc
https://github.com/llvm/llvm-project/commit/b1111356e697a7f5c436846f97adf18a353766dc
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
Log Message:
-----------
[AMDGPU] Pre-commit test for #169213 (NFC)
Commit: 9626c90c335cca55c1a8094f2e802c4139c7173d
https://github.com/llvm/llvm-project/commit/9626c90c335cca55c1a8094f2e802c4139c7173d
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/extensions.bzl
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
M utils/bazel/third_party_build/zlib-ng.BUILD
Log Message:
-----------
[bazel] Use zlib-ng from the BCR (#169450)
This way if a downstream project also uses this, it is dedup'd
Commit: 9c2d5e29947c0ccf5eaef2c11b4533a62bad1f67
https://github.com/llvm/llvm-project/commit/9c2d5e29947c0ccf5eaef2c11b4533a62bad1f67
Author: Erik Enikeev <evonatarius at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
A llvm/test/CodeGen/Mips/fp-strict-fcmp.ll
Log Message:
-----------
[Mips] Set custom lowering for STRICT_FSETCC/STRICT_FSETCCS ops. (#168303)
Commit: 28fde68501032b292f91246c0e79872558d0e74b
https://github.com/llvm/llvm-project/commit/28fde68501032b292f91246c0e79872558d0e74b
Author: Pranav Bhandarkar <pranav.bhandarkar at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
A flang/test/Semantics/OpenMP/target-teams-nesting.f90
Log Message:
-----------
[Flang] - Enhance testing for strictly-nested teams in target regions. (#168437)
This patch enhances the semantics test for checking that teams
directives are strictly nested inside target directives.
Fixes https://github.com/llvm/llvm-project/issues/153173
Commit: 488ed96d665f47d5c31b811288ec1be1b3fa01bc
https://github.com/llvm/llvm-project/commit/488ed96d665f47d5c31b811288ec1be1b3fa01bc
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M orc-rt/unittests/SessionTest.cpp
Log Message:
-----------
[orc-rt] Remove stray debugging output. NFCI. (#169451)
Commit: c25e0d3e2942007919e5a7a0738bea86907bcdb4
https://github.com/llvm/llvm-project/commit/c25e0d3e2942007919e5a7a0738bea86907bcdb4
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/mul-simplification.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-cond-poison.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
Log Message:
-----------
[VPlan] Simplify x + 0 -> x (#169394)
Commit: 675dc35d808d94011f52e650fe1e3218254b5041
https://github.com/llvm/llvm-project/commit/675dc35d808d94011f52e650fe1e3218254b5041
Author: Mend Renovate <bot at renovateapp.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M .github/workflows/gha-codeql.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/llvm-abi-tests.yml
M .github/workflows/scorecard.yml
Log Message:
-----------
Update [Github] Update GHA Dependencies (#169257)
This PR contains the following updates:
| Package | Type | Update | Change | Pending |
|---|---|---|---|---|
| ghcr.io/llvm/ci-ubuntu-24.04-abi-tests | container | digest |
`f80125c` -> `9138b6a` | |
|
[github/codeql-action](https://redirect.github.com/github/codeql-action)
| action | patch | `v4.31.3` -> `v4.31.4` | `v4.31.5` |
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Commit: 44a7d2f22aec6ac2019a3674e1390276c2ee7ca5
https://github.com/llvm/llvm-project/commit/44a7d2f22aec6ac2019a3674e1390276c2ee7ca5
Author: David Green <david.green at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/test/CodeGen/AArch64/combine-sdiv.ll
M llvm/test/CodeGen/AArch64/rem-by-const.ll
M llvm/test/CodeGen/AArch64/srem-lkk.ll
Log Message:
-----------
[AArch64] Add patterns for add(x, trunc(shift)) (#168927)
This can be lowered to a 64bit add where we only use the bottom 32bits
of the result. It is conceptually the same as
https://alive2.llvm.org/ce/z/Xfz3Rf, but with the sext replaced by an
anyext.
Commit: 1d64fd5d42671d15ed8cd0fc31f71a4ad1e791b6
https://github.com/llvm/llvm-project/commit/1d64fd5d42671d15ed8cd0fc31f71a4ad1e791b6
Author: David Green <david.green at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Basic/arm_mve_defs.td
M clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
M clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
M clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
M clang/utils/TableGen/MveEmitter.cpp
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
A llvm/test/CodeGen/Thumb2/mve-intrinsics/strict-intrinsics.ll
M llvm/test/CodeGen/Thumb2/mve-intrinsics/vabdq.ll
M llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
Log Message:
-----------
[ARM] Introduce intrinsics for MVE add/sub/mul under strict-fp. (#169156)
As far as I understand, the MVE fp vadd/vsub/vmul instructions will set
exception flags in the same ways as scalar fadd/fsub/fmul, but will not
honor flush-to-zero (for f32 they always flush, for f16 they follows the
fpsrc flags) and will always use the default rounding mode.
This means that we cannot convert the vadd_f23/vsub_f32/vmul_f32
intrinsics to llvm.constrained.fadd/fsub/fmul and then vadd/vsub/vmul
without changing the expected behaviour under strict-fp. This patch
introduces a set in intrinsics that we can use instead, going from
vadd_f32 -> llvm.arm.mve.vadd -> MVE_VADD.
The current implementations assumes that the standard variant of a
strictfp alternative will be a IRBuilder, this can be changed to take a
IRBuilder or IRInt.
Commit: 30c49a40222a8e2f90565370ab20253c1e426383
https://github.com/llvm/llvm-project/commit/30c49a40222a8e2f90565370ab20253c1e426383
Author: Men-cotton <mencotton0410 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
A mlir/test/Target/LLVMIR/anonymous-tbaa.mlir
Log Message:
-----------
[mlir][LLVMIR] Handle anonymous TBAA roots during metadata emission (#169167)
This commit enhances MLIR's TBAA export with support for anonymous TBAA roots. The import for this was around for a bit but the export was missing.
Fixes: #160721
Commit: 5490bcf4aa3c028e5c2cdbcd0d906e5a876d23bc
https://github.com/llvm/llvm-project/commit/5490bcf4aa3c028e5c2cdbcd0d906e5a876d23bc
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
Log Message:
-----------
[BOLT] Add missing new line. NFC
Commit: f817a1b0394b7f722b4bb13e9aeead5e177ff6d7
https://github.com/llvm/llvm-project/commit/f817a1b0394b7f722b4bb13e9aeead5e177ff6d7
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Optimizer/Builder/Runtime/Reduction.cpp
M lldb/include/lldb/API/SBStructuredData.h
M mlir/include/mlir/Analysis/DataFlow/IntegerRangeAnalysis.h
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
Log Message:
-----------
[NFC] Fix typo of `integer` (#169325)
Commit: a39af125dba2c07f100236d210b6a948b7316acb
https://github.com/llvm/llvm-project/commit/a39af125dba2c07f100236d210b6a948b7316acb
Author: Dharuni R Acharya <125176188+DharuniRAcharya at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
M llvm/lib/IR/CMakeLists.txt
A llvm/lib/IR/NVVMIntrinsicUtils.cpp
Log Message:
-----------
[NVVM] Move pretty-print functions from NVVMIntrinsicUtils.h to cpp file (#168997)
This patch moves the print functions from `NVVMIntrinsicUtils.h` to
`NVVMIntrinsicUtils.cpp`, a file created in the `llvm/lib/IR` directory.
Signed-off-by: Dharuni R Acharya <dharunira at nvidia.com>
Commit: 6193f2aeda1d5ca30cf990e28956824eefdc97f1
https://github.com/llvm/llvm-project/commit/6193f2aeda1d5ca30cf990e28956824eefdc97f1
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
Log Message:
-----------
[AArch64] Assert `expandMOVImm` prioritizes optimal single MOVZ/N (#169341)
The expansion of move immediate in `expandMOVImm` follows the priority
of the `MOV` alias. In addition, the selection there properly prefers
expansion based on perf optimality order. This change adds a simple
assert that `expandMOVImmSimple` expands a single optimal MOVZ/MOVK.
Commit: ed95c4d6ecf0a8e842cb9d91c09d9679c1f3bf79
https://github.com/llvm/llvm-project/commit/ed95c4d6ecf0a8e842cb9d91c09d9679c1f3bf79
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
Log Message:
-----------
[BOLT][BTI] Add MCPlusBuilder::createBTI (#167305)
- creates a BTI j|c landing pad MCInst.
- create getBTIHintNum utility in AArch64/Utils, to make sure BOLT
generates BTI immediates the same way as LLVM.
- add MCPlusBuilder unittests to cover new function.
Commit: 2ce363d25226c2d502d19917ca8502115c953599
https://github.com/llvm/llvm-project/commit/2ce363d25226c2d502d19917ca8502115c953599
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
Log Message:
-----------
[gn build] Port a39af125dba2
Commit: eb568d6d0ce1a2b0f26f47e20b0051842a3f9746
https://github.com/llvm/llvm-project/commit/eb568d6d0ce1a2b0f26f47e20b0051842a3f9746
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
M llvm/test/CodeGen/AArch64/sme-zt0-state.ll
Log Message:
-----------
[AArch64][SME] Handle zeroing ZA and ZT0 in functions with ZT0 state (#166361)
In the MachineSMEABIPass, if we have a function with ZT0 state, then
there are some additional cases where we need to zero ZA and ZT0.
If the function has a private ZA interface, i.e., new ZT0 (and new ZA if
present). Then ZT0/ZA must be zeroed when committing the incoming ZA
save.
If the function has a shared ZA interface, e.g. new ZA and shared ZT0.
Then ZA must be zeroed on function entry (without a ZA save commit).
The logic in the ABI pass has been reworked to use an "ENTRY" state to
handle this (rather than the more specific "CALLER_DORMANT" state).
Commit: a086fb2fbbc0f488dd2a2c60d09196ea7218742f
https://github.com/llvm/llvm-project/commit/a086fb2fbbc0f488dd2a2c60d09196ea7218742f
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
A llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/spillv16.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.mir
Log Message:
-----------
[AMDGPU][gfx1250] Add wait_xcnt before any access that cannot be repeated (#168852)
The xcnt wait is actually required before any memory access that can
only be done once, so atomic stores and volatile accesses are affected.
This patch also ensures buffer instructions are handled.
Commit: cf5234bac45567e2431b9e668999d4f6d65b7ac8
https://github.com/llvm/llvm-project/commit/cf5234bac45567e2431b9e668999d4f6d65b7ac8
Author: Jie Fu <jiefu at tencent.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
Log Message:
-----------
[AArch64] Silence a warning (NFC)
/llvm-project/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp:952:12:
error: unused variable 'SMEFnAttrs' [-Werror,-Wunused-variable]
SMEAttrs SMEFnAttrs = AFI->getSMEFnAttrs();
^
1 error generated.
Commit: a11e7347fb9618b981cde12f494f58d55b509e2c
https://github.com/llvm/llvm-project/commit/a11e7347fb9618b981cde12f494f58d55b509e2c
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M .gitignore
Log Message:
-----------
[llvm][nfc] Ignore OpenAI Codex artifacts (#162481)
Follow-up to #153853 to also ignore Codex artifacts [1]. AGENTS.md may
be at the root or in sub-directories, so unlike other Markdown config
files I've not prefixed it with '/'.
[1] https://github.com/openai/codex/blob/main/docs/getting-started.md#memory-with-agentsmd
Commit: 86fbaef99a53c5a0d3d5b96011797215296ec478
https://github.com/llvm/llvm-project/commit/86fbaef99a53c5a0d3d5b96011797215296ec478
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
A cmake/Modules/GetToolchainDirs.cmake
M flang-rt/CMakeLists.txt
M flang-rt/cmake/modules/AddFlangRT.cmake
M flang-rt/cmake/modules/AddFlangRTOffload.cmake
A flang-rt/cmake/modules/FlangRTIntrospection.cmake
R flang-rt/cmake/modules/GetToolchainDirs.cmake
M flang-rt/lib/runtime/CMakeLists.txt
A flang-rt/lib/runtime/__cuda_builtins.f90
A flang-rt/lib/runtime/__cuda_device.f90
A flang-rt/lib/runtime/__fortran_builtins.f90
A flang-rt/lib/runtime/__fortran_ieee_exceptions.f90
A flang-rt/lib/runtime/__fortran_type_info.f90
A flang-rt/lib/runtime/__ppc_intrinsics.f90
A flang-rt/lib/runtime/__ppc_types.f90
A flang-rt/lib/runtime/cooperative_groups.f90
A flang-rt/lib/runtime/cudadevice.f90
A flang-rt/lib/runtime/ieee_arithmetic.f90
A flang-rt/lib/runtime/ieee_exceptions.f90
A flang-rt/lib/runtime/ieee_features.f90
A flang-rt/lib/runtime/iso_c_binding.f90
A flang-rt/lib/runtime/iso_fortran_env.f90
A flang-rt/lib/runtime/iso_fortran_env_impl.f90
A flang-rt/lib/runtime/mma.f90
M flang-rt/test/lit.site.cfg.py.in
M flang-rt/unittests/CMakeLists.txt
M flang/CMakeLists.txt
M flang/include/flang/Frontend/CompilerInvocation.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Semantics/semantics.cpp
R flang/module/.clang-format
R flang/module/__cuda_builtins.f90
R flang/module/__cuda_device.f90
R flang/module/__fortran_builtins.f90
R flang/module/__fortran_ieee_exceptions.f90
R flang/module/__fortran_type_info.f90
R flang/module/__ppc_intrinsics.f90
R flang/module/__ppc_types.f90
R flang/module/cooperative_groups.f90
R flang/module/cudadevice.f90
R flang/module/ieee_arithmetic.f90
R flang/module/ieee_exceptions.f90
R flang/module/ieee_features.f90
R flang/module/iso_c_binding.f90
R flang/module/iso_fortran_env.f90
R flang/module/iso_fortran_env_impl.f90
R flang/module/mma.f90
M flang/test/CMakeLists.txt
M flang/test/Driver/Inputs/ieee_arithmetic.mod
M flang/test/Driver/Inputs/iso_fortran_env.mod
A flang/test/Driver/intrinsic-module-path.F90
R flang/test/Driver/intrinsic-module-path.f90
M flang/test/Driver/lto-fatlto.f90
M flang/test/Driver/pp-fixed-form.f90
M flang/test/Lower/HLFIR/type-bound-call-mismatch.f90
M flang/test/Lower/OpenMP/simd_aarch64.f90
M flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90
M flang/test/Preprocessing/fixed-free.f
M flang/test/Preprocessing/no-pp-if.f90
M flang/test/Semantics/bug163242.f90
M flang/test/Semantics/bug164303.f90
M flang/test/lit.cfg.py
M flang/test/lit.site.cfg.py.in
M flang/tools/CMakeLists.txt
M flang/tools/bbc/bbc.cpp
R flang/tools/f18/CMakeLists.txt
R flang/tools/f18/dump.cpp
M llvm/runtimes/CMakeLists.txt
M openmp/CMakeLists.txt
M openmp/runtime/CMakeLists.txt
R openmp/runtime/cmake/LibompCheckFortranFlag.cmake
M openmp/runtime/cmake/LibompHandleFlags.cmake
M openmp/runtime/cmake/config-ix.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/test/lit.cfg
M openmp/runtime/test/lit.site.cfg.in
M runtimes/CMakeLists.txt
Log Message:
-----------
[Flang] Move builtin .mod generation into runtimes (#137828)
Move building the .mod files from openmp/flang to openmp/flang-rt using
a shared mechanism. Motivations to do so are:
1. Most modules are target-dependent and need to be re-compiled for each
target separately, which is something the LLVM_ENABLE_RUNTIMES system
already does. Prime example is `iso_c_binding.mod` which encodes the
target's ABI. Most other modules have `#ifdef`-enclosed code as well.
2. CMake has support for Fortran that we should use. Among other things,
it automatically determines module dependencies so there is no need to
hardcode them in the CMakeLists.txt.
3. It allows using Fortran itself to implement Flang-RT. Currently, only
`iso_fortran_env_impl.f90` emits object files that are needed by Fortran
applications (#89403). The workaround of #95388 could be reverted.
Some new dependencies come into play:
* openmp depends on flang-rt for building `lib_omp.mod` and
`lib_omp_kinds.mod`. Currently, if flang-rt is not found then the
modules are not built.
* check-flang depends on flang-rt: If not found, the majority of tests
are disabled. If not building in a bootstrpping build, the location of
the module files can be pointed to using
`-DFLANG_INTRINSIC_MODULES_DIR=<path>`, e.g. in a flang-standalone
build. Alternatively, the test needing any of the intrinsic modules
could be marked with `REQUIRES: flangrt-modules`.
* check-flang depends on openmp: Not a change; tests requiring
`lib_omp.mod` and `lib_omp_kinds.mod` those are already marked with
`openmp_runtime`.
As intrinsic are now specific to the target, their location is moved
from `include/flang` to `<resource-dir>/finclude/flang/<triple>`. The
mechnism to compute the location have been moved from flang-rt
(previously used to compute the location of `libflang_rt.*.a`) to common
locations in `cmake/GetToolchainDirs.cmake` and
`runtimes/CMakeLists.txt` so they can be used by both, openmp and
flang-rt. Potentially the mechnism could also be shared by other
libraries such as compiler-rt.
`finclude` was chosen because `gfortran` uses it as well and avoids
misuse such as `#include <flang/iso_c_binding.mod>`. The search location
is now determined by `ToolChain` in the driver, instead of by the
frontend. Now the driver adds `-fintrinsic-module-path` for that
location to the frontend call (Just like gfortran does).
`-fintrinsic-module-path` had to be fixed for this because ironically it
was only added to `searchDirectories`, but not
`intrinsicModuleDirectories_`. Since the driver determines the location,
tests invoking `flang -fc1` and `bbc` must also be passed the location
by llvm-lit. This works like llvm-lit does for finding the include dirs
for Clang using `-print-file-name=...`.
Commit: f287abd53e03bf0fda9099c0845b25a340a20102
https://github.com/llvm/llvm-project/commit/f287abd53e03bf0fda9099c0845b25a340a20102
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bitcnt-big-integer.ll
M llvm/test/TableGen/CPtrWildcard.td
Log Message:
-----------
[DAG][X86] Improve custom i256/i512 AVX512 CTLZ/CTTZ Handling with MVT::i256/i512 (#168860)
This patch proposes to move the AVX512 CTLZ/CTTZ i256/i512 codegen to
ReplaceNodeResults to allow them to be declared as custom lowering -
this allows expansion of larger int types (e.g. i1024) to fallback to
them during their expansion.
However to declare these i256/i512 ops as custom, we need to add
MVT::i256/i512 simple types - I'm intending to add further large integer
handling in the future, some of which will use vector register
instructions, and its going to be much easier if this can be handled
with i128/i256/i512 types that match the vector register sizes.
This exposed a regression in NVPTX due to their use of EVT::isSimple()
to match their upper integer size bounds.
Commit: 5e7631e14ae334a708b6fc52991a12ab3bb95633
https://github.com/llvm/llvm-project/commit/5e7631e14ae334a708b6fc52991a12ab3bb95633
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll
M llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll
Log Message:
-----------
[LoongArch][DAGCombiner] Combine vand (vnot ..) to vandn (#161037)
After this commit, DAGCombiner will have more opportunities to perform
vector folding. This patch includes several foldings, as follows:
- VANDN(x,NOT(y)) -> AND(NOT(x),NOT(y)) -> NOT(OR(X,Y))
- VANDN(x, SplatVector(Imm)) -> AND(NOT(x), NOT(SplatVector(~Imm)))
Commit: cb63e99e58cbbb687575f2ab3139f9ba7b6e95bf
https://github.com/llvm/llvm-project/commit/cb63e99e58cbbb687575f2ab3139f9ba7b6e95bf
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
M llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
M llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-struct-return.ll
Log Message:
-----------
[VPlan] Include flags in VectorPointerRecipe::printRecipe (#169466)
The change is non-functional with respect to emitted IR.
Commit: 4b137e7446718973e209eb97402d9d06f90b8b0d
https://github.com/llvm/llvm-project/commit/4b137e7446718973e209eb97402d9d06f90b8b0d
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
Log Message:
-----------
[lldb][NFC] Remove code dupl in favour of a named variable in UnwindAssemblyInstEmulation (#169369)
Commit: bc4143b27afaeee1fcf3e8f0024774f3adc1eef9
https://github.com/llvm/llvm-project/commit/bc4143b27afaeee1fcf3e8f0024774f3adc1eef9
Author: Ravil Dorozhinskii <ravil.aviva.com at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[DAG] SDPatternMatch - add m_SpecificFP matcher (#167438)
This patch introduces SpecificFP matcher for SelectionDAG nodes.
This includes:
Adding SpecificFP_match() in SDPatternMatch.h.
Adding test coverage in SelectionDAGPatternMatchTest.cpp.
Closes #165566
Commit: e1b08731e5d81a0483a91da5eb89b1087876b9c2
https://github.com/llvm/llvm-project/commit/e1b08731e5d81a0483a91da5eb89b1087876b9c2
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
R llvm/test/CodeGen/AArch64/pr151592.mir
R llvm/test/CodeGen/AArch64/pr151888.mir
R llvm/test/CodeGen/AArch64/pr164181-reduced.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
R llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
M llvm/test/CodeGen/PowerPC/combine-fneg.ll
M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
M llvm/test/CodeGen/PowerPC/frem.ll
M llvm/test/CodeGen/PowerPC/froundeven-legalization.ll
M llvm/test/CodeGen/PowerPC/half.ll
M llvm/test/CodeGen/PowerPC/ldexp.ll
M llvm/test/CodeGen/PowerPC/llvm.modf.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
R llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
R llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
R llvm/test/CodeGen/X86/pr76416.ll
M llvm/test/CodeGen/X86/subreg-fail.mir
R llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
Log Message:
-----------
Revert "Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG""
This reverts commit bb78728826ff57f3df859e79bfd857b5a175bb6d.
Commit: 51dd3ec13c51b0e399cbceafb84698b7241ed731
https://github.com/llvm/llvm-project/commit/51dd3ec13c51b0e399cbceafb84698b7241ed731
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[MLIR][OpenMP] Bail early in sortMapIndices if indices are the same (#169474)
If we are given the same index in the comparator callback, simply return
false. Otherwise we will end up adding invalid items to
occludedChildren, causing extra items to get removed that should not be,
resulting in failures that manifest in different forms (assertions, asan
failures, ubsan failures, etc.).
Commit: 68c2a8140f7b8a487b7a9d9a53c6568b7336ee62
https://github.com/llvm/llvm-project/commit/68c2a8140f7b8a487b7a9d9a53c6568b7336ee62
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/test/extensions/libcxx/odr_signature.exceptions.sh.cpp
M libcxx/test/extensions/libcxx/odr_signature.hardening.sh.cpp
Log Message:
-----------
[libc++][C++03] Fix ODR tests (#169349)
We don't really need to include `<__config>`. We just need to include a
public C++ header.
Commit: 105900ced185558633e2ca8aa812c8c6c39ef59b
https://github.com/llvm/llvm-project/commit/105900ced185558633e2ca8aa812c8c6c39ef59b
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/__config
M libcxx/include/__configuration/platform.h
M libcxx/include/__random/binomial_distribution.h
M libcxx/src/filesystem/operations.cpp
Log Message:
-----------
[libc++] Always define _LIBCPP_GLIBC_PREREQ (#169405)
Always defining the macro allows us to simplify the few places where
it's used.
Commit: d748c81218bee39dafb9cc0c00ed7831a3ed44c3
https://github.com/llvm/llvm-project/commit/d748c81218bee39dafb9cc0c00ed7831a3ed44c3
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/add_i1.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-entry.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/cse-convergent.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub_i1.ll
M llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
Log Message:
-----------
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
The 16-bit immediate operand of s_waitcnt_depctr / s_wait_alu has some
unused bits. Previously codegen would set these bits to 1, but setting
them to 0 matches the SP3 assembler behaviour better, which in turn
means that we can print them using the human readable SP3 syntax:
s_wait_alu 0xfffd ; unused bits set to 1
s_wait_alu 0xff9d ; unused bits set to 0
s_wait_alu depctr_va_vcc(0) ; unused bits set to 0, human readable
Note that the set of unused bits changed between GFX10.1 and GFX10.3.
Commit: 17b19c50349053ed7721357f806233d633696bf0
https://github.com/llvm/llvm-project/commit/17b19c50349053ed7721357f806233d633696bf0
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/LoopUnrolling.cpp
M clang/test/Analysis/loop-unrolling.cpp
Log Message:
-----------
[analyzer] Unroll loops of compile-time upper-bounded loops (#169400)
Previously, only literal upper-bounded loops were recognized. This patch
relaxes this matching to accept any compile-time deducible constant
expression.
It would be better to rely on the SVals (values from the symbolic
domain), as those could potentially have more accurate answers, but this
one is much simpler.
Note that at the time we calculate this value, we have not evaluated the
sub-exprs of the condition, consequently, we can't just query the
Environment for the folded SVal.
Because of this, the next best tool in our toolbox is comp-time
evaluating the Expr.
rdar://165363923
Commit: 4e37526fdb37bb6e778a5445b05cb1be539fbda7
https://github.com/llvm/llvm-project/commit/4e37526fdb37bb6e778a5445b05cb1be539fbda7
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
Log Message:
-----------
[AMDGPU] Fix test after #169378
Commit: af3af8ea5a4a0102bfd3998d1898eef6d735b2e4
https://github.com/llvm/llvm-project/commit/af3af8ea5a4a0102bfd3998d1898eef6d735b2e4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/X86/setcc-wide-types.ll
Log Message:
-----------
[X86] setcc-wide-types.ll - cleanup check prefixes NFC (#169488)
Match typical prefixes used in x86 SSE/AVX tests
Commit: e06c148af7ed118ef2ff0774c8ad00838638bb2a
https://github.com/llvm/llvm-project/commit/e06c148af7ed118ef2ff0774c8ad00838638bb2a
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Analysis/IVDescriptors.cpp
Log Message:
-----------
[IVDesc] Use SCEVPatternMatch to improve code (NFC) (#168397)
Commit: 07ad928d92eac995e8d2fc48b0aafde511e9f3a0
https://github.com/llvm/llvm-project/commit/07ad928d92eac995e8d2fc48b0aafde511e9f3a0
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/fill_n.h
A libcxx/include/__algorithm/specialized_algorithms.h
M libcxx/include/__bit_reference
M libcxx/include/module.modulemap.in
Log Message:
-----------
[libc++] Introduce __specialized_algorithms (#167295)
Commit: 262716b35be1fc2c8de511b32d65f54448e0e204
https://github.com/llvm/llvm-project/commit/262716b35be1fc2c8de511b32d65f54448e0e204
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 07ad928d92ea
Commit: 4bc654d6497430c1dd5e4e25aaa84b3dec3e1113
https://github.com/llvm/llvm-project/commit/4bc654d6497430c1dd5e4e25aaa84b3dec3e1113
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
R cmake/Modules/GetToolchainDirs.cmake
M flang-rt/CMakeLists.txt
M flang-rt/cmake/modules/AddFlangRT.cmake
M flang-rt/cmake/modules/AddFlangRTOffload.cmake
R flang-rt/cmake/modules/FlangRTIntrospection.cmake
A flang-rt/cmake/modules/GetToolchainDirs.cmake
M flang-rt/lib/runtime/CMakeLists.txt
R flang-rt/lib/runtime/__cuda_builtins.f90
R flang-rt/lib/runtime/__cuda_device.f90
R flang-rt/lib/runtime/__fortran_builtins.f90
R flang-rt/lib/runtime/__fortran_ieee_exceptions.f90
R flang-rt/lib/runtime/__fortran_type_info.f90
R flang-rt/lib/runtime/__ppc_intrinsics.f90
R flang-rt/lib/runtime/__ppc_types.f90
R flang-rt/lib/runtime/cooperative_groups.f90
R flang-rt/lib/runtime/cudadevice.f90
R flang-rt/lib/runtime/ieee_arithmetic.f90
R flang-rt/lib/runtime/ieee_exceptions.f90
R flang-rt/lib/runtime/ieee_features.f90
R flang-rt/lib/runtime/iso_c_binding.f90
R flang-rt/lib/runtime/iso_fortran_env.f90
R flang-rt/lib/runtime/iso_fortran_env_impl.f90
R flang-rt/lib/runtime/mma.f90
M flang-rt/test/lit.site.cfg.py.in
M flang-rt/unittests/CMakeLists.txt
M flang/CMakeLists.txt
M flang/include/flang/Frontend/CompilerInvocation.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Semantics/semantics.cpp
A flang/module/.clang-format
A flang/module/__cuda_builtins.f90
A flang/module/__cuda_device.f90
A flang/module/__fortran_builtins.f90
A flang/module/__fortran_ieee_exceptions.f90
A flang/module/__fortran_type_info.f90
A flang/module/__ppc_intrinsics.f90
A flang/module/__ppc_types.f90
A flang/module/cooperative_groups.f90
A flang/module/cudadevice.f90
A flang/module/ieee_arithmetic.f90
A flang/module/ieee_exceptions.f90
A flang/module/ieee_features.f90
A flang/module/iso_c_binding.f90
A flang/module/iso_fortran_env.f90
A flang/module/iso_fortran_env_impl.f90
A flang/module/mma.f90
M flang/test/CMakeLists.txt
M flang/test/Driver/Inputs/ieee_arithmetic.mod
M flang/test/Driver/Inputs/iso_fortran_env.mod
R flang/test/Driver/intrinsic-module-path.F90
A flang/test/Driver/intrinsic-module-path.f90
M flang/test/Driver/lto-fatlto.f90
M flang/test/Driver/pp-fixed-form.f90
M flang/test/Lower/HLFIR/type-bound-call-mismatch.f90
M flang/test/Lower/OpenMP/simd_aarch64.f90
M flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90
M flang/test/Preprocessing/fixed-free.f
M flang/test/Preprocessing/no-pp-if.f90
M flang/test/Semantics/bug163242.f90
M flang/test/Semantics/bug164303.f90
M flang/test/lit.cfg.py
M flang/test/lit.site.cfg.py.in
M flang/tools/CMakeLists.txt
M flang/tools/bbc/bbc.cpp
A flang/tools/f18/CMakeLists.txt
A flang/tools/f18/dump.cpp
M llvm/runtimes/CMakeLists.txt
M openmp/CMakeLists.txt
M openmp/runtime/CMakeLists.txt
A openmp/runtime/cmake/LibompCheckFortranFlag.cmake
M openmp/runtime/cmake/LibompHandleFlags.cmake
M openmp/runtime/cmake/config-ix.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/test/lit.cfg
M openmp/runtime/test/lit.site.cfg.in
M runtimes/CMakeLists.txt
Log Message:
-----------
Revert "[Flang] Move builtin .mod generation into runtimes" (#169489)
Reverts llvm/llvm-project#137828
Buildbot error in
https://lab.llvm.org/staging/#/builders/105/builds/37275
Commit: 9e53ef3d8c18648517c7afb06bc0cd01ebbbdfa9
https://github.com/llvm/llvm-project/commit/9e53ef3d8c18648517c7afb06bc0cd01ebbbdfa9
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
A mlir/test/Target/LLVMIR/nvvm/mbar_arrive.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_arrive_drop.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_complete_tx.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_expect_tx.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_init.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_invalid.mlir
R mlir/test/Target/LLVMIR/nvvm/mbarriers.mlir
Log Message:
-----------
[MLIR][NVVM] Update mbarrier.arrive.* Op (#168758)
This patch updates the mbarrier.arrive.* family of Ops to include
all features added up-to Blackwell.
* Update the `mbarrier.arrive` Op to include shared_cluster
memory space, cta/cluster scope and an option to lower using
relaxed semantics.
* An `arrive_drop` variant is added for both the `arrive` and
`arrive.nocomplete` operations.
* Updates for expect_tx and complete_tx operations.
* Verifier checks are added wherever appropriate.
* lit tests are added to verify the lowering to the intrinsics.
TODO:
* Updates for the remaining mbarrier family will be done in
subsequent PRs. (mainly, arrive.expect-tx, test_wait and try_waits)
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 6bf3249fe9771c5732d993304ecee11f55927f9f
https://github.com/llvm/llvm-project/commit/6bf3249fe9771c5732d993304ecee11f55927f9f
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Sema/SemaARM.h
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
A clang/test/Sema/AArch64/builtin_vectorelements.c
Log Message:
-----------
[Clang][Sema] Emit diagnostic for __builtin_vectorelements(<SVEType>) when SVE is not available. (#168097)
As is done for other targets, I've moved the target type checking code
into SemaARM and migrated existing uses.
Fixes https://github.com/llvm/llvm-project/issues/155736
Commit: f0e0a2215827facf1f480753a96833f60ccbcb62
https://github.com/llvm/llvm-project/commit/f0e0a2215827facf1f480753a96833f60ccbcb62
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
Log Message:
-----------
[bazel] Delete redundant visibility (#169493)
default_visibility is already public.
Commit: 1919cd63223fdd6acd8a2c2d515f190160275226
https://github.com/llvm/llvm-project/commit/1919cd63223fdd6acd8a2c2d515f190160275226
Author: Colin Kinloch <colin at kinlo.ch>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/CheckerHelpers.cpp
A clang/test/Analysis/std-c-library-functions-eof-2-rad.c
Log Message:
-----------
[analyzer] Fix non decimal macro values in tryExpandAsInteger (#168632)
Values were parsed into an unsigned APInt with just enough of a bit
width to hold the number then interpreted as signed values. This
resulted in hex, octal and binary literals from being interpreted as
negative when the most significant bit is 1.
For example the `-0b11` would have a bit width of 2, would be
interpreted as -1, then negated to become 1.
Commit: 4e9b76e23b29a0576c0b950e06daa2f2a84c1b65
https://github.com/llvm/llvm-project/commit/4e9b76e23b29a0576c0b950e06daa2f2a84c1b65
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/lib/CIR/CodeGen/CIRGenOpenACCHelpers.h
M clang/test/CIR/CodeGenOpenACC/declare-create.cpp
M clang/test/CIR/CodeGenOpenACC/openacc-not-implemented-global.cpp
R clang/test/CIR/CodeGenOpenACC/openacc-not-implemented.cpp
Log Message:
-----------
[OpenACC][CIR] 'declare' lowering for globals/ns/struct-scopes (+create) (#169409)
This patch does the lowering for a 'declare' construct that is not a
function-local-scope. It also does the lowering for 'create', which has
an entry-op of create and exit-op of delete.
Global/NS/Struct scope 'declare's emit a single 'acc_ctor' and
'acc_dtor' (except in the case of 'link') per variable referenced. The
ctor is the entry op followed by a declare_enter. The dtor is a
get_device_ptr, followed by a declare_exit, followed by a delete(exit
op). This DOES include any necessary bounds.
This patch implements all of the above. We use a separate 'visitor' for
the clauses here since it is particularly different from the other uses,
AND there are only 4 valid clauses. Additionally, we had to split the
modifier conversion into its own 'helpers' file, which will hopefully
get some additional use in the future.
Commit: d54168013aa49876c21d53b9a4a39eec23953096
https://github.com/llvm/llvm-project/commit/d54168013aa49876c21d53b9a4a39eec23953096
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/Transforms/Utils/FunctionComparator.h
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
Log Message:
-----------
[LLVM] Use "syncscope" instead of "synchscope" in comments. NFC. (#134615)
This matches the spelling of the keyword in LLVM IR.
Commit: d615c14c22003522c16f7b82646542eb8e2dddca
https://github.com/llvm/llvm-project/commit/d615c14c22003522c16f7b82646542eb8e2dddca
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
Log Message:
-----------
[RISCV] Update SpacemiT-X60 vector floating-point instructions latencies (#150618)
This PR adds hardware-measured latencies for all instructions defined in
Section 13 of the RVV specification: "Vector Floating-Point
Instructions" to the SpacemiT-X60 scheduling model.
Commit: a7e715a1419ec977ff7d82f028a0449f9d20bf1c
https://github.com/llvm/llvm-project/commit/a7e715a1419ec977ff7d82f028a0449f9d20bf1c
Author: Paul Osmialowski <pawel.osmialowski at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/docs/Vectorizers.rst
Log Message:
-----------
[llvm][docs] Correct the list of the available -fveclib= options to match with the reality (#168205)
The command line reality is this:
$ clang -c prog.c -fveclib=accelerate
error: invalid value 'accelerate' in '-fveclib=accelerate'
$ clang -c prog.c -fveclib=Accelerate
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=libmvec
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=LIBMVEC
error: invalid value 'LIBMVEC' in '-fveclib=LIBMVEC'
$ clang -c prog.c -fveclib=massv
error: invalid value 'massv' in '-fveclib=massv'
$ clang -c prog.c -fveclib=MASSV
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=sleef
error: invalid value 'sleef' in '-fveclib=sleef'
$ clang -c prog.c -fveclib=sleefgnuabi
error: invalid value 'sleefgnuabi' in '-fveclib=sleefgnuabi'
$ clang -c prog.c -fveclib=SLEEF
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=darwin_libsystem_m
error: invalid value 'darwin' in '-fveclib=darwin_libsystem_m'
$ clang -c prog.c -fveclib=Darwin_libsystem_m
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=armpl
error: invalid value 'armpl' in '-fveclib=armpl'
$ clang -c prog.c -fveclib=ARMPL
error: invalid value 'ARMPL' in '-fveclib=ARMPL'
$ clang -c prog.c -fveclib=ArmPL
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=amdlibm
error: invalid value 'amdlibm' in '-fveclib=amdlibm'
$ clang -c prog.c -fveclib=AMDLIBM
clang: error: unsupported option 'AMDLIBM' for target 'aarch64'
Commit: b37b307715fd1c449698aabad1fcfd188b265f2c
https://github.com/llvm/llvm-project/commit/b37b307715fd1c449698aabad1fcfd188b265f2c
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/__functional/bind.h
M libcxx/include/__functional/bind_back.h
M libcxx/include/__functional/bind_front.h
M libcxx/include/__functional/function.h
M libcxx/include/__functional/mem_fn.h
M libcxx/include/__functional/reference_wrapper.h
M libcxx/test/libcxx/diagnostics/functional.nodiscard.verify.cpp
M libcxx/test/std/utilities/function.objects/refwrap/refwrap.invoke/robust_against_adl.pass.cpp
Log Message:
-----------
[libc++] Applied `[[nodiscard]]` to some general utilities (#169322)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
The following functions/classes have been annotated in this patch:
- [x] `bind_back`, `bind_front`, `bind`
- [x] `function`, `mem_fn`
- [x] `reference_wrapper`
Commit: 077a280cf586b29c6aa37a17637bcb6b91dc121c
https://github.com/llvm/llvm-project/commit/077a280cf586b29c6aa37a17637bcb6b91dc121c
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
A flang/test/Lower/OpenACC/acc-reduction-remapping.f90
Log Message:
-----------
[flang][acc] remap symbol appearing in reduction clause (#168876)
This patch is a follow-up of #162306 for the reduction clause.
Inside the compute region that carries the reduction clause, a new
hlfir.declare is generated for symbol appearing in the reduction clause.
The input of this hlfir.declare is the acc.reduction result. The related
semantics::Symbol is remapped to the hlfir.declare result so that any
reference to the symbol inside the compute region will use this SSA
value as the starting point instead of the SSA value for the host
address.
Commit: 5818435c437c654c8c17c7ba8b7eb8833b7c3229
https://github.com/llvm/llvm-project/commit/5818435c437c654c8c17c7ba8b7eb8833b7c3229
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/basic.ll
Log Message:
-----------
RuntimeLibcalls: Add a few libm entries from TargetLibraryInfo (#167049)
These are floating-point functions recorded in TargetLibraryInfo,
but missing from RuntimeLibcalls.
Commit: 7f8c43a24949e2aa33e5f03f75ac865bb2f11ad8
https://github.com/llvm/llvm-project/commit/7f8c43a24949e2aa33e5f03f75ac865bb2f11ad8
Author: GrumpyPigSkin <130710602+GrumpyPigSkin at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
A llvm/test/CodeGen/X86/GlobalISel/fp-bitcast.ll
Log Message:
-----------
[X86][GISel] Fix crash on bitcasting i16 <-> half with gisel enabled. (#168456)
Added missing checks for casting half to/from i16 with global-isel
enabled.
Fixes #166557
Commit: d8ae4d503ada5509fb526a782816540eb4d15012
https://github.com/llvm/llvm-project/commit/d8ae4d503ada5509fb526a782816540eb4d15012
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/basic.ll
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/ps.ll
Log Message:
-----------
RuntimeLibcalls: Add __memcpy_chk, __memmove_chk, __memset_chk (#167053)
These were in TargetLibraryInfo, but missing from RuntimeLibcalls.
This only adds the cases that already have the non-chk variants
already. Copies the enabled-by-default logic from TargetLibraryInfo,
which is probably overly permissive. Only isPS opts-out.
Commit: 25c95ebfa82e2f6a20cf1282aaef09d1cc598ee7
https://github.com/llvm/llvm-project/commit/25c95ebfa82e2f6a20cf1282aaef09d1cc598ee7
Author: Ming Yan <ming.yan at terapines.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/test/Fir/FirToSCF/do-loop.fir
Log Message:
-----------
[flang][fir] Convert `fir.do_loop` with the unordered attribute to `scf.parallel`. (#168510)
Refines the existing conversion to allow `fir.do_loop` annotated with
`unordered` to be lowered to `scf.parallel`, while other loops retain
their original lowering.
Commit: a51e2ef0fe73dd9ab6e608304ddf2b489c350cf4
https://github.com/llvm/llvm-project/commit/a51e2ef0fe73dd9ab6e608304ddf2b489c350cf4
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
Log Message:
-----------
[VPlan] Treat VPVector(End)PointerRecipe as single-scalar, if ops are. (#169249)
VPVector(End)PointerRecipes are single-scalar if all their operands are.
This should be effectively NFC currently, but it should re-enable cost
checking for some more VPWidenMemoryRecipe after
https://github.com/llvm/llvm-project/pull/157387 as discovered by
John Brawn.
Commit: eb5297e0ade96fe8a6297763f28219be97dfac76
https://github.com/llvm/llvm-project/commit/eb5297e0ade96fe8a6297763f28219be97dfac76
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/merge_attributes.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sincos_stret.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sleef.ll
Log Message:
-----------
RuntimeLibcalls: Add mustprogress to common function attributes (#167080)
Commit: be2dfce6472c65270900dce1754f5352a83c2e98
https://github.com/llvm/llvm-project/commit/be2dfce6472c65270900dce1754f5352a83c2e98
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copyin.cpp
Log Message:
-----------
[OpenACC][CIR] Global declare 'copyin' clause lowering (#169498)
JUST like the 'create' clause, except the entry op is copyin instead of
create. Most of this is the test.
Commit: 9007b36b4250dff51e1a22f0b1f4084d5ab4fd4a
https://github.com/llvm/llvm-project/commit/9007b36b4250dff51e1a22f0b1f4084d5ab4fd4a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
Log Message:
-----------
[RISCV] Add a InstRW to COPY in RISCVSchedSpacemitX60.td. (#169423)
This prevents the scheduler from thinking copy instructions are free. In
#167008, we saw cases where the scheduler moved ABI copies past other
instructions creating high register pressure that caused the register
allocator to run out of registers. They can't be spilled because the
physical register lifetime was increased, not the virtual register.
Ideally, we would detect what register class the COPY is for, but for now
I've just treated it as a scalar integer copy.
Commit: 4f5fb36ddba6f538ff859d494fe15f19691b88f1
https://github.com/llvm/llvm-project/commit/4f5fb36ddba6f538ff859d494fe15f19691b88f1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Use an enum class for AVL state ins RISCVInsertVSETVLI. NFC (#169455)
Commit: 3564870a9fbfe49b11b47136127b6f972fbac43b
https://github.com/llvm/llvm-project/commit/3564870a9fbfe49b11b47136127b6f972fbac43b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Initialize AltFmt and TWiden in the VSETVLIInfo default constructor. (#169457)
Commit: b3b83ac1e80e4a3f3e4241b2ae0ceabef369a5bf
https://github.com/llvm/llvm-project/commit/b3b83ac1e80e4a3f3e4241b2ae0ceabef369a5bf
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M offload/test/offloading/shared_lib_fp_mapping.c
M offload/test/offloading/static_linking.c
Log Message:
-----------
[offload][lit] Fix compilation of two offload tests (#169399)
These are C tests, not C++, so no function parameters means unspecified
number of parameters, not `void`.
These compile fine on the current tested offload targets because an
error is only
[thrown](https://github.com/llvm/llvm-project/blob/main/clang/lib/Sema/SemaDecl.cpp#L10695)
if the calling convention doesn't support variadic arguments, which they
happen to.
When compiling this test for other targets that do not support variadic
arguments, we get an error, which does not seem intentional.
Just add `void` to the parameter list.
---------
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 031d99836de51f2d6dfeb4f539e2d1af85f4f263
https://github.com/llvm/llvm-project/commit/031d99836de51f2d6dfeb4f539e2d1af85f4f263
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
A llvm/test/CodeGen/SPIRV/function/vararg.ll
Log Message:
-----------
[SPIRV] Error in backend for vararg functions (#169111)
SPIR-V doesn't support variadic functions, though we make an exception
for `printf`.
If we don't error, we generate invalid SPIR-V because the backend has no
idea how to codegen vararg functions as it is not described in the spec.
We get asm like this:
```
%27 = OpFunction %6 None %7
%28 = OpFunctionParameter %4
; -- End function
```
The above asm is totally invalid, there's no `OpFunctionEnd` and it
causes crashes in downstream tools like `spirv-as` and `spirv-link`.
We already have many `printf` tests locking down that this doesn't break
`printf`, it was already handled elsewhere at the time the error check
runs.
Note the SPIR-V Translator does the same thing, see
[here](https://github.com/KhronosGroup/SPIRV-LLVM-Translator/pull/2703).
---------
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: ccbd0d1a69eb71268bfa7066a962bbd37c9893b1
https://github.com/llvm/llvm-project/commit/ccbd0d1a69eb71268bfa7066a962bbd37c9893b1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Add assertions to VSETVLIInfo accessors. NFC (#169462)
Commit: 177e38286cd61a7b5a968636e1f147f128dd25a2
https://github.com/llvm/llvm-project/commit/177e38286cd61a7b5a968636e1f147f128dd25a2
Author: Sayan Saha <sayans at mathworks.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/Utils/QuantUtils.h
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Utils/QuantUtils.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/quant-test.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Get quantized element type with sign info. (#169387)
As mentioned in
https://github.com/llvm/llvm-project/blob/a27bb38ee6f5762e715803d8eb6ffc5a8dd09575/mlir/include/mlir/Dialect/Quant/IR/QuantTypes.h#L109
`QuantType::getStorageType` doesn't capture the sign information. This
lead to the following IR to fail during verification:
```
func.func @clamp(%arg0:tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>) -> (tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>) {
%0 = tosa.clamp %arg0 {max_val = 255 : ui8, min_val = 0 : ui8} : (tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>) -> tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>
return %0 : tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>
}
```
with `'tosa.clamp' op min/max attributes types are incompatible with
input/output element types` error
since `getStorageType` was returning signed integer but the clamp
attributes were unsigned.
This PR updates the usage of `getStorageType` in tosa codebase to
correctly use the signed info for the quantized type.
Commit: 1c3b10f2e2d8f9600fedd5e579aef69d7d31fadc
https://github.com/llvm/llvm-project/commit/1c3b10f2e2d8f9600fedd5e579aef69d7d31fadc
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)
Since #142598 isKernelLDS has been a pointless wrapper around isKernel.
Commit: 02c9e8987a22753417c721eba5e5848f3fe33a24
https://github.com/llvm/llvm-project/commit/02c9e8987a22753417c721eba5e5848f3fe33a24
Author: Marco Elver <elver at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll
Log Message:
-----------
[InstCombine][MemProf] Preserve all metadata (#169242)
When rewriting operator new calls to their hot/cold variants for PGHO,
`!alloc_token` metadata was being dropped. This metadata is required by
the AllocToken pass to correctly instrument the optimized allocation.
Fix it by preserving all metadata.
Commit: b8ef25aa643761233dc5b74d9fb7c38a2064d9c7
https://github.com/llvm/llvm-project/commit/b8ef25aa643761233dc5b74d9fb7c38a2064d9c7
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Transforms/Utils/LoopUtils.cpp
A llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
M llvm/test/Verifier/llvm.loop.estimated_trip_count.ll
M llvm/unittests/Transforms/Utils/LoopUtilsTest.cpp
Log Message:
-----------
[PGO] Fix zeroed estimated trip count (#167792)
Before PR #152775, `llvm::getLoopEstimatedTripCount` never returned 0.
If `llvm::setLoopEstimatedTripCount` were called with 0, it would zero
branch weights, causing `llvm::getLoopEstimatedTripCount` to return
`std::nullopt`.
PR #152775 changed that behavior: if `llvm::setLoopEstimatedTripCount`
is called with 0, it sets `llvm.loop.estimated_trip_count` to 0, causing
`llvm::getLoopEstimatedTripCount` to return 0. However, it kept
documentation saying `llvm::getLoopEstimatedTripCount` returns a
positive count.
Some passes continue to assume `llvm::getLoopEstimatedTripCount` never
returns 0 and crash if it does, as reported in issue #164254. To restore
the behavior they expect, this patch changes
`llvm::getLoopEstimatedTripCount` to return `std::nullopt` when
`llvm.loop.estimated_trip_count` is 0.
Commit: c582688b6912c615da1d08630c178dd3d0072aeb
https://github.com/llvm/llvm-project/commit/c582688b6912c615da1d08630c178dd3d0072aeb
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
Log Message:
-----------
[MLIR][tensor] Simplify ExtractSliceOp::inferResultType (nfc) (#169313)
The `offsets` and `strides` arguments are neither used nor required -
removed them and simplify this hook.
Commit: 6d21ce8797317814ad6f2372d98d21c9900f0579
https://github.com/llvm/llvm-project/commit/6d21ce8797317814ad6f2372d98d21c9900f0579
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceresident.cpp
Log Message:
-----------
[OpenACC][CIR] device_resident lowering for NS/global/struct declare (#169507)
This is the same as create/copyin, except it uses
declare_device_resident for the entry op.
Commit: 7b5163d3001613e9c449f7603f4a0f7f521e79a1
https://github.com/llvm/llvm-project/commit/7b5163d3001613e9c449f7603f4a0f7f521e79a1
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
Log Message:
-----------
[lldb][NFC] use llvm::StringRef in `ExtractContextAndIdentifer` function (#169506)
this avoids allocation when checking if a method contains a path.
Commit: e04cca8561c65b9820f2c284eea164ab9fb7cdce
https://github.com/llvm/llvm-project/commit/e04cca8561c65b9820f2c284eea164ab9fb7cdce
Author: Marco Elver <elver at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A clang/test/CodeGen/memprof-pgho.cpp
Log Message:
-----------
[Clang][MemProf] Add end-to-end test for PGHO rewriting (#169243)
Add an end-to-end (non-LTO) test verifying that the optimization
pipeline is set up correctly for Profile Guided Heap Optimization (PGHO)
transforms. Ensure that both PGHO and AllocToken can stack, and the
AllocToken pass does not interfere with PGHO and vice versa.
Commit: 1a036732d210c2b78404067a1aa0b3a3bba3eaf8
https://github.com/llvm/llvm-project/commit/1a036732d210c2b78404067a1aa0b3a3bba3eaf8
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
A clang/test/Driver/hip-spirv-backend-bindings.c
A clang/test/Driver/hip-spirv-backend-opt.c
A clang/test/Driver/hip-spirv-backend-phases.c
Log Message:
-----------
[clang][Driver] Support for the SPIR-V backend when compiling HIP (#167543)
For HIP, the SPIR-V backend can be optionally activated with the -use-spirv-backend flag. This option uses the SPIR-V BE instead of the SPIR-V translator. These changes also ensure that -use-spirv-backend does not require external dependencies, such as spirv-as and spirv-link
Commit: 17852deda7fb9dabb41023e2673025c630b9369d
https://github.com/llvm/llvm-project/commit/17852deda7fb9dabb41023e2673025c630b9369d
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
M llvm/lib/Target/NVPTX/NVPTXTagInvariantLoads.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
M llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
A llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
A llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
A llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
Log Message:
-----------
[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)
This backend support will allow the LoadStoreVectorizer, in certain
cases, to fill in gaps when creating load/store vectors and generate
LLVM masked load/stores
(https://llvm.org/docs/LangRef.html#llvm-masked-store-intrinsics). To
accomplish this, changes are separated into two parts. This first part
has the backend lowering and TTI changes, and a follow up PR will have
the LSV generate these intrinsics:
https://github.com/llvm/llvm-project/pull/159388.
In this backend change, Masked Loads get lowered to PTX with `#pragma
"used_bytes_mask" [mask];`
(https://docs.nvidia.com/cuda/parallel-thread-execution/#pragma-strings-used-bytes-mask).
And Masked Stores get lowered to PTX using the new sink symbol syntax
(https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-st).
# TTI Changes
TTI changes are needed because NVPTX only supports masked loads/stores
with _constant_ masks. `ScalarizeMaskedMemIntrin.cpp` is adjusted to
check that the mask is constant and pass that result into the TTI check.
Behavior shouldn't change for non-NVPTX targets, which do not care
whether the mask is variable or constant when determining legality, but
all TTI files that implement these API need to be updated.
# Masked store lowering implementation details
If the masked stores make it to the NVPTX backend without being
scalarized, they are handled by the following:
* `NVPTXISelLowering.cpp` - Sets up a custom operation action and
handles it in lowerMSTORE. Similar handling to normal store vectors,
except we read the mask and place a sentinel register `$noreg` in each
position where the mask reads as false.
For example,
```
t10: v8i1 = BUILD_VECTOR Constant:i1<-1>, Constant:i1<0>, Constant:i1<0>, Constant:i1<-1>, Constant:i1<-1>, Constant:i1<0>, Constant:i1<0>, Constant:i1<-1>
t11: ch = masked_store<(store unknown-size into %ir.lsr.iv28, align 32, addrspace 1)> t5:1, t5, t7, undef:i64, t10
->
STV_i32_v8 killed %13:int32regs, $noreg, $noreg, killed %16:int32regs, killed %17:int32regs, $noreg, $noreg, killed %20:int32regs, 0, 0, 1, 8, 0, 32, %4:int64regs, 0, debug-location !18 :: (store unknown-size into %ir.lsr.iv28, align 32, addrspace 1);
```
* `NVPTXInstInfo.td` - changes the definition of store vectors to allow
for a mix of sink symbols and registers.
* `NVPXInstPrinter.h/.cpp` - Handles the `$noreg` case by printing "_".
# Masked load lowering implementation details
Masked loads are routed to normal PTX loads, with one difference: a
`#pragma "used_bytes_mask"` is emitted before the load instruction
(https://docs.nvidia.com/cuda/parallel-thread-execution/#pragma-strings-used-bytes-mask).
To accomplish this, a new operand is added to every NVPTXISD Load type
representing this mask.
* `NVPTXISelLowering.h/.cpp` - Masked loads are converted into normal
NVPTXISD loads with a mask operand in two ways. 1) In type legalization
through replaceLoadVector, which is the normal path, and 2) through
LowerMLOAD, to handle the legal vector types
(v2f16/v2bf16/v2i16/v4i8/v2f32) that will not be type legalized. Both
share the same convertMLOADToLoadWithUsedBytesMask helper. Both default
this operand to UINT32_MAX, representing all bytes on. For the latter,
we need a new `NVPTXISD::MLoadV1` type to represent that edge case
because we cannot put the used bytes mask operand on a generic
LoadSDNode.
* `NVPTXISelDAGToDAG.cpp` - Extract used bytes mask from loads, add them
to created machine instructions.
* `NVPTXInstPrinter.h/.cpp` - Print the pragma when the used bytes mask
isn't all ones.
* `NVPTXForwardParams.cpp`, `NVPTXReplaceImageHandles.cpp` - Update
manual indexing of load operands to account for new operand.
* `NVPTXInsrtInfo.td`, `NVPTXIntrinsics.td` - Add the used bytes mask to
the MI definitions.
* `NVPTXTagInvariantLoads.cpp` - Ensure that masked loads also get
tagged as invariant.
Some generic changes that are needed:
* `LegalizeVectorTypes.cpp` - Ensure flags are preserved when splitting
masked loads.
* `SelectionDAGBuilder.cpp` - Preserve `MD_invariant_load` on masked
load SDNode creation
Commit: 6a395fec1f7663e02c6607e8e10791838c949389
https://github.com/llvm/llvm-project/commit/6a395fec1f7663e02c6607e8e10791838c949389
Author: Guy David <guyda96 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
Log Message:
-----------
[AArch64] Mark FMOVvXfY_ns as rematerializable, cheap (#169186)
Commit: b93bb69dfad5f94565d90575a92203a1a2f3395b
https://github.com/llvm/llvm-project/commit/b93bb69dfad5f94565d90575a92203a1a2f3395b
Author: Samira Bakon <bazuzi at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
Log Message:
-----------
[clang][dataflow] Use containers with deterministic iteration order. (#169512)
Commit: eb1ff56e26fdb48728642f7d26e47b337b7235ea
https://github.com/llvm/llvm-project/commit/eb1ff56e26fdb48728642f7d26e47b337b7235ea
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll
Log Message:
-----------
[SLP][NFC]Add a test for copyable operands, used multiple times, NFC
Commit: d69e70149636efa0293310303878fbf9a5f31433
https://github.com/llvm/llvm-project/commit/d69e70149636efa0293310303878fbf9a5f31433
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
Log Message:
-----------
[PGO] Add missing target datalayout in test (#169520)
The test was added by b8ef25aa643761233dc5b74d9fb7c38a2064d9c7. It
failed on at least the following bots, but the failure did not reproduce
on my test machines or in pre-commit CI:
- https://lab.llvm.org/buildbot/#/builders/190/builds/31638
- https://lab.llvm.org/buildbot/#/builders/190/builds/31638
This fix hopefully addresses at least the warnings there.
Commit: 5999cc8ceef3acef128e1baf8fcefd7164acc677
https://github.com/llvm/llvm-project/commit/5999cc8ceef3acef128e1baf8fcefd7164acc677
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/stack
M libcxx/test/libcxx/diagnostics/stack.nodiscard.verify.cpp
Log Message:
-----------
[libc++][stack] Applied `[[nodiscard]]` (#169468)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 1c5b1501ca50e039ae39075465972761449013e9
https://github.com/llvm/llvm-project/commit/1c5b1501ca50e039ae39075465972761449013e9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/lib/CodeGen/LibcallLoweringInfo.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.h
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/Mips/Mips16ISelLowering.h
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.h
Log Message:
-----------
CodeGen: Move libcall lowering configuration to subtarget (#168621)
Previously libcall lowering decisions were made directly
in the TargetLowering constructor. Pull these into the subtarget
to facilitate turning LibcallLoweringInfo into a separate analysis
in the future.
Commit: 5017370a1ce5009aed2855b645194bc141f72a2d
https://github.com/llvm/llvm-project/commit/5017370a1ce5009aed2855b645194bc141f72a2d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/gws_agpr.ll
Log Message:
-----------
AMDGPU: Add baseline test for gws handling with AGPR inputs (#169372)
Commit: a860c8378f91d9b7713171888e76962b2747fe4e
https://github.com/llvm/llvm-project/commit/a860c8378f91d9b7713171888e76962b2747fe4e
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
R clang/test/Driver/hip-spirv-backend-bindings.c
R clang/test/Driver/hip-spirv-backend-opt.c
R clang/test/Driver/hip-spirv-backend-phases.c
Log Message:
-----------
Revert "[clang][Driver] Support for the SPIR-V backend when compiling HIP (#167543)" (#169528)
This reverts commit 1a036732d210c2b78404067a1aa0b3a3bba3eaf8.
Reverted due to a failure in hip-spirv-backend-opt.c for
fuchsia-x86_64-linux.
Commit: 53e5cfdf8b13e2427797ca6eeda1860f8aa190ef
https://github.com/llvm/llvm-project/commit/53e5cfdf8b13e2427797ca6eeda1860f8aa190ef
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/combined-copy.c
M clang/test/CIR/CodeGenOpenACC/compute-copy.c
M clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceptr.cpp
M clang/test/CIR/CodeGenOpenACC/declare-link.cpp
M clang/test/CIR/CodeGenOpenACC/declare-present.cpp
Log Message:
-----------
[OpenACC][CIR] link clause lowering for global declare (#169524)
The 'link' clause is like the rest of the global clauses (copyin,
create, device_resident), except it only has an entry op(thus no
dtor).
This patch also removes a bunch of now stales TODOs from the tests.
Commit: 8380a48aa0b62be28b653ba6b3d38198680b2bd9
https://github.com/llvm/llvm-project/commit/8380a48aa0b62be28b653ba6b3d38198680b2bd9
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
Log Message:
-----------
[PGO] Add REQUIRES to test (#169531)
The test was added by b8ef25aa643761233dc5b74d9fb7c38a2064d9c7. It
failed on at least the following bots, but the failure did not reproduce
on my test machines or in pre-commit CI:
- https://lab.llvm.org/buildbot/#/builders/190/builds/31643
- https://lab.llvm.org/buildbot/#/builders/65/builds/25949
- https://lab.llvm.org/buildbot/#/builders/154/builds/24417
d69e70149636efa0293310303878fbf9a5f31433 did not fix the failure.
Hopefully this will.
Commit: 1441f0458545243f9278cf87a35c4cb4e1cd62bd
https://github.com/llvm/llvm-project/commit/1441f0458545243f9278cf87a35c4cb4e1cd62bd
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/Address.h
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
A clang/test/CIR/CodeGen/placement-new.cpp
Log Message:
-----------
[CIR] Upstream reserved placement new handling (#169436)
This upstreams the code to support reserved placement new calls.
Commit: 45336992453c83d083ccadf62ae56626dfb0f761
https://github.com/llvm/llvm-project/commit/45336992453c83d083ccadf62ae56626dfb0f761
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
Log Message:
-----------
[BOLT][BTI] Add MCPlusBuilder::isBTILandingPad (#167306)
- takes both implicit and explicit BTIs into account
- fix related comment in
llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
Commit: 83d9c636b753ab37842a25606d95d800dce90398
https://github.com/llvm/llvm-project/commit/83d9c636b753ab37842a25606d95d800dce90398
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M utils/bazel/third_party_build/zlib-ng.BUILD
Log Message:
-----------
[bazel] Add alias for zlib-ng for WORKSPACE compat (#169530)
The consumer of zlib in third-party/BUILD.bazel expects zlib-ng from the
BCR, if you still load this version from your WORKSPACE / MODULE.bazel
you need to use this name instead.
Commit: 012721d3200ceed635495394fe96b17bbaa8653e
https://github.com/llvm/llvm-project/commit/012721d3200ceed635495394fe96b17bbaa8653e
Author: Benjamin Chetioui <3920784+bchetioui at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/test/python/ir/operation.py
Log Message:
-----------
[mlir][python] Propagate error diagnostics when an op couldn't be created. (#169499)
Commit: 4877c593a873657cd18a1ee0bd4a13f4b84c4d3b
https://github.com/llvm/llvm-project/commit/4877c593a873657cd18a1ee0bd4a13f4b84c4d3b
Author: Kaitlin Peng <kaitlinpeng at microsoft.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCombine.td
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h
A llvm/test/CodeGen/SPIRV/GlobalISel/InstCombine/prelegalizercombiner-select-to-faceforward.mir
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/faceforward.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward.ll
Log Message:
-----------
[SPIRV] Add PreLegalizer pattern matching for `faceforward` (#139959)
Tasks completed:
- Pattern match`select(fcmp(dot(p2, p3), 0), p1, -p1)` to
`faceforward(p1, p2, p3)`
- Add pattern matching tests to
`prelegalizercombiner-select-to-faceforward.mir` and `faceforward.ll`
- Add CL extension error test
`llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll`
- Add CL extension test for no pattern matching in
`llvm/test/CodeGen/SPIRV/opencl/faceforward.ll`
Closes #137255.
Commit: d125cab13f08eee4d02d02e46223d14285bb2353
https://github.com/llvm/llvm-project/commit/d125cab13f08eee4d02d02e46223d14285bb2353
Author: Valeriy Savchenko <vsavchenko at apple.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/Transforms/InstCombine/cast-mul-select.ll
M llvm/test/Transforms/InstCombine/cast.ll
M llvm/test/Transforms/InstCombine/catchswitch-phi.ll
M llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
M llvm/test/Transforms/InstCombine/known-bits-lerp-pattern.ll
M llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
M llvm/test/Transforms/InstCombine/logical-select.ll
Log Message:
-----------
[InstCombine] Support multi-use values in cast elimination transforms (#165877)
`canEvaluateTruncated` and `canEvaluateSExtd` previously rejected
multi-use values to avoid duplication. This was overly conservative, if
all users of a multi-use value are part of the transform, we can
evaluate it in a different type without duplication.
This change tracks visited values and defers decisions on multi-use
values until we verify all their users were visited.
`EvaluateInDifferentType` now memoizes multi-use values to avoid
creating duplicates.
Applied to truncation and sext. Zext unchanged due to its dual-return
nature.
Commit: 84df446af980f33f8014578856f8b1f8037888ee
https://github.com/llvm/llvm-project/commit/84df446af980f33f8014578856f8b1f8037888ee
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
Log Message:
-----------
AMDGPU: Remove DummyCGSCC use after buffer lowering passes (#169519)
The fixme the comment refers to was removed.
Commit: 44cffbe5d8de5947780288ca3c366bbd52650314
https://github.com/llvm/llvm-project/commit/44cffbe5d8de5947780288ca3c366bbd52650314
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/fma-combine.ll
Log Message:
-----------
[RISCV] Propagate SDNode flags when combining `(fmul (fneg X), ...)` (#169460)
In #157388, we turned `(fmul (fneg X), Y)` into `(fneg (fmul X, Y))`.
However, we forgot to propagate SDNode flags, specifically fast math
flags, from the original FMUL to the new one. This hinders some of the
subsequent (FMA) DAG combiner patterns that relied on the contraction
flag and as a consequence, missed some of the opportunities to generate
negation FMA instructions like `fnmadd`.
This patch fixes this issue by propagating the flags.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 6a6b99aa8010f16f4e74f78bca1f3c6ca9e94b9f
https://github.com/llvm/llvm-project/commit/6a6b99aa8010f16f4e74f78bca1f3c6ca9e94b9f
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCRecipeBufferization.cpp
M flang/test/Fir/OpenACC/recipe-bufferization.mlir
M flang/test/Lower/OpenACC/acc-firstprivate-derived-allocatable-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-pointer-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-user-assign.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction-remapping.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenACC/do-loops-to-acc-loops.f90
M flang/test/Transforms/OpenACC/acc-implicit-copy-reduction.fir
M flang/test/Transforms/OpenACC/acc-implicit-data-fortran.F90
M flang/test/Transforms/OpenACC/acc-implicit-data.fir
M flang/test/Transforms/OpenACC/acc-implicit-firstprivate.fir
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/test/Dialect/OpenACC/acc-implicit-data-reduction.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
M mlir/test/Dialect/OpenACC/invalid.mlir
M mlir/test/Dialect/OpenACC/legalize-data.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
Log Message:
-----------
[acc][flang][cir] Add recipes to data entry operations (#149210)
This patch refactors the OpenACC dialect to attach recipe symbols
directly to data operations (acc.private, acc.firstprivate,
acc.reduction)
rather than to compute constructs (acc.parallel, acc.serial, acc.loop).
Motivation:
The previous design required compute constructs to carry both the recipe
symbol and the variable reference, leading to complexity. Additionally,
recipes were required even when they could be generated automatically
through MappableType interfaces.
Changes:
- Data operations (acc.private, acc.firstprivate, acc.reduction) now
require a 'recipe' attribute referencing their respective recipe
operations
- Verifier enforces recipe attribute presence for non-MappableType
operands; MappableType operands can generate recipes on demand
- Compute constructs (acc.parallel, acc.serial, acc.loop) no longer
carry recipe symbols in their operands
- Updated flang lowering to attach recipes to data operations instead
of passing them to compute constructs
Format Migration:
Old format:
```
acc.parallel private(@recipe -> %var : !fir.ref<i32>) { ... }
```
New format:
```
%private = acc.private varPtr(%var : !fir.ref<i32>)
recipe(@recipe) -> !fir.ref<i32>
acc.parallel private(%private : !fir.ref<i32>) { ... }
```
Test Updates:
- Updated all CIR and Flang OpenACC tests to new format
- Fixed CHECK lines to verify recipe attributes on data operations
Commit: d5aa686636e0824f2d39ac333537d19bb4f8fc34
https://github.com/llvm/llvm-project/commit/d5aa686636e0824f2d39ac333537d19bb4f8fc34
Author: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
[GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`. (#166204)
`convert-vector-to-llvm` pass applies a set of vector transformation
patterns that are not included in the standard `convert-to-llvm` pass
interface. These additional transformations are required to properly
lower MLIR vector operations. Since not all vector ops have direct
`llvm` dialect lowering, many of them must first be progressively
rewritten into simpler or more canonical vector ops, which are then
lowered to `llvm`. Therefore, running `convert-vector-to-llvm` is
necessary to ensure a complete and correct lowering of vector operations
to the `llvm` dialect.
Commit: 4822f4986fae9bb212e2f35e29839bbd9fb26bea
https://github.com/llvm/llvm-project/commit/4822f4986fae9bb212e2f35e29839bbd9fb26bea
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Analysis/CFG.cpp
M clang/test/Analysis/lifetime-cfg-output.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/unittests/Analysis/FlowSensitive/LoggerTest.cpp
Log Message:
-----------
[LifetimeSafety] Add parameter lifetime tracking in CFG (#169320)
This PR enhances the CFG builder to properly handle function parameters
in lifetime analysis:
1. Added code to include parameters in the initial scope during CFG
construction for both `FunctionDecl` and `BlockDecl` types
2. Added a special case to skip reference parameters, as they don't need
automatic destruction
3. Fixed several test cases that were previously marked as "FIXME" due
to missing parameter lifetime tracking
Previously, Clang's lifetime analysis was not properly tracking the
lifetime of function parameters, causing it to miss important
use-after-return bugs when parameter values were returned by reference
or address. This change ensures that parameters are properly tracked in
the CFG, allowing the analyzer to correctly identify when stack memory
associated with parameters is returned.
Fixes https://github.com/llvm/llvm-project/issues/169014
Commit: f545c2cec12f77f1fb61ccf07393f434d456ad94
https://github.com/llvm/llvm-project/commit/f545c2cec12f77f1fb61ccf07393f434d456ad94
Author: David Stone <davidfromonline at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaDeclCXX.cpp
Log Message:
-----------
[clang][NFC] Don't copy into a vector just to iterate in `IsInitListMemberExprInitialized` (#169385)
Commit: 0c9c62adf165ebf4128bcfe9863fa0c524b46b7b
https://github.com/llvm/llvm-project/commit/0c9c62adf165ebf4128bcfe9863fa0c524b46b7b
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
Log Message:
-----------
[PowerPC ]convert `(setcc (and X, 1), 0, eq)` to `XORI (and X, 1), 1` (#168384)
Convert `(setcc (and X, 1), 0, eq)` to `XORI (and X, 1), 1` , it will save one instruction.
Commit: d7dcc108fc3ada2330277424495b676d52de1765
https://github.com/llvm/llvm-project/commit/d7dcc108fc3ada2330277424495b676d52de1765
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/docs/DeveloperPolicy.rst
M llvm/utils/git/github-automation.py
Log Message:
-----------
[GitHub] Add review instructions for commit access requests (#168971)
As discussed in
https://discourse.llvm.org/t/clarification-on-how-to-accept-commit-access-requests/88728,
clarify reviewer instructions for how to accept commit access requests.
Commit: 1d30ae6e402a28018a5574b7c68d71aac14acd63
https://github.com/llvm/llvm-project/commit/1d30ae6e402a28018a5574b7c68d71aac14acd63
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
AMDGPU: Stop forcing RequiresCodeGenSCCOrder (#169522)
This hasn't been strictly necessary since c897c13dde.
Practically this makes little difference; we still enable IPRA
by default which implies this option. By removing this explicit
force, -enable-ipra=0 has the expected change in the pass pipeline
to remove the DummyCGSCC runs.
Commit: 8f1bb92bbfa45d49103953dad0d0a5dcfd388959
https://github.com/llvm/llvm-project/commit/8f1bb92bbfa45d49103953dad0d0a5dcfd388959
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
M llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
M llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
Log Message:
-----------
[NVPTX] Fix lit test issues from masked load/store implementation (#169535)
>From this commit:
https://github.com/llvm/llvm-project/commit/17852deda7fb9dabb41023e2673025c630b9369d,
Build was broken here:
https://lab.llvm.org/buildbot/#/builders/155/builds/15135/steps/7/logs/stdio.
I think this should fix things.
Commit: 6c8ff4f2bbae6fe29b0ef67edb70e6d73b47beb3
https://github.com/llvm/llvm-project/commit/6c8ff4f2bbae6fe29b0ef67edb70e6d73b47beb3
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Log Message:
-----------
[NVPTX] Fix maybe unused variable in 17852ded (#169542)
Commit: dce95b2ea41e8585cd1e3e2ce07f5d692a970949
https://github.com/llvm/llvm-project/commit/dce95b2ea41e8585cd1e3e2ce07f5d692a970949
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACCLoop.cpp
Log Message:
-----------
[OpenACC][CIR][NFC] Remove 'NYI' diagnostics, since we're done with t… (#169543)
…hese
We've finished all of the clauses/etc that we're going to use this
visitor for, so we can remove the SourceLocation we used just for that,
and replace all NYI with unreachables.
Commit: a8e0afe98853418e1367274e6f04f7ba255de199
https://github.com/llvm/llvm-project/commit/a8e0afe98853418e1367274e6f04f7ba255de199
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/test/CIR/CodeGen/vector-ext-element.cpp
Log Message:
-----------
[CIR] ArraySubscriptExpr on ExtVectorElementExpr (#169158)
Implement ArraySubscriptExpr support for ExtVectorElementExpr
Commit: 2d78b1409eeab558cfc1b64ab39211af00c5f35f
https://github.com/llvm/llvm-project/commit/2d78b1409eeab558cfc1b64ab39211af00c5f35f
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/OpenMPKinds.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/lib/Parse/ParseOpenMP.cpp
A clang/test/OpenMP/need_device_ptr_kind_ast_print.cpp
A clang/test/OpenMP/need_device_ptr_kind_messages.cpp
Log Message:
-----------
[OpenMP][Clang] Parsing/Sema support for `need_device_ptr(fb_nullify/fb_preserve)`. (#168905)
This patch adds parsing, semantic handling, and diagnostics for the
`OpenMP 6.1 fb_nullify` and` fb_preserve` fallback modifiers used with
the `need_device_ptr` map modifier.
Commit: 622dbb372bfefc135c3cdf967ae6f3b55ffa4a16
https://github.com/llvm/llvm-project/commit/622dbb372bfefc135c3cdf967ae6f3b55ffa4a16
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
Log Message:
-----------
AMDGPU: Add more tests for 32-bit constant address space (#168976)
The sub-dword cases just assert now, so comment those out.
Commit: 20ca85b69fc06feb75f67414d54f3830748bb456
https://github.com/llvm/llvm-project/commit/20ca85b69fc06feb75f67414d54f3830748bb456
Author: Jez Ng <me at jezng.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/InputFiles.cpp
M lld/test/MachO/x86-64-relocs.s
Log Message:
-----------
[lld] macho: Support section branch relocations, including the 1-byte form (#169062)
I noticed that we had a hardcoded value of 4 for the pcrel section
relocations, which seems like an issue given that we recently added
support for 1-byte branch relocations in
https://github.com/llvm/llvm-project/pull/164439. The code included an
assert that the relevant relocation had the BYTE4 attribute, but that is
actually not enough to use a hardcoded value of 4: we need to assert
that the *other* `BYTE<n>` attributes are not set either.
However, since we did not support local branch relocations, that doesn't
seem to have mattered in practice. That said, local branch relocations
can be emitted by compilers, and ld64 does handle the 4-byte version of
them, so I've added support for it here.
ld64 actually seems to reject 1-byte section relocations, so the
questionable code is actually probably fine (minus the incorrect
assert). So we have two options: add an equivalent check in LLD, or just
support 1-byte local branch relocations. Supporting it actually requires
less code, so I've gone with that option here.
Commit: 2ee12f191a005363259e3a95ccdf459d9044eadf
https://github.com/llvm/llvm-project/commit/2ee12f191a005363259e3a95ccdf459d9044eadf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/gws_agpr.ll
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
A llvm/test/MC/AMDGPU/ds_gws_sgpr_err.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
Log Message:
-----------
AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)
On targets that require even aligned 64-bit VGPRs, GWS operands
require even alignment of a 32-bit operand. Previously we had a hacky
post-processing which added an implicit operand to try to manage
the constraint. This would require special casing in other passes
to avoid breaking the operand constraint. This moves the handling
into the instruction definition, so other passes no longer need
to consider this edge case. MC still does need to special case this,
to print/parse as a 32-bit register. This also still ends up net
less work than introducing even aligned 32-bit register classes.
This also should be applied to the image special case.
Commit: 3a27fc48117ba7e062c3cfa0006badb64446ed69
https://github.com/llvm/llvm-project/commit/3a27fc48117ba7e062c3cfa0006badb64446ed69
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Omit VTYPE in VSETVLIInfo::print() when state is uninit or unknown. (#169459)
Commit: eab23e199aef18c2052c08171129633233ab98f5
https://github.com/llvm/llvm-project/commit/eab23e199aef18c2052c08171129633233ab98f5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Log Message:
-----------
[RISCV] Don't add Zilsd pairing hints if other part of the pair is reserved. (#169538)
Commit: ebe40066545fd0ad2e88c5e48b7751195d9a9eca
https://github.com/llvm/llvm-project/commit/ebe40066545fd0ad2e88c5e48b7751195d9a9eca
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/CMakeLists.txt
Log Message:
-----------
[mlir] Fix build failure with BUILD_SHARED_LIBS=ON
/usr/bin/ld: tools/mlir/lib/Dialect/GPU/Pipelines/CMakeFiles/obj.MLIRGP
UPipelines.dir/GPUToXeVMPipeline.cpp.o: in function `mlir::gpu::buildLo
werToXeVMPassPipeline(mlir::OpPassManager&, mlir::gpu::GPUToXeVMPipelin
eOptions const&)':
GPUToXeVMPipeline.cpp:(.text._ZN4mlir3gpu28buildLowerToXeVMPassPipeline
ERNS_13OpPassManagerERKNS0_24GPUToXeVMPipelineOptionsE+0x1293): undefin
ed reference to `mlir::createConvertVectorToLLVMPass()'
Commit: 6c48fbc1dcfbd44a47f126f21e575340b67aac06
https://github.com/llvm/llvm-project/commit/6c48fbc1dcfbd44a47f126f21e575340b67aac06
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/test/X86/lit.local.cfg
M bolt/test/lit.local.cfg
Log Message:
-----------
[BOLT][Tests] Use AT&T assembler syntax only for X86 tests (#169541)
Enabling AT&T syntax for all tests is broken when X86 target is not
enabled as reported in #167225.
Commit: 0917a38c694bd2558b79c2b6d51fee2308dd94dd
https://github.com/llvm/llvm-project/commit/0917a38c694bd2558b79c2b6d51fee2308dd94dd
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[PowerPC] Fix a warning
This patch fixes:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15676:17: error: unused
variable 'CC' [-Werror,-Wunused-variable]
Commit: af0fcf85c812867c1d03f390d5afbbbc5b7f1584
https://github.com/llvm/llvm-project/commit/af0fcf85c812867c1d03f390d5afbbbc5b7f1584
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/include/mlir/TableGen/Pattern.h
M mlir/lib/TableGen/Pattern.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
Log Message:
-----------
[mlir][tblgen] Don't echo absolute paths into rewrite pattern source (#168984)
Currently, the declarative pattern rewrite generator will always print
the [source]:[line](s) from which a pattern came. This is a useful
debugging hint, but it causes problem when absolute paths are used as
arguments to mlir-tblgen (which LLVM's build rules automatically do).
Specifially, it causes the source to be tied to the build location,
harning reproducability and our collective ability to get ccache hits
from, say, separate worktrees.
This commit resolves the issue by replacing absolute paths in thes
"Generated from:" comments with their filenames. (The alternative would
have been to implement an entire file-prefix-map the way the C compilers
do, but since this is an isolated incident, I chose to resolve it
locally.)
Commit: 36947982106686570383945c2bbf367f447d9edc
https://github.com/llvm/llvm-project/commit/36947982106686570383945c2bbf367f447d9edc
Author: Sergei Druzhkov <serzhdruzhok at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
Log Message:
-----------
[lldb-dap] Add format support for evaluate request (#169132)
This patch adds support for format option in the `evaluate` request
according to
[DAP](https://microsoft.github.io/debug-adapter-protocol/specification#Requests_Evaluate)
specification. Also, fixed typo in `LLDB_DAP_INVALID_VARRERF` constant.
Commit: 0f941f6866910e55e0e7cff30c48740477be0cd8
https://github.com/llvm/llvm-project/commit/0f941f6866910e55e0e7cff30c48740477be0cd8
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
Log Message:
-----------
[flang][cuda] Add support to allocate scalar character types (#169550)
Add support for character declared like:
```
subroutine sub1()
character*4, device :: b
end subroutine
```
Commit: ad3d9fb3cab7f2e9a7337ca3c1bd0018ff6c6158
https://github.com/llvm/llvm-project/commit/ad3d9fb3cab7f2e9a7337ca3c1bd0018ff6c6158
Author: Petr Penzin <ppenzin at tenstorrent.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
Log Message:
-----------
[RISCV] tt-ascalon-d8 vector scheduling (#167066)
Add the vector scheduling model for tt-ascalon-d8 and corresponding
llvm-mca tests.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 8d920725ca56930d301df1c7e090905423645a49
https://github.com/llvm/llvm-project/commit/8d920725ca56930d301df1c7e090905423645a49
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
Log Message:
-----------
[RISCV] Use FMV.D for moving GPRPairs on RV32_Zdinx (#169556)
This is noted by the specification, and should save a dynamic
instruction.
Code size should be no worse than before, as the pairs of moves can
usually be turned into two 16-bit moves, but `fmv.d` is always a 32-bit
instruction.
LLVM can look through a `FSGNJ_D_IN32X`, in
`RISCVInstrInfo::isCopyInstrImpl` which helps copy propagation.
Commit: dbcf5688cca37543ea3304be68516b3ac476eef3
https://github.com/llvm/llvm-project/commit/dbcf5688cca37543ea3304be68516b3ac476eef3
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
[AMDGPU] Simplify VT comparisons. NFC. (#169526)
Automated with `sed -i 's/\.Value//g' lib/Target/AMDGPU/*.td` plus a
tiny bit of manual reformatting.
Commit: 1c9368e01e6ed45e7dbc523d3bddfd900bb6e504
https://github.com/llvm/llvm-project/commit/1c9368e01e6ed45e7dbc523d3bddfd900bb6e504
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
A clang/test/CIR/CodeGen/copy-constructor.cpp
Log Message:
-----------
[CIR] Upstream non-record array init handling (#169429)
This upstreams the code to handle member initialization for non-record
arrays.
Commit: c475f8e5d809e2109a67c8523472eb28cd7bbb2a
https://github.com/llvm/llvm-project/commit/c475f8e5d809e2109a67c8523472eb28cd7bbb2a
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
A clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
Log Message:
-----------
[HLSL] Update vector swizzle elements individually (#169090)
When individual elements of a vector are updated via vector swizzle, it needs to be handled as separate store operations to the individual vector elements.
Clang treats vectors as one unit, so if a part of a vector needs to be updated, the whole vector is loaded, some elements modified, and then the whole vector is stored.
In HLSL vector elements are handled separately. We need to avoid this load/modify/store sequence to prevent overwriting other vector elements that might be getting updated in parallel.
Fixes #152815
Commit: 091aece72b0149bda6d465301fe3934ca570a592
https://github.com/llvm/llvm-project/commit/091aece72b0149bda6d465301fe3934ca570a592
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[VPlan] Remove redundant transferFlags call from replicateByVF (NFC).
Flags are now passed on construction/cloning. Remove unnecessary
transferFlags call, and make code independent of VPRecipeWithIRFlags, to
support additional recipes in the future.
Commit: 00ffc70ba154b8670fc37d1398ce4473bca3a516
https://github.com/llvm/llvm-project/commit/00ffc70ba154b8670fc37d1398ce4473bca3a516
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
Log Message:
-----------
[SLP][NFC]Add a test with commutative instruction with non-commutative op, NFC
Commit: 074d17e9c8cbc6f22e65ba1211787453ea629ccb
https://github.com/llvm/llvm-project/commit/074d17e9c8cbc6f22e65ba1211787453ea629ccb
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/tsd_shared.h
Log Message:
-----------
[scudo] Lock/unlock MutexTSDs in disable/enable. (#169440)
It is possible that a fork could occur while MutexTSDs is being held and
then cause a deadlock in a forked process when something attempts to
lock it again. Instead add it to the enable/disable list of mutexes.
Commit: e894654532a74b669b0b0830007cc6c979b35d56
https://github.com/llvm/llvm-project/commit/e894654532a74b669b0b0830007cc6c979b35d56
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/addrec-may-wrap-udiv-canonicalize.ll
Log Message:
-----------
[SCEV] Add tests for UDiv canonicalization of AddRecs that may wrap.
Add test cases for canonicalizing AddRecs that may wrap.
Commit: 9bf78ab8dd17ecbbecd4157c67e8fb4d95528194
https://github.com/llvm/llvm-project/commit/9bf78ab8dd17ecbbecd4157c67e8fb4d95528194
Author: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
Revert "[GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`." (#169570)
Reverts llvm/llvm-project#166204
There was a build issue due to a missing dependency.
Commit: 49828c23b59959ca9f2c0dc83aeb9ce7f84b5c31
https://github.com/llvm/llvm-project/commit/49828c23b59959ca9f2c0dc83aeb9ce7f84b5c31
Author: Haowei <haowei at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/cmake/caches/Fuchsia.cmake
Log Message:
-----------
[Fuchsia] Bump minimal OS X target to 11.0 (#169568)
libcxx requires minimal macOS 11 to build. This patch bumps the minimal
OS X target in Fuchsia's cmake cache file to 11.0 to satisfy this
requirement.
Commit: 4f39a4ff0ada92870ca1c2dccad382ea04947da8
https://github.com/llvm/llvm-project/commit/4f39a4ff0ada92870ca1c2dccad382ea04947da8
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCOpsInterfacesTest.cpp
Log Message:
-----------
[acc][flang] Add getInitRegion() to GlobalVariableOpInterface (#169569)
Some globals (e.g., fir.global) have initialization regions that may
transitively reference other globals or type descriptors. Add
getInitRegion() to GlobalVariableOpInterface to retrieve these regions,
returning Region* (nullptr if the global uses attributes for
initialization, as with memref.global).
Commit: 5f777b2c8faca3fe28079fc81a7aefbca1edb803
https://github.com/llvm/llvm-project/commit/5f777b2c8faca3fe28079fc81a7aefbca1edb803
Author: daniilavdeev <daniilavdeev237 at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCSymbol.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/MC/MCSymbol.cpp
A llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
Log Message:
-----------
[dwarf] make dwarf fission compatible with RISCV relaxations 1/2 (#166597)
Currently, -gsplit-dwarf and -mrelax are incompatible options in Clang.
The issue is that .dwo files should not contain any relocations, as they
are not processed by the linker. However, relaxable code emits
relocations in DWARF for debug ranges that reside in the .dwo file when
DWARF fission is enabled.
This patch makes DWARF fission compatible with RISC-V relaxations. It
uses the StartxEndx DWARF forms in .debug_rnglists.dwo, which allow
referencing addresses from .debug_addr instead of using absolute
addresses. This approach eliminates relocations from .dwo files.
Commit: 97023fba5546f9d0e762ccbca89cbb8324a9131a
https://github.com/llvm/llvm-project/commit/97023fba5546f9d0e762ccbca89cbb8324a9131a
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/test/CIR/CodeGen/coro-task.cpp
Log Message:
-----------
[CIR] Emit ready and suspend branches for cir.await (#168814)
This PR adds codegen for `cir.await` ready and suspend. One notable
difference from the classic codegen is that, in the suspend branch, it
emits an `AwaitSuspendWrapper`(`.__await_suspend_wrapper__init`)
function that is always inlined. This function wraps the suspend logic
inside an internal wrapper that gets inlined. Example here:
https://godbolt.org/z/rWYGcaaG4
Commit: ebf5d9ef7de29b55fd9e9d504f83689b4013e0de
https://github.com/llvm/llvm-project/commit/ebf5d9ef7de29b55fd9e9d504f83689b4013e0de
Author: Alan Li <me at alanli.org>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-i8-gep.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-var-delta.ll
R llvm/test/Transforms/StraightLineStrengthReduce/path-compression.ll
R llvm/test/Transforms/StraightLineStrengthReduce/pick-candidate.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll
Log Message:
-----------
Revert "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169546)
This reverts commit f67409c3ec7cd45c55656c8159bc42b3918f1116.
cc @fiigii
Including us, several separate groups are experiencing regressions with
this change. This is the smallest reproducer pasted by @akuegel :
https://github.com/llvm/llvm-project/pull/162930#issuecomment-3574307330
Commit: 9534ed9f30043318798a9544461bc174e273e1f3
https://github.com/llvm/llvm-project/commit/9534ed9f30043318798a9544461bc174e273e1f3
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M orc-rt/include/orc-rt/Error.h
M orc-rt/unittests/ErrorTest.cpp
Log Message:
-----------
[orc-rt] Add ErrorAsOutParameter convenience constructor. (#169467)
Allows construction of ErrorAsOutParameters from Error references.
Commit: fd22706e937f7d2563cfa0e433dd735cc5284599
https://github.com/llvm/llvm-project/commit/fd22706e937f7d2563cfa0e433dd735cc5284599
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
A flang/test/Lower/OpenMP/compiler-directives-loop.f90
Log Message:
-----------
[flang][OpenMP] Skip compiler directives in getCollapsedLoopEval (#169565)
Use `getNestedDoConstruct` from Utils to get the nested DoConstructs.
Fixes https://github.com/llvm/llvm-project/issues/169532
Commit: f7a9fcad99e155fed32d98a2d41d1e3bfdeebf48
https://github.com/llvm/llvm-project/commit/f7a9fcad99e155fed32d98a2d41d1e3bfdeebf48
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/test/Lower/CUDA/cuda-atomicadd.cuf
Log Message:
-----------
[flang][cuda] Use PTX instruction for atomicAdd with 4xf32 (#169581)
Implementation similar to the clang one in
`clang/lib/Headers/__clang_cuda_intrinsics.h`
Commit: 1c034a372403d539700292cd564773ef3531a423
https://github.com/llvm/llvm-project/commit/1c034a372403d539700292cd564773ef3531a423
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
Log Message:
-----------
[compiler-rt] [UBsan] precommit test (#169579)
Commit: 9c414c428d8464c829d551d0d91029339e746842
https://github.com/llvm/llvm-project/commit/9c414c428d8464c829d551d0d91029339e746842
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/CMakeLists.txt
M clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
M clang-tools-extra/clangd/test/index-tools.test
M clang-tools-extra/clangd/test/system-include-extractor.test
Log Message:
-----------
[clangd] Make lit tests work with the internal shell
This makes all of the clangd tests work with the internal shell.
Modifications needed for each test are as follows:
1. system-include-extractor.test was using variable expansion which is
not supported in the internal shell. This patch rewrites it to use
the readfile mechanism along with python. This isn't super pretty but
is readily understandable and there are only two tests across the
monorepo that use this construction, so making it prettier is hard to
justify.
2. include-cleaner-batch-fix.test - Was using $'' construction to create
new lines in a string. Simply replace it with multiple echo commands
to be canonical with the rest of the repository.
3. index-tools.test - Just add IndexBenchmark to the clangd test
depends, so the test now just works unconditionally. This should
significantly increase test coverage at little cost.
Reviewers: ilovepi, HighCommander4, petrhosek, kadircet
Reviewed By: ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/169539
Commit: c51c382c8752e7ba5049ed3662fefb9ffe9283c3
https://github.com/llvm/llvm-project/commit/c51c382c8752e7ba5049ed3662fefb9ffe9283c3
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/lit.cfg.py
Log Message:
-----------
[clangd] Enable lit internal shell by default
Enable it now that all of the tests pass under the internal shell. The
internal shell is slightly faster (10-15%) and also provides a better
debugging experience.
Reviewers: petrhosek, ilovepi, kadircet, HighCommander4
Reviewed By: ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/169540
Commit: 4cfbc44ebe26692c209655c37aeb0b6cbf1d479b
https://github.com/llvm/llvm-project/commit/4cfbc44ebe26692c209655c37aeb0b6cbf1d479b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/lit.cfg.py
Log Message:
-----------
Revert "[clangd] Enable lit internal shell by default"
This reverts commit c51c382c8752e7ba5049ed3662fefb9ffe9283c3.
This breaks at least one buildbot:
1. https://lab.llvm.org/buildbot/#/builders/134/builds/30460
Commit: bd04ef6df50e8e6e5212762fc798ea9fbdcfc897
https://github.com/llvm/llvm-project/commit/bd04ef6df50e8e6e5212762fc798ea9fbdcfc897
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/CMakeLists.txt
M clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
M clang-tools-extra/clangd/test/index-tools.test
M clang-tools-extra/clangd/test/system-include-extractor.test
Log Message:
-----------
Revert "[clangd] Make lit tests work with the internal shell"
This reverts commit 9c414c428d8464c829d551d0d91029339e746842.
This one is causing buildbot failures too at CMake configure time:
1. https://lab.llvm.org/buildbot/#/builders/193/builds/12452
Commit: 3f22ed1152c4c00e95381368ec7d88878f2fd9f9
https://github.com/llvm/llvm-project/commit/3f22ed1152c4c00e95381368ec7d88878f2fd9f9
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M offload/include/OpenMP/InteropAPI.h
M offload/include/PerThreadTable.h
Log Message:
-----------
[OFFLOAD] Add support for indexed per-thread containers (#164263)
Split from #158900 it adds a PerThreadContainer that can use STL-like
indexed containers based on a slightly refactored PerThreadTable.
---------
Co-authored-by: Joseph Huber <huberjn at outlook.com>
Commit: 5d38cddc3b00b428f848fdeddc8334c4560db36a
https://github.com/llvm/llvm-project/commit/5d38cddc3b00b428f848fdeddc8334c4560db36a
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/AST/Expr.cpp
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/CodeGen/scoped-atomic-ops.c
M clang/test/Sema/scoped-atomic-ops.c
Log Message:
-----------
[Clang] Add __scoped_atomic_uinc_wrap and __scoped_atomic_udec_wrap builtins (#168666)
This PR extends __scoped_atomic builtins with inc and dec functions.
They map to LLVM IR `atomicrmw uinc_wrap` and `atomicrmw udec_wrap`.
These enable implementation of OpenCL-style atomic_inc / atomic_dec with
wrap semantics on targets supporting scoped atomics (e.g. GPUs).
---------
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: d889b97f2b1cd7264a5a225edd7daf18c3709bfa
https://github.com/llvm/llvm-project/commit/d889b97f2b1cd7264a5a225edd7daf18c3709bfa
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
Log Message:
-----------
[RISCV][llvm] Support BUILD_VECTOR codegen for P extension (#169083)
Commit: 44c8a011764ae5fb9178d938fc3f1f1bf76bfe49
https://github.com/llvm/llvm-project/commit/44c8a011764ae5fb9178d938fc3f1f1bf76bfe49
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
Log Message:
-----------
[compiler-rt] [UBSan] remove unneeded test cases (#169594)
the target handling will be done in the driver, so removing codegen
tests.
Commit: 175168c620d6a62ab7360693c6415cc1ab1eeb4b
https://github.com/llvm/llvm-project/commit/175168c620d6a62ab7360693c6415cc1ab1eeb4b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Analysis/ThreadSafety.cpp
A clang/test/SemaCXX/no-warn-thread-safety-analysis.cpp
Log Message:
-----------
[Analysis] Make ThreadSafety correctly handle base class destructors (#169593)
Commit: 40f21a7b2f3e7d034cac4a981b09c1a0049df427
https://github.com/llvm/llvm-project/commit/40f21a7b2f3e7d034cac4a981b09c1a0049df427
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
Log Message:
-----------
[llvm][RISCV] Support P Extension CodeGen (#167895)
This patch supports: PSLLI_B, PSLLI_H, PSLLI_W, PSSLAI_H and PSSLAI_W
Commit: 1ea4aa1b91553847ab155f7ed6c22d392d06b38e
https://github.com/llvm/llvm-project/commit/1ea4aa1b91553847ab155f7ed6c22d392d06b38e
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M libclc/clc/lib/generic/atomic/clc_atomic_dec.cl
M libclc/clc/lib/generic/atomic/clc_atomic_def.inc
M libclc/clc/lib/generic/atomic/clc_atomic_inc.cl
Log Message:
-----------
[libclc] Use __scoped_atomic_udec/uinc_wrap to implement _clc_atomic_dec/inc (#168327)
Commit: 222ba6f5ce96d3612b7f62aeacd1d5599fbb8141
https://github.com/llvm/llvm-project/commit/222ba6f5ce96d3612b7f62aeacd1d5599fbb8141
Author: Jan Voung <jvoung at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][dataflow] Handle more glvalue cases of the ConditionalOperator transfer (#168994)
In the dataflow framework, the builtin transfer function currently only
handles the GLValue result case of ConditionalOperator when the
true and false expression StorageLocations are exactly the same.
Ideally / we have wanted to introduce alias sets to handle when the Locs
are different. However, that is a larger change to the framework
(and we may need to introduce weak updates).
For now, do something simpler to at least handle when the GLValue is
immediately cast to an RValue, by making up a distinct StorageLocation
that holds the join of the true and false expression values (when not a
record). This seems like the most common case, so seems worth covering.
The case when an LValue is needed and can be updated later (and
thus needs a link to the original storage locations) seems more rare,
and we currently do not handle such updates either, so this intermediate
step is no different (for that case).
Commit: bfc732efbda2dc1caa78de89600834c083bedd83
https://github.com/llvm/llvm-project/commit/bfc732efbda2dc1caa78de89600834c083bedd83
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M orc-rt/include/orc-rt/Session.h
M orc-rt/lib/executor/Session.cpp
M orc-rt/unittests/SessionTest.cpp
Log Message:
-----------
[orc-rt] Add ControllerAccess interface. (#169598)
ControllerAccess provides an abstract interface for bidirectional RPC
between the executor (running JIT'd code) and the controller (containing
the llvm::orc::ExecutionSession). ControllerAccess implementations are
expected to implement IPC / RPC using a concrete communication method
(shared memory, pipes, sockets, native system IPC, etc).
Calls from executor to controller are made via callController, with
"handler tags" (addresses in the executor) specifying the target handler
in the controller. A handler must be associated in the controller with
the given tag for the call to succeed. This ensures that only registered
entry points in the controller can be used, and avoids leaking
controller addresses into the executor.
Calls in both directions are to "wrapper functions" that take a buffer
of bytes as input and return a buffer of bytes as output. In the ORC
runtime these must be `orc_rt_WrapperFunction`s (see
Session::handleWrapperCall). The interpretation of the byte buffers is
up to the wrapper functions: the ORC runtime imposes no restrictions on
how the bytes are to be interpreted.
ControllerAccess objects may be detached from the Session prior to
Session shutdown, in which case no further calls may be made in either
direction, and any pending results (from calls made that haven't
returned yet) should return errors. If the ControllerAccess class is
still attached at Session shutdown time it will be detached as part of
the shutdown process. The ControllerAccess::disconnect method must
support concurrent entry on multiple threads, and all callers must block
until they can guarantee that no further calls will be received or
accepted.
Commit: e81a564cb0031e93d34a941224b14ec73c69bf65
https://github.com/llvm/llvm-project/commit/e81a564cb0031e93d34a941224b14ec73c69bf65
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/tools/opt/invalid-target.ll
M llvm/tools/opt/optdriver.cpp
Log Message:
-----------
opt: Stop creating TargetMachine to infer the datalayout (#169585)
The Triple directly has the datalayout string in it, so just
use that.
The logical flow here is kind of a mess. We were constructing
a temporary target machine in the asm parser to infer the datalayout,
throwing it away, and then creating another target machine for the
actual compilation. The flow of the Triple construction is still
convoluted, but we can at least drop the TargetMachine.
Commit: 76ec25f729fcc7ae576caf21293cc393e68e7cf7
https://github.com/llvm/llvm-project/commit/76ec25f729fcc7ae576caf21293cc393e68e7cf7
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
Log Message:
-----------
[ORC] Pass FailedSNs by const-ref. NFCI. (#169600)
Avoids a vector copy.
Commit: 4e7c65e85f47443ab3af729e5cf8e693081abb87
https://github.com/llvm/llvm-project/commit/4e7c65e85f47443ab3af729e5cf8e693081abb87
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Log Message:
-----------
[RISCV] Don't add duplicate Zilsd hints. (#169554)
This matches what ARM does. I'm not sure if there are any bad effects
from the duplicate hints. I have seen the duplicates hints in the debug
output and confirmed this removes them.
Commit: a7f9a4db895561b7bf4a1b91fe306b29fd61af6c
https://github.com/llvm/llvm-project/commit/a7f9a4db895561b7bf4a1b91fe306b29fd61af6c
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
Log Message:
-----------
[AMDGPU] Update strict floating point tests to be more comprehensive (#169578)
Commit: a57fe84af0679871d914e0d5fc3f449069f22a19
https://github.com/llvm/llvm-project/commit/a57fe84af0679871d914e0d5fc3f449069f22a19
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/TextNodeDumper.cpp
A clang/test/AST/ast-dump-APValue-addrlabeldiff.c
Log Message:
-----------
[clang] Implement dump() for AddrLabelDiff APValues (#169505)
Commit: 8396d4c10e98fedba5d8f6861087078b2de49674
https://github.com/llvm/llvm-project/commit/8396d4c10e98fedba5d8f6861087078b2de49674
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
Log Message:
-----------
[clang][bytecode][NFC] Clean up Integral::from() functions (#169513)
Commit: 6459f39c377dc8b7d5d81ef365553c8625fb4def
https://github.com/llvm/llvm-project/commit/6459f39c377dc8b7d5d81ef365553c8625fb4def
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/BitcastBuffer.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode] Add some convenience API to BitcastBuffer (#169516)
So we check the offsets before using them.
Commit: 00aca530b1e49281f461965a304a8a36cb41142d
https://github.com/llvm/llvm-project/commit/00aca530b1e49281f461965a304a8a36cb41142d
Author: Dominik Adamski <dominik.adamski at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M flang-rt/cmake/modules/HandleLibs.cmake
Log Message:
-----------
[Flang-rt] Remove COMPILE_ONLY from flang-rt CMake file. (#169534)
COMPILE_ONLY was introduced in cmake 3.27.0. We cannot use this feature,
because LLVM supports cmake 3.20.0.
Commit: e04c01bcc91226d632f81bd3290c180deb0b6db8
https://github.com/llvm/llvm-project/commit/e04c01bcc91226d632f81bd3290c180deb0b6db8
Author: Fangrui Song <i at maskray.me>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCMachOStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCWasmStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp
Log Message:
-----------
MC: Remove unneeded parameter `MCAsmBackend *`. NFC
Commit: 97732ddb5d921a7d5cd6ffc2a23438b607c0d3f6
https://github.com/llvm/llvm-project/commit/97732ddb5d921a7d5cd6ffc2a23438b607c0d3f6
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Program.h
Log Message:
-----------
[clang][bytecode][NFC] Make Program::getNativePointer() const (#169502)
Commit: e493e90a890d92cb13090710d74bb16b3e1075f8
https://github.com/llvm/llvm-project/commit/e493e90a890d92cb13090710d74bb16b3e1075f8
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
Log Message:
-----------
[lldb][NFC] Fix incorrect comments in TestArm64InstEmulation
Commit: 93f2deb1d0a886672683e1e6df9797d11cddf7c5
https://github.com/llvm/llvm-project/commit/93f2deb1d0a886672683e1e6df9797d11cddf7c5
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vle.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/addcarry.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/allow-check.ll
M llvm/test/CodeGen/RISCV/arith-with-overflow.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bitreverse-shift.ll
M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
M llvm/test/CodeGen/RISCV/bswap-shift.ll
M llvm/test/CodeGen/RISCV/clear-cache.ll
M llvm/test/CodeGen/RISCV/copy-frameindex.mir
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-zfa.ll
M llvm/test/CodeGen/RISCV/double_reduct.ll
M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
M llvm/test/CodeGen/RISCV/fixed-csr.ll
M llvm/test/CodeGen/RISCV/float-arith-strict.ll
M llvm/test/CodeGen/RISCV/float-arith.ll
M llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-convert-strict.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/float-select-verify.ll
M llvm/test/CodeGen/RISCV/float-zfa.ll
M llvm/test/CodeGen/RISCV/flt-rounds.ll
M llvm/test/CodeGen/RISCV/fmax-fmin.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/fpenv.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/frm-dependency.ll
M llvm/test/CodeGen/RISCV/get-register-invalid.ll
M llvm/test/CodeGen/RISCV/get-register-noreserve.ll
M llvm/test/CodeGen/RISCV/get-register-reserve.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/half-zfa.ll
M llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
M llvm/test/CodeGen/RISCV/i64-icmp.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll
M llvm/test/CodeGen/RISCV/intrinsics/trap.ll
M llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/machine-combiner.ll
M llvm/test/CodeGen/RISCV/machine-cse.ll
M llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll
M llvm/test/CodeGen/RISCV/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/memset-inline.ll
M llvm/test/CodeGen/RISCV/min-max.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/module-target-abi3.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsic-optimizations.ll
M llvm/test/CodeGen/RISCV/pei-crash.ll
M llvm/test/CodeGen/RISCV/pr135206.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/pr92193.ll
M llvm/test/CodeGen/RISCV/prefetch.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/readcyclecounter.ll
M llvm/test/CodeGen/RISCV/readsteadycounter.ll
M llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/replace-with-veclib-sleef-scalable.ll
M llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbkx-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
M llvm/test/CodeGen/RISCV/rv64-float-convert.ll
M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-args.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-frame-setup.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
M llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbkx-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
M llvm/test/CodeGen/RISCV/rvv/commutable.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-negative.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvw.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vp-fsub-and-vp-fmul.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
M llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/llround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/lround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/marith-vp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int-e64.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int-e64.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-crash-zvl32b.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mixed-float-bf16-arith.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/pr63459.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
M llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
M llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfwmacc_4x4x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e4m3.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e5m2.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e4m3.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e5m2.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_f_f.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_s.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_u.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_s.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_u.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte16.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte32.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte64.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte8.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettk.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettm.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettnt.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste16.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste32.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste64.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste8.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtdiscard.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_t_v.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_v_t.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtzero_t.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands-i1.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/smulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/splats-with-mixed-vl.ll
M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
M llvm/test/CodeGen/RISCV/rvv/trunc-sat-clip-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/ushl_sat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vadc.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/rvv/vaesdf.ll
M llvm/test/CodeGen/RISCV/rvv/vaesdm.ll
M llvm/test/CodeGen/RISCV/rvv/vaesef.ll
M llvm/test/CodeGen/RISCV/rvv/vaesem.ll
M llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll
M llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll
M llvm/test/CodeGen/RISCV/rvv/vaesz.ll
M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vand.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn.ll
M llvm/test/CodeGen/RISCV/rvv/vasub.ll
M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
M llvm/test/CodeGen/RISCV/rvv/vbrev.ll
M llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
M llvm/test/CodeGen/RISCV/rvv/vclmul.ll
M llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vclz.ll
M llvm/test/CodeGen/RISCV/rvv/vcompress.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/vcpopv.ll
M llvm/test/CodeGen/RISCV/rvv/vctz.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
M llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll
M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vfirst.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/vfmerge-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv-bf-s.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv-s-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv-v-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-bf-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-bf.ll
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M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
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M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvtbf16-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vfrec7-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfrec7.ll
M llvm/test/CodeGen/RISCV/rvv/vfredmax.ll
M llvm/test/CodeGen/RISCV/rvv/vfredmin.ll
M llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
M llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnj-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjn-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjx-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1down-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1up-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-w-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-bf-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-bf-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvtbf16-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmaccbf16.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
M llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-w-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vghsh.ll
M llvm/test/CodeGen/RISCV/rvv/vgmul.ll
M llvm/test/CodeGen/RISCV/rvv/vid.ll
M llvm/test/CodeGen/RISCV/rvv/viota.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-no-prop.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vle.ll
M llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
M llvm/test/CodeGen/RISCV/rvv/vleff.ll
M llvm/test/CodeGen/RISCV/rvv/vlm.ll
M llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlse.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vmand.ll
M llvm/test/CodeGen/RISCV/rvv/vmandn.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu.ll
M llvm/test/CodeGen/RISCV/rvv/vmclr.ll
M llvm/test/CodeGen/RISCV/rvv/vmerge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu.ll
M llvm/test/CodeGen/RISCV/rvv/vmnand.ll
M llvm/test/CodeGen/RISCV/rvv/vmnor.ll
M llvm/test/CodeGen/RISCV/rvv/vmor.ll
M llvm/test/CodeGen/RISCV/rvv/vmorn.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmset.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsif.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vmsof.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul.ll
M llvm/test/CodeGen/RISCV/rvv/vmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.x.s.ll
M llvm/test/CodeGen/RISCV/rvv/vmxnor.ll
M llvm/test/CodeGen/RISCV/rvv/vmxor.ll
M llvm/test/CodeGen/RISCV/rvv/vnclip.ll
M llvm/test/CodeGen/RISCV/rvv/vnclipu.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vor.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vqdot.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotsu.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotu.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotus.ll
M llvm/test/CodeGen/RISCV/rvv/vredand.ll
M llvm/test/CodeGen/RISCV/rvv/vredmax.ll
M llvm/test/CodeGen/RISCV/rvv/vredmaxu.ll
M llvm/test/CodeGen/RISCV/rvv/vredmin.ll
M llvm/test/CodeGen/RISCV/rvv/vredminu.ll
M llvm/test/CodeGen/RISCV/rvv/vredor.ll
M llvm/test/CodeGen/RISCV/rvv/vredsum.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vredxor.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu.ll
M llvm/test/CodeGen/RISCV/rvv/vrev8.ll
M llvm/test/CodeGen/RISCV/rvv/vrgather.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll
M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrol.ll
M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vror.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
M llvm/test/CodeGen/RISCV/rvv/vse.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-valid-elen-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvlmax-ext.ll
M llvm/test/CodeGen/RISCV/rvv/vsext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsext.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
M llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1down-constant-vl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1up-constant-vl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/vslidedown.ll
M llvm/test/CodeGen/RISCV/rvv/vslideup.ll
M llvm/test/CodeGen/RISCV/rvv/vsll.ll
M llvm/test/CodeGen/RISCV/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/rvv/vsm3c.ll
M llvm/test/CodeGen/RISCV/rvv/vsm3me.ll
M llvm/test/CodeGen/RISCV/rvv/vsm4k.ll
M llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
M llvm/test/CodeGen/RISCV/rvv/vsmul.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsra.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssub.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccus.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/vwredsum.ll
M llvm/test/CodeGen/RISCV/rvv/vwredsumu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vxor.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vzext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vzext.ll
M llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xv.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvv.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvw.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqa.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqasu.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqau.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqaus.ll
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
M llvm/test/CodeGen/RISCV/sadd_sat.ll
M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/saverestore.ll
M llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/simplify-condbr.ll
M llvm/test/CodeGen/RISCV/ssub_sat.ll
M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/thread-pointer.ll
M llvm/test/CodeGen/RISCV/uadd_sat.ll
M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/RISCV/usub_sat.ll
M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
M llvm/test/CodeGen/RISCV/vlenb.ll
M llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xcvalu.ll
M llvm/test/CodeGen/RISCV/xcvbitmanip.ll
M llvm/test/CodeGen/RISCV/xcvmac.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
M llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll
Log Message:
-----------
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
As @mshockwave mentioned in
https://github.com/llvm/llvm-project/pull/156415, we don't need to
declare intrinsics in tests now, this pr removes them.
Commit: de674fb6c250608197a70ae3fdef5519597054f6
https://github.com/llvm/llvm-project/commit/de674fb6c250608197a70ae3fdef5519597054f6
Author: David Green <david.green at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/addtruncshift.ll
Log Message:
-----------
[AArch64] Add vector tests for add(trunc(shift))
Commit: 19655231718929362f338fb73a6d4ae587ad927e
https://github.com/llvm/llvm-project/commit/19655231718929362f338fb73a6d4ae587ad927e
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir][tensor] Add new builders for insert_slice/extract_slice Ops (nfc) (#169533)
Adds new builders for `tensor.insert_slice` and `tensor.extract_slice`
Ops for which the _offsets_ and the _strides_ are all 0s and 1s,
respecitvely. This allows us to write:
```cpp
// No offsets and no strides - implicitly set to 0s and 1s,
// respectively.
tensor::InsertSliceOp::create(rewriter, loc, src, dest, writeSizes);
```
instead of:
```cpp
// Strides are initialised explicitly to 1s
Attribute oneIdxAttr = rewriter.getIndexAttr(1);
SmallVector<OpFoldResult> writeStrides(destRank, oneIdxAttr);
// Offsets are initialised explicitly to 0s
Attribute zeroIdxAttr = rewriter.getIndexAttr(0);
SmallVector<OpFoldResult> writeOffsets(destRank, zeroIdxAttr);
tensor::InsertSliceOp::create(rewriter, loc, src, dest, writeOffsets,
writeSizes, writeStrides);
```
Commit: 76079ecc891e2781168d9a92a4ff024aaffa77db
https://github.com/llvm/llvm-project/commit/76079ecc891e2781168d9a92a4ff024aaffa77db
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaExprCXX.cpp
A clang/test/Sema/AArch64/sve-vector-conditional-op.cpp
Log Message:
-----------
[clang][Sema] Merge Check[Sizeless]VectorConditionalTypes implementations (#169165)
These two functions are almost identical, except for the handling
different vector types, so merging them eliminates some duplication.
This also fixes some bugs, as "sizeless" vector code was missing checks
for several cases.
This meant type checking would crash if:
- The LHS or RHS type was void
- The LHS or RHS type was a fixed-length vector type
- There was not a scalable vector type for the result element count/size
These are fixed with this patch and tested in
Sema/AArch64/sve-vector-conditional-op.cpp.
Fixes #169025
Commit: 63e4b8c64105ea429f0d35f82b8492d6526b8c54
https://github.com/llvm/llvm-project/commit/63e4b8c64105ea429f0d35f82b8492d6526b8c54
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
Log Message:
-----------
[clang][bytecode][NFC] Remove unused Integral range functions (#169508)
Commit: f481f5bef90d0dd10a9d885b2e4bbfd015e6606d
https://github.com/llvm/llvm-project/commit/f481f5bef90d0dd10a9d885b2e4bbfd015e6606d
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
M flang/test/Lower/OpenMP/delayed-privatization-reduction-byref.f90
M flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array-lb.f90
M flang/test/Lower/OpenMP/parallel-reduction-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array2.f90
M flang/test/Lower/OpenMP/parallel-reduction-pointer-array.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/reduction-array-intrinsic.f90
M flang/test/Lower/OpenMP/sections-array-reduction.f90
M flang/test/Lower/OpenMP/taskgroup-task-array-reduction.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-lb.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-lb2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-multiple-clauses.f90
M flang/test/Lower/OpenMP/wsloop-reduction-pointer.f90
M flang/test/Lower/do_concurrent_reduce_allocatable.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/allocatable_gpu_reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-block-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-reduction.mlir
Log Message:
-----------
[OpenMP][flang] Add initial support for by-ref reductions on the GPU (#165714)
Adds initial support for GPU by-ref reductions. The main problem for
reduction by reference is that, prior to this PR, we were shuffling
(from remote lanes within the same warp or across different warps within
the block) pointers/references to the private reduction values rather
than the private reduction values themselves.
In particular, this diff adds support for reductions on scalar
allocatables where reductions happen on loops nested in `target`
regions. For example:
```fortran
integer :: i
real, allocatable :: scalar_alloc
allocate(scalar_alloc)
scalar_alloc = 0
!$omp target map(tofrom: scalar_alloc)
!$omp parallel do reduction(+: scalar_alloc)
do i = 1, 1000000
scalar_alloc = scalar_alloc + 1
end do
!$omp end target
```
This PR supports by-ref reductions on the intra- and inter-warp levels.
So far, there are still steps to be takens for full support of by-ref
reductions, for example:
* Support inter-block value combination is still not supported.
Therefore, `target teams distribute parallel do` is still not supported.
* Support for dynamically-sized arrays still needs to be added.
* Support for more than one allocatable/array on the same `reduction`
clause.
Commit: c43ac96331bc309c2a92ae20a7ae5fadfecbd073
https://github.com/llvm/llvm-project/commit/c43ac96331bc309c2a92ae20a7ae5fadfecbd073
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaAttr.cpp
Log Message:
-----------
[LifetimeSafety] Move GSL pointer/owner type detection to LifetimeAnnotations (#169620)
Refactored GSL pointer and owner type detection functions to improve code organization and reusability.
Commit: 3036de77239f0b29b3619ff6e468ccf5845c7e91
https://github.com/llvm/llvm-project/commit/3036de77239f0b29b3619ff6e468ccf5845c7e91
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
A llvm/test/Analysis/LoopCacheAnalysis/crash-after-pr164798.ll
Log Message:
-----------
[LoopCacheAnalysis] Fix crash after #164798 (#169486)
Fix the assertion failure after #164798. The issue is that the
comparison `Sizes.back() == ElementSize` can fail when their types are
different. We should cast them to the wider type before the comparison.
Commit: c0a7b15d0158a79786a38f5e94fa8315d4c9f0fe
https://github.com/llvm/llvm-project/commit/c0a7b15d0158a79786a38f5e94fa8315d4c9f0fe
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/pr39160.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-uniform-load.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/nsw-crash.ll
M llvm/test/Transforms/LoopVectorize/scev-exitlim-crash.ll
M llvm/test/Transforms/LoopVectorize/value-ptr-bug.ll
M llvm/test/Transforms/LoopVectorize/vector-to-scalar-cast.ll
M llvm/test/Transforms/LoopVectorize/version-mem-access.ll
Log Message:
-----------
[LV][NFC] Remove remaining uses of undef in tests (#169357)
Split off from PR #163525, this standalone patch replaces almost all the
remaining cases where undef is used as value in loop vectoriser tests.
This will reduce the likelihood of contributors hitting the `undef
deprecator` warning in github.
NOTE: The remaining use of undef in iv_outside_user.ll will be fixed in
a separate PR.
I've removed the test stride_undef from version-mem-access.ll, since
there is already a stride_poison test.
Commit: 04bddda08ab2126f74c902f6630c133382170001
https://github.com/llvm/llvm-project/commit/04bddda08ab2126f74c902f6630c133382170001
Author: Steven Perron <stevenperron at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-array.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-simple.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-struct.ll
Log Message:
-----------
[SPIRV] Improve Logical SPIR-V Pointer Access and GEP Legalization (#169076)
This commit improves the handling of GetElementPtr (GEP) instructions
for
Logical SPIR-V. It includes:
- Rewriting of GEPs that are not allowed in Logical SPIR-V
(specifically,
handling non-zero first indices by rebuilding access chains or adjusting
types).
- Better deduction of element types for pointer casting.
- Updates to instruction selection to ensure GEPs are correctly lowered
to
OpAccessChain or OpInBoundsAccessChain only when valid (e.g. first index
0).
- Support for standard HLSL cbuffer layouts in tests.
Commit: 2d4a8dadba88889ca19adee4fbf907d8c5a40282
https://github.com/llvm/llvm-project/commit/2d4a8dadba88889ca19adee4fbf907d8c5a40282
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilogue-vectorization-fix-scalar-resume-values.ll
M llvm/test/Transforms/LoopVectorize/AArch64/f128-fmuladd-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/licm-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr151664-cost-hoisted-vector-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-fixed-width-inorder-core.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-multi-block.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-unroll.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-loop-backedge-elimination-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/LoongArch/defaults.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
M llvm/test/Transforms/LoopVectorize/X86/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-step.ll
M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
M llvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll
M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
M llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/pr23997.ll
M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
M llvm/test/Transforms/LoopVectorize/X86/pr47437.ll
M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/X86/widened-value-used-as-scalar-and-first-lane.ll
M llvm/test/Transforms/LoopVectorize/assume.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/cse-casts.ll
M llvm/test/Transforms/LoopVectorize/cse-gep-source-element-type.ll
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
M llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
M llvm/test/Transforms/LoopVectorize/expand-scev-after-invoke.ll
M llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
M llvm/test/Transforms/LoopVectorize/if-reduction.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleave-with-i65-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-nested-loop.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/minimumnum-maximumnum-reductions.ll
M llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/noalias-scope-decl.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/pr37248.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-odd-interleave-counts.ll
M llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/reverse-induction-gep-nowrap-flags.ll
M llvm/test/Transforms/LoopVectorize/reverse_induction.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
M llvm/test/Transforms/LoopVectorize/select-cmp.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-hint.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
M llvm/test/Transforms/LoopVectorize/struct-return-replicate.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-outside-iv-users.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll
A llvm/test/Transforms/LoopVectorize/vector-pointer-gep-idxty-addrspace.ll
Log Message:
-----------
[VPlan] Use DL index type consistently for GEPs (#169396)
In preparation to strip VPUnrollPartAccessor and unroll recipes
directly, strip unnecessary complication in getGEPIndexTy, as the unroll
part will no longer be available in follow-ups (see #168886 for
instance). The patch also helps by doing a mass test update up-front.
Narrowing the GEP index type conditionally does not yield any benefit,
and the change is non-functional in terms of emitted assembly. While at
it, avoid hard-coding address-space 0, and use the pointer operand's
address space to get the GEP index type.
Commit: 800da10a3a697922042303daa4fe3e06aea34729
https://github.com/llvm/llvm-project/commit/800da10a3a697922042303daa4fe3e06aea34729
Author: J. Ryan Stinnett <jryans at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DebugOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/DebugInfo/Generic/dbg-info-all-calls-described.c
M clang/test/Driver/debug-options.c
Log Message:
-----------
[clang][DebugInfo] Add call site debug info flag (#169574)
This adds a default enabled flag to control attachment of call site
debug info. `-gno-call-site-info` can be used to disable this feature
when needed.
This should help those concerned about debug info size in
https://github.com/llvm/llvm-project/issues/168851.
Commit: d090311aa7df7cbd93412c31685893aefc4ad341
https://github.com/llvm/llvm-project/commit/d090311aa7df7cbd93412c31685893aefc4ad341
Author: Naveen Seth Hanig <naveen.hanig at outlook.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/Compiler.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/CommonArgs.h
A clang/include/clang/Driver/CreateASTUnitFromArgs.h
A clang/include/clang/Driver/CreateInvocationFromArgs.h
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Frontend/CompilerInvocation.h
A clang/include/clang/Frontend/StandaloneDiagnostic.h
M clang/include/clang/Frontend/Utils.h
M clang/include/clang/Options/OptionUtils.h
M clang/lib/CrossTU/CMakeLists.txt
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Driver/CMakeLists.txt
A clang/lib/Driver/CreateASTUnitFromArgs.cpp
A clang/lib/Driver/CreateInvocationFromArgs.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CMakeLists.txt
M clang/lib/Frontend/CompilerInvocation.cpp
R clang/lib/Frontend/CreateInvocationFromCommandLine.cpp
A clang/lib/Frontend/StandaloneDiagnostic.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Options/OptionUtils.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/tools/c-index-test/CMakeLists.txt
M clang/tools/c-index-test/core_main.cpp
M clang/tools/diagtool/CMakeLists.txt
M clang/tools/diagtool/ShowEnabledWarnings.cpp
M clang/tools/driver/cc1_main.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexer.cpp
M clang/tools/libclang/CMakeLists.txt
M clang/tools/libclang/Indexing.cpp
M clang/unittests/Driver/DXCModeTest.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M clang/unittests/Frontend/UtilsTest.cpp
M clang/unittests/Sema/CMakeLists.txt
M clang/unittests/Sema/SemaNoloadLookupTest.cpp
M clang/unittests/Serialization/ForceCheckFileInputTest.cpp
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Serialization/NoCommentsTest.cpp
M clang/unittests/Serialization/PreambleInNamedModulesTest.cpp
M clang/unittests/Serialization/VarDeclConstantInitTest.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
M clang/unittests/Tooling/Syntax/TreeTestBase.cpp
M flang/lib/Frontend/CMakeLists.txt
M flang/lib/Frontend/CompilerInvocation.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangHost.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/unittests/Expression/ClangParserTest.cpp
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
Reland "[clang] Refactor to remove clangDriver dependency from clangFrontend and flangFrontend" (#169599)
This relands #165277 by reverting #169397.
This also relands the corresponding Bazel port by reverting #169410.
The original revert was due to a report of a broken build, which was
later resolved by fully clearing the build directory.
Commit: cc1c41724ddab0112937e30e1eaa984595b7f48e
https://github.com/llvm/llvm-project/commit/cc1c41724ddab0112937e30e1eaa984595b7f48e
Author: daniilavdeev <daniilavdeev237 at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
Log Message:
-----------
[dwarf] make dwarf fission compatible with RISCV relaxations 2/2 (#164813)
This patch makes DWARF fission compatible with RISC-V relaxations by
using indirect addressing for the DW_AT_high_pc attribute. This
eliminates the remaining relocations in .dwo files.
Commit: bbbe511ea2f8d6e4f3977ef1bb28a4fb30323f9a
https://github.com/llvm/llvm-project/commit/bbbe511ea2f8d6e4f3977ef1bb28a4fb30323f9a
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
A clang/test/Driver/hip-spirv-backend-bindings.c
A clang/test/Driver/hip-spirv-backend-opt.c
A clang/test/Driver/hip-spirv-backend-phases.c
Log Message:
-----------
Reland "[clang][Driver] Support for the SPIR-V backend when compiling HIP" (#169637)
This relands "[clang][Driver] Support for the SPIR-V backend when compiling HIP" #167543. The only new change is a small fix for the multicall driver.
For HIP, the SPIR-V backend can be optionally activated with the -use-spirv-backend flag. This option uses the SPIR-V BE instead of the SPIR-V translator. These changes also ensure that -use-spirv-backend does not require external dependencies, such as spirv-as and spirv-link
Commit: 2b8d363ac1a8cca21c32afc039cb28f0f1608300
https://github.com/llvm/llvm-project/commit/2b8d363ac1a8cca21c32afc039cb28f0f1608300
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/Delinearization.h
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/lib/Analysis/Delinearization.cpp
Log Message:
-----------
[Delinearization] Remove tryDelinearizeFixedSizeImpl (#169046)
`tryDelinearizeFixedSizeImpl` is a heuristic function relying on GEP's
type information. Using these information to drive an optimization
heuristic is not allowed, so this function should be removed. As #161822
and #164798 have eliminated all calls to this, this patch removes the
function itself.
Commit: 23f90304507612fde6d4afb79e58dd4283b7be49
https://github.com/llvm/llvm-project/commit/23f90304507612fde6d4afb79e58dd4283b7be49
Author: Md Abdullah Shahneous Bari <md.abdullah.shahneous.bari at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
Reland: [GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`. (#169573)
`convert-vector-to-llvm` pass applies a set of vector transformation
patterns that are not included in the standard `convert-to-llvm` pass
interface. These additional transformations are required to properly
lower MLIR vector operations. Since not all vector ops have direct
`llvm` dialect lowering, many of them must first be progressively
rewritten into simpler or more canonical vector ops, which are then
lowered to `llvm`. Therefore, running `convert-vector-to-llvm` is
necessary to ensure a complete and correct lowering of vector operations
to the `llvm` dialect.
Original PR: https://github.com/llvm/llvm-project/pull/166204 +
post-commit failure fixes.
Commit: 0a35f44f58f322dece584265e252e21b3ca03530
https://github.com/llvm/llvm-project/commit/0a35f44f58f322dece584265e252e21b3ca03530
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaExpr.cpp
M clang/test/SemaHIP/amdgpu-gfx950-load-to-lds.hip
Log Message:
-----------
[HIP] Perform implicit pointer cast when compiling HIP, not when -fcuda-is-device (#165387)
When compiling HIP device code, we add implicit casts for the pointer arguments passed to built-in calls.
When compiling for the host, apply the same casts, since the device side of the source (device functions and kernels) should still pass type checks.
Commit: e3de8ff548a84645141fe16fad156525604c12ca
https://github.com/llvm/llvm-project/commit/e3de8ff548a84645141fe16fad156525604c12ca
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
Log Message:
-----------
[gn build] Port d090311aa7df
Commit: 4cc8cc81e3aa10e01ce6d54321cbddbc64f1bd15
https://github.com/llvm/llvm-project/commit/4cc8cc81e3aa10e01ce6d54321cbddbc64f1bd15
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads.ll
Log Message:
-----------
[VPlan] Hoist predicated loads with complementary masks. (#168373)
This patch adds a new VPlan transformation to hoist predicated loads, if
we can prove they execute unconditionally, i.e. there are 2 predicated
loads to the same address with complementary masks. Then we are
guaranteed to execute one of them on each iteration, allowing us to
remove the mask.
The transform groups masked replicating loads by their address SCEV,
then checks if there are 2 loads with complementary mask. If that is the
case, we check if there are any writes that may alias the load address
in the blocks between the first and last load with the same address.
The transforms operates after linearizing the CFG, but before
introducing replicate regions, which means this is just checking a chain
of consecutive blocks.
Currently this only uses noalias metadata to check for no-alias (using
the helpers added in https://github.com/llvm/llvm-project/pull/166247).
Then we create an unpredicated VPReplicateRecipe at the position of the
first load, then replace all users of the grouped loads with it.
Small Alive2 proof for hoisting with complementary masks:
https://alive2.llvm.org/ce/z/kUx742
PR: https://github.com/llvm/llvm-project/pull/168373
Commit: 637f206241756e769c5cf84da27aacc217549a52
https://github.com/llvm/llvm-project/commit/637f206241756e769c5cf84da27aacc217549a52
Author: Marco Elver <elver at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
M llvm/include/llvm/Support/AllocToken.h
M llvm/lib/Support/AllocToken.cpp
Log Message:
-----------
[Support] Add getAllocTokenModeAsString() helper (#169650)
Add a helper function getAllocTokenModeAsString() to convert
AllocTokenMode values to their string representation.
NFC.
Commit: b20d35c4a2b01090e54b8732a3a9d5b69de3e10c
https://github.com/llvm/llvm-project/commit/b20d35c4a2b01090e54b8732a3a9d5b69de3e10c
Author: David Green <david.green at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/addtruncshift.ll
Log Message:
-----------
[AArch64] Combine vector add(trunc(shift)) (#169523)
This adds a combine for
add(trunc(ashr(A, C)), trunc(lshr(A, BW-1))), with C >= BW
->
X = trunc(ashr(A, C)); add(x, lshr(X, BW-1)
The original converts into ashr+lshr+xtn+xtn+add. The second becomes
ashr+xtn+usra. The first form has less total latency due to more
parallelism,
but more micro-ops and seems to be slower in practice.
Commit: cd1ad5a9e08800043f03f73348b56372a983afa2
https://github.com/llvm/llvm-project/commit/cd1ad5a9e08800043f03f73348b56372a983afa2
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
Log Message:
-----------
[CIR] Add missing switch cases for AO__scoped_atomic_uinc/udec_wrap in emitAtomicOp (#169610)
Fix build error: enumeration values 'AO__scoped_atomic_udec_wrap' and
'AO__scoped_atomic_uinc_wrap' not handled in switch [-Werror,-Wswitch]
The two builtins were added in 5d38cddc3b00.
Commit: de4e12849bae65699f705bbf10110366ab36dfc4
https://github.com/llvm/llvm-project/commit/de4e12849bae65699f705bbf10110366ab36dfc4
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
[BOLT] Fix assertion test (#169635)
The AArch64_BTI MCPlusBuilder unittest was failing in no assertion
builds. Add `#ifndef NDEBUG` to exclude the assertion test from
no assertion builds.
Commit: 75ae0e882d923fd08360380e010935dd3e960a1b
https://github.com/llvm/llvm-project/commit/75ae0e882d923fd08360380e010935dd3e960a1b
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[OpenMP] Add docs for fb_nullify/fb_preserve (#169558)
Adding documentation following the merge of
https://github.com/llvm/llvm-project/pull/168905.
Commit: ff0c347d003098db82db312d5da8ac925c0002dd
https://github.com/llvm/llvm-project/commit/ff0c347d003098db82db312d5da8ac925c0002dd
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
A llvm/test/tools/opt/infer-data-layout-target-abi.ll
M llvm/tools/opt/optdriver.cpp
Log Message:
-----------
opt: Try to respect target-abi command line option (#169604)
Mips seems kind of broken with these options. n32 seems to
override the 64-bit arch with 32-bit pointers, and trying
to use any 32-bit mips triple also just errors with any
options.
Commit: 35dfeb7b4d720f16e9ded25527a0631d63736d78
https://github.com/llvm/llvm-project/commit/35dfeb7b4d720f16e9ded25527a0631d63736d78
Author: Steven Perron <stevenperron at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/SPIRV/OpVariable_order.ll
M llvm/test/CodeGen/SPIRV/SpecConstants/restore-spec-type.ll
M llvm/test/CodeGen/SPIRV/basic_float_types.ll
M llvm/test/CodeGen/SPIRV/basic_int_types.ll
M llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll
M llvm/test/CodeGen/SPIRV/builtin_intrinsics_32.ll
M llvm/test/CodeGen/SPIRV/builtin_intrinsics_64.ll
M llvm/test/CodeGen/SPIRV/builtin_vars-decorate.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
M llvm/test/CodeGen/SPIRV/event-zero-const.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/decoration.ll
M llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
M llvm/test/CodeGen/SPIRV/freeze.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/AddUint64.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll
M llvm/test/CodeGen/SPIRV/instructions/insertvalue-undef-ptr.ll
M llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll
R llvm/test/CodeGen/SPIRV/keep-tracked-const.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/bitreverse_small_type.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/lifetime.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/uadd.with.overflow.ll
M llvm/test/CodeGen/SPIRV/logical-access-chain.ll
M llvm/test/CodeGen/SPIRV/logical-struct-access.ll
M llvm/test/CodeGen/SPIRV/phi-insert-point.ll
M llvm/test/CodeGen/SPIRV/phi-ptrcast-dominate.ll
M llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll
M llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll
M llvm/test/CodeGen/SPIRV/pointers/gep-types-1.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll
M llvm/test/CodeGen/SPIRV/pointers/global-addrspacecast.ll
M llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll
M llvm/test/CodeGen/SPIRV/pointers/phi-chain-types.ll
M llvm/test/CodeGen/SPIRV/pointers/pointer-addrspacecast.ll
M llvm/test/CodeGen/SPIRV/pointers/ptr-eq-types.ll
M llvm/test/CodeGen/SPIRV/pointers/resource-vector-load-store.ll
M llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll
A llvm/test/CodeGen/SPIRV/remove-dead-type-intrinsics.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse-subbyte.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpGenericCastToPtr.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpPtrCastToGeneric.ll
M llvm/test/CodeGen/SPIRV/transcoding/fcmp.ll
M llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll
M llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
Log Message:
-----------
[SPIRV] Enable DCE in instruction selection and update tests (#168428)
The instruction selection pass for SPIR-V now performs dead code
elimination (DCE).
This change removes unused instructions, leading to more optimized
SPIR-V output.
As a consequence of this, several tests were updated to ensure their
continued
correctness and to prevent previously tested code from being optimized
away.
Specifically:
- Many tests now store computed values into global variables to ensure
they are
not eliminated by DCE, allowing their code generation to be verified.
- The test `keep-tracked-const.ll` was removed because it no longer
tested
its original intent. The check statements in this test were for
constants
generated when expanding a G_TRUNC instruction, which is now removed by
DCE
instead of being expanded.
- A new test, `remove-dead-type-intrinsics.ll`, was added to confirm
that dead
struct types are correctly removed by the compiler.
These updates improve the SPIR-V backends optimization capabilities and
maintain the robustness of the test suite.
---------
Co-authored-by: Nathan Gauër <github at keenuts.net>
Commit: 0c2701fe7fa002e1befc5f86c268a7964f96d286
https://github.com/llvm/llvm-project/commit/0c2701fe7fa002e1befc5f86c268a7964f96d286
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AMDGPU/R600.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/ARM/ARM.td
M llvm/lib/Target/AVR/AVR.td
M llvm/lib/Target/BPF/BPF.td
M llvm/lib/Target/CSKY/CSKY.td
M llvm/lib/Target/DirectX/DirectX.td
M llvm/lib/Target/Hexagon/Hexagon.td
M llvm/lib/Target/Lanai/Lanai.td
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/M68k/M68k.td
M llvm/lib/Target/MSP430/MSP430.td
M llvm/lib/Target/Mips/Mips.td
M llvm/lib/Target/NVPTX/NVPTX.td
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/SPIRV/SPIRV.td
M llvm/lib/Target/Sparc/Sparc.td
M llvm/lib/Target/SystemZ/SystemZ.td
M llvm/lib/Target/VE/VE.td
M llvm/lib/Target/WebAssembly/WebAssembly.td
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/XCore/XCore.td
M llvm/lib/Target/Xtensa/Xtensa.td
Log Message:
-----------
CodeGen: Make all targets override pseudos with pointers (#159881)
This eliminates the need to have PointerLikeRegClass handling in
codegen.
Commit: 6e983e3876afe5e502d96cef3d4b0fbb7cd068ed
https://github.com/llvm/llvm-project/commit/6e983e3876afe5e502d96cef3d4b0fbb7cd068ed
Author: Steven Perron <stevenperron at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVIRMapping.h
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-peeled-array-minimal.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-peeled-array.ll
Log Message:
-----------
[SPIRV] Support Peeled Array Layouts for HLSL CBuffers (#169078)
This commit adds support for 'peeled arrays' in HLSL constant buffers.
HLSL CBuffers may have padding between array elements but not after the
last element. This is represented in LLVM IR as {[N-1 x {T, pad}], T}.
Changes include:
- Recognition of the peeled array pattern.
- Logic to reconstitute these into SPIR-V compatible arrays.
- Support for spirv.Padding type in GlobalRegistry and Builtins.
- Updates to SPIRVCBufferAccess to correctly calculate member offsets
in these padded structures.
Depends on https://github.com/llvm/llvm-project/pull/169076
Commit: e7bcd80e5bbc9c4c287d835a1df46742ba0fc3e9
https://github.com/llvm/llvm-project/commit/e7bcd80e5bbc9c4c287d835a1df46742ba0fc3e9
Author: Steven Perron <stevenperron at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/logical-memcpy.ll
Log Message:
-----------
[SPIRV] Use OpCopyMemory for logical SPIRV memcpy (#169348)
This commit modifies the SPIRV instruction selector to emit
`OpCopyMemory`
instead of `OpCopyMemorySized` when generating SPIRV for logical
addressing.
Previously, `G_MEMCPY` was translated to `OpCopyMemorySized`, which
requires an
explicit size operand. However, for logical SPIRV, the size of the
pointee type
is implicitly known. This change ensures that `OpCopyMemory` is used,
which is
more appropriate for logical SPIRV and aligns with the SPIR-V
specification for
logical addressing.
Commit: 7bf459bce34280273942e4a75ce9eab4d4b4e496
https://github.com/llvm/llvm-project/commit/7bf459bce34280273942e4a75ce9eab4d4b4e496
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/TableGen/DuplicateFieldValues.td
M llvm/test/TableGen/RegClassByHwMode.td
M llvm/test/TableGen/def-multiple-operands.td
M llvm/test/TableGen/get-named-operand-idx.td
M llvm/test/TableGen/get-operand-type-no-expand.td
M llvm/test/TableGen/get-operand-type.td
M llvm/test/TableGen/target-specialized-pseudos.td
M llvm/utils/TableGen/InstrInfoEmitter.cpp
Log Message:
-----------
CodeGen: Make target overrides of PointerLikeRegClass mandatory (#159882)
Most targets should now use the convenience multiclass to fixup
the operand definitions of pointer-using pseudoinstructions:
defm : RemapAllTargetPseudoPointerOperands<target_ptr_regclass>;
Commit: 9b88cd9945c5077f0d07f04cd9c9e8e146c48a1b
https://github.com/llvm/llvm-project/commit/9b88cd9945c5077f0d07f04cd9c9e8e146c48a1b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCInstrDesc.h
M llvm/include/llvm/Target/Target.td
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/InstructionEncoding.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/InstrInfoEmitter.cpp
Log Message:
-----------
CodeGen: Remove PointerLikeRegClass handling from codegen (#159883)
All uses have been migrated to RegClassByHwMode. This is now
an implementation detail of InstrInfoEmitter for pseudoinstructions.
Commit: 43e69b18920ecabcf7c6c5fb898f9b18120200f2
https://github.com/llvm/llvm-project/commit/43e69b18920ecabcf7c6c5fb898f9b18120200f2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/basic.ll
Log Message:
-----------
RuntimeLibcalls: Add malloc and free entries (#167081)
Calloc was already here, but not the others. Also add
manual type information.
Commit: 59b3d1814afca973d1417ed2f1d5dac4af3de636
https://github.com/llvm/llvm-project/commit/59b3d1814afca973d1417ed2f1d5dac4af3de636
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
Log Message:
-----------
RuntimeLibcalls: Add more function entries from TargetLibraryInfo (#167082)
Script scraped dump of most functions in TargetLibraryInfo.def,
with existing entries and a few special cases removed. This only
adds the definitions, and doesn't add them to any system yet.
Adding them in the correct places is the hard part, since it's
all written as opt-out with manually written exemptions in
TargetLibraryInfo.
Commit: 9e1d3cac8562fab0a62c1ab19228da5ff6fb26c5
https://github.com/llvm/llvm-project/commit/9e1d3cac8562fab0a62c1ab19228da5ff6fb26c5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/darwin.ll
Log Message:
-----------
RuntimeLibcalls: Add memset_pattern* calls to darwin systems (#167083)
This is one of the easier cases to comprehend in TargetLibraryInfo's
setup.
Commit: e8b9d4217046727845d107c6d4e4ff275e6ee1b4
https://github.com/llvm/llvm-project/commit/e8b9d4217046727845d107c6d4e4ff275e6ee1b4
Author: anoopkg6 <anoop.kumar6 at ibm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Linux.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/tysan/tysan_platform.h
Log Message:
-----------
[tysan] Type Sanitizer support for SystemZ (#162396)
Type Sanitizer support for SystemZ.
Co-authored-by: anoopkg6 <anoopkg6 at github.com>
Commit: 44c9d3a6f5d155ce7d934244dd673b7a8cd5296b
https://github.com/llvm/llvm-project/commit/44c9d3a6f5d155ce7d934244dd673b7a8cd5296b
Author: anoopkg6 <anoop.kumar6 at ibm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Linux.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
Log Message:
-----------
[scudo] Add scudo_standalone support for SystemZ (#166187)
Add Support for scudo_standalone for SystemZ without enabling gwp_asan.
Co-authored-by: anoopkg6 <anoopkg6 at github.com>
Commit: c333f7dab9f89734777f7d19bc7b68c86f393216
https://github.com/llvm/llvm-project/commit/c333f7dab9f89734777f7d19bc7b68c86f393216
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
Log Message:
-----------
[mlir][xegpu] Add layout based SIMT distribution support for `vector.extract/insert_strided_slice` (#168626)
This PR adds general SIMT distribution support for
`vector.extract/insert_strided_slice`. Currently vector distribution
already have support for these operations but have restrictions to avoid
requiring layouts during distribution logic. For example,
`extract_stride_slice` require that distributed dimension is fully
extracted. However, more complex cases may require extracting partially
from distributed dimension (eg. 8x16xf16 extraction from 8x32xf16).
These types of cases need the layouts to reason about how the data is
spread across SIMT lanes.
Currently, we don't have layout access in vector distribution so these
new patterns are place in XeGPU side. They have higher pattern benefit
so that they will be tried first before trying regular vector
distribution based patterns.
Commit: 96cbbebc20dc62e6a780952e3745f67aaefcdf13
https://github.com/llvm/llvm-project/commit/96cbbebc20dc62e6a780952e3745f67aaefcdf13
Author: Shaoce SUN <sunshaoce at outlook.com>
Date: 2025-11-27 (Thu, 27 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
Log Message:
-----------
[MC][RISCV] Add missing Predicates for NDS_FMV_BF16_X (#169662)
run
```shell
build/bin/llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-index=-1
```
error:
```
---
mode: latency
key:
instructions:
- 'NDS_FMV_BF16_X F2_H X11'
- 'NDS_FMV_X_BF16 X26 F2_H'
config: ''
register_initial_values:
- 'X11=0x0'
cpu_name: generic
llvm_triple: riscv64-unknown-linux-gnu
min_instructions: 10000
measurements: []
error: actual measurements skipped.
info: Repeating two instructions
assembled_snippet: 41116AE48145538105F0530D01E0538105F0530D01E0538105F0530D01E0538105F0530D01E0226D41018280
...
LLVM ERROR: Attempting to emit FMV_H_X instruction but the Feature_HasHalfFPLoadStoreMove predicate(s) are not met
```
Commit: 071d1fb8beda4c0ec9ede0acab12a382f34758fe
https://github.com/llvm/llvm-project/commit/071d1fb8beda4c0ec9ede0acab12a382f34758fe
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[LV] Use VPReductionRecipe for partial reductions (#147513)
Partial reductions can easily be represented by the VPReductionRecipe
class by setting their scale factor to something greater than 1. This PR
merges the two together and gives VPReductionRecipe a VFScaleFactor so
that it can choose to generate the partial reduction intrinsic at
execute time.
Stacked PRs:
1. https://github.com/llvm/llvm-project/pull/147026
2. https://github.com/llvm/llvm-project/pull/147255
3. https://github.com/llvm/llvm-project/pull/156976
4. https://github.com/llvm/llvm-project/pull/160154
5. https://github.com/llvm/llvm-project/pull/147302
6. https://github.com/llvm/llvm-project/pull/162503
7. -> https://github.com/llvm/llvm-project/pull/147513
Replaces https://github.com/llvm/llvm-project/pull/146073 .
Commit: 7c3c8dabd6ddcbf153ff2c7024ba1164524e5423
https://github.com/llvm/llvm-project/commit/7c3c8dabd6ddcbf153ff2c7024ba1164524e5423
Author: daniilavdeev <daniilavdeev237 at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/test/Driver/riscv-features.c
Log Message:
-----------
Revert [Driver] Error for -gsplit-dwarf with RISC-V linker relaxation (#169653)
This patch reverts 80a4e6fd31a06143b83947785ea3bd5c04344ea6
After the relevant patches clang now supports dwarf fission with RISC-V
linker relaxations, so we can remove the related driver error.
Commit: 9bd30e2f272536e82730b115720fa807d7be9be9
https://github.com/llvm/llvm-project/commit/9bd30e2f272536e82730b115720fa807d7be9be9
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fully-unrolled-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll
Log Message:
-----------
[AArch64] Enable maximising scalable vector bandwidth (#166748)
This PR enables maximising scalable vector bandwidth for all AArch64
cores other than the V1 and N2. Those two have shown small regressions
that we'll investigate, fix and then enable.
Commit: e99029ef0f0f0bacd8b734058e9cf2be971f16de
https://github.com/llvm/llvm-project/commit/e99029ef0f0f0bacd8b734058e9cf2be971f16de
Author: Kaitlin Peng <kaitlinpeng at microsoft.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h
M clang/test/CodeGenHLSL/builtins/faceforward.hlsl
Log Message:
-----------
[HLSL] Remove `faceforward` SPIRV fast path (#169547)
Commit: cca66a21c20537171712b3adf35b4b82de5f2ad5
https://github.com/llvm/llvm-project/commit/cca66a21c20537171712b3adf35b4b82de5f2ad5
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][BTI] Add MCPlusBuilder::updateBTIVariant (#167308)
Checks if an instruction is BTI, and updates the immediate value to the
newly requested variant.
This can be used in situations when the compiler already inserted a BTI
landing pad to a location, but BOLT needs to update it to a different
variant.
Example: br x0 to a location with a BTI c.
Commit: b78b5ba225c121fb4463791bcbdd78be19e49213
https://github.com/llvm/llvm-project/commit/b78b5ba225c121fb4463791bcbdd78be19e49213
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
R llvm/test/MC/PowerPC/ppc64-encoding-ISA31-errors.s
M llvm/test/MC/PowerPC/ppc64-errors.s
Log Message:
-----------
[NFC][PowerPC] Merge ppc64 encoding error tests (#169669)
Based on the RUN lines, there is actually no need for different versions
of these error files since no cpu specific
option needed. Combine to reduce confusion and maintenance as these are
not huge files.
Commit: 356479191ca001df47136c89cc9a761c64a6323c
https://github.com/llvm/llvm-project/commit/356479191ca001df47136c89cc9a761c64a6323c
Author: Lucie Choi <clucie at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
A llvm/test/Transforms/IndVarSimplify/skip-predication-convergence.ll
A llvm/test/Transforms/IndVarSimplify/skip-predication-nested-convergence.ll
Log Message:
-----------
[IndVarSimplify] Fix `IndVarSimplify` to skip unfolding predicates when the loop contains control convergence operations. (#165643)
Skip constant folding the loop predicates if the loop contains control
convergence tokens referenced outside the loop.
Fixes https://github.com/llvm/llvm-project/issues/164496.
Verified
[loop_peeling.test](https://github.com/llvm/offload-test-suite/pull/473)
passes with the fix.
Similar control convergence issues are found on other passes.
https://github.com/llvm/llvm-project/issues/165642
HLSL used for tests:
```hlsl
RWStructuredBuffer<uint> Out : register(u0);
[numthreads(8,1,1)]
void main(uint3 TID : SV_GroupThreadID) {
for (uint i = 0; i < 8; i++) {
if (i == TID.x) {
Out[TID.x] = WaveActiveMax(TID.x);
break;
}
}
}
```
With nested loop:
```hlsl
RWStructuredBuffer<uint> Out : register(u0);
[numthreads(8,8,1)]
void main(uint3 TID : SV_GroupThreadID) {
for (uint i = 0; i < 8; i++) {
for (uint j = 0; j < 8; j++) {
if (i == TID.x && j == TID.y) {
uint index = TID.x * 8 + TID.y;
Out[index] = WaveActiveMax(index);
break;
}
}
}
}
```
Commit: 84d511df8dcdd6da00be41b250312d84b5de41a7
https://github.com/llvm/llvm-project/commit/84d511df8dcdd6da00be41b250312d84b5de41a7
Author: Jason-VanBeusekom <jason.van-beusekom at hpe.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M offload/include/omptarget.h
M offload/libomptarget/PluginManager.cpp
M offload/libomptarget/device.cpp
A offload/test/api/omp_indirect_call_table_manual.c
Log Message:
-----------
[OpenMP][clang] Register vtables on device for indirect calls runtime (#167011)
This is a branch off of
https://github.com/llvm/llvm-project/pull/159856, in which consists of
the runtime portion of the changes required to support indirect function
and virtual function calls on an `omp target device` when the virtual
class / indirect function is mapped to the device from the host.
Key Changes
- Introduced a new flag OMP_DECLARE_TARGET_INDIRECT_VTABLE to mark
VTable registrations
- Modified setupIndirectCallTable to support both VTable entries and
indirect function pointers
Details:
The setupIndirectCallTable implementation was modified to support this
registration type by retrieving the first address of the VTable and
inferring the remaining data needed to build the indirect call table.
Since the Vtables / Classes registered as indirect can be larger than 8
bytes, and the vtables may not be at the first address we either need to
pass the size to __llvm_omp_indirect_call_lookup and have a check at
each step of the binary search, or add multiple entries to the indirect
table for each address registered. The latter was chosen.
Commit: a00def3f20e166d4fb9328e6f0bc0742cd0afa31 is not a part of this
PR and is handled / reviewed in:
https://github.com/llvm/llvm-project/pull/159856,
This is PR (2/3)
Register Vtable PR (1/3):
https://github.com/llvm/llvm-project/pull/159856,
Codegen / _llvm_omp_indirect_call_lookup PR (3/3):
https://github.com/llvm/llvm-project/pull/159857
Commit: 954fa0f9bae73a2214d1d5079d6c3c028dca42ce
https://github.com/llvm/llvm-project/commit/954fa0f9bae73a2214d1d5079d6c3c028dca42ce
Author: Moritz Zielke <moritz.zielke at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
Log Message:
-----------
[Clang] Allow AVX/AVX512 subvector shuffles in constexpr (#168700)
Resolves #160514
Enables usage of the following x86 intrinsics in `constexpr`:
```
_mm256_shuffle_i64x2 _mm256_mask_shuffle_i64x2 _mm256_maskz_shuffle_i64x2
_mm256_shuffle_f64x2 _mm256_mask_shuffle_f64x2 _mm256_maskz_shuffle_f64x2
_mm512_shuffle_i64x2 _mm512_mask_shuffle_i64x2 _mm512_maskz_shuffle_i64x2
_mm512_shuffle_f64x2 _mm512_mask_shuffle_f64x2 _mm512_maskz_shuffle_f64x2
_mm256_shuffle_i32x4 _mm256_mask_shuffle_i32x4 _mm256_maskz_shuffle_i32x4
_mm256_shuffle_f32x4 _mm256_mask_shuffle_f32x4 _mm256_maskz_shuffle_f32x4
_mm512_shuffle_i32x4 _mm512_mask_shuffle_i32x4 _mm512_maskz_shuffle_i32x4
_mm512_shuffle_f32x4 _mm512_mask_shuffle_f32x4 _mm512_maskz_shuffle_f32x4
```
Commit: 411a53e16fbc9bfe23fd887c918c3ec5d74fa2bc
https://github.com/llvm/llvm-project/commit/411a53e16fbc9bfe23fd887c918c3ec5d74fa2bc
Author: Letu Ren <fantasquex at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/builtins-floating-point.c
Log Message:
-----------
[CIR] Upstream Builtin Exp2Op (#169152)
Add the cir::exp2 operation and handling for the related builtins.
Commit: 0940f686dc332557f0368290ebc3d9aff1f36714
https://github.com/llvm/llvm-project/commit/0940f686dc332557f0368290ebc3d9aff1f36714
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/unittests/Support/JobserverTest.cpp
Log Message:
-----------
Move static test variable into the #if that uses it (#169695)
Fixes -Wunused-variable when compiling without LLVM_ENABLE_THREADS
Commit: c98e867822d8e741159ff0be09ccc2a5c7841a28
https://github.com/llvm/llvm-project/commit/c98e867822d8e741159ff0be09ccc2a5c7841a28
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaType.cpp
M clang/test/SemaCXX/return.cpp
Log Message:
-----------
[Clang] Fix false positive -Wignored-qualifiers (#169664)
A deduced return type can be an object type, in which case `const` can
have an effect.
Delay the diagnostic to the point at which the type is deduced.
Add tests for lambdas.
Fixes #43054
Note that there is a discussion in #43054 about adding a separate
warning for "const return types are weird" for the class type cases, but
it would have to be a separate warning - warning which currently exists
in clang-tidy as `readability-const-return-type`.
Commit: 18805b6ce9a4887ea6a19ce7e4f8fc943a716ec5
https://github.com/llvm/llvm-project/commit/18805b6ce9a4887ea6a19ce7e4f8fc943a716ec5
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/test/CIR/CodeGen/count-of.c
Log Message:
-----------
[CIR] CountOf VLA with Array element type (#169404)
Implement CountOf on VariableArrayType with IntegerConstant SizeExpr
Commit: 587e279a880add8017bdc9484c3bf9030fdcec8f
https://github.com/llvm/llvm-project/commit/587e279a880add8017bdc9484c3bf9030fdcec8f
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
Log Message:
-----------
[CIR][NFC] Cleanup builtin helper function interfaces (#169586)
A couple of builtin helper functions were taking a clang::Expr argument
but only using it to build an MLIR location. This change updates these
functions to take a location directly.
Commit: 5ab3375b2cf461ab02704d129a1f4d5ba1a1e275
https://github.com/llvm/llvm-project/commit/5ab3375b2cf461ab02704d129a1f4d5ba1a1e275
Author: Janet Yang <qxy11 at meta.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lldb/include/lldb/API/SBTarget.h
M lldb/include/lldb/Target/Target.h
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/source/API/SBTarget.cpp
M lldb/source/Target/Target.cpp
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
M lldb/test/API/tools/lldb-dap/startDebugging/TestDAP_startDebugging.py
M lldb/tools/lldb-dap/CMakeLists.txt
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPForward.h
A lldb/tools/lldb-dap/DAPSessionManager.cpp
A lldb/tools/lldb-dap/DAPSessionManager.h
M lldb/tools/lldb-dap/EventHelper.cpp
M lldb/tools/lldb-dap/EventHelper.h
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/LaunchRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/package.json
M lldb/tools/lldb-dap/tool/lldb-dap.cpp
M lldb/unittests/DAP/CMakeLists.txt
A lldb/unittests/DAP/DAPSessionManagerTest.cpp
M llvm/utils/gn/secondary/lldb/tools/lldb-dap/BUILD.gn
Log Message:
-----------
[lldb-dap] Add multi-session support with shared debugger instances (#163653)
## Summary:
This change introduces a `DAPSessionManager` to enable multiple DAP
sessions to share debugger instances when needed, for things like child
process debugging and some scripting hooks that create dynamically new
targets.
Changes include:
- Add `DAPSessionManager` singleton to track and coordinate all active DAP
sessions
- Support attaching to an existing target via its globally unique target
ID (targetId parameter)
- Share debugger instances across sessions when new targets are created
dynamically
- Refactor event thread management to allow sharing event threads
between sessions and move event thread and event thread handlers to `EventHelpers`
- Add `eBroadcastBitNewTargetCreated` event to notify when new targets are
created
- Extract session names from target creation events
- Defer debugger initialization from 'initialize' request to
'launch'/'attach' requests. The only time the debugger is used currently
in between its creation in `InitializeRequestHandler` and the `Launch`
or `Attach` requests is during the `TelemetryDispatcher` destruction
call at the end of the `DAP::HandleObject` call, so this is safe.
This enables scenarios when new targets are created dynamically so that
the debug adapter can automatically start a new debug session for the
spawned target while sharing the debugger instance.
## Tests:
The refactoring maintains backward compatibility. All existing DAP test
cases pass.
Also added a few basic unit tests for DAPSessionManager
```
>> ninja DAPTests
>> ./tools/lldb/unittests/DAP/DAPTests
>>./bin/llvm-lit -v ../llvm-project/lldb/test/API/tools/lldb-dap/
```
Commit: bf43b95025124017b37aa8fd0ee7dc94ac4d670e
https://github.com/llvm/llvm-project/commit/bf43b95025124017b37aa8fd0ee7dc94ac4d670e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.h
Log Message:
-----------
[flang][OpenMP] Remove unused #include "dump-parse-tree.h", NFC (#169708)
Commit: a059afafde068773693c1fab4d89c208b1437f76
https://github.com/llvm/llvm-project/commit/a059afafde068773693c1fab4d89c208b1437f76
Author: Igor Kudrin <ikudrin at accesssoftek.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lldb/source/Target/Process.cpp
M lldb/source/Target/Target.cpp
M lldb/unittests/Target/MemoryTest.cpp
Log Message:
-----------
[lldb] Fix reading 32-bit signed integers (#169150)
Both `Target::ReadSignedIntegerFromMemory()` and
`Process::ReadSignedIntegerFromMemory()` internally created an unsigned
scalar, so extending the value later did not duplicate the sign bit.
Commit: 66e18b86b8b1e98eeb71d7ab57cb09a26dff6b96
https://github.com/llvm/llvm-project/commit/66e18b86b8b1e98eeb71d7ab57cb09a26dff6b96
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/user-with-multi-copyable-ops.ll
Log Message:
-----------
[SLP][NFC]Add a test with single op inst, used in many nodes, NFC.
Commit: d09644a294c8393eb7a2cc586762a8d3f60b5aeb
https://github.com/llvm/llvm-project/commit/d09644a294c8393eb7a2cc586762a8d3f60b5aeb
Author: Ravil Dorozhinskii <ravil.aviva.com at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[ROCDL] Added missing `cluster.load.async.to.lds` op (gfx1250) (#169042)
* Added missing cluster.load ops with different sizes. Extended all
rocdl tests
Commit: 72e51d389f66d9cc6b55fd74b56fbbd087672a43
https://github.com/llvm/llvm-project/commit/72e51d389f66d9cc6b55fd74b56fbbd087672a43
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
Log Message:
-----------
Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)"
This reverts commit a6edeedbfa308876d6f2b1648729d52970bb07e6.
The following fixes have landed, addressing issues causing the original
revert:
* https://github.com/llvm/llvm-project/pull/169298
* https://github.com/llvm/llvm-project/pull/167897
* https://github.com/llvm/llvm-project/pull/168949
Original message:
Building on top of https://github.com/llvm/llvm-project/pull/148817,
introduce a new abstract LastActiveLane opcode that gets lowered to
Not(Mask) → FirstActiveLane(NotMask) → Sub(result, 1).
When folding the tail, update all extracts for uses outside the loop the
extract the value of the last actice lane.
See also https://github.com/llvm/llvm-project/issues/148603
PR: https://github.com/llvm/llvm-project/pull/149042
Commit: 684f64c0baca15c84e222c0f7c7455e8c505e575
https://github.com/llvm/llvm-project/commit/684f64c0baca15c84e222c0f7c7455e8c505e575
Author: n2h9 <13541181+n2h9 at users.noreply.github.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/builders/darwin.py
Log Message:
-----------
[lldb] [test-suite] fix typo in variable in darwin builder (#169254)
While taking a look at the code of lldb test-suite packages, I have
noticed that in `get_triple_str` in `darwin.py` env is added inside a
`components` list, which is probably supposed to be `component` (defined
on the line 61).
Signed-off-by: Nikita B <n2h9z4 at gmail.com>
Commit: a4d42775b9af0d961f71934e38342a9384534022
https://github.com/llvm/llvm-project/commit/a4d42775b9af0d961f71934e38342a9384534022
Author: n2h9 <13541181+n2h9 at users.noreply.github.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lldb/bindings/interface/SBTargetExtensions.i
M lldb/examples/python/templates/scripted_process.py
M lldb/include/lldb/API/SBTarget.h
M lldb/source/API/SBTarget.cpp
M lldb/test/API/python_api/target/TestTargetAPI.py
Log Message:
-----------
[lldb] [scripting bridge] 167388 chore: add api to return arch name for target (#168273)
This pr fixes #167388 .
## Description
This pr adds new method `GetArchName` to `SBTarget` so that no need to
parse triple to get arch name in client code.
## Testing
### All from `TestTargetAPI.py`
run test with
```
./build/bin/lldb-dotest -v -p TestTargetAPI.py
```
<details>
<summary>existing tests (without newly added)</summary>
<img width="1425" height="804" alt="image"
src="https://github.com/user-attachments/assets/617e4c69-5c6b-44c4-9aeb-b751a47e253c"
/>
</details>
<details>
<summary>existing tests (with newly added)</summary>
<img width="1422" height="778" alt="image"
src="https://github.com/user-attachments/assets/746990a1-df88-4348-a090-224963d3c640"
/>
</details>
### Only `test_get_arch_name`
run test with
```
./build/bin/lldb-dotest -v -p TestTargetAPI.py -f test_get_arch_name_dwarf -f test_get_arch_name_dwo -f test_get_arch_name_dsym lldb/test/API/python_api/target
```
<details>
<summary>only newly added</summary>
<img width="1422" height="778" alt="image"
src="https://github.com/user-attachments/assets/fcaafa5d-2622-4171-acee-e104ecee0652"
/>
</details>
---------
Signed-off-by: Nikita B <n2h9z4 at gmail.com>
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: d58ebe339c920e1a90f4fd87b0873a119e5f9d05
https://github.com/llvm/llvm-project/commit/d58ebe339c920e1a90f4fd87b0873a119e5f9d05
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
Log Message:
-----------
Revert "Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)""
This reverts commit 72e51d389f66d9cc6b55fd74b56fbbd087672a43.
Missed some test updates.
Commit: 9af00e62ecc33960ada5366bffc369a647699fe9
https://github.com/llvm/llvm-project/commit/9af00e62ecc33960ada5366bffc369a647699fe9
Author: Erick Ochoa Lopez <erick.ochoalopez at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/test/Dialect/AMDGPU/ops.mlir
Log Message:
-----------
[mlir][amdgpu] Add make_dma_base operation (#169086)
Commit: cabcb5ae55f117d15f41aed8f064dc528ddc9e8f
https://github.com/llvm/llvm-project/commit/cabcb5ae55f117d15f41aed8f064dc528ddc9e8f
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
Log Message:
-----------
[CIR][NFC] Fix build problem inside an assert (#169715)
A recent change introduced a failure in debug builds due to an incorrect
level of indirection inside an assert. This fixes that.
Commit: f8eca64a2820553ffc22c58ac39c2e5c14888e61
https://github.com/llvm/llvm-project/commit/f8eca64a2820553ffc22c58ac39c2e5c14888e61
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
Log Message:
-----------
Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)"
This reverts commit a6edeedbfa308876d6f2b1648729d52970bb07e6.
The following fixes have landed, addressing issues causing the original
revert:
* https://github.com/llvm/llvm-project/pull/169298
* https://github.com/llvm/llvm-project/pull/167897
* https://github.com/llvm/llvm-project/pull/168949
Original message:
Building on top of https://github.com/llvm/llvm-project/pull/148817,
introduce a new abstract LastActiveLane opcode that gets lowered to
Not(Mask) → FirstActiveLane(NotMask) → Sub(result, 1).
When folding the tail, update all extracts for uses outside the loop the
extract the value of the last actice lane.
See also https://github.com/llvm/llvm-project/issues/148603
PR: https://github.com/llvm/llvm-project/pull/149042
Commit: cec837e3e09f7751e668c89aed894d547d542ae6
https://github.com/llvm/llvm-project/commit/cec837e3e09f7751e668c89aed894d547d542ae6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/CodeGen/X86/addcarry.ll
Log Message:
-----------
[X86] addcarry.ll - add test coverage for #169691 (#169716)
Commit: bbb8f7aaf8c2cc7f68b59ed0d5abed068c581682
https://github.com/llvm/llvm-project/commit/bbb8f7aaf8c2cc7f68b59ed0d5abed068c581682
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M libcxx/include/__flat_map/flat_map.h
M libcxx/include/__flat_map/utils.h
M libcxx/test/libcxx/diagnostics/flat_map.nodiscard.verify.cpp
M libcxx/test/std/containers/container.adaptors/flat.map/flat.map.access/index_transparent.pass.cpp
Log Message:
-----------
[libc++][flat_map] Applied `[[nodiscard]]` (#169453)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 8706d82bd420fdfb95e207df6d56f73274ec7d20
https://github.com/llvm/llvm-project/commit/8706d82bd420fdfb95e207df6d56f73274ec7d20
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M libcxx/include/__compare/is_eq.h
M libcxx/include/__coroutine/coroutine_handle.h
M libcxx/include/__coroutine/noop_coroutine_handle.h
M libcxx/include/__utility/cmp.h
M libcxx/include/initializer_list
M libcxx/test/libcxx/diagnostics/utility.nodiscard.verify.cpp
A libcxx/test/libcxx/language.support/nodiscard.verify.cpp
Log Message:
-----------
[libc++] Applied `[[nodiscard]]` to Language Support (partially) (#169611)
https://wg21.link/#support
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
The following was implemented in this patch:
- [x] `<compare>`
- [x] `<corotine>`
- [x] `<initializer_list>`
- [x] Integer comparisons
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Co-authored-by: A. Jiang <de34 at live.cn>
Commit: 3a25a4a68705d7861c5b0312667f3bc43359da41
https://github.com/llvm/llvm-project/commit/3a25a4a68705d7861c5b0312667f3bc43359da41
Author: Björn Schäpers <bjoern at hazardy.de>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/Format.cpp
M clang/lib/Format/IntegerLiteralSeparatorFixer.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/IntegerLiteralSeparatorTest.cpp
Log Message:
-----------
[clang-format] Add xxxMaxDigitsNoSeparator (#164286)
This basically adds a Leave option for a specific range of literals.
Commit: c378bb135455787a5d8b1f4da5d3522a3e6a60b9
https://github.com/llvm/llvm-project/commit/c378bb135455787a5d8b1f4da5d3522a3e6a60b9
Author: Peter Collingbourne <pcc at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
A llvm/test/CodeGen/AArch64/ptrauth-irelative.ll
M llvm/test/CodeGen/AArch64/ptrauth-type-info-vptr-discr.ll
Log Message:
-----------
CodeGen: Optionally emit PAuth relocations as IRELATIVE relocations.
This supports the following use cases:
- ConstantPtrAuth expressions that are unrepresentable using standard PAuth
relocations such as expressions involving an integer operand or
deactivation symbols.
- libc implementations that do not support PAuth relocations.
For more information see the RFC:
https://discourse.llvm.org/t/rfc-structure-protection-a-family-of-uaf-mitigation-techniques/85555
Reviewers: MaskRay, fmayer, smithp35, kovdan01
Reviewed By: fmayer
Pull Request: https://github.com/llvm/llvm-project/pull/133533
Commit: 8c6798f7e739b12d938c4f9cb745d574b1d601e9
https://github.com/llvm/llvm-project/commit/8c6798f7e739b12d938c4f9cb745d574b1d601e9
Author: Peter Collingbourne <pcc at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M .github/workflows/gha-codeql.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/llvm-abi-tests.yml
M .github/workflows/scorecard.yml
M .gitignore
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/test/X86/lit.local.cfg
M bolt/test/lit.local.cfg
M bolt/unittests/Core/MCPlusBuilder.cpp
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/Compiler.cpp
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/cmake/caches/Fuchsia.cmake
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/DebugOptions.def
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenMPKinds.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Basic/arm_mve_defs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/CommonArgs.h
A clang/include/clang/Driver/CreateASTUnitFromArgs.h
A clang/include/clang/Driver/CreateInvocationFromArgs.h
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Format/Format.h
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Frontend/CompilerInvocation.h
A clang/include/clang/Frontend/StandaloneDiagnostic.h
M clang/include/clang/Frontend/Utils.h
M clang/include/clang/Options/OptionUtils.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaARM.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/lib/AST/ByteCode/BitcastBuffer.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Program.h
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/CFG.cpp
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
M clang/lib/Analysis/ThreadSafety.cpp
M clang/lib/CIR/CodeGen/Address.h
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/lib/CIR/CodeGen/CIRGenOpenACCHelpers.h
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACCLoop.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CrossTU/CMakeLists.txt
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Driver/CMakeLists.txt
A clang/lib/Driver/CreateASTUnitFromArgs.cpp
A clang/lib/Driver/CreateInvocationFromArgs.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/IntegerLiteralSeparatorFixer.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CMakeLists.txt
M clang/lib/Frontend/CompilerInvocation.cpp
R clang/lib/Frontend/CreateInvocationFromCommandLine.cpp
A clang/lib/Frontend/StandaloneDiagnostic.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Options/OptionUtils.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/StaticAnalyzer/Core/CheckerHelpers.cpp
M clang/lib/StaticAnalyzer/Core/LoopUnrolling.cpp
M clang/lib/Tooling/Tooling.cpp
A clang/test/AST/ast-dump-APValue-addrlabeldiff.c
M clang/test/Analysis/lifetime-cfg-output.cpp
M clang/test/Analysis/loop-unrolling.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
A clang/test/Analysis/std-c-library-functions-eof-2-rad.c
M clang/test/CIR/CodeGen/builtins-floating-point.c
A clang/test/CIR/CodeGen/copy-constructor.cpp
M clang/test/CIR/CodeGen/coro-task.cpp
A clang/test/CIR/CodeGen/count-of.c
A clang/test/CIR/CodeGen/placement-new.cpp
M clang/test/CIR/CodeGen/vector-ext-element.cpp
M clang/test/CIR/CodeGenOpenACC/combined-copy.c
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-copy.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copyin.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
M clang/test/CIR/CodeGenOpenACC/declare-create.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceptr.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceresident.cpp
M clang/test/CIR/CodeGenOpenACC/declare-link.cpp
M clang/test/CIR/CodeGenOpenACC/declare-present.cpp
M clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/openacc-not-implemented-global.cpp
R clang/test/CIR/CodeGenOpenACC/openacc-not-implemented.cpp
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
M clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
M clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
A clang/test/CodeGen/memprof-pgho.cpp
M clang/test/CodeGen/scoped-atomic-ops.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
M clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
A clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
M clang/test/CodeGenHLSL/builtins/faceforward.hlsl
M clang/test/DebugInfo/Generic/dbg-info-all-calls-described.c
M clang/test/Driver/debug-options.c
A clang/test/Driver/hip-spirv-backend-bindings.c
A clang/test/Driver/hip-spirv-backend-opt.c
A clang/test/Driver/hip-spirv-backend-phases.c
M clang/test/Driver/riscv-features.c
A clang/test/OpenMP/need_device_ptr_kind_ast_print.cpp
A clang/test/OpenMP/need_device_ptr_kind_messages.cpp
A clang/test/Sema/AArch64/builtin_vectorelements.c
A clang/test/Sema/AArch64/sve-vector-conditional-op.cpp
M clang/test/Sema/scoped-atomic-ops.c
M clang/test/Sema/warn-lifetime-safety.cpp
A clang/test/SemaCXX/no-warn-thread-safety-analysis.cpp
M clang/test/SemaCXX/return.cpp
M clang/test/SemaHIP/amdgpu-gfx950-load-to-lds.hip
M clang/tools/c-index-test/CMakeLists.txt
M clang/tools/c-index-test/core_main.cpp
M clang/tools/diagtool/CMakeLists.txt
M clang/tools/diagtool/ShowEnabledWarnings.cpp
M clang/tools/driver/cc1_main.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexer.cpp
M clang/tools/libclang/CMakeLists.txt
M clang/tools/libclang/Indexing.cpp
M clang/unittests/Analysis/FlowSensitive/LoggerTest.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
M clang/unittests/Driver/DXCModeTest.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/IntegerLiteralSeparatorTest.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M clang/unittests/Frontend/UtilsTest.cpp
M clang/unittests/Sema/CMakeLists.txt
M clang/unittests/Sema/SemaNoloadLookupTest.cpp
M clang/unittests/Serialization/ForceCheckFileInputTest.cpp
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Serialization/NoCommentsTest.cpp
M clang/unittests/Serialization/PreambleInNamedModulesTest.cpp
M clang/unittests/Serialization/VarDeclConstantInitTest.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
M clang/unittests/Tooling/Syntax/TreeTestBase.cpp
M clang/utils/TableGen/MveEmitter.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/scudo/standalone/tsd_shared.h
M compiler-rt/lib/tysan/tysan_platform.h
M flang-rt/cmake/modules/HandleLibs.cmake
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Frontend/CMakeLists.txt
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Reduction.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCRecipeBufferization.cpp
M flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/FirToSCF/do-loop.fir
M flang/test/Fir/OpenACC/recipe-bufferization.mlir
M flang/test/Lower/CUDA/cuda-atomicadd.cuf
M flang/test/Lower/OpenACC/acc-firstprivate-derived-allocatable-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-pointer-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-user-assign.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
A flang/test/Lower/OpenACC/acc-reduction-remapping.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenACC/do-loops-to-acc-loops.f90
A flang/test/Lower/OpenMP/compiler-directives-loop.f90
M flang/test/Lower/OpenMP/delayed-privatization-reduction-byref.f90
M flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array-lb.f90
M flang/test/Lower/OpenMP/parallel-reduction-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array2.f90
M flang/test/Lower/OpenMP/parallel-reduction-pointer-array.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/reduction-array-intrinsic.f90
M flang/test/Lower/OpenMP/sections-array-reduction.f90
M flang/test/Lower/OpenMP/taskgroup-task-array-reduction.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-lb.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-lb2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-multiple-clauses.f90
M flang/test/Lower/OpenMP/wsloop-reduction-pointer.f90
M flang/test/Lower/do_concurrent_reduce_allocatable.f90
A flang/test/Semantics/OpenMP/target-teams-nesting.f90
M flang/test/Transforms/OpenACC/acc-implicit-copy-reduction.fir
M flang/test/Transforms/OpenACC/acc-implicit-data-fortran.F90
M flang/test/Transforms/OpenACC/acc-implicit-data.fir
M flang/test/Transforms/OpenACC/acc-implicit-firstprivate.fir
M libclc/clc/lib/generic/atomic/clc_atomic_dec.cl
M libclc/clc/lib/generic/atomic/clc_atomic_def.inc
M libclc/clc/lib/generic/atomic/clc_atomic_inc.cl
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/fill_n.h
A libcxx/include/__algorithm/specialized_algorithms.h
M libcxx/include/__bit_reference
M libcxx/include/__compare/is_eq.h
M libcxx/include/__config
M libcxx/include/__configuration/platform.h
M libcxx/include/__coroutine/coroutine_handle.h
M libcxx/include/__coroutine/noop_coroutine_handle.h
M libcxx/include/__flat_map/flat_map.h
M libcxx/include/__flat_map/utils.h
M libcxx/include/__functional/bind.h
M libcxx/include/__functional/bind_back.h
M libcxx/include/__functional/bind_front.h
M libcxx/include/__functional/function.h
M libcxx/include/__functional/mem_fn.h
M libcxx/include/__functional/reference_wrapper.h
M libcxx/include/__random/binomial_distribution.h
M libcxx/include/__utility/cmp.h
M libcxx/include/initializer_list
M libcxx/include/module.modulemap.in
M libcxx/include/stack
M libcxx/src/filesystem/operations.cpp
M libcxx/test/extensions/libcxx/odr_signature.exceptions.sh.cpp
M libcxx/test/extensions/libcxx/odr_signature.hardening.sh.cpp
M libcxx/test/libcxx/diagnostics/flat_map.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/functional.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/stack.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/utility.nodiscard.verify.cpp
A libcxx/test/libcxx/language.support/nodiscard.verify.cpp
M libcxx/test/std/containers/container.adaptors/flat.map/flat.map.access/index_transparent.pass.cpp
M libcxx/test/std/utilities/function.objects/refwrap/refwrap.invoke/robust_against_adl.pass.cpp
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/InputFiles.cpp
M lld/test/MachO/x86-64-relocs.s
M lldb/bindings/interface/SBTargetExtensions.i
M lldb/examples/python/templates/scripted_process.py
M lldb/include/lldb/API/SBStructuredData.h
M lldb/include/lldb/API/SBTarget.h
M lldb/include/lldb/Target/Target.h
M lldb/packages/Python/lldbsuite/test/builders/darwin.py
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/source/API/SBTarget.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangHost.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/Target.cpp
M lldb/test/API/python_api/target/TestTargetAPI.py
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/test/API/tools/lldb-dap/startDebugging/TestDAP_startDebugging.py
M lldb/tools/lldb-dap/CMakeLists.txt
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPForward.h
A lldb/tools/lldb-dap/DAPSessionManager.cpp
A lldb/tools/lldb-dap/DAPSessionManager.h
M lldb/tools/lldb-dap/EventHelper.cpp
M lldb/tools/lldb-dap/EventHelper.h
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/LaunchRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/package.json
M lldb/tools/lldb-dap/tool/lldb-dap.cpp
M lldb/unittests/DAP/CMakeLists.txt
A lldb/unittests/DAP/DAPSessionManagerTest.cpp
M lldb/unittests/Expression/ClangParserTest.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
M lldb/unittests/Target/MemoryTest.cpp
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
M llvm/docs/DeveloperPolicy.rst
M llvm/docs/LangRef.rst
M llvm/docs/Vectorizers.rst
M llvm/include/llvm/Analysis/Delinearization.h
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/MC/MCInstrDesc.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCSymbol.h
M llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
M llvm/include/llvm/Support/AllocToken.h
M llvm/include/llvm/Target/Target.td
M llvm/include/llvm/Transforms/Utils/FunctionComparator.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Analysis/Delinearization.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/LibcallLoweringInfo.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/CMakeLists.txt
A llvm/lib/IR/NVVMIntrinsicUtils.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCMachOStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCSymbol.cpp
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
M llvm/lib/MC/MCWasmStreamer.cpp
M llvm/lib/Support/AllocToken.cpp
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp
M llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/R600.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/ARM/ARM.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp
M llvm/lib/Target/AVR/AVR.td
M llvm/lib/Target/BPF/BPF.td
M llvm/lib/Target/CSKY/CSKY.td
M llvm/lib/Target/DirectX/DirectX.td
M llvm/lib/Target/Hexagon/Hexagon.td
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/Lanai.td
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/M68k/M68k.td
M llvm/lib/Target/MSP430/MSP430.td
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.h
M llvm/lib/Target/Mips/Mips.td
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/Mips/Mips16ISelLowering.h
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTX.td
M llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
M llvm/lib/Target/NVPTX/NVPTXTagInvariantLoads.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRV.td
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.cpp
M llvm/lib/Target/SPIRV/SPIRVCombine.td
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVIRMapping.h
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/Sparc/Sparc.td
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.h
M llvm/lib/Target/SystemZ/SystemZ.td
M llvm/lib/Target/VE/VE.td
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssembly.td
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Target/XCore/XCore.td
M llvm/lib/Target/Xtensa/Xtensa.td
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
M llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
A llvm/test/Analysis/LoopCacheAnalysis/crash-after-pr164798.ll
A llvm/test/Analysis/ScalarEvolution/addrec-may-wrap-udiv-canonicalize.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
A llvm/test/CodeGen/AArch64/addtruncshift.ll
M llvm/test/CodeGen/AArch64/combine-sdiv.ll
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
R llvm/test/CodeGen/AArch64/pr151592.mir
R llvm/test/CodeGen/AArch64/pr151888.mir
R llvm/test/CodeGen/AArch64/pr164181-reduced.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
R llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/AArch64/rem-by-const.ll
A llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
M llvm/test/CodeGen/AArch64/sme-zt0-state.ll
M llvm/test/CodeGen/AArch64/srem-lkk.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/add_i1.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-entry.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/cse-convergent.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
A llvm/test/CodeGen/AMDGPU/gws_agpr.ll
M llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
A llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
M llvm/test/CodeGen/AMDGPU/spillv16.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub_i1.ll
M llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
M llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
M llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
A llvm/test/CodeGen/Mips/fp-strict-fcmp.ll
M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
M llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
A llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
A llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
A llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
M llvm/test/CodeGen/PowerPC/combine-fneg.ll
M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
M llvm/test/CodeGen/PowerPC/frem.ll
M llvm/test/CodeGen/PowerPC/froundeven-legalization.ll
M llvm/test/CodeGen/PowerPC/half.ll
M llvm/test/CodeGen/PowerPC/ldexp.ll
M llvm/test/CodeGen/PowerPC/llvm.modf.ll
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vle.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/addcarry.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/allow-check.ll
M llvm/test/CodeGen/RISCV/arith-with-overflow.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bitreverse-shift.ll
M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
M llvm/test/CodeGen/RISCV/bswap-shift.ll
M llvm/test/CodeGen/RISCV/clear-cache.ll
M llvm/test/CodeGen/RISCV/copy-frameindex.mir
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/double-zfa.ll
M llvm/test/CodeGen/RISCV/double_reduct.ll
M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
M llvm/test/CodeGen/RISCV/fixed-csr.ll
M llvm/test/CodeGen/RISCV/float-arith-strict.ll
M llvm/test/CodeGen/RISCV/float-arith.ll
M llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-convert-strict.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/float-select-verify.ll
M llvm/test/CodeGen/RISCV/float-zfa.ll
M llvm/test/CodeGen/RISCV/flt-rounds.ll
A llvm/test/CodeGen/RISCV/fma-combine.ll
M llvm/test/CodeGen/RISCV/fmax-fmin.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/fpenv.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/frm-dependency.ll
M llvm/test/CodeGen/RISCV/get-register-invalid.ll
M llvm/test/CodeGen/RISCV/get-register-noreserve.ll
M llvm/test/CodeGen/RISCV/get-register-reserve.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/half-zfa.ll
M llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
M llvm/test/CodeGen/RISCV/i64-icmp.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll
M llvm/test/CodeGen/RISCV/intrinsics/trap.ll
M llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/machine-combiner.ll
M llvm/test/CodeGen/RISCV/machine-cse.ll
M llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll
M llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
M llvm/test/CodeGen/RISCV/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/memset-inline.ll
M llvm/test/CodeGen/RISCV/min-max.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/module-target-abi3.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsic-optimizations.ll
M llvm/test/CodeGen/RISCV/pei-crash.ll
M llvm/test/CodeGen/RISCV/pr135206.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/pr92193.ll
M llvm/test/CodeGen/RISCV/prefetch.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/readcyclecounter.ll
M llvm/test/CodeGen/RISCV/readsteadycounter.ll
M llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/replace-with-veclib-sleef-scalable.ll
M llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbkx-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
M llvm/test/CodeGen/RISCV/rv64-float-convert.ll
M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-args.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-frame-setup.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
M llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbkx-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
M llvm/test/CodeGen/RISCV/rvv/commutable.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-negative.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvw.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vp-fsub-and-vp-fmul.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
M llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/llround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/lround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/marith-vp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int-e64.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int-e64.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-crash-zvl32b.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mixed-float-bf16-arith.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/pr63459.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
M llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
M llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfwmacc_4x4x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e4m3.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e5m2.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e4m3.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e5m2.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_f_f.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_s.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_u.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_s.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_u.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte16.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte32.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte64.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte8.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettk.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettm.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettnt.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste16.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste32.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste64.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste8.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtdiscard.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_t_v.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_v_t.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtzero_t.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands-i1.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/smulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/splats-with-mixed-vl.ll
M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
M llvm/test/CodeGen/RISCV/rvv/trunc-sat-clip-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/ushl_sat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vadc.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/rvv/vaesdf.ll
M llvm/test/CodeGen/RISCV/rvv/vaesdm.ll
M llvm/test/CodeGen/RISCV/rvv/vaesef.ll
M llvm/test/CodeGen/RISCV/rvv/vaesem.ll
M llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll
M llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll
M llvm/test/CodeGen/RISCV/rvv/vaesz.ll
M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vand.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn.ll
M llvm/test/CodeGen/RISCV/rvv/vasub.ll
M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
M llvm/test/CodeGen/RISCV/rvv/vbrev.ll
M llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
M llvm/test/CodeGen/RISCV/rvv/vclmul.ll
M llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vclz.ll
M llvm/test/CodeGen/RISCV/rvv/vcompress.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/vcpopv.ll
M llvm/test/CodeGen/RISCV/rvv/vctz.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
M llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll
M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vfirst.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/vfmerge-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv-bf-s.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv-s-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv-v-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-bf-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvtbf16-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vfrec7-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfrec7.ll
M llvm/test/CodeGen/RISCV/rvv/vfredmax.ll
M llvm/test/CodeGen/RISCV/rvv/vfredmin.ll
M llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
M llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnj-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjn-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjx-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1down-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1up-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-w-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-bf-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-bf-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvtbf16-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmaccbf16.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
M llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-w-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vghsh.ll
M llvm/test/CodeGen/RISCV/rvv/vgmul.ll
M llvm/test/CodeGen/RISCV/rvv/vid.ll
M llvm/test/CodeGen/RISCV/rvv/viota.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-no-prop.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vle.ll
M llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
M llvm/test/CodeGen/RISCV/rvv/vleff.ll
M llvm/test/CodeGen/RISCV/rvv/vlm.ll
M llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlse.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vmand.ll
M llvm/test/CodeGen/RISCV/rvv/vmandn.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu.ll
M llvm/test/CodeGen/RISCV/rvv/vmclr.ll
M llvm/test/CodeGen/RISCV/rvv/vmerge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu.ll
M llvm/test/CodeGen/RISCV/rvv/vmnand.ll
M llvm/test/CodeGen/RISCV/rvv/vmnor.ll
M llvm/test/CodeGen/RISCV/rvv/vmor.ll
M llvm/test/CodeGen/RISCV/rvv/vmorn.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmset.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsif.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vmsof.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul.ll
M llvm/test/CodeGen/RISCV/rvv/vmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.x.s.ll
M llvm/test/CodeGen/RISCV/rvv/vmxnor.ll
M llvm/test/CodeGen/RISCV/rvv/vmxor.ll
M llvm/test/CodeGen/RISCV/rvv/vnclip.ll
M llvm/test/CodeGen/RISCV/rvv/vnclipu.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vor.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vqdot.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotsu.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotu.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotus.ll
M llvm/test/CodeGen/RISCV/rvv/vredand.ll
M llvm/test/CodeGen/RISCV/rvv/vredmax.ll
M llvm/test/CodeGen/RISCV/rvv/vredmaxu.ll
M llvm/test/CodeGen/RISCV/rvv/vredmin.ll
M llvm/test/CodeGen/RISCV/rvv/vredminu.ll
M llvm/test/CodeGen/RISCV/rvv/vredor.ll
M llvm/test/CodeGen/RISCV/rvv/vredsum.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vredxor.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu.ll
M llvm/test/CodeGen/RISCV/rvv/vrev8.ll
M llvm/test/CodeGen/RISCV/rvv/vrgather.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll
M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrol.ll
M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vror.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
M llvm/test/CodeGen/RISCV/rvv/vse.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-valid-elen-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvlmax-ext.ll
M llvm/test/CodeGen/RISCV/rvv/vsext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsext.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
M llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1down-constant-vl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1up-constant-vl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/vslidedown.ll
M llvm/test/CodeGen/RISCV/rvv/vslideup.ll
M llvm/test/CodeGen/RISCV/rvv/vsll.ll
M llvm/test/CodeGen/RISCV/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/rvv/vsm3c.ll
M llvm/test/CodeGen/RISCV/rvv/vsm3me.ll
M llvm/test/CodeGen/RISCV/rvv/vsm4k.ll
M llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
M llvm/test/CodeGen/RISCV/rvv/vsmul.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsra.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssub.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccus.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/vwredsum.ll
M llvm/test/CodeGen/RISCV/rvv/vwredsumu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vxor.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vzext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vzext.ll
M llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xv.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvv.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvw.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqa.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqasu.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqau.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqaus.ll
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
M llvm/test/CodeGen/RISCV/sadd_sat.ll
M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/saverestore.ll
M llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/simplify-condbr.ll
M llvm/test/CodeGen/RISCV/ssub_sat.ll
M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/thread-pointer.ll
M llvm/test/CodeGen/RISCV/uadd_sat.ll
M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/RISCV/usub_sat.ll
M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
M llvm/test/CodeGen/RISCV/vlenb.ll
M llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xcvalu.ll
M llvm/test/CodeGen/RISCV/xcvbitmanip.ll
M llvm/test/CodeGen/RISCV/xcvmac.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
M llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll
A llvm/test/CodeGen/SPIRV/GlobalISel/InstCombine/prelegalizercombiner-select-to-faceforward.mir
M llvm/test/CodeGen/SPIRV/OpVariable_order.ll
M llvm/test/CodeGen/SPIRV/SpecConstants/restore-spec-type.ll
M llvm/test/CodeGen/SPIRV/basic_float_types.ll
M llvm/test/CodeGen/SPIRV/basic_int_types.ll
M llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll
M llvm/test/CodeGen/SPIRV/builtin_intrinsics_32.ll
M llvm/test/CodeGen/SPIRV/builtin_intrinsics_64.ll
M llvm/test/CodeGen/SPIRV/builtin_vars-decorate.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
M llvm/test/CodeGen/SPIRV/event-zero-const.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/decoration.ll
M llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
M llvm/test/CodeGen/SPIRV/freeze.ll
A llvm/test/CodeGen/SPIRV/function/vararg.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/AddUint64.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/faceforward.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-array.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-peeled-array-minimal.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-peeled-array.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-simple.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-struct.ll
M llvm/test/CodeGen/SPIRV/instructions/insertvalue-undef-ptr.ll
M llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll
R llvm/test/CodeGen/SPIRV/keep-tracked-const.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/bitreverse_small_type.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/lifetime.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/logical-memcpy.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/uadd.with.overflow.ll
M llvm/test/CodeGen/SPIRV/logical-access-chain.ll
M llvm/test/CodeGen/SPIRV/logical-struct-access.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward.ll
M llvm/test/CodeGen/SPIRV/phi-insert-point.ll
M llvm/test/CodeGen/SPIRV/phi-ptrcast-dominate.ll
M llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll
M llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll
M llvm/test/CodeGen/SPIRV/pointers/gep-types-1.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll
M llvm/test/CodeGen/SPIRV/pointers/global-addrspacecast.ll
M llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll
M llvm/test/CodeGen/SPIRV/pointers/phi-chain-types.ll
M llvm/test/CodeGen/SPIRV/pointers/pointer-addrspacecast.ll
M llvm/test/CodeGen/SPIRV/pointers/ptr-eq-types.ll
M llvm/test/CodeGen/SPIRV/pointers/resource-vector-load-store.ll
M llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll
A llvm/test/CodeGen/SPIRV/remove-dead-type-intrinsics.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse-subbyte.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpGenericCastToPtr.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpPtrCastToGeneric.ll
M llvm/test/CodeGen/SPIRV/transcoding/fcmp.ll
M llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll
M llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
A llvm/test/CodeGen/Thumb2/mve-intrinsics/strict-intrinsics.ll
M llvm/test/CodeGen/Thumb2/mve-intrinsics/vabdq.ll
M llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
A llvm/test/CodeGen/X86/GlobalISel/fp-bitcast.ll
M llvm/test/CodeGen/X86/addcarry.ll
M llvm/test/CodeGen/X86/bitcnt-big-integer.ll
R llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
R llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
R llvm/test/CodeGen/X86/pr76416.ll
M llvm/test/CodeGen/X86/setcc-wide-types.ll
M llvm/test/CodeGen/X86/subreg-fail.mir
R llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
A llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
A llvm/test/MC/AMDGPU/ds_gws_sgpr_err.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
R llvm/test/MC/PowerPC/ppc64-encoding-ISA31-errors.s
M llvm/test/MC/PowerPC/ppc64-errors.s
M llvm/test/TableGen/CPtrWildcard.td
M llvm/test/TableGen/DuplicateFieldValues.td
M llvm/test/TableGen/RegClassByHwMode.td
M llvm/test/TableGen/def-multiple-operands.td
M llvm/test/TableGen/get-named-operand-idx.td
M llvm/test/TableGen/get-operand-type-no-expand.td
M llvm/test/TableGen/get-operand-type.td
M llvm/test/TableGen/target-specialized-pseudos.td
A llvm/test/Transforms/IndVarSimplify/skip-predication-convergence.ll
A llvm/test/Transforms/IndVarSimplify/skip-predication-nested-convergence.ll
M llvm/test/Transforms/InstCombine/cast-mul-select.ll
M llvm/test/Transforms/InstCombine/cast.ll
M llvm/test/Transforms/InstCombine/catchswitch-phi.ll
M llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
M llvm/test/Transforms/InstCombine/known-bits-lerp-pattern.ll
M llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
M llvm/test/Transforms/InstCombine/logical-select.ll
M llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilogue-vectorization-fix-scalar-resume-values.ll
M llvm/test/Transforms/LoopVectorize/AArch64/f128-fmuladd-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fully-unrolled-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/licm-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/mul-simplification.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr151664-cost-hoisted-vector-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-fixed-width-inorder-core.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-multi-block.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-unroll.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-loop-backedge-elimination-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll
M llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
M llvm/test/Transforms/LoopVectorize/LoongArch/defaults.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
M llvm/test/Transforms/LoopVectorize/X86/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-step.ll
M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
M llvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll
M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
M llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/pr23997.ll
M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
M llvm/test/Transforms/LoopVectorize/X86/pr39160.ll
M llvm/test/Transforms/LoopVectorize/X86/pr47437.ll
M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/X86/widened-value-used-as-scalar-and-first-lane.ll
M llvm/test/Transforms/LoopVectorize/assume.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/cse-casts.ll
M llvm/test/Transforms/LoopVectorize/cse-gep-source-element-type.ll
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
M llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
M llvm/test/Transforms/LoopVectorize/expand-scev-after-invoke.ll
M llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/if-reduction.ll
M llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleave-with-i65-induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-uniform-load.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-nested-loop.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/minimumnum-maximumnum-reductions.ll
M llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/noalias-scope-decl.ll
M llvm/test/Transforms/LoopVectorize/nsw-crash.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/pr37248.ll
M llvm/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-odd-interleave-counts.ll
M llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/reverse-induction-gep-nowrap-flags.ll
M llvm/test/Transforms/LoopVectorize/reverse_induction.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/scev-exitlim-crash.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
M llvm/test/Transforms/LoopVectorize/select-cmp.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-cond-poison.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-hint.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
M llvm/test/Transforms/LoopVectorize/struct-return-replicate.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
M llvm/test/Transforms/LoopVectorize/value-ptr-bug.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-outside-iv-users.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll
A llvm/test/Transforms/LoopVectorize/vector-pointer-gep-idxty-addrspace.ll
M llvm/test/Transforms/LoopVectorize/vector-to-scalar-cast.ll
A llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
M llvm/test/Transforms/LoopVectorize/version-mem-access.ll
M llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-struct-return.ll
A llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll
A llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
A llvm/test/Transforms/SLPVectorizer/X86/user-with-multi-copyable-ops.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-i8-gep.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-var-delta.ll
R llvm/test/Transforms/StraightLineStrengthReduce/path-compression.ll
R llvm/test/Transforms/StraightLineStrengthReduce/pick-candidate.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/basic.ll
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/darwin.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/merge_attributes.ll
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/ps.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sincos_stret.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sleef.ll
M llvm/test/Verifier/llvm.loop.estimated_trip_count.ll
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
A llvm/test/tools/opt/infer-data-layout-target-abi.ll
M llvm/test/tools/opt/invalid-target.ll
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
M llvm/tools/opt/optdriver.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/Support/JobserverTest.cpp
M llvm/unittests/Transforms/Utils/LoopUtilsTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/InstructionEncoding.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/InstrInfoEmitter.cpp
M llvm/utils/git/github-automation.py
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/tools/lldb-dap/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
M mlir/include/mlir/Analysis/DataFlow/IntegerRangeAnalysis.h
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/include/mlir/Dialect/Tosa/Utils/QuantUtils.h
M mlir/include/mlir/TableGen/Pattern.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/GPU/Pipelines/CMakeLists.txt
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Utils/QuantUtils.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/lib/TableGen/Pattern.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Dialect/AMDGPU/ops.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-data-reduction.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
M mlir/test/Dialect/OpenACC/invalid.mlir
M mlir/test/Dialect/OpenACC/legalize-data.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/quant-test.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
M mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
A mlir/test/Target/LLVMIR/allocatable_gpu_reduction.mlir
A mlir/test/Target/LLVMIR/anonymous-tbaa.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_arrive.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_arrive_drop.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_complete_tx.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_expect_tx.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_init.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_invalid.mlir
R mlir/test/Target/LLVMIR/nvvm/mbarriers.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-block-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-reduction.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M mlir/test/python/ir/operation.py
M mlir/tools/mlir-tblgen/RewriterGen.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCOpsInterfacesTest.cpp
M offload/include/OpenMP/InteropAPI.h
M offload/include/PerThreadTable.h
M offload/include/omptarget.h
M offload/libomptarget/PluginManager.cpp
M offload/libomptarget/device.cpp
A offload/test/api/omp_indirect_call_table_manual.c
M offload/test/offloading/shared_lib_fp_mapping.c
M offload/test/offloading/static_linking.c
M orc-rt/include/orc-rt/Error.h
M orc-rt/include/orc-rt/Session.h
M orc-rt/lib/executor/Session.cpp
M orc-rt/unittests/ErrorTest.cpp
M orc-rt/unittests/SessionTest.cpp
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/extensions.bzl
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
M utils/bazel/third_party_build/zlib-ng.BUILD
Log Message:
-----------
[𝘀𝗽𝗿] landed version
Created using spr 1.3.6-beta.1
Compare: https://github.com/llvm/llvm-project/compare/9ddfc41b0fd0...8c6798f7e739
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