[all-commits] [llvm/llvm-project] b8ef25: [PGO] Fix zeroed estimated trip count (#167792)
Marco Elver via All-commits
all-commits at lists.llvm.org
Wed Nov 26 07:52:23 PST 2025
Branch: refs/heads/users/melver/spr/main.clangcodegen-move-alloctoken-pass-to-backend-lto-phases
Home: https://github.com/llvm/llvm-project
Commit: b8ef25aa643761233dc5b74d9fb7c38a2064d9c7
https://github.com/llvm/llvm-project/commit/b8ef25aa643761233dc5b74d9fb7c38a2064d9c7
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Transforms/Utils/LoopUtils.cpp
A llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
M llvm/test/Verifier/llvm.loop.estimated_trip_count.ll
M llvm/unittests/Transforms/Utils/LoopUtilsTest.cpp
Log Message:
-----------
[PGO] Fix zeroed estimated trip count (#167792)
Before PR #152775, `llvm::getLoopEstimatedTripCount` never returned 0.
If `llvm::setLoopEstimatedTripCount` were called with 0, it would zero
branch weights, causing `llvm::getLoopEstimatedTripCount` to return
`std::nullopt`.
PR #152775 changed that behavior: if `llvm::setLoopEstimatedTripCount`
is called with 0, it sets `llvm.loop.estimated_trip_count` to 0, causing
`llvm::getLoopEstimatedTripCount` to return 0. However, it kept
documentation saying `llvm::getLoopEstimatedTripCount` returns a
positive count.
Some passes continue to assume `llvm::getLoopEstimatedTripCount` never
returns 0 and crash if it does, as reported in issue #164254. To restore
the behavior they expect, this patch changes
`llvm::getLoopEstimatedTripCount` to return `std::nullopt` when
`llvm.loop.estimated_trip_count` is 0.
Commit: c582688b6912c615da1d08630c178dd3d0072aeb
https://github.com/llvm/llvm-project/commit/c582688b6912c615da1d08630c178dd3d0072aeb
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
Log Message:
-----------
[MLIR][tensor] Simplify ExtractSliceOp::inferResultType (nfc) (#169313)
The `offsets` and `strides` arguments are neither used nor required -
removed them and simplify this hook.
Commit: 6d21ce8797317814ad6f2372d98d21c9900f0579
https://github.com/llvm/llvm-project/commit/6d21ce8797317814ad6f2372d98d21c9900f0579
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceresident.cpp
Log Message:
-----------
[OpenACC][CIR] device_resident lowering for NS/global/struct declare (#169507)
This is the same as create/copyin, except it uses
declare_device_resident for the entry op.
Commit: 7b5163d3001613e9c449f7603f4a0f7f521e79a1
https://github.com/llvm/llvm-project/commit/7b5163d3001613e9c449f7603f4a0f7f521e79a1
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
Log Message:
-----------
[lldb][NFC] use llvm::StringRef in `ExtractContextAndIdentifer` function (#169506)
this avoids allocation when checking if a method contains a path.
Commit: e04cca8561c65b9820f2c284eea164ab9fb7cdce
https://github.com/llvm/llvm-project/commit/e04cca8561c65b9820f2c284eea164ab9fb7cdce
Author: Marco Elver <elver at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A clang/test/CodeGen/memprof-pgho.cpp
Log Message:
-----------
[Clang][MemProf] Add end-to-end test for PGHO rewriting (#169243)
Add an end-to-end (non-LTO) test verifying that the optimization
pipeline is set up correctly for Profile Guided Heap Optimization (PGHO)
transforms. Ensure that both PGHO and AllocToken can stack, and the
AllocToken pass does not interfere with PGHO and vice versa.
Commit: 1a036732d210c2b78404067a1aa0b3a3bba3eaf8
https://github.com/llvm/llvm-project/commit/1a036732d210c2b78404067a1aa0b3a3bba3eaf8
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
A clang/test/Driver/hip-spirv-backend-bindings.c
A clang/test/Driver/hip-spirv-backend-opt.c
A clang/test/Driver/hip-spirv-backend-phases.c
Log Message:
-----------
[clang][Driver] Support for the SPIR-V backend when compiling HIP (#167543)
For HIP, the SPIR-V backend can be optionally activated with the -use-spirv-backend flag. This option uses the SPIR-V BE instead of the SPIR-V translator. These changes also ensure that -use-spirv-backend does not require external dependencies, such as spirv-as and spirv-link
Commit: 17852deda7fb9dabb41023e2673025c630b9369d
https://github.com/llvm/llvm-project/commit/17852deda7fb9dabb41023e2673025c630b9369d
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
M llvm/lib/Target/NVPTX/NVPTXTagInvariantLoads.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
M llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
A llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
A llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
A llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
Log Message:
-----------
[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)
This backend support will allow the LoadStoreVectorizer, in certain
cases, to fill in gaps when creating load/store vectors and generate
LLVM masked load/stores
(https://llvm.org/docs/LangRef.html#llvm-masked-store-intrinsics). To
accomplish this, changes are separated into two parts. This first part
has the backend lowering and TTI changes, and a follow up PR will have
the LSV generate these intrinsics:
https://github.com/llvm/llvm-project/pull/159388.
In this backend change, Masked Loads get lowered to PTX with `#pragma
"used_bytes_mask" [mask];`
(https://docs.nvidia.com/cuda/parallel-thread-execution/#pragma-strings-used-bytes-mask).
And Masked Stores get lowered to PTX using the new sink symbol syntax
(https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-st).
# TTI Changes
TTI changes are needed because NVPTX only supports masked loads/stores
with _constant_ masks. `ScalarizeMaskedMemIntrin.cpp` is adjusted to
check that the mask is constant and pass that result into the TTI check.
Behavior shouldn't change for non-NVPTX targets, which do not care
whether the mask is variable or constant when determining legality, but
all TTI files that implement these API need to be updated.
# Masked store lowering implementation details
If the masked stores make it to the NVPTX backend without being
scalarized, they are handled by the following:
* `NVPTXISelLowering.cpp` - Sets up a custom operation action and
handles it in lowerMSTORE. Similar handling to normal store vectors,
except we read the mask and place a sentinel register `$noreg` in each
position where the mask reads as false.
For example,
```
t10: v8i1 = BUILD_VECTOR Constant:i1<-1>, Constant:i1<0>, Constant:i1<0>, Constant:i1<-1>, Constant:i1<-1>, Constant:i1<0>, Constant:i1<0>, Constant:i1<-1>
t11: ch = masked_store<(store unknown-size into %ir.lsr.iv28, align 32, addrspace 1)> t5:1, t5, t7, undef:i64, t10
->
STV_i32_v8 killed %13:int32regs, $noreg, $noreg, killed %16:int32regs, killed %17:int32regs, $noreg, $noreg, killed %20:int32regs, 0, 0, 1, 8, 0, 32, %4:int64regs, 0, debug-location !18 :: (store unknown-size into %ir.lsr.iv28, align 32, addrspace 1);
```
* `NVPTXInstInfo.td` - changes the definition of store vectors to allow
for a mix of sink symbols and registers.
* `NVPXInstPrinter.h/.cpp` - Handles the `$noreg` case by printing "_".
# Masked load lowering implementation details
Masked loads are routed to normal PTX loads, with one difference: a
`#pragma "used_bytes_mask"` is emitted before the load instruction
(https://docs.nvidia.com/cuda/parallel-thread-execution/#pragma-strings-used-bytes-mask).
To accomplish this, a new operand is added to every NVPTXISD Load type
representing this mask.
* `NVPTXISelLowering.h/.cpp` - Masked loads are converted into normal
NVPTXISD loads with a mask operand in two ways. 1) In type legalization
through replaceLoadVector, which is the normal path, and 2) through
LowerMLOAD, to handle the legal vector types
(v2f16/v2bf16/v2i16/v4i8/v2f32) that will not be type legalized. Both
share the same convertMLOADToLoadWithUsedBytesMask helper. Both default
this operand to UINT32_MAX, representing all bytes on. For the latter,
we need a new `NVPTXISD::MLoadV1` type to represent that edge case
because we cannot put the used bytes mask operand on a generic
LoadSDNode.
* `NVPTXISelDAGToDAG.cpp` - Extract used bytes mask from loads, add them
to created machine instructions.
* `NVPTXInstPrinter.h/.cpp` - Print the pragma when the used bytes mask
isn't all ones.
* `NVPTXForwardParams.cpp`, `NVPTXReplaceImageHandles.cpp` - Update
manual indexing of load operands to account for new operand.
* `NVPTXInsrtInfo.td`, `NVPTXIntrinsics.td` - Add the used bytes mask to
the MI definitions.
* `NVPTXTagInvariantLoads.cpp` - Ensure that masked loads also get
tagged as invariant.
Some generic changes that are needed:
* `LegalizeVectorTypes.cpp` - Ensure flags are preserved when splitting
masked loads.
* `SelectionDAGBuilder.cpp` - Preserve `MD_invariant_load` on masked
load SDNode creation
Commit: 6a395fec1f7663e02c6607e8e10791838c949389
https://github.com/llvm/llvm-project/commit/6a395fec1f7663e02c6607e8e10791838c949389
Author: Guy David <guyda96 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
Log Message:
-----------
[AArch64] Mark FMOVvXfY_ns as rematerializable, cheap (#169186)
Commit: b93bb69dfad5f94565d90575a92203a1a2f3395b
https://github.com/llvm/llvm-project/commit/b93bb69dfad5f94565d90575a92203a1a2f3395b
Author: Samira Bakon <bazuzi at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
Log Message:
-----------
[clang][dataflow] Use containers with deterministic iteration order. (#169512)
Commit: eb1ff56e26fdb48728642f7d26e47b337b7235ea
https://github.com/llvm/llvm-project/commit/eb1ff56e26fdb48728642f7d26e47b337b7235ea
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll
Log Message:
-----------
[SLP][NFC]Add a test for copyable operands, used multiple times, NFC
Commit: d69e70149636efa0293310303878fbf9a5f31433
https://github.com/llvm/llvm-project/commit/d69e70149636efa0293310303878fbf9a5f31433
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
Log Message:
-----------
[PGO] Add missing target datalayout in test (#169520)
The test was added by b8ef25aa643761233dc5b74d9fb7c38a2064d9c7. It
failed on at least the following bots, but the failure did not reproduce
on my test machines or in pre-commit CI:
- https://lab.llvm.org/buildbot/#/builders/190/builds/31638
- https://lab.llvm.org/buildbot/#/builders/190/builds/31638
This fix hopefully addresses at least the warnings there.
Commit: 5999cc8ceef3acef128e1baf8fcefd7164acc677
https://github.com/llvm/llvm-project/commit/5999cc8ceef3acef128e1baf8fcefd7164acc677
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/stack
M libcxx/test/libcxx/diagnostics/stack.nodiscard.verify.cpp
Log Message:
-----------
[libc++][stack] Applied `[[nodiscard]]` (#169468)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 1c5b1501ca50e039ae39075465972761449013e9
https://github.com/llvm/llvm-project/commit/1c5b1501ca50e039ae39075465972761449013e9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/lib/CodeGen/LibcallLoweringInfo.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.h
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/Mips/Mips16ISelLowering.h
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.h
Log Message:
-----------
CodeGen: Move libcall lowering configuration to subtarget (#168621)
Previously libcall lowering decisions were made directly
in the TargetLowering constructor. Pull these into the subtarget
to facilitate turning LibcallLoweringInfo into a separate analysis
in the future.
Commit: 5017370a1ce5009aed2855b645194bc141f72a2d
https://github.com/llvm/llvm-project/commit/5017370a1ce5009aed2855b645194bc141f72a2d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/gws_agpr.ll
Log Message:
-----------
AMDGPU: Add baseline test for gws handling with AGPR inputs (#169372)
Commit: a860c8378f91d9b7713171888e76962b2747fe4e
https://github.com/llvm/llvm-project/commit/a860c8378f91d9b7713171888e76962b2747fe4e
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
R clang/test/Driver/hip-spirv-backend-bindings.c
R clang/test/Driver/hip-spirv-backend-opt.c
R clang/test/Driver/hip-spirv-backend-phases.c
Log Message:
-----------
Revert "[clang][Driver] Support for the SPIR-V backend when compiling HIP (#167543)" (#169528)
This reverts commit 1a036732d210c2b78404067a1aa0b3a3bba3eaf8.
Reverted due to a failure in hip-spirv-backend-opt.c for
fuchsia-x86_64-linux.
Commit: 53e5cfdf8b13e2427797ca6eeda1860f8aa190ef
https://github.com/llvm/llvm-project/commit/53e5cfdf8b13e2427797ca6eeda1860f8aa190ef
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/combined-copy.c
M clang/test/CIR/CodeGenOpenACC/compute-copy.c
M clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceptr.cpp
M clang/test/CIR/CodeGenOpenACC/declare-link.cpp
M clang/test/CIR/CodeGenOpenACC/declare-present.cpp
Log Message:
-----------
[OpenACC][CIR] link clause lowering for global declare (#169524)
The 'link' clause is like the rest of the global clauses (copyin,
create, device_resident), except it only has an entry op(thus no
dtor).
This patch also removes a bunch of now stales TODOs from the tests.
Commit: 8380a48aa0b62be28b653ba6b3d38198680b2bd9
https://github.com/llvm/llvm-project/commit/8380a48aa0b62be28b653ba6b3d38198680b2bd9
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
Log Message:
-----------
[PGO] Add REQUIRES to test (#169531)
The test was added by b8ef25aa643761233dc5b74d9fb7c38a2064d9c7. It
failed on at least the following bots, but the failure did not reproduce
on my test machines or in pre-commit CI:
- https://lab.llvm.org/buildbot/#/builders/190/builds/31643
- https://lab.llvm.org/buildbot/#/builders/65/builds/25949
- https://lab.llvm.org/buildbot/#/builders/154/builds/24417
d69e70149636efa0293310303878fbf9a5f31433 did not fix the failure.
Hopefully this will.
Commit: 1441f0458545243f9278cf87a35c4cb4e1cd62bd
https://github.com/llvm/llvm-project/commit/1441f0458545243f9278cf87a35c4cb4e1cd62bd
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/Address.h
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
A clang/test/CIR/CodeGen/placement-new.cpp
Log Message:
-----------
[CIR] Upstream reserved placement new handling (#169436)
This upstreams the code to support reserved placement new calls.
Commit: 45336992453c83d083ccadf62ae56626dfb0f761
https://github.com/llvm/llvm-project/commit/45336992453c83d083ccadf62ae56626dfb0f761
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
Log Message:
-----------
[BOLT][BTI] Add MCPlusBuilder::isBTILandingPad (#167306)
- takes both implicit and explicit BTIs into account
- fix related comment in
llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
Commit: 83d9c636b753ab37842a25606d95d800dce90398
https://github.com/llvm/llvm-project/commit/83d9c636b753ab37842a25606d95d800dce90398
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M utils/bazel/third_party_build/zlib-ng.BUILD
Log Message:
-----------
[bazel] Add alias for zlib-ng for WORKSPACE compat (#169530)
The consumer of zlib in third-party/BUILD.bazel expects zlib-ng from the
BCR, if you still load this version from your WORKSPACE / MODULE.bazel
you need to use this name instead.
Commit: 012721d3200ceed635495394fe96b17bbaa8653e
https://github.com/llvm/llvm-project/commit/012721d3200ceed635495394fe96b17bbaa8653e
Author: Benjamin Chetioui <3920784+bchetioui at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/test/python/ir/operation.py
Log Message:
-----------
[mlir][python] Propagate error diagnostics when an op couldn't be created. (#169499)
Commit: 4877c593a873657cd18a1ee0bd4a13f4b84c4d3b
https://github.com/llvm/llvm-project/commit/4877c593a873657cd18a1ee0bd4a13f4b84c4d3b
Author: Kaitlin Peng <kaitlinpeng at microsoft.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCombine.td
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h
A llvm/test/CodeGen/SPIRV/GlobalISel/InstCombine/prelegalizercombiner-select-to-faceforward.mir
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/faceforward.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward.ll
Log Message:
-----------
[SPIRV] Add PreLegalizer pattern matching for `faceforward` (#139959)
Tasks completed:
- Pattern match`select(fcmp(dot(p2, p3), 0), p1, -p1)` to
`faceforward(p1, p2, p3)`
- Add pattern matching tests to
`prelegalizercombiner-select-to-faceforward.mir` and `faceforward.ll`
- Add CL extension error test
`llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll`
- Add CL extension test for no pattern matching in
`llvm/test/CodeGen/SPIRV/opencl/faceforward.ll`
Closes #137255.
Commit: d125cab13f08eee4d02d02e46223d14285bb2353
https://github.com/llvm/llvm-project/commit/d125cab13f08eee4d02d02e46223d14285bb2353
Author: Valeriy Savchenko <vsavchenko at apple.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/Transforms/InstCombine/cast-mul-select.ll
M llvm/test/Transforms/InstCombine/cast.ll
M llvm/test/Transforms/InstCombine/catchswitch-phi.ll
M llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
M llvm/test/Transforms/InstCombine/known-bits-lerp-pattern.ll
M llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
M llvm/test/Transforms/InstCombine/logical-select.ll
Log Message:
-----------
[InstCombine] Support multi-use values in cast elimination transforms (#165877)
`canEvaluateTruncated` and `canEvaluateSExtd` previously rejected
multi-use values to avoid duplication. This was overly conservative, if
all users of a multi-use value are part of the transform, we can
evaluate it in a different type without duplication.
This change tracks visited values and defers decisions on multi-use
values until we verify all their users were visited.
`EvaluateInDifferentType` now memoizes multi-use values to avoid
creating duplicates.
Applied to truncation and sext. Zext unchanged due to its dual-return
nature.
Commit: 84df446af980f33f8014578856f8b1f8037888ee
https://github.com/llvm/llvm-project/commit/84df446af980f33f8014578856f8b1f8037888ee
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
Log Message:
-----------
AMDGPU: Remove DummyCGSCC use after buffer lowering passes (#169519)
The fixme the comment refers to was removed.
Commit: 44cffbe5d8de5947780288ca3c366bbd52650314
https://github.com/llvm/llvm-project/commit/44cffbe5d8de5947780288ca3c366bbd52650314
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/fma-combine.ll
Log Message:
-----------
[RISCV] Propagate SDNode flags when combining `(fmul (fneg X), ...)` (#169460)
In #157388, we turned `(fmul (fneg X), Y)` into `(fneg (fmul X, Y))`.
However, we forgot to propagate SDNode flags, specifically fast math
flags, from the original FMUL to the new one. This hinders some of the
subsequent (FMA) DAG combiner patterns that relied on the contraction
flag and as a consequence, missed some of the opportunities to generate
negation FMA instructions like `fnmadd`.
This patch fixes this issue by propagating the flags.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 6a6b99aa8010f16f4e74f78bca1f3c6ca9e94b9f
https://github.com/llvm/llvm-project/commit/6a6b99aa8010f16f4e74f78bca1f3c6ca9e94b9f
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCRecipeBufferization.cpp
M flang/test/Fir/OpenACC/recipe-bufferization.mlir
M flang/test/Lower/OpenACC/acc-firstprivate-derived-allocatable-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-pointer-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-user-assign.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction-remapping.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenACC/do-loops-to-acc-loops.f90
M flang/test/Transforms/OpenACC/acc-implicit-copy-reduction.fir
M flang/test/Transforms/OpenACC/acc-implicit-data-fortran.F90
M flang/test/Transforms/OpenACC/acc-implicit-data.fir
M flang/test/Transforms/OpenACC/acc-implicit-firstprivate.fir
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/test/Dialect/OpenACC/acc-implicit-data-reduction.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
M mlir/test/Dialect/OpenACC/invalid.mlir
M mlir/test/Dialect/OpenACC/legalize-data.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
Log Message:
-----------
[acc][flang][cir] Add recipes to data entry operations (#149210)
This patch refactors the OpenACC dialect to attach recipe symbols
directly to data operations (acc.private, acc.firstprivate,
acc.reduction)
rather than to compute constructs (acc.parallel, acc.serial, acc.loop).
Motivation:
The previous design required compute constructs to carry both the recipe
symbol and the variable reference, leading to complexity. Additionally,
recipes were required even when they could be generated automatically
through MappableType interfaces.
Changes:
- Data operations (acc.private, acc.firstprivate, acc.reduction) now
require a 'recipe' attribute referencing their respective recipe
operations
- Verifier enforces recipe attribute presence for non-MappableType
operands; MappableType operands can generate recipes on demand
- Compute constructs (acc.parallel, acc.serial, acc.loop) no longer
carry recipe symbols in their operands
- Updated flang lowering to attach recipes to data operations instead
of passing them to compute constructs
Format Migration:
Old format:
```
acc.parallel private(@recipe -> %var : !fir.ref<i32>) { ... }
```
New format:
```
%private = acc.private varPtr(%var : !fir.ref<i32>)
recipe(@recipe) -> !fir.ref<i32>
acc.parallel private(%private : !fir.ref<i32>) { ... }
```
Test Updates:
- Updated all CIR and Flang OpenACC tests to new format
- Fixed CHECK lines to verify recipe attributes on data operations
Commit: d5aa686636e0824f2d39ac333537d19bb4f8fc34
https://github.com/llvm/llvm-project/commit/d5aa686636e0824f2d39ac333537d19bb4f8fc34
Author: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
[GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`. (#166204)
`convert-vector-to-llvm` pass applies a set of vector transformation
patterns that are not included in the standard `convert-to-llvm` pass
interface. These additional transformations are required to properly
lower MLIR vector operations. Since not all vector ops have direct
`llvm` dialect lowering, many of them must first be progressively
rewritten into simpler or more canonical vector ops, which are then
lowered to `llvm`. Therefore, running `convert-vector-to-llvm` is
necessary to ensure a complete and correct lowering of vector operations
to the `llvm` dialect.
Commit: 4822f4986fae9bb212e2f35e29839bbd9fb26bea
https://github.com/llvm/llvm-project/commit/4822f4986fae9bb212e2f35e29839bbd9fb26bea
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Analysis/CFG.cpp
M clang/test/Analysis/lifetime-cfg-output.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/unittests/Analysis/FlowSensitive/LoggerTest.cpp
Log Message:
-----------
[LifetimeSafety] Add parameter lifetime tracking in CFG (#169320)
This PR enhances the CFG builder to properly handle function parameters
in lifetime analysis:
1. Added code to include parameters in the initial scope during CFG
construction for both `FunctionDecl` and `BlockDecl` types
2. Added a special case to skip reference parameters, as they don't need
automatic destruction
3. Fixed several test cases that were previously marked as "FIXME" due
to missing parameter lifetime tracking
Previously, Clang's lifetime analysis was not properly tracking the
lifetime of function parameters, causing it to miss important
use-after-return bugs when parameter values were returned by reference
or address. This change ensures that parameters are properly tracked in
the CFG, allowing the analyzer to correctly identify when stack memory
associated with parameters is returned.
Fixes https://github.com/llvm/llvm-project/issues/169014
Commit: f545c2cec12f77f1fb61ccf07393f434d456ad94
https://github.com/llvm/llvm-project/commit/f545c2cec12f77f1fb61ccf07393f434d456ad94
Author: David Stone <davidfromonline at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaDeclCXX.cpp
Log Message:
-----------
[clang][NFC] Don't copy into a vector just to iterate in `IsInitListMemberExprInitialized` (#169385)
Commit: 0c9c62adf165ebf4128bcfe9863fa0c524b46b7b
https://github.com/llvm/llvm-project/commit/0c9c62adf165ebf4128bcfe9863fa0c524b46b7b
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
Log Message:
-----------
[PowerPC ]convert `(setcc (and X, 1), 0, eq)` to `XORI (and X, 1), 1` (#168384)
Convert `(setcc (and X, 1), 0, eq)` to `XORI (and X, 1), 1` , it will save one instruction.
Commit: d7dcc108fc3ada2330277424495b676d52de1765
https://github.com/llvm/llvm-project/commit/d7dcc108fc3ada2330277424495b676d52de1765
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/docs/DeveloperPolicy.rst
M llvm/utils/git/github-automation.py
Log Message:
-----------
[GitHub] Add review instructions for commit access requests (#168971)
As discussed in
https://discourse.llvm.org/t/clarification-on-how-to-accept-commit-access-requests/88728,
clarify reviewer instructions for how to accept commit access requests.
Commit: 1d30ae6e402a28018a5574b7c68d71aac14acd63
https://github.com/llvm/llvm-project/commit/1d30ae6e402a28018a5574b7c68d71aac14acd63
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
AMDGPU: Stop forcing RequiresCodeGenSCCOrder (#169522)
This hasn't been strictly necessary since c897c13dde.
Practically this makes little difference; we still enable IPRA
by default which implies this option. By removing this explicit
force, -enable-ipra=0 has the expected change in the pass pipeline
to remove the DummyCGSCC runs.
Commit: 8f1bb92bbfa45d49103953dad0d0a5dcfd388959
https://github.com/llvm/llvm-project/commit/8f1bb92bbfa45d49103953dad0d0a5dcfd388959
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
M llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
M llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
Log Message:
-----------
[NVPTX] Fix lit test issues from masked load/store implementation (#169535)
>From this commit:
https://github.com/llvm/llvm-project/commit/17852deda7fb9dabb41023e2673025c630b9369d,
Build was broken here:
https://lab.llvm.org/buildbot/#/builders/155/builds/15135/steps/7/logs/stdio.
I think this should fix things.
Commit: 6c8ff4f2bbae6fe29b0ef67edb70e6d73b47beb3
https://github.com/llvm/llvm-project/commit/6c8ff4f2bbae6fe29b0ef67edb70e6d73b47beb3
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Log Message:
-----------
[NVPTX] Fix maybe unused variable in 17852ded (#169542)
Commit: dce95b2ea41e8585cd1e3e2ce07f5d692a970949
https://github.com/llvm/llvm-project/commit/dce95b2ea41e8585cd1e3e2ce07f5d692a970949
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACCLoop.cpp
Log Message:
-----------
[OpenACC][CIR][NFC] Remove 'NYI' diagnostics, since we're done with t… (#169543)
…hese
We've finished all of the clauses/etc that we're going to use this
visitor for, so we can remove the SourceLocation we used just for that,
and replace all NYI with unreachables.
Commit: a8e0afe98853418e1367274e6f04f7ba255de199
https://github.com/llvm/llvm-project/commit/a8e0afe98853418e1367274e6f04f7ba255de199
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/test/CIR/CodeGen/vector-ext-element.cpp
Log Message:
-----------
[CIR] ArraySubscriptExpr on ExtVectorElementExpr (#169158)
Implement ArraySubscriptExpr support for ExtVectorElementExpr
Commit: 2d78b1409eeab558cfc1b64ab39211af00c5f35f
https://github.com/llvm/llvm-project/commit/2d78b1409eeab558cfc1b64ab39211af00c5f35f
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/OpenMPKinds.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/lib/Parse/ParseOpenMP.cpp
A clang/test/OpenMP/need_device_ptr_kind_ast_print.cpp
A clang/test/OpenMP/need_device_ptr_kind_messages.cpp
Log Message:
-----------
[OpenMP][Clang] Parsing/Sema support for `need_device_ptr(fb_nullify/fb_preserve)`. (#168905)
This patch adds parsing, semantic handling, and diagnostics for the
`OpenMP 6.1 fb_nullify` and` fb_preserve` fallback modifiers used with
the `need_device_ptr` map modifier.
Commit: 622dbb372bfefc135c3cdf967ae6f3b55ffa4a16
https://github.com/llvm/llvm-project/commit/622dbb372bfefc135c3cdf967ae6f3b55ffa4a16
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
Log Message:
-----------
AMDGPU: Add more tests for 32-bit constant address space (#168976)
The sub-dword cases just assert now, so comment those out.
Commit: 20ca85b69fc06feb75f67414d54f3830748bb456
https://github.com/llvm/llvm-project/commit/20ca85b69fc06feb75f67414d54f3830748bb456
Author: Jez Ng <me at jezng.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/InputFiles.cpp
M lld/test/MachO/x86-64-relocs.s
Log Message:
-----------
[lld] macho: Support section branch relocations, including the 1-byte form (#169062)
I noticed that we had a hardcoded value of 4 for the pcrel section
relocations, which seems like an issue given that we recently added
support for 1-byte branch relocations in
https://github.com/llvm/llvm-project/pull/164439. The code included an
assert that the relevant relocation had the BYTE4 attribute, but that is
actually not enough to use a hardcoded value of 4: we need to assert
that the *other* `BYTE<n>` attributes are not set either.
However, since we did not support local branch relocations, that doesn't
seem to have mattered in practice. That said, local branch relocations
can be emitted by compilers, and ld64 does handle the 4-byte version of
them, so I've added support for it here.
ld64 actually seems to reject 1-byte section relocations, so the
questionable code is actually probably fine (minus the incorrect
assert). So we have two options: add an equivalent check in LLD, or just
support 1-byte local branch relocations. Supporting it actually requires
less code, so I've gone with that option here.
Commit: 2ee12f191a005363259e3a95ccdf459d9044eadf
https://github.com/llvm/llvm-project/commit/2ee12f191a005363259e3a95ccdf459d9044eadf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/gws_agpr.ll
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
A llvm/test/MC/AMDGPU/ds_gws_sgpr_err.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
Log Message:
-----------
AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)
On targets that require even aligned 64-bit VGPRs, GWS operands
require even alignment of a 32-bit operand. Previously we had a hacky
post-processing which added an implicit operand to try to manage
the constraint. This would require special casing in other passes
to avoid breaking the operand constraint. This moves the handling
into the instruction definition, so other passes no longer need
to consider this edge case. MC still does need to special case this,
to print/parse as a 32-bit register. This also still ends up net
less work than introducing even aligned 32-bit register classes.
This also should be applied to the image special case.
Commit: 3a27fc48117ba7e062c3cfa0006badb64446ed69
https://github.com/llvm/llvm-project/commit/3a27fc48117ba7e062c3cfa0006badb64446ed69
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Omit VTYPE in VSETVLIInfo::print() when state is uninit or unknown. (#169459)
Commit: eab23e199aef18c2052c08171129633233ab98f5
https://github.com/llvm/llvm-project/commit/eab23e199aef18c2052c08171129633233ab98f5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Log Message:
-----------
[RISCV] Don't add Zilsd pairing hints if other part of the pair is reserved. (#169538)
Commit: ebe40066545fd0ad2e88c5e48b7751195d9a9eca
https://github.com/llvm/llvm-project/commit/ebe40066545fd0ad2e88c5e48b7751195d9a9eca
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/CMakeLists.txt
Log Message:
-----------
[mlir] Fix build failure with BUILD_SHARED_LIBS=ON
/usr/bin/ld: tools/mlir/lib/Dialect/GPU/Pipelines/CMakeFiles/obj.MLIRGP
UPipelines.dir/GPUToXeVMPipeline.cpp.o: in function `mlir::gpu::buildLo
werToXeVMPassPipeline(mlir::OpPassManager&, mlir::gpu::GPUToXeVMPipelin
eOptions const&)':
GPUToXeVMPipeline.cpp:(.text._ZN4mlir3gpu28buildLowerToXeVMPassPipeline
ERNS_13OpPassManagerERKNS0_24GPUToXeVMPipelineOptionsE+0x1293): undefin
ed reference to `mlir::createConvertVectorToLLVMPass()'
Commit: 6c48fbc1dcfbd44a47f126f21e575340b67aac06
https://github.com/llvm/llvm-project/commit/6c48fbc1dcfbd44a47f126f21e575340b67aac06
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/test/X86/lit.local.cfg
M bolt/test/lit.local.cfg
Log Message:
-----------
[BOLT][Tests] Use AT&T assembler syntax only for X86 tests (#169541)
Enabling AT&T syntax for all tests is broken when X86 target is not
enabled as reported in #167225.
Commit: 0917a38c694bd2558b79c2b6d51fee2308dd94dd
https://github.com/llvm/llvm-project/commit/0917a38c694bd2558b79c2b6d51fee2308dd94dd
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[PowerPC] Fix a warning
This patch fixes:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15676:17: error: unused
variable 'CC' [-Werror,-Wunused-variable]
Commit: af0fcf85c812867c1d03f390d5afbbbc5b7f1584
https://github.com/llvm/llvm-project/commit/af0fcf85c812867c1d03f390d5afbbbc5b7f1584
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/include/mlir/TableGen/Pattern.h
M mlir/lib/TableGen/Pattern.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
Log Message:
-----------
[mlir][tblgen] Don't echo absolute paths into rewrite pattern source (#168984)
Currently, the declarative pattern rewrite generator will always print
the [source]:[line](s) from which a pattern came. This is a useful
debugging hint, but it causes problem when absolute paths are used as
arguments to mlir-tblgen (which LLVM's build rules automatically do).
Specifially, it causes the source to be tied to the build location,
harning reproducability and our collective ability to get ccache hits
from, say, separate worktrees.
This commit resolves the issue by replacing absolute paths in thes
"Generated from:" comments with their filenames. (The alternative would
have been to implement an entire file-prefix-map the way the C compilers
do, but since this is an isolated incident, I chose to resolve it
locally.)
Commit: 36947982106686570383945c2bbf367f447d9edc
https://github.com/llvm/llvm-project/commit/36947982106686570383945c2bbf367f447d9edc
Author: Sergei Druzhkov <serzhdruzhok at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
Log Message:
-----------
[lldb-dap] Add format support for evaluate request (#169132)
This patch adds support for format option in the `evaluate` request
according to
[DAP](https://microsoft.github.io/debug-adapter-protocol/specification#Requests_Evaluate)
specification. Also, fixed typo in `LLDB_DAP_INVALID_VARRERF` constant.
Commit: 0f941f6866910e55e0e7cff30c48740477be0cd8
https://github.com/llvm/llvm-project/commit/0f941f6866910e55e0e7cff30c48740477be0cd8
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
Log Message:
-----------
[flang][cuda] Add support to allocate scalar character types (#169550)
Add support for character declared like:
```
subroutine sub1()
character*4, device :: b
end subroutine
```
Commit: ad3d9fb3cab7f2e9a7337ca3c1bd0018ff6c6158
https://github.com/llvm/llvm-project/commit/ad3d9fb3cab7f2e9a7337ca3c1bd0018ff6c6158
Author: Petr Penzin <ppenzin at tenstorrent.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
Log Message:
-----------
[RISCV] tt-ascalon-d8 vector scheduling (#167066)
Add the vector scheduling model for tt-ascalon-d8 and corresponding
llvm-mca tests.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 8d920725ca56930d301df1c7e090905423645a49
https://github.com/llvm/llvm-project/commit/8d920725ca56930d301df1c7e090905423645a49
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
Log Message:
-----------
[RISCV] Use FMV.D for moving GPRPairs on RV32_Zdinx (#169556)
This is noted by the specification, and should save a dynamic
instruction.
Code size should be no worse than before, as the pairs of moves can
usually be turned into two 16-bit moves, but `fmv.d` is always a 32-bit
instruction.
LLVM can look through a `FSGNJ_D_IN32X`, in
`RISCVInstrInfo::isCopyInstrImpl` which helps copy propagation.
Commit: dbcf5688cca37543ea3304be68516b3ac476eef3
https://github.com/llvm/llvm-project/commit/dbcf5688cca37543ea3304be68516b3ac476eef3
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
[AMDGPU] Simplify VT comparisons. NFC. (#169526)
Automated with `sed -i 's/\.Value//g' lib/Target/AMDGPU/*.td` plus a
tiny bit of manual reformatting.
Commit: 1c9368e01e6ed45e7dbc523d3bddfd900bb6e504
https://github.com/llvm/llvm-project/commit/1c9368e01e6ed45e7dbc523d3bddfd900bb6e504
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
A clang/test/CIR/CodeGen/copy-constructor.cpp
Log Message:
-----------
[CIR] Upstream non-record array init handling (#169429)
This upstreams the code to handle member initialization for non-record
arrays.
Commit: c475f8e5d809e2109a67c8523472eb28cd7bbb2a
https://github.com/llvm/llvm-project/commit/c475f8e5d809e2109a67c8523472eb28cd7bbb2a
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
A clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
Log Message:
-----------
[HLSL] Update vector swizzle elements individually (#169090)
When individual elements of a vector are updated via vector swizzle, it needs to be handled as separate store operations to the individual vector elements.
Clang treats vectors as one unit, so if a part of a vector needs to be updated, the whole vector is loaded, some elements modified, and then the whole vector is stored.
In HLSL vector elements are handled separately. We need to avoid this load/modify/store sequence to prevent overwriting other vector elements that might be getting updated in parallel.
Fixes #152815
Commit: 091aece72b0149bda6d465301fe3934ca570a592
https://github.com/llvm/llvm-project/commit/091aece72b0149bda6d465301fe3934ca570a592
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[VPlan] Remove redundant transferFlags call from replicateByVF (NFC).
Flags are now passed on construction/cloning. Remove unnecessary
transferFlags call, and make code independent of VPRecipeWithIRFlags, to
support additional recipes in the future.
Commit: 00ffc70ba154b8670fc37d1398ce4473bca3a516
https://github.com/llvm/llvm-project/commit/00ffc70ba154b8670fc37d1398ce4473bca3a516
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
Log Message:
-----------
[SLP][NFC]Add a test with commutative instruction with non-commutative op, NFC
Commit: 074d17e9c8cbc6f22e65ba1211787453ea629ccb
https://github.com/llvm/llvm-project/commit/074d17e9c8cbc6f22e65ba1211787453ea629ccb
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/tsd_shared.h
Log Message:
-----------
[scudo] Lock/unlock MutexTSDs in disable/enable. (#169440)
It is possible that a fork could occur while MutexTSDs is being held and
then cause a deadlock in a forked process when something attempts to
lock it again. Instead add it to the enable/disable list of mutexes.
Commit: e894654532a74b669b0b0830007cc6c979b35d56
https://github.com/llvm/llvm-project/commit/e894654532a74b669b0b0830007cc6c979b35d56
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/addrec-may-wrap-udiv-canonicalize.ll
Log Message:
-----------
[SCEV] Add tests for UDiv canonicalization of AddRecs that may wrap.
Add test cases for canonicalizing AddRecs that may wrap.
Commit: 9bf78ab8dd17ecbbecd4157c67e8fb4d95528194
https://github.com/llvm/llvm-project/commit/9bf78ab8dd17ecbbecd4157c67e8fb4d95528194
Author: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
Revert "[GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`." (#169570)
Reverts llvm/llvm-project#166204
There was a build issue due to a missing dependency.
Commit: 49828c23b59959ca9f2c0dc83aeb9ce7f84b5c31
https://github.com/llvm/llvm-project/commit/49828c23b59959ca9f2c0dc83aeb9ce7f84b5c31
Author: Haowei <haowei at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/cmake/caches/Fuchsia.cmake
Log Message:
-----------
[Fuchsia] Bump minimal OS X target to 11.0 (#169568)
libcxx requires minimal macOS 11 to build. This patch bumps the minimal
OS X target in Fuchsia's cmake cache file to 11.0 to satisfy this
requirement.
Commit: 4f39a4ff0ada92870ca1c2dccad382ea04947da8
https://github.com/llvm/llvm-project/commit/4f39a4ff0ada92870ca1c2dccad382ea04947da8
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCOpsInterfacesTest.cpp
Log Message:
-----------
[acc][flang] Add getInitRegion() to GlobalVariableOpInterface (#169569)
Some globals (e.g., fir.global) have initialization regions that may
transitively reference other globals or type descriptors. Add
getInitRegion() to GlobalVariableOpInterface to retrieve these regions,
returning Region* (nullptr if the global uses attributes for
initialization, as with memref.global).
Commit: 5f777b2c8faca3fe28079fc81a7aefbca1edb803
https://github.com/llvm/llvm-project/commit/5f777b2c8faca3fe28079fc81a7aefbca1edb803
Author: daniilavdeev <daniilavdeev237 at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCSymbol.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/MC/MCSymbol.cpp
A llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
Log Message:
-----------
[dwarf] make dwarf fission compatible with RISCV relaxations 1/2 (#166597)
Currently, -gsplit-dwarf and -mrelax are incompatible options in Clang.
The issue is that .dwo files should not contain any relocations, as they
are not processed by the linker. However, relaxable code emits
relocations in DWARF for debug ranges that reside in the .dwo file when
DWARF fission is enabled.
This patch makes DWARF fission compatible with RISC-V relaxations. It
uses the StartxEndx DWARF forms in .debug_rnglists.dwo, which allow
referencing addresses from .debug_addr instead of using absolute
addresses. This approach eliminates relocations from .dwo files.
Commit: 97023fba5546f9d0e762ccbca89cbb8324a9131a
https://github.com/llvm/llvm-project/commit/97023fba5546f9d0e762ccbca89cbb8324a9131a
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/test/CIR/CodeGen/coro-task.cpp
Log Message:
-----------
[CIR] Emit ready and suspend branches for cir.await (#168814)
This PR adds codegen for `cir.await` ready and suspend. One notable
difference from the classic codegen is that, in the suspend branch, it
emits an `AwaitSuspendWrapper`(`.__await_suspend_wrapper__init`)
function that is always inlined. This function wraps the suspend logic
inside an internal wrapper that gets inlined. Example here:
https://godbolt.org/z/rWYGcaaG4
Commit: ebf5d9ef7de29b55fd9e9d504f83689b4013e0de
https://github.com/llvm/llvm-project/commit/ebf5d9ef7de29b55fd9e9d504f83689b4013e0de
Author: Alan Li <me at alanli.org>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-i8-gep.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-var-delta.ll
R llvm/test/Transforms/StraightLineStrengthReduce/path-compression.ll
R llvm/test/Transforms/StraightLineStrengthReduce/pick-candidate.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll
Log Message:
-----------
Revert "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169546)
This reverts commit f67409c3ec7cd45c55656c8159bc42b3918f1116.
cc @fiigii
Including us, several separate groups are experiencing regressions with
this change. This is the smallest reproducer pasted by @akuegel :
https://github.com/llvm/llvm-project/pull/162930#issuecomment-3574307330
Commit: 9534ed9f30043318798a9544461bc174e273e1f3
https://github.com/llvm/llvm-project/commit/9534ed9f30043318798a9544461bc174e273e1f3
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M orc-rt/include/orc-rt/Error.h
M orc-rt/unittests/ErrorTest.cpp
Log Message:
-----------
[orc-rt] Add ErrorAsOutParameter convenience constructor. (#169467)
Allows construction of ErrorAsOutParameters from Error references.
Commit: fd22706e937f7d2563cfa0e433dd735cc5284599
https://github.com/llvm/llvm-project/commit/fd22706e937f7d2563cfa0e433dd735cc5284599
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
A flang/test/Lower/OpenMP/compiler-directives-loop.f90
Log Message:
-----------
[flang][OpenMP] Skip compiler directives in getCollapsedLoopEval (#169565)
Use `getNestedDoConstruct` from Utils to get the nested DoConstructs.
Fixes https://github.com/llvm/llvm-project/issues/169532
Commit: f7a9fcad99e155fed32d98a2d41d1e3bfdeebf48
https://github.com/llvm/llvm-project/commit/f7a9fcad99e155fed32d98a2d41d1e3bfdeebf48
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/test/Lower/CUDA/cuda-atomicadd.cuf
Log Message:
-----------
[flang][cuda] Use PTX instruction for atomicAdd with 4xf32 (#169581)
Implementation similar to the clang one in
`clang/lib/Headers/__clang_cuda_intrinsics.h`
Commit: 1c034a372403d539700292cd564773ef3531a423
https://github.com/llvm/llvm-project/commit/1c034a372403d539700292cd564773ef3531a423
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
Log Message:
-----------
[compiler-rt] [UBsan] precommit test (#169579)
Commit: 9c414c428d8464c829d551d0d91029339e746842
https://github.com/llvm/llvm-project/commit/9c414c428d8464c829d551d0d91029339e746842
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/CMakeLists.txt
M clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
M clang-tools-extra/clangd/test/index-tools.test
M clang-tools-extra/clangd/test/system-include-extractor.test
Log Message:
-----------
[clangd] Make lit tests work with the internal shell
This makes all of the clangd tests work with the internal shell.
Modifications needed for each test are as follows:
1. system-include-extractor.test was using variable expansion which is
not supported in the internal shell. This patch rewrites it to use
the readfile mechanism along with python. This isn't super pretty but
is readily understandable and there are only two tests across the
monorepo that use this construction, so making it prettier is hard to
justify.
2. include-cleaner-batch-fix.test - Was using $'' construction to create
new lines in a string. Simply replace it with multiple echo commands
to be canonical with the rest of the repository.
3. index-tools.test - Just add IndexBenchmark to the clangd test
depends, so the test now just works unconditionally. This should
significantly increase test coverage at little cost.
Reviewers: ilovepi, HighCommander4, petrhosek, kadircet
Reviewed By: ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/169539
Commit: c51c382c8752e7ba5049ed3662fefb9ffe9283c3
https://github.com/llvm/llvm-project/commit/c51c382c8752e7ba5049ed3662fefb9ffe9283c3
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/lit.cfg.py
Log Message:
-----------
[clangd] Enable lit internal shell by default
Enable it now that all of the tests pass under the internal shell. The
internal shell is slightly faster (10-15%) and also provides a better
debugging experience.
Reviewers: petrhosek, ilovepi, kadircet, HighCommander4
Reviewed By: ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/169540
Commit: 4cfbc44ebe26692c209655c37aeb0b6cbf1d479b
https://github.com/llvm/llvm-project/commit/4cfbc44ebe26692c209655c37aeb0b6cbf1d479b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/lit.cfg.py
Log Message:
-----------
Revert "[clangd] Enable lit internal shell by default"
This reverts commit c51c382c8752e7ba5049ed3662fefb9ffe9283c3.
This breaks at least one buildbot:
1. https://lab.llvm.org/buildbot/#/builders/134/builds/30460
Commit: bd04ef6df50e8e6e5212762fc798ea9fbdcfc897
https://github.com/llvm/llvm-project/commit/bd04ef6df50e8e6e5212762fc798ea9fbdcfc897
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/CMakeLists.txt
M clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
M clang-tools-extra/clangd/test/index-tools.test
M clang-tools-extra/clangd/test/system-include-extractor.test
Log Message:
-----------
Revert "[clangd] Make lit tests work with the internal shell"
This reverts commit 9c414c428d8464c829d551d0d91029339e746842.
This one is causing buildbot failures too at CMake configure time:
1. https://lab.llvm.org/buildbot/#/builders/193/builds/12452
Commit: 3f22ed1152c4c00e95381368ec7d88878f2fd9f9
https://github.com/llvm/llvm-project/commit/3f22ed1152c4c00e95381368ec7d88878f2fd9f9
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M offload/include/OpenMP/InteropAPI.h
M offload/include/PerThreadTable.h
Log Message:
-----------
[OFFLOAD] Add support for indexed per-thread containers (#164263)
Split from #158900 it adds a PerThreadContainer that can use STL-like
indexed containers based on a slightly refactored PerThreadTable.
---------
Co-authored-by: Joseph Huber <huberjn at outlook.com>
Commit: 5d38cddc3b00b428f848fdeddc8334c4560db36a
https://github.com/llvm/llvm-project/commit/5d38cddc3b00b428f848fdeddc8334c4560db36a
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/AST/Expr.cpp
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/CodeGen/scoped-atomic-ops.c
M clang/test/Sema/scoped-atomic-ops.c
Log Message:
-----------
[Clang] Add __scoped_atomic_uinc_wrap and __scoped_atomic_udec_wrap builtins (#168666)
This PR extends __scoped_atomic builtins with inc and dec functions.
They map to LLVM IR `atomicrmw uinc_wrap` and `atomicrmw udec_wrap`.
These enable implementation of OpenCL-style atomic_inc / atomic_dec with
wrap semantics on targets supporting scoped atomics (e.g. GPUs).
---------
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: d889b97f2b1cd7264a5a225edd7daf18c3709bfa
https://github.com/llvm/llvm-project/commit/d889b97f2b1cd7264a5a225edd7daf18c3709bfa
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
Log Message:
-----------
[RISCV][llvm] Support BUILD_VECTOR codegen for P extension (#169083)
Commit: 44c8a011764ae5fb9178d938fc3f1f1bf76bfe49
https://github.com/llvm/llvm-project/commit/44c8a011764ae5fb9178d938fc3f1f1bf76bfe49
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
Log Message:
-----------
[compiler-rt] [UBSan] remove unneeded test cases (#169594)
the target handling will be done in the driver, so removing codegen
tests.
Commit: 175168c620d6a62ab7360693c6415cc1ab1eeb4b
https://github.com/llvm/llvm-project/commit/175168c620d6a62ab7360693c6415cc1ab1eeb4b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Analysis/ThreadSafety.cpp
A clang/test/SemaCXX/no-warn-thread-safety-analysis.cpp
Log Message:
-----------
[Analysis] Make ThreadSafety correctly handle base class destructors (#169593)
Commit: 40f21a7b2f3e7d034cac4a981b09c1a0049df427
https://github.com/llvm/llvm-project/commit/40f21a7b2f3e7d034cac4a981b09c1a0049df427
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
Log Message:
-----------
[llvm][RISCV] Support P Extension CodeGen (#167895)
This patch supports: PSLLI_B, PSLLI_H, PSLLI_W, PSSLAI_H and PSSLAI_W
Commit: 1ea4aa1b91553847ab155f7ed6c22d392d06b38e
https://github.com/llvm/llvm-project/commit/1ea4aa1b91553847ab155f7ed6c22d392d06b38e
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M libclc/clc/lib/generic/atomic/clc_atomic_dec.cl
M libclc/clc/lib/generic/atomic/clc_atomic_def.inc
M libclc/clc/lib/generic/atomic/clc_atomic_inc.cl
Log Message:
-----------
[libclc] Use __scoped_atomic_udec/uinc_wrap to implement _clc_atomic_dec/inc (#168327)
Commit: 222ba6f5ce96d3612b7f62aeacd1d5599fbb8141
https://github.com/llvm/llvm-project/commit/222ba6f5ce96d3612b7f62aeacd1d5599fbb8141
Author: Jan Voung <jvoung at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][dataflow] Handle more glvalue cases of the ConditionalOperator transfer (#168994)
In the dataflow framework, the builtin transfer function currently only
handles the GLValue result case of ConditionalOperator when the
true and false expression StorageLocations are exactly the same.
Ideally / we have wanted to introduce alias sets to handle when the Locs
are different. However, that is a larger change to the framework
(and we may need to introduce weak updates).
For now, do something simpler to at least handle when the GLValue is
immediately cast to an RValue, by making up a distinct StorageLocation
that holds the join of the true and false expression values (when not a
record). This seems like the most common case, so seems worth covering.
The case when an LValue is needed and can be updated later (and
thus needs a link to the original storage locations) seems more rare,
and we currently do not handle such updates either, so this intermediate
step is no different (for that case).
Commit: bfc732efbda2dc1caa78de89600834c083bedd83
https://github.com/llvm/llvm-project/commit/bfc732efbda2dc1caa78de89600834c083bedd83
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M orc-rt/include/orc-rt/Session.h
M orc-rt/lib/executor/Session.cpp
M orc-rt/unittests/SessionTest.cpp
Log Message:
-----------
[orc-rt] Add ControllerAccess interface. (#169598)
ControllerAccess provides an abstract interface for bidirectional RPC
between the executor (running JIT'd code) and the controller (containing
the llvm::orc::ExecutionSession). ControllerAccess implementations are
expected to implement IPC / RPC using a concrete communication method
(shared memory, pipes, sockets, native system IPC, etc).
Calls from executor to controller are made via callController, with
"handler tags" (addresses in the executor) specifying the target handler
in the controller. A handler must be associated in the controller with
the given tag for the call to succeed. This ensures that only registered
entry points in the controller can be used, and avoids leaking
controller addresses into the executor.
Calls in both directions are to "wrapper functions" that take a buffer
of bytes as input and return a buffer of bytes as output. In the ORC
runtime these must be `orc_rt_WrapperFunction`s (see
Session::handleWrapperCall). The interpretation of the byte buffers is
up to the wrapper functions: the ORC runtime imposes no restrictions on
how the bytes are to be interpreted.
ControllerAccess objects may be detached from the Session prior to
Session shutdown, in which case no further calls may be made in either
direction, and any pending results (from calls made that haven't
returned yet) should return errors. If the ControllerAccess class is
still attached at Session shutdown time it will be detached as part of
the shutdown process. The ControllerAccess::disconnect method must
support concurrent entry on multiple threads, and all callers must block
until they can guarantee that no further calls will be received or
accepted.
Commit: e81a564cb0031e93d34a941224b14ec73c69bf65
https://github.com/llvm/llvm-project/commit/e81a564cb0031e93d34a941224b14ec73c69bf65
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/tools/opt/invalid-target.ll
M llvm/tools/opt/optdriver.cpp
Log Message:
-----------
opt: Stop creating TargetMachine to infer the datalayout (#169585)
The Triple directly has the datalayout string in it, so just
use that.
The logical flow here is kind of a mess. We were constructing
a temporary target machine in the asm parser to infer the datalayout,
throwing it away, and then creating another target machine for the
actual compilation. The flow of the Triple construction is still
convoluted, but we can at least drop the TargetMachine.
Commit: 76ec25f729fcc7ae576caf21293cc393e68e7cf7
https://github.com/llvm/llvm-project/commit/76ec25f729fcc7ae576caf21293cc393e68e7cf7
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
Log Message:
-----------
[ORC] Pass FailedSNs by const-ref. NFCI. (#169600)
Avoids a vector copy.
Commit: 4e7c65e85f47443ab3af729e5cf8e693081abb87
https://github.com/llvm/llvm-project/commit/4e7c65e85f47443ab3af729e5cf8e693081abb87
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Log Message:
-----------
[RISCV] Don't add duplicate Zilsd hints. (#169554)
This matches what ARM does. I'm not sure if there are any bad effects
from the duplicate hints. I have seen the duplicates hints in the debug
output and confirmed this removes them.
Commit: a7f9a4db895561b7bf4a1b91fe306b29fd61af6c
https://github.com/llvm/llvm-project/commit/a7f9a4db895561b7bf4a1b91fe306b29fd61af6c
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
Log Message:
-----------
[AMDGPU] Update strict floating point tests to be more comprehensive (#169578)
Commit: a57fe84af0679871d914e0d5fc3f449069f22a19
https://github.com/llvm/llvm-project/commit/a57fe84af0679871d914e0d5fc3f449069f22a19
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/TextNodeDumper.cpp
A clang/test/AST/ast-dump-APValue-addrlabeldiff.c
Log Message:
-----------
[clang] Implement dump() for AddrLabelDiff APValues (#169505)
Commit: 8396d4c10e98fedba5d8f6861087078b2de49674
https://github.com/llvm/llvm-project/commit/8396d4c10e98fedba5d8f6861087078b2de49674
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
Log Message:
-----------
[clang][bytecode][NFC] Clean up Integral::from() functions (#169513)
Commit: 6459f39c377dc8b7d5d81ef365553c8625fb4def
https://github.com/llvm/llvm-project/commit/6459f39c377dc8b7d5d81ef365553c8625fb4def
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/BitcastBuffer.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode] Add some convenience API to BitcastBuffer (#169516)
So we check the offsets before using them.
Commit: 00aca530b1e49281f461965a304a8a36cb41142d
https://github.com/llvm/llvm-project/commit/00aca530b1e49281f461965a304a8a36cb41142d
Author: Dominik Adamski <dominik.adamski at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M flang-rt/cmake/modules/HandleLibs.cmake
Log Message:
-----------
[Flang-rt] Remove COMPILE_ONLY from flang-rt CMake file. (#169534)
COMPILE_ONLY was introduced in cmake 3.27.0. We cannot use this feature,
because LLVM supports cmake 3.20.0.
Commit: e04c01bcc91226d632f81bd3290c180deb0b6db8
https://github.com/llvm/llvm-project/commit/e04c01bcc91226d632f81bd3290c180deb0b6db8
Author: Fangrui Song <i at maskray.me>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCMachOStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCWasmStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp
Log Message:
-----------
MC: Remove unneeded parameter `MCAsmBackend *`. NFC
Commit: 97732ddb5d921a7d5cd6ffc2a23438b607c0d3f6
https://github.com/llvm/llvm-project/commit/97732ddb5d921a7d5cd6ffc2a23438b607c0d3f6
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Program.h
Log Message:
-----------
[clang][bytecode][NFC] Make Program::getNativePointer() const (#169502)
Commit: e493e90a890d92cb13090710d74bb16b3e1075f8
https://github.com/llvm/llvm-project/commit/e493e90a890d92cb13090710d74bb16b3e1075f8
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
Log Message:
-----------
[lldb][NFC] Fix incorrect comments in TestArm64InstEmulation
Commit: 93f2deb1d0a886672683e1e6df9797d11cddf7c5
https://github.com/llvm/llvm-project/commit/93f2deb1d0a886672683e1e6df9797d11cddf7c5
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vle.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/addcarry.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/allow-check.ll
M llvm/test/CodeGen/RISCV/arith-with-overflow.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bitreverse-shift.ll
M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
M llvm/test/CodeGen/RISCV/bswap-shift.ll
M llvm/test/CodeGen/RISCV/clear-cache.ll
M llvm/test/CodeGen/RISCV/copy-frameindex.mir
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-zfa.ll
M llvm/test/CodeGen/RISCV/double_reduct.ll
M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
M llvm/test/CodeGen/RISCV/fixed-csr.ll
M llvm/test/CodeGen/RISCV/float-arith-strict.ll
M llvm/test/CodeGen/RISCV/float-arith.ll
M llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-convert-strict.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/float-select-verify.ll
M llvm/test/CodeGen/RISCV/float-zfa.ll
M llvm/test/CodeGen/RISCV/flt-rounds.ll
M llvm/test/CodeGen/RISCV/fmax-fmin.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/fpenv.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/frm-dependency.ll
M llvm/test/CodeGen/RISCV/get-register-invalid.ll
M llvm/test/CodeGen/RISCV/get-register-noreserve.ll
M llvm/test/CodeGen/RISCV/get-register-reserve.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/half-zfa.ll
M llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
M llvm/test/CodeGen/RISCV/i64-icmp.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll
M llvm/test/CodeGen/RISCV/intrinsics/trap.ll
M llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/machine-combiner.ll
M llvm/test/CodeGen/RISCV/machine-cse.ll
M llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll
M llvm/test/CodeGen/RISCV/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/memset-inline.ll
M llvm/test/CodeGen/RISCV/min-max.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/module-target-abi3.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsic-optimizations.ll
M llvm/test/CodeGen/RISCV/pei-crash.ll
M llvm/test/CodeGen/RISCV/pr135206.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/pr92193.ll
M llvm/test/CodeGen/RISCV/prefetch.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/readcyclecounter.ll
M llvm/test/CodeGen/RISCV/readsteadycounter.ll
M llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/replace-with-veclib-sleef-scalable.ll
M llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbkx-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic-autoupgrade.ll
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M llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
M llvm/test/CodeGen/RISCV/rv64-float-convert.ll
M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-args.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-frame-setup.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
M llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbkx-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
M llvm/test/CodeGen/RISCV/rvv/commutable.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-negative.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp-mask.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp-mask.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvv.ll
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M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/fold-vp-fsub-and-vp-fmul.ll
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M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
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M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/lround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/marith-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int-e64.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-crash-zvl32b.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mixed-float-bf16-arith.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/pr63459.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
M llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
M llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfwmacc_4x4x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e4m3.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e5m2.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e4m3.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e5m2.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_f_f.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_s.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_u.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_s.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_u.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte16.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte32.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte64.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte8.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettk.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettm.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettnt.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste16.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste32.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste64.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste8.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtdiscard.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_t_v.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_v_t.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtzero_t.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands-i1.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/smulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/splats-with-mixed-vl.ll
M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
M llvm/test/CodeGen/RISCV/rvv/trunc-sat-clip-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/ushl_sat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vadc.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/rvv/vaesdf.ll
M llvm/test/CodeGen/RISCV/rvv/vaesdm.ll
M llvm/test/CodeGen/RISCV/rvv/vaesef.ll
M llvm/test/CodeGen/RISCV/rvv/vaesem.ll
M llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll
M llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll
M llvm/test/CodeGen/RISCV/rvv/vaesz.ll
M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vand.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn.ll
M llvm/test/CodeGen/RISCV/rvv/vasub.ll
M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
M llvm/test/CodeGen/RISCV/rvv/vbrev.ll
M llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
M llvm/test/CodeGen/RISCV/rvv/vclmul.ll
M llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vclz.ll
M llvm/test/CodeGen/RISCV/rvv/vcompress.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/vcpopv.ll
M llvm/test/CodeGen/RISCV/rvv/vctz.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
M llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll
M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vfirst.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/vfmerge-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv-bf-s.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv-s-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv-v-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-bf-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvtbf16-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vfrec7-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfrec7.ll
M llvm/test/CodeGen/RISCV/rvv/vfredmax.ll
M llvm/test/CodeGen/RISCV/rvv/vfredmin.ll
M llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
M llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnj-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjn-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjx-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll
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M llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1up-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/vfsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/vfwadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-w-bf.ll
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M llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-bf-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-bf-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
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M llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
M llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-w-bf.ll
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M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vghsh.ll
M llvm/test/CodeGen/RISCV/rvv/vgmul.ll
M llvm/test/CodeGen/RISCV/rvv/vid.ll
M llvm/test/CodeGen/RISCV/rvv/viota.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-no-prop.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vle.ll
M llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
M llvm/test/CodeGen/RISCV/rvv/vleff.ll
M llvm/test/CodeGen/RISCV/rvv/vlm.ll
M llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlse.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vmand.ll
M llvm/test/CodeGen/RISCV/rvv/vmandn.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu.ll
M llvm/test/CodeGen/RISCV/rvv/vmclr.ll
M llvm/test/CodeGen/RISCV/rvv/vmerge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu.ll
M llvm/test/CodeGen/RISCV/rvv/vmnand.ll
M llvm/test/CodeGen/RISCV/rvv/vmnor.ll
M llvm/test/CodeGen/RISCV/rvv/vmor.ll
M llvm/test/CodeGen/RISCV/rvv/vmorn.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmset.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsif.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vmsof.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul.ll
M llvm/test/CodeGen/RISCV/rvv/vmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.x.s.ll
M llvm/test/CodeGen/RISCV/rvv/vmxnor.ll
M llvm/test/CodeGen/RISCV/rvv/vmxor.ll
M llvm/test/CodeGen/RISCV/rvv/vnclip.ll
M llvm/test/CodeGen/RISCV/rvv/vnclipu.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vor.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vqdot.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotsu.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotu.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotus.ll
M llvm/test/CodeGen/RISCV/rvv/vredand.ll
M llvm/test/CodeGen/RISCV/rvv/vredmax.ll
M llvm/test/CodeGen/RISCV/rvv/vredmaxu.ll
M llvm/test/CodeGen/RISCV/rvv/vredmin.ll
M llvm/test/CodeGen/RISCV/rvv/vredminu.ll
M llvm/test/CodeGen/RISCV/rvv/vredor.ll
M llvm/test/CodeGen/RISCV/rvv/vredsum.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vredxor.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu.ll
M llvm/test/CodeGen/RISCV/rvv/vrev8.ll
M llvm/test/CodeGen/RISCV/rvv/vrgather.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll
M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrol.ll
M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vror.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
M llvm/test/CodeGen/RISCV/rvv/vse.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-valid-elen-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvlmax-ext.ll
M llvm/test/CodeGen/RISCV/rvv/vsext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsext.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
M llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1down-constant-vl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1up-constant-vl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/vslidedown.ll
M llvm/test/CodeGen/RISCV/rvv/vslideup.ll
M llvm/test/CodeGen/RISCV/rvv/vsll.ll
M llvm/test/CodeGen/RISCV/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/rvv/vsm3c.ll
M llvm/test/CodeGen/RISCV/rvv/vsm3me.ll
M llvm/test/CodeGen/RISCV/rvv/vsm4k.ll
M llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
M llvm/test/CodeGen/RISCV/rvv/vsmul.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsra.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssub.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccus.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/vwredsum.ll
M llvm/test/CodeGen/RISCV/rvv/vwredsumu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vxor.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vzext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vzext.ll
M llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xv.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvv.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvw.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqa.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqasu.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqau.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqaus.ll
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
M llvm/test/CodeGen/RISCV/sadd_sat.ll
M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/saverestore.ll
M llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/simplify-condbr.ll
M llvm/test/CodeGen/RISCV/ssub_sat.ll
M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/thread-pointer.ll
M llvm/test/CodeGen/RISCV/uadd_sat.ll
M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/RISCV/usub_sat.ll
M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
M llvm/test/CodeGen/RISCV/vlenb.ll
M llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xcvalu.ll
M llvm/test/CodeGen/RISCV/xcvbitmanip.ll
M llvm/test/CodeGen/RISCV/xcvmac.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
M llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll
Log Message:
-----------
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
As @mshockwave mentioned in
https://github.com/llvm/llvm-project/pull/156415, we don't need to
declare intrinsics in tests now, this pr removes them.
Commit: de674fb6c250608197a70ae3fdef5519597054f6
https://github.com/llvm/llvm-project/commit/de674fb6c250608197a70ae3fdef5519597054f6
Author: David Green <david.green at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/addtruncshift.ll
Log Message:
-----------
[AArch64] Add vector tests for add(trunc(shift))
Commit: 19655231718929362f338fb73a6d4ae587ad927e
https://github.com/llvm/llvm-project/commit/19655231718929362f338fb73a6d4ae587ad927e
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir][tensor] Add new builders for insert_slice/extract_slice Ops (nfc) (#169533)
Adds new builders for `tensor.insert_slice` and `tensor.extract_slice`
Ops for which the _offsets_ and the _strides_ are all 0s and 1s,
respecitvely. This allows us to write:
```cpp
// No offsets and no strides - implicitly set to 0s and 1s,
// respectively.
tensor::InsertSliceOp::create(rewriter, loc, src, dest, writeSizes);
```
instead of:
```cpp
// Strides are initialised explicitly to 1s
Attribute oneIdxAttr = rewriter.getIndexAttr(1);
SmallVector<OpFoldResult> writeStrides(destRank, oneIdxAttr);
// Offsets are initialised explicitly to 0s
Attribute zeroIdxAttr = rewriter.getIndexAttr(0);
SmallVector<OpFoldResult> writeOffsets(destRank, zeroIdxAttr);
tensor::InsertSliceOp::create(rewriter, loc, src, dest, writeOffsets,
writeSizes, writeStrides);
```
Commit: 76079ecc891e2781168d9a92a4ff024aaffa77db
https://github.com/llvm/llvm-project/commit/76079ecc891e2781168d9a92a4ff024aaffa77db
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaExprCXX.cpp
A clang/test/Sema/AArch64/sve-vector-conditional-op.cpp
Log Message:
-----------
[clang][Sema] Merge Check[Sizeless]VectorConditionalTypes implementations (#169165)
These two functions are almost identical, except for the handling
different vector types, so merging them eliminates some duplication.
This also fixes some bugs, as "sizeless" vector code was missing checks
for several cases.
This meant type checking would crash if:
- The LHS or RHS type was void
- The LHS or RHS type was a fixed-length vector type
- There was not a scalable vector type for the result element count/size
These are fixed with this patch and tested in
Sema/AArch64/sve-vector-conditional-op.cpp.
Fixes #169025
Commit: 63e4b8c64105ea429f0d35f82b8492d6526b8c54
https://github.com/llvm/llvm-project/commit/63e4b8c64105ea429f0d35f82b8492d6526b8c54
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
Log Message:
-----------
[clang][bytecode][NFC] Remove unused Integral range functions (#169508)
Commit: f481f5bef90d0dd10a9d885b2e4bbfd015e6606d
https://github.com/llvm/llvm-project/commit/f481f5bef90d0dd10a9d885b2e4bbfd015e6606d
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
M flang/test/Lower/OpenMP/delayed-privatization-reduction-byref.f90
M flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array-lb.f90
M flang/test/Lower/OpenMP/parallel-reduction-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array2.f90
M flang/test/Lower/OpenMP/parallel-reduction-pointer-array.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/reduction-array-intrinsic.f90
M flang/test/Lower/OpenMP/sections-array-reduction.f90
M flang/test/Lower/OpenMP/taskgroup-task-array-reduction.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-lb.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-lb2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-multiple-clauses.f90
M flang/test/Lower/OpenMP/wsloop-reduction-pointer.f90
M flang/test/Lower/do_concurrent_reduce_allocatable.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/allocatable_gpu_reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-block-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-reduction.mlir
Log Message:
-----------
[OpenMP][flang] Add initial support for by-ref reductions on the GPU (#165714)
Adds initial support for GPU by-ref reductions. The main problem for
reduction by reference is that, prior to this PR, we were shuffling
(from remote lanes within the same warp or across different warps within
the block) pointers/references to the private reduction values rather
than the private reduction values themselves.
In particular, this diff adds support for reductions on scalar
allocatables where reductions happen on loops nested in `target`
regions. For example:
```fortran
integer :: i
real, allocatable :: scalar_alloc
allocate(scalar_alloc)
scalar_alloc = 0
!$omp target map(tofrom: scalar_alloc)
!$omp parallel do reduction(+: scalar_alloc)
do i = 1, 1000000
scalar_alloc = scalar_alloc + 1
end do
!$omp end target
```
This PR supports by-ref reductions on the intra- and inter-warp levels.
So far, there are still steps to be takens for full support of by-ref
reductions, for example:
* Support inter-block value combination is still not supported.
Therefore, `target teams distribute parallel do` is still not supported.
* Support for dynamically-sized arrays still needs to be added.
* Support for more than one allocatable/array on the same `reduction`
clause.
Commit: c43ac96331bc309c2a92ae20a7ae5fadfecbd073
https://github.com/llvm/llvm-project/commit/c43ac96331bc309c2a92ae20a7ae5fadfecbd073
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaAttr.cpp
Log Message:
-----------
[LifetimeSafety] Move GSL pointer/owner type detection to LifetimeAnnotations (#169620)
Refactored GSL pointer and owner type detection functions to improve code organization and reusability.
Commit: 3036de77239f0b29b3619ff6e468ccf5845c7e91
https://github.com/llvm/llvm-project/commit/3036de77239f0b29b3619ff6e468ccf5845c7e91
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
A llvm/test/Analysis/LoopCacheAnalysis/crash-after-pr164798.ll
Log Message:
-----------
[LoopCacheAnalysis] Fix crash after #164798 (#169486)
Fix the assertion failure after #164798. The issue is that the
comparison `Sizes.back() == ElementSize` can fail when their types are
different. We should cast them to the wider type before the comparison.
Commit: c0a7b15d0158a79786a38f5e94fa8315d4c9f0fe
https://github.com/llvm/llvm-project/commit/c0a7b15d0158a79786a38f5e94fa8315d4c9f0fe
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/pr39160.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-uniform-load.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/nsw-crash.ll
M llvm/test/Transforms/LoopVectorize/scev-exitlim-crash.ll
M llvm/test/Transforms/LoopVectorize/value-ptr-bug.ll
M llvm/test/Transforms/LoopVectorize/vector-to-scalar-cast.ll
M llvm/test/Transforms/LoopVectorize/version-mem-access.ll
Log Message:
-----------
[LV][NFC] Remove remaining uses of undef in tests (#169357)
Split off from PR #163525, this standalone patch replaces almost all the
remaining cases where undef is used as value in loop vectoriser tests.
This will reduce the likelihood of contributors hitting the `undef
deprecator` warning in github.
NOTE: The remaining use of undef in iv_outside_user.ll will be fixed in
a separate PR.
I've removed the test stride_undef from version-mem-access.ll, since
there is already a stride_poison test.
Commit: 04bddda08ab2126f74c902f6630c133382170001
https://github.com/llvm/llvm-project/commit/04bddda08ab2126f74c902f6630c133382170001
Author: Steven Perron <stevenperron at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-array.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-simple.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-struct.ll
Log Message:
-----------
[SPIRV] Improve Logical SPIR-V Pointer Access and GEP Legalization (#169076)
This commit improves the handling of GetElementPtr (GEP) instructions
for
Logical SPIR-V. It includes:
- Rewriting of GEPs that are not allowed in Logical SPIR-V
(specifically,
handling non-zero first indices by rebuilding access chains or adjusting
types).
- Better deduction of element types for pointer casting.
- Updates to instruction selection to ensure GEPs are correctly lowered
to
OpAccessChain or OpInBoundsAccessChain only when valid (e.g. first index
0).
- Support for standard HLSL cbuffer layouts in tests.
Commit: 2d4a8dadba88889ca19adee4fbf907d8c5a40282
https://github.com/llvm/llvm-project/commit/2d4a8dadba88889ca19adee4fbf907d8c5a40282
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilogue-vectorization-fix-scalar-resume-values.ll
M llvm/test/Transforms/LoopVectorize/AArch64/f128-fmuladd-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/licm-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr151664-cost-hoisted-vector-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-fixed-width-inorder-core.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-multi-block.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-unroll.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-loop-backedge-elimination-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/LoongArch/defaults.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
M llvm/test/Transforms/LoopVectorize/X86/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-step.ll
M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
M llvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll
M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
M llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/pr23997.ll
M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
M llvm/test/Transforms/LoopVectorize/X86/pr47437.ll
M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/X86/widened-value-used-as-scalar-and-first-lane.ll
M llvm/test/Transforms/LoopVectorize/assume.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/cse-casts.ll
M llvm/test/Transforms/LoopVectorize/cse-gep-source-element-type.ll
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
M llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
M llvm/test/Transforms/LoopVectorize/expand-scev-after-invoke.ll
M llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
M llvm/test/Transforms/LoopVectorize/if-reduction.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleave-with-i65-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-nested-loop.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/minimumnum-maximumnum-reductions.ll
M llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/noalias-scope-decl.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/pr37248.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-odd-interleave-counts.ll
M llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/reverse-induction-gep-nowrap-flags.ll
M llvm/test/Transforms/LoopVectorize/reverse_induction.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
M llvm/test/Transforms/LoopVectorize/select-cmp.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-hint.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
M llvm/test/Transforms/LoopVectorize/struct-return-replicate.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-outside-iv-users.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll
A llvm/test/Transforms/LoopVectorize/vector-pointer-gep-idxty-addrspace.ll
Log Message:
-----------
[VPlan] Use DL index type consistently for GEPs (#169396)
In preparation to strip VPUnrollPartAccessor and unroll recipes
directly, strip unnecessary complication in getGEPIndexTy, as the unroll
part will no longer be available in follow-ups (see #168886 for
instance). The patch also helps by doing a mass test update up-front.
Narrowing the GEP index type conditionally does not yield any benefit,
and the change is non-functional in terms of emitted assembly. While at
it, avoid hard-coding address-space 0, and use the pointer operand's
address space to get the GEP index type.
Commit: 800da10a3a697922042303daa4fe3e06aea34729
https://github.com/llvm/llvm-project/commit/800da10a3a697922042303daa4fe3e06aea34729
Author: J. Ryan Stinnett <jryans at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DebugOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/DebugInfo/Generic/dbg-info-all-calls-described.c
M clang/test/Driver/debug-options.c
Log Message:
-----------
[clang][DebugInfo] Add call site debug info flag (#169574)
This adds a default enabled flag to control attachment of call site
debug info. `-gno-call-site-info` can be used to disable this feature
when needed.
This should help those concerned about debug info size in
https://github.com/llvm/llvm-project/issues/168851.
Commit: d090311aa7df7cbd93412c31685893aefc4ad341
https://github.com/llvm/llvm-project/commit/d090311aa7df7cbd93412c31685893aefc4ad341
Author: Naveen Seth Hanig <naveen.hanig at outlook.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/Compiler.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/CommonArgs.h
A clang/include/clang/Driver/CreateASTUnitFromArgs.h
A clang/include/clang/Driver/CreateInvocationFromArgs.h
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Frontend/CompilerInvocation.h
A clang/include/clang/Frontend/StandaloneDiagnostic.h
M clang/include/clang/Frontend/Utils.h
M clang/include/clang/Options/OptionUtils.h
M clang/lib/CrossTU/CMakeLists.txt
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Driver/CMakeLists.txt
A clang/lib/Driver/CreateASTUnitFromArgs.cpp
A clang/lib/Driver/CreateInvocationFromArgs.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CMakeLists.txt
M clang/lib/Frontend/CompilerInvocation.cpp
R clang/lib/Frontend/CreateInvocationFromCommandLine.cpp
A clang/lib/Frontend/StandaloneDiagnostic.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Options/OptionUtils.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/tools/c-index-test/CMakeLists.txt
M clang/tools/c-index-test/core_main.cpp
M clang/tools/diagtool/CMakeLists.txt
M clang/tools/diagtool/ShowEnabledWarnings.cpp
M clang/tools/driver/cc1_main.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexer.cpp
M clang/tools/libclang/CMakeLists.txt
M clang/tools/libclang/Indexing.cpp
M clang/unittests/Driver/DXCModeTest.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M clang/unittests/Frontend/UtilsTest.cpp
M clang/unittests/Sema/CMakeLists.txt
M clang/unittests/Sema/SemaNoloadLookupTest.cpp
M clang/unittests/Serialization/ForceCheckFileInputTest.cpp
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Serialization/NoCommentsTest.cpp
M clang/unittests/Serialization/PreambleInNamedModulesTest.cpp
M clang/unittests/Serialization/VarDeclConstantInitTest.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
M clang/unittests/Tooling/Syntax/TreeTestBase.cpp
M flang/lib/Frontend/CMakeLists.txt
M flang/lib/Frontend/CompilerInvocation.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangHost.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/unittests/Expression/ClangParserTest.cpp
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
Reland "[clang] Refactor to remove clangDriver dependency from clangFrontend and flangFrontend" (#169599)
This relands #165277 by reverting #169397.
This also relands the corresponding Bazel port by reverting #169410.
The original revert was due to a report of a broken build, which was
later resolved by fully clearing the build directory.
Commit: cc1c41724ddab0112937e30e1eaa984595b7f48e
https://github.com/llvm/llvm-project/commit/cc1c41724ddab0112937e30e1eaa984595b7f48e
Author: daniilavdeev <daniilavdeev237 at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
Log Message:
-----------
[dwarf] make dwarf fission compatible with RISCV relaxations 2/2 (#164813)
This patch makes DWARF fission compatible with RISC-V relaxations by
using indirect addressing for the DW_AT_high_pc attribute. This
eliminates the remaining relocations in .dwo files.
Commit: bbbe511ea2f8d6e4f3977ef1bb28a4fb30323f9a
https://github.com/llvm/llvm-project/commit/bbbe511ea2f8d6e4f3977ef1bb28a4fb30323f9a
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
A clang/test/Driver/hip-spirv-backend-bindings.c
A clang/test/Driver/hip-spirv-backend-opt.c
A clang/test/Driver/hip-spirv-backend-phases.c
Log Message:
-----------
Reland "[clang][Driver] Support for the SPIR-V backend when compiling HIP" (#169637)
This relands "[clang][Driver] Support for the SPIR-V backend when compiling HIP" #167543. The only new change is a small fix for the multicall driver.
For HIP, the SPIR-V backend can be optionally activated with the -use-spirv-backend flag. This option uses the SPIR-V BE instead of the SPIR-V translator. These changes also ensure that -use-spirv-backend does not require external dependencies, such as spirv-as and spirv-link
Commit: 2b8d363ac1a8cca21c32afc039cb28f0f1608300
https://github.com/llvm/llvm-project/commit/2b8d363ac1a8cca21c32afc039cb28f0f1608300
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/Delinearization.h
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/lib/Analysis/Delinearization.cpp
Log Message:
-----------
[Delinearization] Remove tryDelinearizeFixedSizeImpl (#169046)
`tryDelinearizeFixedSizeImpl` is a heuristic function relying on GEP's
type information. Using these information to drive an optimization
heuristic is not allowed, so this function should be removed. As #161822
and #164798 have eliminated all calls to this, this patch removes the
function itself.
Commit: 23f90304507612fde6d4afb79e58dd4283b7be49
https://github.com/llvm/llvm-project/commit/23f90304507612fde6d4afb79e58dd4283b7be49
Author: Md Abdullah Shahneous Bari <md.abdullah.shahneous.bari at intel.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
Reland: [GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`. (#169573)
`convert-vector-to-llvm` pass applies a set of vector transformation
patterns that are not included in the standard `convert-to-llvm` pass
interface. These additional transformations are required to properly
lower MLIR vector operations. Since not all vector ops have direct
`llvm` dialect lowering, many of them must first be progressively
rewritten into simpler or more canonical vector ops, which are then
lowered to `llvm`. Therefore, running `convert-vector-to-llvm` is
necessary to ensure a complete and correct lowering of vector operations
to the `llvm` dialect.
Original PR: https://github.com/llvm/llvm-project/pull/166204 +
post-commit failure fixes.
Commit: 0a35f44f58f322dece584265e252e21b3ca03530
https://github.com/llvm/llvm-project/commit/0a35f44f58f322dece584265e252e21b3ca03530
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaExpr.cpp
M clang/test/SemaHIP/amdgpu-gfx950-load-to-lds.hip
Log Message:
-----------
[HIP] Perform implicit pointer cast when compiling HIP, not when -fcuda-is-device (#165387)
When compiling HIP device code, we add implicit casts for the pointer arguments passed to built-in calls.
When compiling for the host, apply the same casts, since the device side of the source (device functions and kernels) should still pass type checks.
Commit: e3de8ff548a84645141fe16fad156525604c12ca
https://github.com/llvm/llvm-project/commit/e3de8ff548a84645141fe16fad156525604c12ca
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
Log Message:
-----------
[gn build] Port d090311aa7df
Commit: 4cc8cc81e3aa10e01ce6d54321cbddbc64f1bd15
https://github.com/llvm/llvm-project/commit/4cc8cc81e3aa10e01ce6d54321cbddbc64f1bd15
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads.ll
Log Message:
-----------
[VPlan] Hoist predicated loads with complementary masks. (#168373)
This patch adds a new VPlan transformation to hoist predicated loads, if
we can prove they execute unconditionally, i.e. there are 2 predicated
loads to the same address with complementary masks. Then we are
guaranteed to execute one of them on each iteration, allowing us to
remove the mask.
The transform groups masked replicating loads by their address SCEV,
then checks if there are 2 loads with complementary mask. If that is the
case, we check if there are any writes that may alias the load address
in the blocks between the first and last load with the same address.
The transforms operates after linearizing the CFG, but before
introducing replicate regions, which means this is just checking a chain
of consecutive blocks.
Currently this only uses noalias metadata to check for no-alias (using
the helpers added in https://github.com/llvm/llvm-project/pull/166247).
Then we create an unpredicated VPReplicateRecipe at the position of the
first load, then replace all users of the grouped loads with it.
Small Alive2 proof for hoisting with complementary masks:
https://alive2.llvm.org/ce/z/kUx742
PR: https://github.com/llvm/llvm-project/pull/168373
Commit: 637f206241756e769c5cf84da27aacc217549a52
https://github.com/llvm/llvm-project/commit/637f206241756e769c5cf84da27aacc217549a52
Author: Marco Elver <elver at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
M llvm/include/llvm/Support/AllocToken.h
M llvm/lib/Support/AllocToken.cpp
Log Message:
-----------
[Support] Add getAllocTokenModeAsString() helper (#169650)
Add a helper function getAllocTokenModeAsString() to convert
AllocTokenMode values to their string representation.
NFC.
Commit: 71507d3205c462493c06d35a472cf7e132271c3d
https://github.com/llvm/llvm-project/commit/71507d3205c462493c06d35a472cf7e132271c3d
Author: Marco Elver <elver at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/test/X86/lit.local.cfg
M bolt/test/lit.local.cfg
M bolt/unittests/Core/MCPlusBuilder.cpp
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/Compiler.cpp
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/cmake/caches/Fuchsia.cmake
M clang/docs/AllocToken.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DebugOptions.def
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenMPKinds.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/CommonArgs.h
A clang/include/clang/Driver/CreateASTUnitFromArgs.h
A clang/include/clang/Driver/CreateInvocationFromArgs.h
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Frontend/CompilerInvocation.h
A clang/include/clang/Frontend/StandaloneDiagnostic.h
M clang/include/clang/Frontend/Utils.h
M clang/include/clang/Options/OptionUtils.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/lib/AST/ByteCode/BitcastBuffer.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Program.h
M clang/lib/AST/Expr.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/CFG.cpp
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
M clang/lib/Analysis/ThreadSafety.cpp
M clang/lib/CIR/CodeGen/Address.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACCLoop.cpp
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CrossTU/CMakeLists.txt
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Driver/CMakeLists.txt
A clang/lib/Driver/CreateASTUnitFromArgs.cpp
A clang/lib/Driver/CreateInvocationFromArgs.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CMakeLists.txt
M clang/lib/Frontend/CompilerInvocation.cpp
R clang/lib/Frontend/CreateInvocationFromCommandLine.cpp
A clang/lib/Frontend/StandaloneDiagnostic.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Options/OptionUtils.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Tooling/Tooling.cpp
A clang/test/AST/ast-dump-APValue-addrlabeldiff.c
M clang/test/Analysis/lifetime-cfg-output.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
A clang/test/CIR/CodeGen/copy-constructor.cpp
M clang/test/CIR/CodeGen/coro-task.cpp
A clang/test/CIR/CodeGen/placement-new.cpp
M clang/test/CIR/CodeGen/vector-ext-element.cpp
M clang/test/CIR/CodeGenOpenACC/combined-copy.c
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-copy.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceptr.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceresident.cpp
M clang/test/CIR/CodeGenOpenACC/declare-link.cpp
M clang/test/CIR/CodeGenOpenACC/declare-present.cpp
M clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGen/scoped-atomic-ops.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
M clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
A clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
M clang/test/DebugInfo/Generic/dbg-info-all-calls-described.c
M clang/test/Driver/debug-options.c
M clang/test/Driver/fsanitize-alloc-token.c
A clang/test/Driver/hip-spirv-backend-bindings.c
A clang/test/Driver/hip-spirv-backend-opt.c
A clang/test/Driver/hip-spirv-backend-phases.c
A clang/test/OpenMP/need_device_ptr_kind_ast_print.cpp
A clang/test/OpenMP/need_device_ptr_kind_messages.cpp
A clang/test/Sema/AArch64/sve-vector-conditional-op.cpp
M clang/test/Sema/scoped-atomic-ops.c
M clang/test/Sema/warn-lifetime-safety.cpp
A clang/test/SemaCXX/no-warn-thread-safety-analysis.cpp
M clang/test/SemaHIP/amdgpu-gfx950-load-to-lds.hip
M clang/tools/c-index-test/CMakeLists.txt
M clang/tools/c-index-test/core_main.cpp
M clang/tools/diagtool/CMakeLists.txt
M clang/tools/diagtool/ShowEnabledWarnings.cpp
M clang/tools/driver/cc1_main.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexer.cpp
M clang/tools/libclang/CMakeLists.txt
M clang/tools/libclang/Indexing.cpp
M clang/unittests/Analysis/FlowSensitive/LoggerTest.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
M clang/unittests/Driver/DXCModeTest.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M clang/unittests/Frontend/UtilsTest.cpp
M clang/unittests/Sema/CMakeLists.txt
M clang/unittests/Sema/SemaNoloadLookupTest.cpp
M clang/unittests/Serialization/ForceCheckFileInputTest.cpp
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Serialization/NoCommentsTest.cpp
M clang/unittests/Serialization/PreambleInNamedModulesTest.cpp
M clang/unittests/Serialization/VarDeclConstantInitTest.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
M clang/unittests/Tooling/Syntax/TreeTestBase.cpp
M compiler-rt/lib/scudo/standalone/tsd_shared.h
M flang-rt/cmake/modules/HandleLibs.cmake
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/lib/Frontend/CMakeLists.txt
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCRecipeBufferization.cpp
M flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/OpenACC/recipe-bufferization.mlir
M flang/test/Lower/CUDA/cuda-atomicadd.cuf
M flang/test/Lower/OpenACC/acc-firstprivate-derived-allocatable-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-pointer-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-user-assign.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction-remapping.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenACC/do-loops-to-acc-loops.f90
A flang/test/Lower/OpenMP/compiler-directives-loop.f90
M flang/test/Lower/OpenMP/delayed-privatization-reduction-byref.f90
M flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array-lb.f90
M flang/test/Lower/OpenMP/parallel-reduction-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array2.f90
M flang/test/Lower/OpenMP/parallel-reduction-pointer-array.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/reduction-array-intrinsic.f90
M flang/test/Lower/OpenMP/sections-array-reduction.f90
M flang/test/Lower/OpenMP/taskgroup-task-array-reduction.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-lb.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-lb2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-multiple-clauses.f90
M flang/test/Lower/OpenMP/wsloop-reduction-pointer.f90
M flang/test/Lower/do_concurrent_reduce_allocatable.f90
M flang/test/Transforms/OpenACC/acc-implicit-copy-reduction.fir
M flang/test/Transforms/OpenACC/acc-implicit-data-fortran.F90
M flang/test/Transforms/OpenACC/acc-implicit-data.fir
M flang/test/Transforms/OpenACC/acc-implicit-firstprivate.fir
M libclc/clc/lib/generic/atomic/clc_atomic_dec.cl
M libclc/clc/lib/generic/atomic/clc_atomic_def.inc
M libclc/clc/lib/generic/atomic/clc_atomic_inc.cl
M libcxx/include/stack
M libcxx/test/libcxx/diagnostics/stack.nodiscard.verify.cpp
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/InputFiles.cpp
M lld/test/MachO/x86-64-relocs.s
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangHost.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/unittests/Expression/ClangParserTest.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
M llvm/docs/DeveloperPolicy.rst
M llvm/docs/LangRef.rst
M llvm/include/llvm/Analysis/Delinearization.h
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCSymbol.h
M llvm/include/llvm/Support/AllocToken.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Analysis/Delinearization.cpp
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/LibcallLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCMachOStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCSymbol.cpp
M llvm/lib/MC/MCWasmStreamer.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Support/AllocToken.cpp
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.h
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/Mips/Mips16ISelLowering.h
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
M llvm/lib/Target/NVPTX/NVPTXTagInvariantLoads.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVCombine.td
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/Instrumentation/AllocToken.cpp
M llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
A llvm/test/Analysis/LoopCacheAnalysis/crash-after-pr164798.ll
A llvm/test/Analysis/ScalarEvolution/addrec-may-wrap-udiv-canonicalize.ll
A llvm/test/CodeGen/AArch64/addtruncshift.ll
A llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
A llvm/test/CodeGen/AMDGPU/gws_agpr.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
M llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
A llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
A llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
A llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vle.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/addcarry.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/allow-check.ll
M llvm/test/CodeGen/RISCV/arith-with-overflow.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bitreverse-shift.ll
M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
M llvm/test/CodeGen/RISCV/bswap-shift.ll
M llvm/test/CodeGen/RISCV/clear-cache.ll
M llvm/test/CodeGen/RISCV/copy-frameindex.mir
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/double-zfa.ll
M llvm/test/CodeGen/RISCV/double_reduct.ll
M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
M llvm/test/CodeGen/RISCV/fixed-csr.ll
M llvm/test/CodeGen/RISCV/float-arith-strict.ll
M llvm/test/CodeGen/RISCV/float-arith.ll
M llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-convert-strict.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/float-select-verify.ll
M llvm/test/CodeGen/RISCV/float-zfa.ll
M llvm/test/CodeGen/RISCV/flt-rounds.ll
A llvm/test/CodeGen/RISCV/fma-combine.ll
M llvm/test/CodeGen/RISCV/fmax-fmin.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/fpenv.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/frm-dependency.ll
M llvm/test/CodeGen/RISCV/get-register-invalid.ll
M llvm/test/CodeGen/RISCV/get-register-noreserve.ll
M llvm/test/CodeGen/RISCV/get-register-reserve.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/half-zfa.ll
M llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
M llvm/test/CodeGen/RISCV/i64-icmp.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll
M llvm/test/CodeGen/RISCV/intrinsics/trap.ll
M llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/machine-combiner.ll
M llvm/test/CodeGen/RISCV/machine-cse.ll
M llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll
M llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
M llvm/test/CodeGen/RISCV/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/memset-inline.ll
M llvm/test/CodeGen/RISCV/min-max.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/module-target-abi3.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsic-optimizations.ll
M llvm/test/CodeGen/RISCV/pei-crash.ll
M llvm/test/CodeGen/RISCV/pr135206.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/pr92193.ll
M llvm/test/CodeGen/RISCV/prefetch.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/readcyclecounter.ll
M llvm/test/CodeGen/RISCV/readsteadycounter.ll
M llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/replace-with-veclib-sleef-scalable.ll
M llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zbkx-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
M llvm/test/CodeGen/RISCV/rv64-float-convert.ll
M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-args.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-frame-setup.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
M llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbkx-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
M llvm/test/CodeGen/RISCV/rvv/commutable.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-negative.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvw.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll
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M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vp-fsub-and-vp-fmul.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
M llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/llround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/lround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/marith-vp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int-e64.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int-e64.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-crash-zvl32b.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mixed-float-bf16-arith.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/pr63459.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
M llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
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M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll
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M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfwmacc_4x4x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_2x8x2.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
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M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e5m2.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e4m3.ll
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M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_s.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_u.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_s.ll
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M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte16.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte32.ll
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M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste32.ll
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M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste8.ll
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M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_t_v.ll
M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_v_t.ll
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M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
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M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
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M llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
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M llvm/test/CodeGen/RISCV/rvv/vmxnor.ll
M llvm/test/CodeGen/RISCV/rvv/vmxor.ll
M llvm/test/CodeGen/RISCV/rvv/vnclip.ll
M llvm/test/CodeGen/RISCV/rvv/vnclipu.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vor.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vqdot.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotsu.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotu.ll
M llvm/test/CodeGen/RISCV/rvv/vqdotus.ll
M llvm/test/CodeGen/RISCV/rvv/vredand.ll
M llvm/test/CodeGen/RISCV/rvv/vredmax.ll
M llvm/test/CodeGen/RISCV/rvv/vredmaxu.ll
M llvm/test/CodeGen/RISCV/rvv/vredmin.ll
M llvm/test/CodeGen/RISCV/rvv/vredminu.ll
M llvm/test/CodeGen/RISCV/rvv/vredor.ll
M llvm/test/CodeGen/RISCV/rvv/vredsum.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vredxor.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu.ll
M llvm/test/CodeGen/RISCV/rvv/vrev8.ll
M llvm/test/CodeGen/RISCV/rvv/vrgather.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll
M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrol.ll
M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vror.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
M llvm/test/CodeGen/RISCV/rvv/vse.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-valid-elen-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvlmax-ext.ll
M llvm/test/CodeGen/RISCV/rvv/vsext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsext.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
M llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
M llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1down-constant-vl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1up-constant-vl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/vslidedown.ll
M llvm/test/CodeGen/RISCV/rvv/vslideup.ll
M llvm/test/CodeGen/RISCV/rvv/vsll.ll
M llvm/test/CodeGen/RISCV/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/rvv/vsm3c.ll
M llvm/test/CodeGen/RISCV/rvv/vsm3me.ll
M llvm/test/CodeGen/RISCV/rvv/vsm4k.ll
M llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
M llvm/test/CodeGen/RISCV/rvv/vsmul.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsra.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssub.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccus.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/vwredsum.ll
M llvm/test/CodeGen/RISCV/rvv/vwredsumu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vxor.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vzext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vzext.ll
M llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xv.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvv.ll
M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvw.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqa.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqasu.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqau.ll
M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqaus.ll
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
M llvm/test/CodeGen/RISCV/sadd_sat.ll
M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/saverestore.ll
M llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/simplify-condbr.ll
M llvm/test/CodeGen/RISCV/ssub_sat.ll
M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/thread-pointer.ll
M llvm/test/CodeGen/RISCV/uadd_sat.ll
M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/RISCV/usub_sat.ll
M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
M llvm/test/CodeGen/RISCV/vlenb.ll
M llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xcvalu.ll
M llvm/test/CodeGen/RISCV/xcvbitmanip.ll
M llvm/test/CodeGen/RISCV/xcvmac.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
M llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll
A llvm/test/CodeGen/SPIRV/GlobalISel/InstCombine/prelegalizercombiner-select-to-faceforward.mir
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/faceforward.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-array.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-simple.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-struct.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward.ll
A llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
A llvm/test/Instrumentation/AllocToken/module-flags.ll
M llvm/test/LTO/X86/alloc-token.ll
A llvm/test/MC/AMDGPU/ds_gws_sgpr_err.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-lto-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Transforms/InstCombine/cast-mul-select.ll
M llvm/test/Transforms/InstCombine/cast.ll
M llvm/test/Transforms/InstCombine/catchswitch-phi.ll
M llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
M llvm/test/Transforms/InstCombine/known-bits-lerp-pattern.ll
M llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
M llvm/test/Transforms/InstCombine/logical-select.ll
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilogue-vectorization-fix-scalar-resume-values.ll
M llvm/test/Transforms/LoopVectorize/AArch64/f128-fmuladd-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/licm-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr151664-cost-hoisted-vector-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-fixed-width-inorder-core.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-multi-block.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-unroll.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-loop-backedge-elimination-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/LoongArch/defaults.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
M llvm/test/Transforms/LoopVectorize/X86/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-step.ll
M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
M llvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll
M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
M llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/pr23997.ll
M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
M llvm/test/Transforms/LoopVectorize/X86/pr39160.ll
M llvm/test/Transforms/LoopVectorize/X86/pr47437.ll
M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/X86/widened-value-used-as-scalar-and-first-lane.ll
M llvm/test/Transforms/LoopVectorize/assume.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/cse-casts.ll
M llvm/test/Transforms/LoopVectorize/cse-gep-source-element-type.ll
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
M llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
M llvm/test/Transforms/LoopVectorize/expand-scev-after-invoke.ll
M llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/if-reduction.ll
M llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleave-with-i65-induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-uniform-load.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-nested-loop.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/minimumnum-maximumnum-reductions.ll
M llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/noalias-scope-decl.ll
M llvm/test/Transforms/LoopVectorize/nsw-crash.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/pr37248.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-odd-interleave-counts.ll
M llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/reverse-induction-gep-nowrap-flags.ll
M llvm/test/Transforms/LoopVectorize/reverse_induction.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/scev-exitlim-crash.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
M llvm/test/Transforms/LoopVectorize/select-cmp.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-hint.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
M llvm/test/Transforms/LoopVectorize/struct-return-replicate.ll
M llvm/test/Transforms/LoopVectorize/value-ptr-bug.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-outside-iv-users.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll
A llvm/test/Transforms/LoopVectorize/vector-pointer-gep-idxty-addrspace.ll
M llvm/test/Transforms/LoopVectorize/vector-to-scalar-cast.ll
A llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
M llvm/test/Transforms/LoopVectorize/version-mem-access.ll
A llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll
A llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-i8-gep.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-var-delta.ll
R llvm/test/Transforms/StraightLineStrengthReduce/path-compression.ll
R llvm/test/Transforms/StraightLineStrengthReduce/pick-candidate.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll
M llvm/test/Verifier/llvm.loop.estimated_trip_count.ll
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
M llvm/test/tools/opt/invalid-target.ll
M llvm/tools/opt/optdriver.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/Transforms/Utils/LoopUtilsTest.cpp
M llvm/utils/git/github-automation.py
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/include/mlir/TableGen/Pattern.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
M mlir/lib/Dialect/GPU/Pipelines/CMakeLists.txt
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
M mlir/lib/TableGen/Pattern.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenACC/acc-implicit-data-reduction.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
M mlir/test/Dialect/OpenACC/invalid.mlir
M mlir/test/Dialect/OpenACC/legalize-data.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
A mlir/test/Target/LLVMIR/allocatable_gpu_reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-block-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-reduction.mlir
M mlir/test/python/ir/operation.py
M mlir/tools/mlir-tblgen/RewriterGen.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCOpsInterfacesTest.cpp
M offload/include/OpenMP/InteropAPI.h
M offload/include/PerThreadTable.h
M orc-rt/include/orc-rt/Error.h
M orc-rt/include/orc-rt/Session.h
M orc-rt/lib/executor/Session.cpp
M orc-rt/unittests/ErrorTest.cpp
M orc-rt/unittests/SessionTest.cpp
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/third_party_build/zlib-ng.BUILD
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.8-beta.1
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/2bc80c66b8fe...71507d3205c4
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