[all-commits] [llvm/llvm-project] 93f2de: [RISCV] Remove intrinsic declarations in tests, NF...

[Jianjian Guan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 93f2deb1d0a886672683e1e6df9797d11cddf7c5
      https://github.com/llvm/llvm-project/commit/93f2deb1d0a886672683e1e6df9797d11cddf7c5
  Author: Jianjian Guan <jacquesguan at me.com>
  Date:   2025-11-26 (Wed, 26 Nov 2025)

  Changed paths:
    M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vle.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlm.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlse.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vse.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsm.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei-rv64.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsse.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei-rv64.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
    M llvm/test/CodeGen/RISCV/abds-neg.ll
    M llvm/test/CodeGen/RISCV/abds.ll
    M llvm/test/CodeGen/RISCV/abdu-neg.ll
    M llvm/test/CodeGen/RISCV/abdu.ll
    M llvm/test/CodeGen/RISCV/addcarry.ll
    M llvm/test/CodeGen/RISCV/alloca.ll
    M llvm/test/CodeGen/RISCV/allow-check.ll
    M llvm/test/CodeGen/RISCV/arith-with-overflow.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll
    M llvm/test/CodeGen/RISCV/bfloat-arith.ll
    M llvm/test/CodeGen/RISCV/bfloat-convert.ll
    M llvm/test/CodeGen/RISCV/bitreverse-shift.ll
    M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
    M llvm/test/CodeGen/RISCV/bswap-shift.ll
    M llvm/test/CodeGen/RISCV/clear-cache.ll
    M llvm/test/CodeGen/RISCV/copy-frameindex.mir
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
    M llvm/test/CodeGen/RISCV/double-arith-strict.ll
    M llvm/test/CodeGen/RISCV/double-arith.ll
    M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/double-convert-strict.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
    M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
    M llvm/test/CodeGen/RISCV/double-intrinsics.ll
    M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
    M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/double-round-conv.ll
    M llvm/test/CodeGen/RISCV/double-zfa.ll
    M llvm/test/CodeGen/RISCV/double_reduct.ll
    M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
    M llvm/test/CodeGen/RISCV/fixed-csr.ll
    M llvm/test/CodeGen/RISCV/float-arith-strict.ll
    M llvm/test/CodeGen/RISCV/float-arith.ll
    M llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/float-convert-strict.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
    M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
    M llvm/test/CodeGen/RISCV/float-intrinsics.ll
    M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
    M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/float-round-conv.ll
    M llvm/test/CodeGen/RISCV/float-select-verify.ll
    M llvm/test/CodeGen/RISCV/float-zfa.ll
    M llvm/test/CodeGen/RISCV/flt-rounds.ll
    M llvm/test/CodeGen/RISCV/fmax-fmin.ll
    M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/fpenv.ll
    M llvm/test/CodeGen/RISCV/frame.ll
    M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
    M llvm/test/CodeGen/RISCV/frm-dependency.ll
    M llvm/test/CodeGen/RISCV/get-register-invalid.ll
    M llvm/test/CodeGen/RISCV/get-register-noreserve.ll
    M llvm/test/CodeGen/RISCV/get-register-reserve.ll
    M llvm/test/CodeGen/RISCV/half-arith-strict.ll
    M llvm/test/CodeGen/RISCV/half-arith.ll
    M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/half-convert-strict.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
    M llvm/test/CodeGen/RISCV/half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/half-maximum-minimum.ll
    M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/half-round-conv.ll
    M llvm/test/CodeGen/RISCV/half-zfa.ll
    M llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
    M llvm/test/CodeGen/RISCV/i64-icmp.ll
    M llvm/test/CodeGen/RISCV/iabs.ll
    M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
    M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll
    M llvm/test/CodeGen/RISCV/intrinsics/trap.ll
    M llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
    M llvm/test/CodeGen/RISCV/live-sp.mir
    M llvm/test/CodeGen/RISCV/llvm.exp10.ll
    M llvm/test/CodeGen/RISCV/llvm.frexp.ll
    M llvm/test/CodeGen/RISCV/machine-combiner.ll
    M llvm/test/CodeGen/RISCV/machine-cse.ll
    M llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll
    M llvm/test/CodeGen/RISCV/memcpy-inline.ll
    M llvm/test/CodeGen/RISCV/memcpy.ll
    M llvm/test/CodeGen/RISCV/memmove.ll
    M llvm/test/CodeGen/RISCV/memset-inline.ll
    M llvm/test/CodeGen/RISCV/min-max.ll
    M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
    M llvm/test/CodeGen/RISCV/module-target-abi3.ll
    M llvm/test/CodeGen/RISCV/neg-abs.ll
    M llvm/test/CodeGen/RISCV/overflow-intrinsic-optimizations.ll
    M llvm/test/CodeGen/RISCV/pei-crash.ll
    M llvm/test/CodeGen/RISCV/pr135206.ll
    M llvm/test/CodeGen/RISCV/pr56457.ll
    M llvm/test/CodeGen/RISCV/pr69586.ll
    M llvm/test/CodeGen/RISCV/pr92193.ll
    M llvm/test/CodeGen/RISCV/prefetch.ll
    M llvm/test/CodeGen/RISCV/push-pop-popret.ll
    M llvm/test/CodeGen/RISCV/readcyclecounter.ll
    M llvm/test/CodeGen/RISCV/readsteadycounter.ll
    M llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/replace-with-veclib-sleef-scalable.ll
    M llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/rv32p.ll
    M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zbkx-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic-autoupgrade.ll
    M llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic-autoupgrade.ll
    M llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic-autoupgrade.ll
    M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
    M llvm/test/CodeGen/RISCV/rv64-float-convert.ll
    M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
    M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
    M llvm/test/CodeGen/RISCV/rv64-stackmap-args.ll
    M llvm/test/CodeGen/RISCV/rv64-stackmap-frame-setup.ll
    M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
    M llvm/test/CodeGen/RISCV/rv64-stackmap.ll
    M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll
    M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
    M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll
    M llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll
    M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
    M llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
    M llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
    M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
    M llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
    M llvm/test/CodeGen/RISCV/rv64p.ll
    M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbkx-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll
    M llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
    M llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
    M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade.ll
    M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
    M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
    M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
    M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
    M llvm/test/CodeGen/RISCV/rvv/abd.ll
    M llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
    M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
    M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
    M llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
    M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/commutable.ll
    M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
    M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
    M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-negative.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-x.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvw.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
    M llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fold-vp-fsub-and-vp-fmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
    M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl.ll
    M llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
    M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/llrint-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/llround-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/lround-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/marith-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-load-int-e64.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-store-int-e64.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/memcpy-crash-zvl32b.ll
    M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
    M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mixed-float-bf16-arith.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
    M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
    M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/pr63459.ll
    M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
    M llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
    M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare.ll
    M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
    M llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vfwmacc_4x4x4.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_2x8x2.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_2x8x2.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_2x8x2.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_2x8x2.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e4m3.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e5m2.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e4m3.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e5m2.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_f_f.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_s.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_u.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_s.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_u.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte16.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte32.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte64.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte8.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettk.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettm.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettnt.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste16.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste32.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste64.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste8.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtdiscard.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_t_v.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_v_t.ll
    M llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtzero_t.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/smulo-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/splats-with-mixed-vl.ll
    M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
    M llvm/test/CodeGen/RISCV/rvv/trunc-sat-clip-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
    M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
    M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
    M llvm/test/CodeGen/RISCV/rvv/ushl_sat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/vadc.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vaesdf.ll
    M llvm/test/CodeGen/RISCV/rvv/vaesdm.ll
    M llvm/test/CodeGen/RISCV/rvv/vaesef.ll
    M llvm/test/CodeGen/RISCV/rvv/vaesem.ll
    M llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll
    M llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll
    M llvm/test/CodeGen/RISCV/rvv/vaesz.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vand.ll
    M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vandn.ll
    M llvm/test/CodeGen/RISCV/rvv/vasub.ll
    M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
    M llvm/test/CodeGen/RISCV/rvv/vbrev.ll
    M llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
    M llvm/test/CodeGen/RISCV/rvv/vclmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
    M llvm/test/CodeGen/RISCV/rvv/vclz.ll
    M llvm/test/CodeGen/RISCV/rvv/vcompress.ll
    M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vcpop.ll
    M llvm/test/CodeGen/RISCV/rvv/vcpopv.ll
    M llvm/test/CodeGen/RISCV/rvv/vctz.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll
    M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfclass-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfclass.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv.ll
    M llvm/test/CodeGen/RISCV/rvv/vfirst.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmacc-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmerge-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv-bf-s.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv-s-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv-v-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-bf-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvtbf16-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfpext-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrec7-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrec7.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredmax.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredmin.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-bf16.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnj-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjn-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjx-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1down-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1up-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-w-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-bf-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-bf-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvtbf16-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmaccbf16.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub-w-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vghsh.ll
    M llvm/test/CodeGen/RISCV/rvv/vgmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vid.ll
    M llvm/test/CodeGen/RISCV/rvv/viota.ll
    M llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-no-prop.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
    M llvm/test/CodeGen/RISCV/rvv/vle.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff.ll
    M llvm/test/CodeGen/RISCV/rvv/vlm.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlse.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadc.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vmand.ll
    M llvm/test/CodeGen/RISCV/rvv/vmandn.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmclr.ll
    M llvm/test/CodeGen/RISCV/rvv/vmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfeq-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfge-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfgt-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfle-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
    M llvm/test/CodeGen/RISCV/rvv/vmflt-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfne-bf.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmnand.ll
    M llvm/test/CodeGen/RISCV/rvv/vmnor.ll
    M llvm/test/CodeGen/RISCV/rvv/vmor.ll
    M llvm/test/CodeGen/RISCV/rvv/vmorn.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
    M llvm/test/CodeGen/RISCV/rvv/vmset.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsif.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsof.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.v.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.x.s.ll
    M llvm/test/CodeGen/RISCV/rvv/vmxnor.ll
    M llvm/test/CodeGen/RISCV/rvv/vmxor.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclip.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclipu.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vor.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vqdot.ll
    M llvm/test/CodeGen/RISCV/rvv/vqdotsu.ll
    M llvm/test/CodeGen/RISCV/rvv/vqdotu.ll
    M llvm/test/CodeGen/RISCV/rvv/vqdotus.ll
    M llvm/test/CodeGen/RISCV/rvv/vredand.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmax.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmaxu.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmin.ll
    M llvm/test/CodeGen/RISCV/rvv/vredminu.ll
    M llvm/test/CodeGen/RISCV/rvv/vredor.ll
    M llvm/test/CodeGen/RISCV/rvv/vredsum.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vredxor.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu.ll
    M llvm/test/CodeGen/RISCV/rvv/vrev8.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgather.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll
    M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrol.ll
    M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vror.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/vsbc.ll
    M llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
    M llvm/test/CodeGen/RISCV/rvv/vse.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-vp-bf16.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-valid-elen-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvlmax-ext.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext.ll
    M llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
    M llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
    M llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
    M llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1down-constant-vl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1down.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1up-constant-vl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1up.ll
    M llvm/test/CodeGen/RISCV/rvv/vslidedown.ll
    M llvm/test/CodeGen/RISCV/rvv/vslideup.ll
    M llvm/test/CodeGen/RISCV/rvv/vsll.ll
    M llvm/test/CodeGen/RISCV/rvv/vsm.ll
    M llvm/test/CodeGen/RISCV/rvv/vsm3c.ll
    M llvm/test/CodeGen/RISCV/rvv/vsm3me.ll
    M llvm/test/CodeGen/RISCV/rvv/vsm4k.ll
    M llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl.ll
    M llvm/test/CodeGen/RISCV/rvv/vsse.ll
    M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccsu.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccu.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccus.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulsu.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulu.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsum.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsumu.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsll.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor.ll
    M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext.ll
    M llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll
    M llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll
    M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xv.ll
    M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvv.ll
    M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvw.ll
    M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqa.ll
    M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqasu.ll
    M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqau.ll
    M llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqaus.ll
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
    M llvm/test/CodeGen/RISCV/sadd_sat.ll
    M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/saverestore.ll
    M llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
    M llvm/test/CodeGen/RISCV/sextw-removal.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
    M llvm/test/CodeGen/RISCV/simplify-condbr.ll
    M llvm/test/CodeGen/RISCV/ssub_sat.ll
    M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/tail-calls.ll
    M llvm/test/CodeGen/RISCV/thread-pointer.ll
    M llvm/test/CodeGen/RISCV/uadd_sat.ll
    M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/RISCV/usub_sat.ll
    M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
    M llvm/test/CodeGen/RISCV/vararg.ll
    M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
    M llvm/test/CodeGen/RISCV/vlenb.ll
    M llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll
    M llvm/test/CodeGen/RISCV/xcvalu.ll
    M llvm/test/CodeGen/RISCV/xcvbitmanip.ll
    M llvm/test/CodeGen/RISCV/xcvmac.ll
    M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
    M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
    M llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
    M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
    M llvm/test/CodeGen/RISCV/zfh-half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
    M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll

  Log Message:
  -----------
  [RISCV] Remove intrinsic declarations in tests, NFC (#167474)

As @mshockwave mentioned in
https://github.com/llvm/llvm-project/pull/156415, we don't need to
declare intrinsics in tests now, this pr removes them.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications