[all-commits] [llvm/llvm-project] d5aa68: [GPUToXeVMPipeline][Pipeline] Modify pipeline to a...
Aiden Grossman via All-commits
all-commits at lists.llvm.org
Tue Nov 25 16:47:20 PST 2025
Branch: refs/heads/users/boomanaiden154/main.clangd-enable-lit-internal-shell-by-default
Home: https://github.com/llvm/llvm-project
Commit: d5aa686636e0824f2d39ac333537d19bb4f8fc34
https://github.com/llvm/llvm-project/commit/d5aa686636e0824f2d39ac333537d19bb4f8fc34
Author: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
[GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`. (#166204)
`convert-vector-to-llvm` pass applies a set of vector transformation
patterns that are not included in the standard `convert-to-llvm` pass
interface. These additional transformations are required to properly
lower MLIR vector operations. Since not all vector ops have direct
`llvm` dialect lowering, many of them must first be progressively
rewritten into simpler or more canonical vector ops, which are then
lowered to `llvm`. Therefore, running `convert-vector-to-llvm` is
necessary to ensure a complete and correct lowering of vector operations
to the `llvm` dialect.
Commit: 4822f4986fae9bb212e2f35e29839bbd9fb26bea
https://github.com/llvm/llvm-project/commit/4822f4986fae9bb212e2f35e29839bbd9fb26bea
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Analysis/CFG.cpp
M clang/test/Analysis/lifetime-cfg-output.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/unittests/Analysis/FlowSensitive/LoggerTest.cpp
Log Message:
-----------
[LifetimeSafety] Add parameter lifetime tracking in CFG (#169320)
This PR enhances the CFG builder to properly handle function parameters
in lifetime analysis:
1. Added code to include parameters in the initial scope during CFG
construction for both `FunctionDecl` and `BlockDecl` types
2. Added a special case to skip reference parameters, as they don't need
automatic destruction
3. Fixed several test cases that were previously marked as "FIXME" due
to missing parameter lifetime tracking
Previously, Clang's lifetime analysis was not properly tracking the
lifetime of function parameters, causing it to miss important
use-after-return bugs when parameter values were returned by reference
or address. This change ensures that parameters are properly tracked in
the CFG, allowing the analyzer to correctly identify when stack memory
associated with parameters is returned.
Fixes https://github.com/llvm/llvm-project/issues/169014
Commit: f545c2cec12f77f1fb61ccf07393f434d456ad94
https://github.com/llvm/llvm-project/commit/f545c2cec12f77f1fb61ccf07393f434d456ad94
Author: David Stone <davidfromonline at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaDeclCXX.cpp
Log Message:
-----------
[clang][NFC] Don't copy into a vector just to iterate in `IsInitListMemberExprInitialized` (#169385)
Commit: 0c9c62adf165ebf4128bcfe9863fa0c524b46b7b
https://github.com/llvm/llvm-project/commit/0c9c62adf165ebf4128bcfe9863fa0c524b46b7b
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
Log Message:
-----------
[PowerPC ]convert `(setcc (and X, 1), 0, eq)` to `XORI (and X, 1), 1` (#168384)
Convert `(setcc (and X, 1), 0, eq)` to `XORI (and X, 1), 1` , it will save one instruction.
Commit: d7dcc108fc3ada2330277424495b676d52de1765
https://github.com/llvm/llvm-project/commit/d7dcc108fc3ada2330277424495b676d52de1765
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/docs/DeveloperPolicy.rst
M llvm/utils/git/github-automation.py
Log Message:
-----------
[GitHub] Add review instructions for commit access requests (#168971)
As discussed in
https://discourse.llvm.org/t/clarification-on-how-to-accept-commit-access-requests/88728,
clarify reviewer instructions for how to accept commit access requests.
Commit: 1d30ae6e402a28018a5574b7c68d71aac14acd63
https://github.com/llvm/llvm-project/commit/1d30ae6e402a28018a5574b7c68d71aac14acd63
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
AMDGPU: Stop forcing RequiresCodeGenSCCOrder (#169522)
This hasn't been strictly necessary since c897c13dde.
Practically this makes little difference; we still enable IPRA
by default which implies this option. By removing this explicit
force, -enable-ipra=0 has the expected change in the pass pipeline
to remove the DummyCGSCC runs.
Commit: 8f1bb92bbfa45d49103953dad0d0a5dcfd388959
https://github.com/llvm/llvm-project/commit/8f1bb92bbfa45d49103953dad0d0a5dcfd388959
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
M llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
M llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
Log Message:
-----------
[NVPTX] Fix lit test issues from masked load/store implementation (#169535)
>From this commit:
https://github.com/llvm/llvm-project/commit/17852deda7fb9dabb41023e2673025c630b9369d,
Build was broken here:
https://lab.llvm.org/buildbot/#/builders/155/builds/15135/steps/7/logs/stdio.
I think this should fix things.
Commit: 6c8ff4f2bbae6fe29b0ef67edb70e6d73b47beb3
https://github.com/llvm/llvm-project/commit/6c8ff4f2bbae6fe29b0ef67edb70e6d73b47beb3
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Log Message:
-----------
[NVPTX] Fix maybe unused variable in 17852ded (#169542)
Commit: dce95b2ea41e8585cd1e3e2ce07f5d692a970949
https://github.com/llvm/llvm-project/commit/dce95b2ea41e8585cd1e3e2ce07f5d692a970949
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACCLoop.cpp
Log Message:
-----------
[OpenACC][CIR][NFC] Remove 'NYI' diagnostics, since we're done with t… (#169543)
…hese
We've finished all of the clauses/etc that we're going to use this
visitor for, so we can remove the SourceLocation we used just for that,
and replace all NYI with unreachables.
Commit: a8e0afe98853418e1367274e6f04f7ba255de199
https://github.com/llvm/llvm-project/commit/a8e0afe98853418e1367274e6f04f7ba255de199
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/test/CIR/CodeGen/vector-ext-element.cpp
Log Message:
-----------
[CIR] ArraySubscriptExpr on ExtVectorElementExpr (#169158)
Implement ArraySubscriptExpr support for ExtVectorElementExpr
Commit: 2d78b1409eeab558cfc1b64ab39211af00c5f35f
https://github.com/llvm/llvm-project/commit/2d78b1409eeab558cfc1b64ab39211af00c5f35f
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/OpenMPKinds.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/lib/Parse/ParseOpenMP.cpp
A clang/test/OpenMP/need_device_ptr_kind_ast_print.cpp
A clang/test/OpenMP/need_device_ptr_kind_messages.cpp
Log Message:
-----------
[OpenMP][Clang] Parsing/Sema support for `need_device_ptr(fb_nullify/fb_preserve)`. (#168905)
This patch adds parsing, semantic handling, and diagnostics for the
`OpenMP 6.1 fb_nullify` and` fb_preserve` fallback modifiers used with
the `need_device_ptr` map modifier.
Commit: 622dbb372bfefc135c3cdf967ae6f3b55ffa4a16
https://github.com/llvm/llvm-project/commit/622dbb372bfefc135c3cdf967ae6f3b55ffa4a16
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
Log Message:
-----------
AMDGPU: Add more tests for 32-bit constant address space (#168976)
The sub-dword cases just assert now, so comment those out.
Commit: 20ca85b69fc06feb75f67414d54f3830748bb456
https://github.com/llvm/llvm-project/commit/20ca85b69fc06feb75f67414d54f3830748bb456
Author: Jez Ng <me at jezng.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/InputFiles.cpp
M lld/test/MachO/x86-64-relocs.s
Log Message:
-----------
[lld] macho: Support section branch relocations, including the 1-byte form (#169062)
I noticed that we had a hardcoded value of 4 for the pcrel section
relocations, which seems like an issue given that we recently added
support for 1-byte branch relocations in
https://github.com/llvm/llvm-project/pull/164439. The code included an
assert that the relevant relocation had the BYTE4 attribute, but that is
actually not enough to use a hardcoded value of 4: we need to assert
that the *other* `BYTE<n>` attributes are not set either.
However, since we did not support local branch relocations, that doesn't
seem to have mattered in practice. That said, local branch relocations
can be emitted by compilers, and ld64 does handle the 4-byte version of
them, so I've added support for it here.
ld64 actually seems to reject 1-byte section relocations, so the
questionable code is actually probably fine (minus the incorrect
assert). So we have two options: add an equivalent check in LLD, or just
support 1-byte local branch relocations. Supporting it actually requires
less code, so I've gone with that option here.
Commit: 2ee12f191a005363259e3a95ccdf459d9044eadf
https://github.com/llvm/llvm-project/commit/2ee12f191a005363259e3a95ccdf459d9044eadf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/gws_agpr.ll
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
A llvm/test/MC/AMDGPU/ds_gws_sgpr_err.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
Log Message:
-----------
AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)
On targets that require even aligned 64-bit VGPRs, GWS operands
require even alignment of a 32-bit operand. Previously we had a hacky
post-processing which added an implicit operand to try to manage
the constraint. This would require special casing in other passes
to avoid breaking the operand constraint. This moves the handling
into the instruction definition, so other passes no longer need
to consider this edge case. MC still does need to special case this,
to print/parse as a 32-bit register. This also still ends up net
less work than introducing even aligned 32-bit register classes.
This also should be applied to the image special case.
Commit: 3a27fc48117ba7e062c3cfa0006badb64446ed69
https://github.com/llvm/llvm-project/commit/3a27fc48117ba7e062c3cfa0006badb64446ed69
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Omit VTYPE in VSETVLIInfo::print() when state is uninit or unknown. (#169459)
Commit: eab23e199aef18c2052c08171129633233ab98f5
https://github.com/llvm/llvm-project/commit/eab23e199aef18c2052c08171129633233ab98f5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Log Message:
-----------
[RISCV] Don't add Zilsd pairing hints if other part of the pair is reserved. (#169538)
Commit: ebe40066545fd0ad2e88c5e48b7751195d9a9eca
https://github.com/llvm/llvm-project/commit/ebe40066545fd0ad2e88c5e48b7751195d9a9eca
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/CMakeLists.txt
Log Message:
-----------
[mlir] Fix build failure with BUILD_SHARED_LIBS=ON
/usr/bin/ld: tools/mlir/lib/Dialect/GPU/Pipelines/CMakeFiles/obj.MLIRGP
UPipelines.dir/GPUToXeVMPipeline.cpp.o: in function `mlir::gpu::buildLo
werToXeVMPassPipeline(mlir::OpPassManager&, mlir::gpu::GPUToXeVMPipelin
eOptions const&)':
GPUToXeVMPipeline.cpp:(.text._ZN4mlir3gpu28buildLowerToXeVMPassPipeline
ERNS_13OpPassManagerERKNS0_24GPUToXeVMPipelineOptionsE+0x1293): undefin
ed reference to `mlir::createConvertVectorToLLVMPass()'
Commit: 6c48fbc1dcfbd44a47f126f21e575340b67aac06
https://github.com/llvm/llvm-project/commit/6c48fbc1dcfbd44a47f126f21e575340b67aac06
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/test/X86/lit.local.cfg
M bolt/test/lit.local.cfg
Log Message:
-----------
[BOLT][Tests] Use AT&T assembler syntax only for X86 tests (#169541)
Enabling AT&T syntax for all tests is broken when X86 target is not
enabled as reported in #167225.
Commit: 0917a38c694bd2558b79c2b6d51fee2308dd94dd
https://github.com/llvm/llvm-project/commit/0917a38c694bd2558b79c2b6d51fee2308dd94dd
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[PowerPC] Fix a warning
This patch fixes:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15676:17: error: unused
variable 'CC' [-Werror,-Wunused-variable]
Commit: af0fcf85c812867c1d03f390d5afbbbc5b7f1584
https://github.com/llvm/llvm-project/commit/af0fcf85c812867c1d03f390d5afbbbc5b7f1584
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/include/mlir/TableGen/Pattern.h
M mlir/lib/TableGen/Pattern.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
Log Message:
-----------
[mlir][tblgen] Don't echo absolute paths into rewrite pattern source (#168984)
Currently, the declarative pattern rewrite generator will always print
the [source]:[line](s) from which a pattern came. This is a useful
debugging hint, but it causes problem when absolute paths are used as
arguments to mlir-tblgen (which LLVM's build rules automatically do).
Specifially, it causes the source to be tied to the build location,
harning reproducability and our collective ability to get ccache hits
from, say, separate worktrees.
This commit resolves the issue by replacing absolute paths in thes
"Generated from:" comments with their filenames. (The alternative would
have been to implement an entire file-prefix-map the way the C compilers
do, but since this is an isolated incident, I chose to resolve it
locally.)
Commit: 36947982106686570383945c2bbf367f447d9edc
https://github.com/llvm/llvm-project/commit/36947982106686570383945c2bbf367f447d9edc
Author: Sergei Druzhkov <serzhdruzhok at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
Log Message:
-----------
[lldb-dap] Add format support for evaluate request (#169132)
This patch adds support for format option in the `evaluate` request
according to
[DAP](https://microsoft.github.io/debug-adapter-protocol/specification#Requests_Evaluate)
specification. Also, fixed typo in `LLDB_DAP_INVALID_VARRERF` constant.
Commit: 0f941f6866910e55e0e7cff30c48740477be0cd8
https://github.com/llvm/llvm-project/commit/0f941f6866910e55e0e7cff30c48740477be0cd8
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
Log Message:
-----------
[flang][cuda] Add support to allocate scalar character types (#169550)
Add support for character declared like:
```
subroutine sub1()
character*4, device :: b
end subroutine
```
Commit: ad3d9fb3cab7f2e9a7337ca3c1bd0018ff6c6158
https://github.com/llvm/llvm-project/commit/ad3d9fb3cab7f2e9a7337ca3c1bd0018ff6c6158
Author: Petr Penzin <ppenzin at tenstorrent.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
Log Message:
-----------
[RISCV] tt-ascalon-d8 vector scheduling (#167066)
Add the vector scheduling model for tt-ascalon-d8 and corresponding
llvm-mca tests.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 8d920725ca56930d301df1c7e090905423645a49
https://github.com/llvm/llvm-project/commit/8d920725ca56930d301df1c7e090905423645a49
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
Log Message:
-----------
[RISCV] Use FMV.D for moving GPRPairs on RV32_Zdinx (#169556)
This is noted by the specification, and should save a dynamic
instruction.
Code size should be no worse than before, as the pairs of moves can
usually be turned into two 16-bit moves, but `fmv.d` is always a 32-bit
instruction.
LLVM can look through a `FSGNJ_D_IN32X`, in
`RISCVInstrInfo::isCopyInstrImpl` which helps copy propagation.
Commit: dbcf5688cca37543ea3304be68516b3ac476eef3
https://github.com/llvm/llvm-project/commit/dbcf5688cca37543ea3304be68516b3ac476eef3
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
[AMDGPU] Simplify VT comparisons. NFC. (#169526)
Automated with `sed -i 's/\.Value//g' lib/Target/AMDGPU/*.td` plus a
tiny bit of manual reformatting.
Commit: 1c9368e01e6ed45e7dbc523d3bddfd900bb6e504
https://github.com/llvm/llvm-project/commit/1c9368e01e6ed45e7dbc523d3bddfd900bb6e504
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
A clang/test/CIR/CodeGen/copy-constructor.cpp
Log Message:
-----------
[CIR] Upstream non-record array init handling (#169429)
This upstreams the code to handle member initialization for non-record
arrays.
Commit: c475f8e5d809e2109a67c8523472eb28cd7bbb2a
https://github.com/llvm/llvm-project/commit/c475f8e5d809e2109a67c8523472eb28cd7bbb2a
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
A clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
Log Message:
-----------
[HLSL] Update vector swizzle elements individually (#169090)
When individual elements of a vector are updated via vector swizzle, it needs to be handled as separate store operations to the individual vector elements.
Clang treats vectors as one unit, so if a part of a vector needs to be updated, the whole vector is loaded, some elements modified, and then the whole vector is stored.
In HLSL vector elements are handled separately. We need to avoid this load/modify/store sequence to prevent overwriting other vector elements that might be getting updated in parallel.
Fixes #152815
Commit: 091aece72b0149bda6d465301fe3934ca570a592
https://github.com/llvm/llvm-project/commit/091aece72b0149bda6d465301fe3934ca570a592
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[VPlan] Remove redundant transferFlags call from replicateByVF (NFC).
Flags are now passed on construction/cloning. Remove unnecessary
transferFlags call, and make code independent of VPRecipeWithIRFlags, to
support additional recipes in the future.
Commit: 00ffc70ba154b8670fc37d1398ce4473bca3a516
https://github.com/llvm/llvm-project/commit/00ffc70ba154b8670fc37d1398ce4473bca3a516
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
Log Message:
-----------
[SLP][NFC]Add a test with commutative instruction with non-commutative op, NFC
Commit: 074d17e9c8cbc6f22e65ba1211787453ea629ccb
https://github.com/llvm/llvm-project/commit/074d17e9c8cbc6f22e65ba1211787453ea629ccb
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/tsd_shared.h
Log Message:
-----------
[scudo] Lock/unlock MutexTSDs in disable/enable. (#169440)
It is possible that a fork could occur while MutexTSDs is being held and
then cause a deadlock in a forked process when something attempts to
lock it again. Instead add it to the enable/disable list of mutexes.
Commit: e894654532a74b669b0b0830007cc6c979b35d56
https://github.com/llvm/llvm-project/commit/e894654532a74b669b0b0830007cc6c979b35d56
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/addrec-may-wrap-udiv-canonicalize.ll
Log Message:
-----------
[SCEV] Add tests for UDiv canonicalization of AddRecs that may wrap.
Add test cases for canonicalizing AddRecs that may wrap.
Commit: 9bf78ab8dd17ecbbecd4157c67e8fb4d95528194
https://github.com/llvm/llvm-project/commit/9bf78ab8dd17ecbbecd4157c67e8fb4d95528194
Author: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
Revert "[GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`." (#169570)
Reverts llvm/llvm-project#166204
There was a build issue due to a missing dependency.
Commit: 49828c23b59959ca9f2c0dc83aeb9ce7f84b5c31
https://github.com/llvm/llvm-project/commit/49828c23b59959ca9f2c0dc83aeb9ce7f84b5c31
Author: Haowei <haowei at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/cmake/caches/Fuchsia.cmake
Log Message:
-----------
[Fuchsia] Bump minimal OS X target to 11.0 (#169568)
libcxx requires minimal macOS 11 to build. This patch bumps the minimal
OS X target in Fuchsia's cmake cache file to 11.0 to satisfy this
requirement.
Commit: 4f39a4ff0ada92870ca1c2dccad382ea04947da8
https://github.com/llvm/llvm-project/commit/4f39a4ff0ada92870ca1c2dccad382ea04947da8
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCOpsInterfacesTest.cpp
Log Message:
-----------
[acc][flang] Add getInitRegion() to GlobalVariableOpInterface (#169569)
Some globals (e.g., fir.global) have initialization regions that may
transitively reference other globals or type descriptors. Add
getInitRegion() to GlobalVariableOpInterface to retrieve these regions,
returning Region* (nullptr if the global uses attributes for
initialization, as with memref.global).
Commit: 5f777b2c8faca3fe28079fc81a7aefbca1edb803
https://github.com/llvm/llvm-project/commit/5f777b2c8faca3fe28079fc81a7aefbca1edb803
Author: daniilavdeev <daniilavdeev237 at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCSymbol.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/MC/MCSymbol.cpp
A llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
Log Message:
-----------
[dwarf] make dwarf fission compatible with RISCV relaxations 1/2 (#166597)
Currently, -gsplit-dwarf and -mrelax are incompatible options in Clang.
The issue is that .dwo files should not contain any relocations, as they
are not processed by the linker. However, relaxable code emits
relocations in DWARF for debug ranges that reside in the .dwo file when
DWARF fission is enabled.
This patch makes DWARF fission compatible with RISC-V relaxations. It
uses the StartxEndx DWARF forms in .debug_rnglists.dwo, which allow
referencing addresses from .debug_addr instead of using absolute
addresses. This approach eliminates relocations from .dwo files.
Commit: 97023fba5546f9d0e762ccbca89cbb8324a9131a
https://github.com/llvm/llvm-project/commit/97023fba5546f9d0e762ccbca89cbb8324a9131a
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/test/CIR/CodeGen/coro-task.cpp
Log Message:
-----------
[CIR] Emit ready and suspend branches for cir.await (#168814)
This PR adds codegen for `cir.await` ready and suspend. One notable
difference from the classic codegen is that, in the suspend branch, it
emits an `AwaitSuspendWrapper`(`.__await_suspend_wrapper__init`)
function that is always inlined. This function wraps the suspend logic
inside an internal wrapper that gets inlined. Example here:
https://godbolt.org/z/rWYGcaaG4
Commit: ebf5d9ef7de29b55fd9e9d504f83689b4013e0de
https://github.com/llvm/llvm-project/commit/ebf5d9ef7de29b55fd9e9d504f83689b4013e0de
Author: Alan Li <me at alanli.org>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-i8-gep.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-var-delta.ll
R llvm/test/Transforms/StraightLineStrengthReduce/path-compression.ll
R llvm/test/Transforms/StraightLineStrengthReduce/pick-candidate.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll
Log Message:
-----------
Revert "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169546)
This reverts commit f67409c3ec7cd45c55656c8159bc42b3918f1116.
cc @fiigii
Including us, several separate groups are experiencing regressions with
this change. This is the smallest reproducer pasted by @akuegel :
https://github.com/llvm/llvm-project/pull/162930#issuecomment-3574307330
Commit: 9534ed9f30043318798a9544461bc174e273e1f3
https://github.com/llvm/llvm-project/commit/9534ed9f30043318798a9544461bc174e273e1f3
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M orc-rt/include/orc-rt/Error.h
M orc-rt/unittests/ErrorTest.cpp
Log Message:
-----------
[orc-rt] Add ErrorAsOutParameter convenience constructor. (#169467)
Allows construction of ErrorAsOutParameters from Error references.
Commit: fd22706e937f7d2563cfa0e433dd735cc5284599
https://github.com/llvm/llvm-project/commit/fd22706e937f7d2563cfa0e433dd735cc5284599
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
A flang/test/Lower/OpenMP/compiler-directives-loop.f90
Log Message:
-----------
[flang][OpenMP] Skip compiler directives in getCollapsedLoopEval (#169565)
Use `getNestedDoConstruct` from Utils to get the nested DoConstructs.
Fixes https://github.com/llvm/llvm-project/issues/169532
Commit: f7a9fcad99e155fed32d98a2d41d1e3bfdeebf48
https://github.com/llvm/llvm-project/commit/f7a9fcad99e155fed32d98a2d41d1e3bfdeebf48
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/test/Lower/CUDA/cuda-atomicadd.cuf
Log Message:
-----------
[flang][cuda] Use PTX instruction for atomicAdd with 4xf32 (#169581)
Implementation similar to the clang one in
`clang/lib/Headers/__clang_cuda_intrinsics.h`
Commit: 1c034a372403d539700292cd564773ef3531a423
https://github.com/llvm/llvm-project/commit/1c034a372403d539700292cd564773ef3531a423
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
Log Message:
-----------
[compiler-rt] [UBsan] precommit test (#169579)
Commit: 9c414c428d8464c829d551d0d91029339e746842
https://github.com/llvm/llvm-project/commit/9c414c428d8464c829d551d0d91029339e746842
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/test/CMakeLists.txt
M clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
M clang-tools-extra/clangd/test/index-tools.test
M clang-tools-extra/clangd/test/system-include-extractor.test
Log Message:
-----------
[clangd] Make lit tests work with the internal shell
This makes all of the clangd tests work with the internal shell.
Modifications needed for each test are as follows:
1. system-include-extractor.test was using variable expansion which is
not supported in the internal shell. This patch rewrites it to use
the readfile mechanism along with python. This isn't super pretty but
is readily understandable and there are only two tests across the
monorepo that use this construction, so making it prettier is hard to
justify.
2. include-cleaner-batch-fix.test - Was using $'' construction to create
new lines in a string. Simply replace it with multiple echo commands
to be canonical with the rest of the repository.
3. index-tools.test - Just add IndexBenchmark to the clangd test
depends, so the test now just works unconditionally. This should
significantly increase test coverage at little cost.
Reviewers: ilovepi, HighCommander4, petrhosek, kadircet
Reviewed By: ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/169539
Commit: fa1a7c2231fa1e06db3b9c29b210e3c7c83d7e66
https://github.com/llvm/llvm-project/commit/fa1a7c2231fa1e06db3b9c29b210e3c7c83d7e66
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M bolt/test/X86/lit.local.cfg
M bolt/test/lit.local.cfg
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/cmake/caches/Fuchsia.cmake
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/OpenMPKinds.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/lib/Analysis/CFG.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACCLoop.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/test/Analysis/lifetime-cfg-output.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
A clang/test/CIR/CodeGen/copy-constructor.cpp
M clang/test/CIR/CodeGen/coro-task.cpp
M clang/test/CIR/CodeGen/vector-ext-element.cpp
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
M clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
A clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
A clang/test/OpenMP/need_device_ptr_kind_ast_print.cpp
A clang/test/OpenMP/need_device_ptr_kind_messages.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/unittests/Analysis/FlowSensitive/LoggerTest.cpp
M compiler-rt/lib/scudo/standalone/tsd_shared.h
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Lower/CUDA/cuda-atomicadd.cuf
A flang/test/Lower/OpenMP/compiler-directives-loop.f90
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/InputFiles.cpp
M lld/test/MachO/x86-64-relocs.s
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M llvm/docs/DeveloperPolicy.rst
M llvm/include/llvm/MC/MCSymbol.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/MC/MCSymbol.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
A llvm/test/Analysis/ScalarEvolution/addrec-may-wrap-udiv-canonicalize.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/gws_agpr.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
M llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
M llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
A llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
A llvm/test/MC/AMDGPU/ds_gws_sgpr_err.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
A llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-i8-gep.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-var-delta.ll
R llvm/test/Transforms/StraightLineStrengthReduce/path-compression.ll
R llvm/test/Transforms/StraightLineStrengthReduce/pick-candidate.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
M llvm/utils/git/github-automation.py
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/include/mlir/TableGen/Pattern.h
M mlir/lib/Dialect/GPU/Pipelines/CMakeLists.txt
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/TableGen/Pattern.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCOpsInterfacesTest.cpp
M orc-rt/include/orc-rt/Error.h
M orc-rt/unittests/ErrorTest.cpp
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/d4526fb6e793...fa1a7c2231fa
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