[all-commits] [llvm/llvm-project] 1e1974: [compiler-rt] [test] Avoid error printouts if os.s...
Florian Mayer via All-commits
all-commits at lists.llvm.org
Tue Nov 25 15:47:52 PST 2025
Branch: refs/heads/users/fmayer/spr/main.ubsan-use-fsanitize-recover-runtime-in-codegen
Home: https://github.com/llvm/llvm-project
Commit: 1e1974a903c505de1f42257044b7a03a390d7a8b
https://github.com/llvm/llvm-project/commit/1e1974a903c505de1f42257044b7a03a390d7a8b
Author: Martin Storsjö <martin at martin.st>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M compiler-rt/test/lit.common.cfg.py
Log Message:
-----------
[compiler-rt] [test] Avoid error printouts if os.sysconf is missing (#168857)
This avoids dozens of instances of benign error messages being printed
when running the tests on e.g. Windows:
Traceback (most recent call last):
File "<stdin>", line 1, in <module>
AttributeError: module 'os' has no attribute 'sysconf'
Co-authored-by: Florian Mayer <fmayer at google.com>
Commit: adf4c1dbb62600747fc74843efcdca5c3ee9c26a
https://github.com/llvm/llvm-project/commit/adf4c1dbb62600747fc74843efcdca5c3ee9c26a
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel][clang] Port dea330b38d9c18b68219abdb52baaa72c9f1103d (#169410)
Commit: ba98668dcacc6d6b223f8a53b3c52a7cea2063e8
https://github.com/llvm/llvm-project/commit/ba98668dcacc6d6b223f8a53b3c52a7cea2063e8
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/test/Lower/identical-block-merge-disable.f90
M flang/test/Lower/implicit-interface.f90
M flang/test/Lower/inline_directive.f90
M flang/test/Lower/io-statement-1.f90
M flang/test/Lower/io-write.f90
M flang/test/Lower/location.f90
M flang/test/Lower/module_definition.f90
M flang/test/Lower/module_use.f90
M flang/test/Lower/module_use_in_same_file.f90
M flang/test/Lower/namelist-common-block.f90
M flang/test/Lower/nested-where.f90
M flang/test/Lower/nullify-polymorphic.f90
M flang/test/Lower/pointer-association-polymorphic.f90
M flang/test/Lower/pointer-disassociate.f90
M flang/test/Lower/polymorphic-temp.f90
M flang/test/Lower/polymorphic-types.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/procedure-declarations.f90
M flang/test/Lower/read-write-buffer.f90
M flang/test/Lower/select-type.f90
M flang/test/Lower/statement-function.f90
M flang/test/Lower/variable.f90
M flang/test/Lower/volatile-allocatable.f90
M flang/test/Lower/volatile-openmp1.f90
Log Message:
-----------
[flang][NFC] Strip trailing whitespace from tests (8 of N)
Only some fortran source files in flang/test/Lower have been modified.
The other files in the directory will be cleaned up in subsequent commits
Commit: 4650f8521d85a4dea310b47bd7edce9e0b73ecf0
https://github.com/llvm/llvm-project/commit/4650f8521d85a4dea310b47bd7edce9e0b73ecf0
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/test/Dialect/MemRef/canonicalize.mlir
Log Message:
-----------
[MemRef] Remove memref.dim OffsetSizeAndStrideOpInterface folding (#169327)
OffsetSizeAndStrideOpInterface does not specify whether it's operating
on the input or output shape and in fact different ops implement this in
different ways, which is also why SubviewOp is special cased here.
This "marked as dynamic but not really dynamic" folding is better
handled by shape inference, so just remove the bad fold.
Commit: 590bb3e8e63af0fb46eadf510761bd00e264c018
https://github.com/llvm/llvm-project/commit/590bb3e8e63af0fb46eadf510761bd00e264c018
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
[AArch64] Improve host feature detection. (#160410)
SVE depends on a combination of host support and operating system
support. Sometimes those don't line up with detected host CPU name; make
sure SVE is disabled when it isn't available. Implement this for both
Windows and Linux. (We don't have a codepath for other operating
systems. If someone wants to implement this, it should be possible to
adapt fmv code from compiler-rt.)
While I'm here, also add support for detecting other Windows CPU
features.
For Windows, declare constants ourselves so the code builds on older
SDKs; we also do this in compiler-rt.
Commit: a50824926c07bc42e3d9a9e39de19cc7c71714a5
https://github.com/llvm/llvm-project/commit/a50824926c07bc42e3d9a9e39de19cc7c71714a5
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/SanitizerArgs.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/SanitizerArgs.cpp
M clang/test/Driver/fsanitize.c
Log Message:
-----------
[UBsan] add -fsanitize-handler-preserve-all-regs flag (#168644)
This is currently a no op.
This will be supported for the minimal runtime in a follow up. This
allows
to improve codegen for fsanitize-recover by compiling the handlers with
[[clang::preserve_all]]. This makes sure that the caller does not need
to spill any registers. We do not expect this function to be called
frequently, so this is beneficial for code size.
Commit: ab5ae9a61febab0c76430acc061336b3b8fffe52
https://github.com/llvm/llvm-project/commit/ab5ae9a61febab0c76430acc061336b3b8fffe52
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/module/cooperative_groups.f90
Log Message:
-----------
[flang][cuda] Implement this_cluster for cooperative groups (#169414)
Implement `this_cluster` like `this_group` by lowering it directly like
an intrinsic function. Use the NVVM operation to get the rank and size
information and populate the derived type.
Commit: 4e7ce57e0e2ea04ab04c45127e6862a710460ebd
https://github.com/llvm/llvm-project/commit/4e7ce57e0e2ea04ab04c45127e6862a710460ebd
Author: Yury Plyakhin <yury.plyakhin at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h
M llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
Log Message:
-----------
[Offload][NFC] Offload wrapper cleanup/refactoring (#169411)
Addresses feedback from
https://github.com/llvm/llvm-project/pull/147508#pullrequestreview-3272708203
:
- Update access modifiers for SYCLWrapper members.
- Update comments.
- Update types.
Commit: 9cff3f51d35c4273a48b987bdeddd10248ecb5e4
https://github.com/llvm/llvm-project/commit/9cff3f51d35c4273a48b987bdeddd10248ecb5e4
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Semantics/OpenMP/compiler-directives-loop.f90
M flang/test/Semantics/OpenMP/loop-association.f90
Log Message:
-----------
[flang][OpenMP] Tolerate compiler directives in loop constructs (#169346)
PR168884 flagged compiler directives (!dir$ ...) inside OpenMP loop
constructs as errors. This caused some customer applications to fail to
compile (issue 169229).
Downgrade the error to a warning, and gracefully ignore compiler
directives when lowering loop constructs to MLIR.
Fixes https://github.com/llvm/llvm-project/issues/169229
Commit: 435dbbacad475b12b6cae0a8296e8a46ea684812
https://github.com/llvm/llvm-project/commit/435dbbacad475b12b6cae0a8296e8a46ea684812
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
A clang/test/CIR/CodeGen/global-array-dtor.cpp
Log Message:
-----------
[CIR] Fix a problem with global array dtor lowering (#169416)
In the LoweringPrepare pass, the handling for global array destructor
lowering was mishandling the insertion point, so that if this code
needed to create a declaration for the __cxa_atexit function, that
declaration was being created in the dtor region, rather than at module
scope. This change fixes that.
Commit: fd94b410ef60ca0a0494c2164d7897b698315443
https://github.com/llvm/llvm-project/commit/fd94b410ef60ca0a0494c2164d7897b698315443
Author: Scott Linder <scott.linder at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCDwarf.h
Log Message:
-----------
[MC] Use a variant to hold MCCFIInstruction state (NFC) (#164720)
AMDGPU requires more complex CFI rules, normally these would be
expressed with .cfi_escape, however this would make the CFI unreadable
and makes it difficult to update registers in CFI instructions (also
something AMDGPU requires).
Authored-by: Emma Pilkington <Emma.Pilkington at amd.com>
Commit: ab2a302f0ee8b31404aa4cc454caee40f46602bd
https://github.com/llvm/llvm-project/commit/ab2a302f0ee8b31404aa4cc454caee40f46602bd
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/module/cooperative_groups.f90
A flang/test/Lower/CUDA/cuda-cluster.cuf
Log Message:
-----------
[flang][cuda] Add support for cluster_dim_blocks in cooperative_groups (#169417)
Commit: 420f62e05cc8c54253f52bb99f9b44ad5b9c4f89
https://github.com/llvm/llvm-project/commit/420f62e05cc8c54253f52bb99f9b44ad5b9c4f89
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
M compiler-rt/lib/scudo/standalone/tests/quarantine_test.cpp
M compiler-rt/lib/scudo/standalone/tests/size_class_map_test.cpp
Log Message:
-----------
[scudo] Only print stats when the test fails. (#168000)
When running the tests on other platforms, printing the stats on all of
the passing tests makes it hard to see failure output. Therefore, this
change only prints the stats if the test actually fails.
Commit: d9cf0db2a26245394a1722f688f520e745358373
https://github.com/llvm/llvm-project/commit/d9cf0db2a26245394a1722f688f520e745358373
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/src/new.cpp
Log Message:
-----------
Fix path to aligned_alloc.h in #include statement (#169418)
This fixes #166172.
Commit: 73de1e26b4500f4ffd97c52922b0d45308d54f6d
https://github.com/llvm/llvm-project/commit/73de1e26b4500f4ffd97c52922b0d45308d54f6d
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
Log Message:
-----------
Orc fix waitingongraph coalescer remove (#169287)
Commit: a8a504a08d14b7e855af7616a2663f25508cc184
https://github.com/llvm/llvm-project/commit/a8a504a08d14b7e855af7616a2663f25508cc184
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
Log Message:
-----------
RuntimeLibcalls: Add definitions for vector math functions (#167026)
This is mostly the output of a vibe coded script running on
VecFuncs.def, with a lot of manual cleanups and fixing where the
vibes were off. This is not yet wired up to anything (except for the
handful of calls which are already manually enabled). In the future
the SystemLibrary mechanism needs to be generalized to allow plugging
these sets in based on the flag.
One annoying piece is there are some name conflicts across the
libraries. Some of the libmvec functions have name collisions with some
sleef functions. I solved this by just adding a prefix to the libmvec functions.
It would probably be a good idea to add a prefix to every group. It gets ugly,
particularly since some of the sleef functions started to use a Sleef_
prefix, but mostly do not.
Commit: 25dee656c7d2a3ba90cf4d243c047ea14616e91a
https://github.com/llvm/llvm-project/commit/25dee656c7d2a3ba90cf4d243c047ea14616e91a
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets.cpp
A clang/test/Misc/opencl-c-3.0.incorrect_define.cl
Log Message:
-----------
[OpenCL] Disable __opencl_c_ext_fp64_* features if cl_khr_fp64 is not supported (#169252)
Fix kernel build when cl_khr_fp64 is not enabled:
opencl-c.h:13785:50: error: unknown type name 'atomic_double'
13785 | double __ovld atomic_fetch_min(volatile __global atomic_double
*, double);
opencl-c.h:13785:67: error: use of type 'double' requires cl_khr_fp64
and __opencl_c_fp64 support
13785 | double __ovld atomic_fetch_min(volatile __global atomic_double
*, double);
This is a regression introduced by 423bdb2b. Before that commit,
__opencl_c_ext_fp64_global_atomic_add was guarded by cl_khr_fp64 in
opencl-c-base.h.
Commit: 8947ba017fd8968292e7541a1bbfb82863e54041
https://github.com/llvm/llvm-project/commit/8947ba017fd8968292e7541a1bbfb82863e54041
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A libclc/clc/include/clc/atomic/clc_atomic_flag_clear.h
A libclc/clc/include/clc/atomic/clc_atomic_flag_test_and_set.h
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/atomic/clc_atomic_flag_clear.cl
A libclc/clc/lib/generic/atomic/clc_atomic_flag_test_and_set.cl
A libclc/opencl/include/clc/opencl/atomic/atomic_flag_clear.h
A libclc/opencl/include/clc/opencl/atomic/atomic_flag_test_and_set.h
A libclc/opencl/include/clc/opencl/atomic/atomic_init.h
A libclc/opencl/include/clc/opencl/atomic/atomic_init.inc
A libclc/opencl/include/clc/opencl/types.h
A libclc/opencl/include/clc/opencl/utils.h
M libclc/opencl/lib/generic/SOURCES
A libclc/opencl/lib/generic/atomic/atomic_flag_clear.cl
A libclc/opencl/lib/generic/atomic/atomic_flag_test_and_set.cl
A libclc/opencl/lib/generic/atomic/atomic_init.cl
A libclc/opencl/lib/generic/atomic/atomic_init.inc
Log Message:
-----------
[libclc] Add atomic_init, atomic_flag_clear and atomic_flag_test_and_set (#168329)
Commit: 81e91ea1c52a77093a44a186958cca29cf4d3dd8
https://github.com/llvm/llvm-project/commit/81e91ea1c52a77093a44a186958cca29cf4d3dd8
Author: Chengjun <chengjunp at Nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/NVPTX/bswap.ll
Log Message:
-----------
[NVPTX] Use PRMT instruction to lower i16 bswap (#168968)
Previously, i16 `bswap` was lowered using multiple shift and OR
operations. This patch adds a pattern to directly lower i16 `bswap`
using the `PRMT` (permute) instruction, which is more efficient.
Additionally, the lowering of `bswap` is moved into operation
legalization, which allows for DAGCombiner to optimize the lowered code.
Commit: ac4cf404d8f39e316f37c3732ab75be729604107
https://github.com/llvm/llvm-project/commit/ac4cf404d8f39e316f37c3732ab75be729604107
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/extensions.bzl
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
A utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
A utils/bazel/llvm-project-overlay/third-party/cc_library_wrapper.bzl
M utils/bazel/third_party_build/zstd.BUILD
Log Message:
-----------
[bazel] Use zstd from the BCR (#169146)
This way if the downstream consuming project uses zstd we make sure
they are dedup'd. This uses a new rule to make sure layering_check still
works while allowing us to augment the upstream library rules with LLVM
specific `defines`.
Commit: e23328b45719683c76deae7fab9a24523bf25520
https://github.com/llvm/llvm-project/commit/e23328b45719683c76deae7fab9a24523bf25520
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/module/cooperative_groups.f90
M flang/test/Lower/CUDA/cuda-cluster.cuf
Log Message:
-----------
[flang][cuda] Add support for cluster_block_index in cooperative groups (#169427)
Commit: 1b8626b5064fc58caa8dfd268b8b854f9f1b8543
https://github.com/llvm/llvm-project/commit/1b8626b5064fc58caa8dfd268b8b854f9f1b8543
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/docs/HIPSupport.rst
Log Message:
-----------
Improve HIP docs on fat binary registration ordering (#168566)
Clarify how Clang-generated HIP fat binaries are registered and
unregistered with the HIP runtime, and how this interacts with global
constructors, destructors, and atexit handlers. Document that there is
no strong guarantee on ordering relative to user-defined global
ctors/dtors, recommend that HIP application developers avoid using
kernels or device variables from global ctors/dtors, and describe the
implications for HIP runtime developers (synchronization and guards in
__hipRegisterFatBinary/__hipUnregisterFatBinary). This is motivated by
questions from HIP application and runtime developers about fat binary
registration/unregistration order and its potential interference with
their own initialization and teardown code.
Commit: 2f8e71287542a597be246d34699c93345d096f22
https://github.com/llvm/llvm-project/commit/2f8e71287542a597be246d34699c93345d096f22
Author: Abhinav Gaba <abhinav.gaba at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
A offload/test/mapping/use_device_addr/target_data_use_device_addr_arrsec_fallback.c
A offload/test/mapping/use_device_addr/target_data_use_device_addr_var_fallback.c
A offload/test/mapping/use_device_ptr/target_data_use_device_ptr_var_fallback.c
Log Message:
-----------
[NFC][OpenMP] Add use_device_ptr/addr tests for when the lookup fails. (#169428)
As per OpenMP 5.1, the pointers are expected to retain their original
values when a lookup fails and there is no device pointer to translate
to.
Commit: 78994706d87e617e8063dfb73a585c8f7c7e738c
https://github.com/llvm/llvm-project/commit/78994706d87e617e8063dfb73a585c8f7c7e738c
Author: Matthias Springer <me at m-sp.org>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Conversion/ArithToAPFloat/ArithToAPFloat.cpp
M mlir/lib/ExecutionEngine/APFloatWrappers.cpp
M mlir/test/Conversion/ArithToApfloat/arith-to-apfloat.mlir
M mlir/test/Integration/Dialect/Arith/CPU/test-apfloat-emulation.mlir
Log Message:
-----------
[mlir][arith] Add support for `extf`, `truncf` to `ArithToAPFloat` (#169275)
Add support for `arith.extf` and `arith.truncf`. No support for custom
rounding modes yet.
Commit: e6f2fbb0fa6b519643916e11552c88d680958ede
https://github.com/llvm/llvm-project/commit/e6f2fbb0fa6b519643916e11552c88d680958ede
Author: Ryan Mast <3969255+nightlark at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M .gitattributes
A clang/bindings/python/.git_archival.txt
A clang/bindings/python/.gitignore
A clang/bindings/python/pyproject.toml
Log Message:
-----------
[libclang/python] Enable packaging clang python bindings (#125806)
This adds a pyproject.toml file for packaging the clang Python bindings
as a sdist tarball and pure Python wheel packages for the clang python
bindings. It is required to move updates of the clang and libclang PyPI
packages to the LLVM monorepo. Versioning information is derived from
LLVM git tags (using hatch-vcs, which is based on setuptools_scm), so no
manual updates are needed to bump version numbers. The minimum python
version required is set to 3.10 due to cindex.py using PEP 604 union
type syntax (str | bytes | None).
The .git_archival.txt file is populated with version information needed
to get accurate version information if the bindings are installed from
an LLVM/clang source code archive. The .gitignore file is populated with
files that may get created as part of building/testing the sdist and
wheel that should not be committed to source control.
This is first step for addressing #125220, and moving publishing of the
clang and libclang PyPI packages into the LLVM monorepo.
Signed-off-by: Ryan Mast <mast.ryan at gmail.com>
Commit: 1782d27e67b9cde01a3722a1380ae3558da64452
https://github.com/llvm/llvm-project/commit/1782d27e67b9cde01a3722a1380ae3558da64452
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchSelectionDAGInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchSelectionDAGInfo.h
Log Message:
-----------
[LoongArch] Fix for `VLDREPL` node validation (#168993)
Commit: 196f6de75a0fe6c66e58a9bbd90b30f7c4a69bde
https://github.com/llvm/llvm-project/commit/196f6de75a0fe6c66e58a9bbd90b30f7c4a69bde
Author: Mend Renovate <bot at renovateapp.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M .github/workflows/bazel-checks.yml
M .github/workflows/build-ci-container-tooling.yml
M .github/workflows/build-ci-container-windows.yml
M .github/workflows/build-ci-container.yml
M .github/workflows/build-metrics-container.yml
M .github/workflows/check-ci.yml
M .github/workflows/ci-post-commit-analyzer.yml
M .github/workflows/commit-access-greeter.yml
M .github/workflows/commit-access-review.yml
M .github/workflows/docs.yml
M .github/workflows/email-check.yaml
M .github/workflows/gha-codeql.yml
M .github/workflows/hlsl-test-all.yaml
M .github/workflows/issue-release-workflow.yml
M .github/workflows/issue-subscriber.yml
M .github/workflows/issue-write.yml
M .github/workflows/libc-fullbuild-tests.yml
M .github/workflows/libc-overlay-tests.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/libclang-python-tests.yml
M .github/workflows/libcxx-build-and-test.yaml
M .github/workflows/libcxx-build-containers.yml
M .github/workflows/libcxx-check-generated-files.yml
M .github/workflows/libcxx-run-benchmarks.yml
M .github/workflows/llvm-abi-tests.yml
M .github/workflows/merged-prs.yml
M .github/workflows/mlir-spirv-tests.yml
M .github/workflows/new-prs.yml
M .github/workflows/pr-code-format.yml
M .github/workflows/pr-code-lint.yml
M .github/workflows/pr-request-release-note.yml
M .github/workflows/pr-subscriber.yml
M .github/workflows/premerge.yaml
M .github/workflows/release-asset-audit.yml
M .github/workflows/release-binaries.yml
M .github/workflows/release-documentation.yml
M .github/workflows/release-doxygen.yml
M .github/workflows/release-lit.yml
M .github/workflows/release-sources.yml
M .github/workflows/release-tasks.yml
M .github/workflows/scorecard.yml
M .github/workflows/spirv-tests.yml
M .github/workflows/test-unprivileged-download-artifact.yml
M .github/workflows/version-check.yml
Log Message:
-----------
Update actions/checkout action to v6 (#169258)
This PR contains the following updates:
| Package | Type | Update | Change |
|---|---|---|---|
| [actions/checkout](https://redirect.github.com/actions/checkout) |
action | major | `v5.0.0` -> `v6.0.0` |
Commit: 3db8ed05004d4a1f2fb7cb34813c5e44a2e6722a
https://github.com/llvm/llvm-project/commit/3db8ed05004d4a1f2fb7cb34813c5e44a2e6722a
Author: Matthias Springer <me at m-sp.org>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Conversion/ArithToAPFloat/ArithToAPFloat.cpp
M mlir/lib/ExecutionEngine/APFloatWrappers.cpp
M mlir/test/Conversion/ArithToApfloat/arith-to-apfloat.mlir
M mlir/test/Integration/Dialect/Arith/CPU/test-apfloat-emulation.mlir
Log Message:
-----------
[mlir][arith] Add support for `fptosi`, `fptoui` to `ArithToAPFloat` (#169277)
Add support for `arith.fptosi` and `arith.fptoui`.
Commit: d7f630139023d3d13d38f0bc42536b67f1f5e38f
https://github.com/llvm/llvm-project/commit/d7f630139023d3d13d38f0bc42536b67f1f5e38f
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/string
M libcxx/test/libcxx/diagnostics/string.nodiscard.verify.cpp
Log Message:
-----------
[libc++][string] Applied `[[nodiscard]]` to non-member functions (#169330)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: b63a1883c153245837933e646bdf6c2b4a7bb36b
https://github.com/llvm/llvm-project/commit/b63a1883c153245837933e646bdf6c2b4a7bb36b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Use a switch in VSETVLIInfo::print(). NFC (#169441)
This allows the compiler to verify we've covered all enum values.
Commit: 8217c6415ab76c2a0f06705100c76207cd1e6bc0
https://github.com/llvm/llvm-project/commit/8217c6415ab76c2a0f06705100c76207cd1e6bc0
Author: Kewen Meng <Kewen.Meng at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCDwarf.h
Log Message:
-----------
Revert "[MC] Use a variant to hold MCCFIInstruction state (NFC)" (#169442)
Reverts llvm/llvm-project#164720
Revert to unblock bots.
https://lab.llvm.org/buildbot/#/builders/140/builds/34645
Commit: 6ec686735c850d05592b28783f8300c725a50d78
https://github.com/llvm/llvm-project/commit/6ec686735c850d05592b28783f8300c725a50d78
Author: Matthias Springer <me at m-sp.org>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Conversion/ArithToAPFloat/ArithToAPFloat.cpp
M mlir/lib/ExecutionEngine/APFloatWrappers.cpp
M mlir/test/Conversion/ArithToApfloat/arith-to-apfloat.mlir
M mlir/test/Integration/Dialect/Arith/CPU/test-apfloat-emulation.mlir
Log Message:
-----------
[mlir][arith] Add support for `sitofp`, `uitofp` to `ArithToAPFloat` (#169284)
Add support for `arith.sitofp` and `arith.uitofp`.
Commit: 31d4150fd476f204d3f2a8e2d656a668158a70d8
https://github.com/llvm/llvm-project/commit/31d4150fd476f204d3f2a8e2d656a668158a70d8
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
A llvm/test/TableGen/ValueTypeByHwModeMissingRegInfo.td
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Log Message:
-----------
[TableGen] Change a reachable assert to a fatal error
I hit this when using a RegisterClass with a ValueTypeByHwMode that
was missing the RegInfos field. Add a test for this error.
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/169439
Commit: f0bb5cfda7c54f3fa0c1ef0bbe82e3405ed80110
https://github.com/llvm/llvm-project/commit/f0bb5cfda7c54f3fa0c1ef0bbe82e3405ed80110
Author: Erik Enikeev <evonatarius at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsInstrFPU.td
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
A llvm/test/CodeGen/Mips/fp-intrinsics.ll
Log Message:
-----------
[Mips] Add instruction selection for strict FP (#168870)
This consists of marking the various strict opcodes as legal, and
adjusting instruction selection patterns so that 'op' is 'any_op'. The
changes are similar to those in D114946 for AArch64 and #160696 for ARM.
Only Mips32/64 FPU instructions are affected.
Added lowering for for STRICT_FP_TO_UINT and STRICT_FP_TO_SINT ops.
Commit: c6f433e880a01a29325f4d7d2b98c84feecf2297
https://github.com/llvm/llvm-project/commit/c6f433e880a01a29325f4d7d2b98c84feecf2297
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel][libc] Remove target compatibility restrictions for float128 (#169292)
The restrictions here aren't nearly as much about the OS as the compiler
and architecture, but the Bazel restriction was OS-based. Everything
seems to work well on even Arm64 macOS, and I would expect most BSDs and
other OSes to work well with Clang's support on x86-64.
The source code here already handles detecting when there is compiler
support for the type. And the users of this don't `select` or do
anything else to conditionally include the header, so it seems better to
not restrict access to the header from the build system, and instead
continue making the source code compatible or a no-op on relevant
configurations.
Commit: 26362c68579dd4375198aae4651b4d5f8a36c715
https://github.com/llvm/llvm-project/commit/26362c68579dd4375198aae4651b4d5f8a36c715
Author: Petr Penzin <ppenzin at tenstorrent.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add segmented tunes to tt-ascalon-d8 (#168800)
Add TuneOptimizedNFnSegmentedLoadStore tune flags to tt-ascalon-d8
processor definition.
Commit: b1111356e697a7f5c436846f97adf18a353766dc
https://github.com/llvm/llvm-project/commit/b1111356e697a7f5c436846f97adf18a353766dc
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
Log Message:
-----------
[AMDGPU] Pre-commit test for #169213 (NFC)
Commit: 9626c90c335cca55c1a8094f2e802c4139c7173d
https://github.com/llvm/llvm-project/commit/9626c90c335cca55c1a8094f2e802c4139c7173d
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/extensions.bzl
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
M utils/bazel/third_party_build/zlib-ng.BUILD
Log Message:
-----------
[bazel] Use zlib-ng from the BCR (#169450)
This way if a downstream project also uses this, it is dedup'd
Commit: 9c2d5e29947c0ccf5eaef2c11b4533a62bad1f67
https://github.com/llvm/llvm-project/commit/9c2d5e29947c0ccf5eaef2c11b4533a62bad1f67
Author: Erik Enikeev <evonatarius at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
A llvm/test/CodeGen/Mips/fp-strict-fcmp.ll
Log Message:
-----------
[Mips] Set custom lowering for STRICT_FSETCC/STRICT_FSETCCS ops. (#168303)
Commit: 28fde68501032b292f91246c0e79872558d0e74b
https://github.com/llvm/llvm-project/commit/28fde68501032b292f91246c0e79872558d0e74b
Author: Pranav Bhandarkar <pranav.bhandarkar at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
A flang/test/Semantics/OpenMP/target-teams-nesting.f90
Log Message:
-----------
[Flang] - Enhance testing for strictly-nested teams in target regions. (#168437)
This patch enhances the semantics test for checking that teams
directives are strictly nested inside target directives.
Fixes https://github.com/llvm/llvm-project/issues/153173
Commit: 488ed96d665f47d5c31b811288ec1be1b3fa01bc
https://github.com/llvm/llvm-project/commit/488ed96d665f47d5c31b811288ec1be1b3fa01bc
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M orc-rt/unittests/SessionTest.cpp
Log Message:
-----------
[orc-rt] Remove stray debugging output. NFCI. (#169451)
Commit: c25e0d3e2942007919e5a7a0738bea86907bcdb4
https://github.com/llvm/llvm-project/commit/c25e0d3e2942007919e5a7a0738bea86907bcdb4
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/mul-simplification.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-cond-poison.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
Log Message:
-----------
[VPlan] Simplify x + 0 -> x (#169394)
Commit: 675dc35d808d94011f52e650fe1e3218254b5041
https://github.com/llvm/llvm-project/commit/675dc35d808d94011f52e650fe1e3218254b5041
Author: Mend Renovate <bot at renovateapp.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M .github/workflows/gha-codeql.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/llvm-abi-tests.yml
M .github/workflows/scorecard.yml
Log Message:
-----------
Update [Github] Update GHA Dependencies (#169257)
This PR contains the following updates:
| Package | Type | Update | Change | Pending |
|---|---|---|---|---|
| ghcr.io/llvm/ci-ubuntu-24.04-abi-tests | container | digest |
`f80125c` -> `9138b6a` | |
|
[github/codeql-action](https://redirect.github.com/github/codeql-action)
| action | patch | `v4.31.3` -> `v4.31.4` | `v4.31.5` |
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##### CodeQL Action Changelog
See the [releases
page](https://redirect.github.com/github/codeql-action/releases) for the
relevant changes to the CodeQL CLI and language packs.
##### 4.31.4 - 18 Nov 2025
No user facing changes.
See the full
[CHANGELOG.md](https://redirect.github.com/github/codeql-action/blob/v4.31.4/CHANGELOG.md)
for more information.
</details>
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Commit: 44a7d2f22aec6ac2019a3674e1390276c2ee7ca5
https://github.com/llvm/llvm-project/commit/44a7d2f22aec6ac2019a3674e1390276c2ee7ca5
Author: David Green <david.green at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/test/CodeGen/AArch64/combine-sdiv.ll
M llvm/test/CodeGen/AArch64/rem-by-const.ll
M llvm/test/CodeGen/AArch64/srem-lkk.ll
Log Message:
-----------
[AArch64] Add patterns for add(x, trunc(shift)) (#168927)
This can be lowered to a 64bit add where we only use the bottom 32bits
of the result. It is conceptually the same as
https://alive2.llvm.org/ce/z/Xfz3Rf, but with the sext replaced by an
anyext.
Commit: 1d64fd5d42671d15ed8cd0fc31f71a4ad1e791b6
https://github.com/llvm/llvm-project/commit/1d64fd5d42671d15ed8cd0fc31f71a4ad1e791b6
Author: David Green <david.green at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Basic/arm_mve_defs.td
M clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
M clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
M clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
M clang/utils/TableGen/MveEmitter.cpp
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
A llvm/test/CodeGen/Thumb2/mve-intrinsics/strict-intrinsics.ll
M llvm/test/CodeGen/Thumb2/mve-intrinsics/vabdq.ll
M llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
Log Message:
-----------
[ARM] Introduce intrinsics for MVE add/sub/mul under strict-fp. (#169156)
As far as I understand, the MVE fp vadd/vsub/vmul instructions will set
exception flags in the same ways as scalar fadd/fsub/fmul, but will not
honor flush-to-zero (for f32 they always flush, for f16 they follows the
fpsrc flags) and will always use the default rounding mode.
This means that we cannot convert the vadd_f23/vsub_f32/vmul_f32
intrinsics to llvm.constrained.fadd/fsub/fmul and then vadd/vsub/vmul
without changing the expected behaviour under strict-fp. This patch
introduces a set in intrinsics that we can use instead, going from
vadd_f32 -> llvm.arm.mve.vadd -> MVE_VADD.
The current implementations assumes that the standard variant of a
strictfp alternative will be a IRBuilder, this can be changed to take a
IRBuilder or IRInt.
Commit: 30c49a40222a8e2f90565370ab20253c1e426383
https://github.com/llvm/llvm-project/commit/30c49a40222a8e2f90565370ab20253c1e426383
Author: Men-cotton <mencotton0410 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
A mlir/test/Target/LLVMIR/anonymous-tbaa.mlir
Log Message:
-----------
[mlir][LLVMIR] Handle anonymous TBAA roots during metadata emission (#169167)
This commit enhances MLIR's TBAA export with support for anonymous TBAA roots. The import for this was around for a bit but the export was missing.
Fixes: #160721
Commit: 5490bcf4aa3c028e5c2cdbcd0d906e5a876d23bc
https://github.com/llvm/llvm-project/commit/5490bcf4aa3c028e5c2cdbcd0d906e5a876d23bc
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
Log Message:
-----------
[BOLT] Add missing new line. NFC
Commit: f817a1b0394b7f722b4bb13e9aeead5e177ff6d7
https://github.com/llvm/llvm-project/commit/f817a1b0394b7f722b4bb13e9aeead5e177ff6d7
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Optimizer/Builder/Runtime/Reduction.cpp
M lldb/include/lldb/API/SBStructuredData.h
M mlir/include/mlir/Analysis/DataFlow/IntegerRangeAnalysis.h
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
Log Message:
-----------
[NFC] Fix typo of `integer` (#169325)
Commit: a39af125dba2c07f100236d210b6a948b7316acb
https://github.com/llvm/llvm-project/commit/a39af125dba2c07f100236d210b6a948b7316acb
Author: Dharuni R Acharya <125176188+DharuniRAcharya at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
M llvm/lib/IR/CMakeLists.txt
A llvm/lib/IR/NVVMIntrinsicUtils.cpp
Log Message:
-----------
[NVVM] Move pretty-print functions from NVVMIntrinsicUtils.h to cpp file (#168997)
This patch moves the print functions from `NVVMIntrinsicUtils.h` to
`NVVMIntrinsicUtils.cpp`, a file created in the `llvm/lib/IR` directory.
Signed-off-by: Dharuni R Acharya <dharunira at nvidia.com>
Commit: 6193f2aeda1d5ca30cf990e28956824eefdc97f1
https://github.com/llvm/llvm-project/commit/6193f2aeda1d5ca30cf990e28956824eefdc97f1
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
Log Message:
-----------
[AArch64] Assert `expandMOVImm` prioritizes optimal single MOVZ/N (#169341)
The expansion of move immediate in `expandMOVImm` follows the priority
of the `MOV` alias. In addition, the selection there properly prefers
expansion based on perf optimality order. This change adds a simple
assert that `expandMOVImmSimple` expands a single optimal MOVZ/MOVK.
Commit: ed95c4d6ecf0a8e842cb9d91c09d9679c1f3bf79
https://github.com/llvm/llvm-project/commit/ed95c4d6ecf0a8e842cb9d91c09d9679c1f3bf79
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
Log Message:
-----------
[BOLT][BTI] Add MCPlusBuilder::createBTI (#167305)
- creates a BTI j|c landing pad MCInst.
- create getBTIHintNum utility in AArch64/Utils, to make sure BOLT
generates BTI immediates the same way as LLVM.
- add MCPlusBuilder unittests to cover new function.
Commit: 2ce363d25226c2d502d19917ca8502115c953599
https://github.com/llvm/llvm-project/commit/2ce363d25226c2d502d19917ca8502115c953599
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
Log Message:
-----------
[gn build] Port a39af125dba2
Commit: eb568d6d0ce1a2b0f26f47e20b0051842a3f9746
https://github.com/llvm/llvm-project/commit/eb568d6d0ce1a2b0f26f47e20b0051842a3f9746
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
M llvm/test/CodeGen/AArch64/sme-zt0-state.ll
Log Message:
-----------
[AArch64][SME] Handle zeroing ZA and ZT0 in functions with ZT0 state (#166361)
In the MachineSMEABIPass, if we have a function with ZT0 state, then
there are some additional cases where we need to zero ZA and ZT0.
If the function has a private ZA interface, i.e., new ZT0 (and new ZA if
present). Then ZT0/ZA must be zeroed when committing the incoming ZA
save.
If the function has a shared ZA interface, e.g. new ZA and shared ZT0.
Then ZA must be zeroed on function entry (without a ZA save commit).
The logic in the ABI pass has been reworked to use an "ENTRY" state to
handle this (rather than the more specific "CALLER_DORMANT" state).
Commit: a086fb2fbbc0f488dd2a2c60d09196ea7218742f
https://github.com/llvm/llvm-project/commit/a086fb2fbbc0f488dd2a2c60d09196ea7218742f
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
A llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/spillv16.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.mir
Log Message:
-----------
[AMDGPU][gfx1250] Add wait_xcnt before any access that cannot be repeated (#168852)
The xcnt wait is actually required before any memory access that can
only be done once, so atomic stores and volatile accesses are affected.
This patch also ensures buffer instructions are handled.
Commit: cf5234bac45567e2431b9e668999d4f6d65b7ac8
https://github.com/llvm/llvm-project/commit/cf5234bac45567e2431b9e668999d4f6d65b7ac8
Author: Jie Fu <jiefu at tencent.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
Log Message:
-----------
[AArch64] Silence a warning (NFC)
/llvm-project/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp:952:12:
error: unused variable 'SMEFnAttrs' [-Werror,-Wunused-variable]
SMEAttrs SMEFnAttrs = AFI->getSMEFnAttrs();
^
1 error generated.
Commit: a11e7347fb9618b981cde12f494f58d55b509e2c
https://github.com/llvm/llvm-project/commit/a11e7347fb9618b981cde12f494f58d55b509e2c
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M .gitignore
Log Message:
-----------
[llvm][nfc] Ignore OpenAI Codex artifacts (#162481)
Follow-up to #153853 to also ignore Codex artifacts [1]. AGENTS.md may
be at the root or in sub-directories, so unlike other Markdown config
files I've not prefixed it with '/'.
[1] https://github.com/openai/codex/blob/main/docs/getting-started.md#memory-with-agentsmd
Commit: 86fbaef99a53c5a0d3d5b96011797215296ec478
https://github.com/llvm/llvm-project/commit/86fbaef99a53c5a0d3d5b96011797215296ec478
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
A cmake/Modules/GetToolchainDirs.cmake
M flang-rt/CMakeLists.txt
M flang-rt/cmake/modules/AddFlangRT.cmake
M flang-rt/cmake/modules/AddFlangRTOffload.cmake
A flang-rt/cmake/modules/FlangRTIntrospection.cmake
R flang-rt/cmake/modules/GetToolchainDirs.cmake
M flang-rt/lib/runtime/CMakeLists.txt
A flang-rt/lib/runtime/__cuda_builtins.f90
A flang-rt/lib/runtime/__cuda_device.f90
A flang-rt/lib/runtime/__fortran_builtins.f90
A flang-rt/lib/runtime/__fortran_ieee_exceptions.f90
A flang-rt/lib/runtime/__fortran_type_info.f90
A flang-rt/lib/runtime/__ppc_intrinsics.f90
A flang-rt/lib/runtime/__ppc_types.f90
A flang-rt/lib/runtime/cooperative_groups.f90
A flang-rt/lib/runtime/cudadevice.f90
A flang-rt/lib/runtime/ieee_arithmetic.f90
A flang-rt/lib/runtime/ieee_exceptions.f90
A flang-rt/lib/runtime/ieee_features.f90
A flang-rt/lib/runtime/iso_c_binding.f90
A flang-rt/lib/runtime/iso_fortran_env.f90
A flang-rt/lib/runtime/iso_fortran_env_impl.f90
A flang-rt/lib/runtime/mma.f90
M flang-rt/test/lit.site.cfg.py.in
M flang-rt/unittests/CMakeLists.txt
M flang/CMakeLists.txt
M flang/include/flang/Frontend/CompilerInvocation.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Semantics/semantics.cpp
R flang/module/.clang-format
R flang/module/__cuda_builtins.f90
R flang/module/__cuda_device.f90
R flang/module/__fortran_builtins.f90
R flang/module/__fortran_ieee_exceptions.f90
R flang/module/__fortran_type_info.f90
R flang/module/__ppc_intrinsics.f90
R flang/module/__ppc_types.f90
R flang/module/cooperative_groups.f90
R flang/module/cudadevice.f90
R flang/module/ieee_arithmetic.f90
R flang/module/ieee_exceptions.f90
R flang/module/ieee_features.f90
R flang/module/iso_c_binding.f90
R flang/module/iso_fortran_env.f90
R flang/module/iso_fortran_env_impl.f90
R flang/module/mma.f90
M flang/test/CMakeLists.txt
M flang/test/Driver/Inputs/ieee_arithmetic.mod
M flang/test/Driver/Inputs/iso_fortran_env.mod
A flang/test/Driver/intrinsic-module-path.F90
R flang/test/Driver/intrinsic-module-path.f90
M flang/test/Driver/lto-fatlto.f90
M flang/test/Driver/pp-fixed-form.f90
M flang/test/Lower/HLFIR/type-bound-call-mismatch.f90
M flang/test/Lower/OpenMP/simd_aarch64.f90
M flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90
M flang/test/Preprocessing/fixed-free.f
M flang/test/Preprocessing/no-pp-if.f90
M flang/test/Semantics/bug163242.f90
M flang/test/Semantics/bug164303.f90
M flang/test/lit.cfg.py
M flang/test/lit.site.cfg.py.in
M flang/tools/CMakeLists.txt
M flang/tools/bbc/bbc.cpp
R flang/tools/f18/CMakeLists.txt
R flang/tools/f18/dump.cpp
M llvm/runtimes/CMakeLists.txt
M openmp/CMakeLists.txt
M openmp/runtime/CMakeLists.txt
R openmp/runtime/cmake/LibompCheckFortranFlag.cmake
M openmp/runtime/cmake/LibompHandleFlags.cmake
M openmp/runtime/cmake/config-ix.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/test/lit.cfg
M openmp/runtime/test/lit.site.cfg.in
M runtimes/CMakeLists.txt
Log Message:
-----------
[Flang] Move builtin .mod generation into runtimes (#137828)
Move building the .mod files from openmp/flang to openmp/flang-rt using
a shared mechanism. Motivations to do so are:
1. Most modules are target-dependent and need to be re-compiled for each
target separately, which is something the LLVM_ENABLE_RUNTIMES system
already does. Prime example is `iso_c_binding.mod` which encodes the
target's ABI. Most other modules have `#ifdef`-enclosed code as well.
2. CMake has support for Fortran that we should use. Among other things,
it automatically determines module dependencies so there is no need to
hardcode them in the CMakeLists.txt.
3. It allows using Fortran itself to implement Flang-RT. Currently, only
`iso_fortran_env_impl.f90` emits object files that are needed by Fortran
applications (#89403). The workaround of #95388 could be reverted.
Some new dependencies come into play:
* openmp depends on flang-rt for building `lib_omp.mod` and
`lib_omp_kinds.mod`. Currently, if flang-rt is not found then the
modules are not built.
* check-flang depends on flang-rt: If not found, the majority of tests
are disabled. If not building in a bootstrpping build, the location of
the module files can be pointed to using
`-DFLANG_INTRINSIC_MODULES_DIR=<path>`, e.g. in a flang-standalone
build. Alternatively, the test needing any of the intrinsic modules
could be marked with `REQUIRES: flangrt-modules`.
* check-flang depends on openmp: Not a change; tests requiring
`lib_omp.mod` and `lib_omp_kinds.mod` those are already marked with
`openmp_runtime`.
As intrinsic are now specific to the target, their location is moved
from `include/flang` to `<resource-dir>/finclude/flang/<triple>`. The
mechnism to compute the location have been moved from flang-rt
(previously used to compute the location of `libflang_rt.*.a`) to common
locations in `cmake/GetToolchainDirs.cmake` and
`runtimes/CMakeLists.txt` so they can be used by both, openmp and
flang-rt. Potentially the mechnism could also be shared by other
libraries such as compiler-rt.
`finclude` was chosen because `gfortran` uses it as well and avoids
misuse such as `#include <flang/iso_c_binding.mod>`. The search location
is now determined by `ToolChain` in the driver, instead of by the
frontend. Now the driver adds `-fintrinsic-module-path` for that
location to the frontend call (Just like gfortran does).
`-fintrinsic-module-path` had to be fixed for this because ironically it
was only added to `searchDirectories`, but not
`intrinsicModuleDirectories_`. Since the driver determines the location,
tests invoking `flang -fc1` and `bbc` must also be passed the location
by llvm-lit. This works like llvm-lit does for finding the include dirs
for Clang using `-print-file-name=...`.
Commit: f287abd53e03bf0fda9099c0845b25a340a20102
https://github.com/llvm/llvm-project/commit/f287abd53e03bf0fda9099c0845b25a340a20102
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bitcnt-big-integer.ll
M llvm/test/TableGen/CPtrWildcard.td
Log Message:
-----------
[DAG][X86] Improve custom i256/i512 AVX512 CTLZ/CTTZ Handling with MVT::i256/i512 (#168860)
This patch proposes to move the AVX512 CTLZ/CTTZ i256/i512 codegen to
ReplaceNodeResults to allow them to be declared as custom lowering -
this allows expansion of larger int types (e.g. i1024) to fallback to
them during their expansion.
However to declare these i256/i512 ops as custom, we need to add
MVT::i256/i512 simple types - I'm intending to add further large integer
handling in the future, some of which will use vector register
instructions, and its going to be much easier if this can be handled
with i128/i256/i512 types that match the vector register sizes.
This exposed a regression in NVPTX due to their use of EVT::isSimple()
to match their upper integer size bounds.
Commit: 5e7631e14ae334a708b6fc52991a12ab3bb95633
https://github.com/llvm/llvm-project/commit/5e7631e14ae334a708b6fc52991a12ab3bb95633
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll
M llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll
Log Message:
-----------
[LoongArch][DAGCombiner] Combine vand (vnot ..) to vandn (#161037)
After this commit, DAGCombiner will have more opportunities to perform
vector folding. This patch includes several foldings, as follows:
- VANDN(x,NOT(y)) -> AND(NOT(x),NOT(y)) -> NOT(OR(X,Y))
- VANDN(x, SplatVector(Imm)) -> AND(NOT(x), NOT(SplatVector(~Imm)))
Commit: cb63e99e58cbbb687575f2ab3139f9ba7b6e95bf
https://github.com/llvm/llvm-project/commit/cb63e99e58cbbb687575f2ab3139f9ba7b6e95bf
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
M llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
M llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-struct-return.ll
Log Message:
-----------
[VPlan] Include flags in VectorPointerRecipe::printRecipe (#169466)
The change is non-functional with respect to emitted IR.
Commit: 4b137e7446718973e209eb97402d9d06f90b8b0d
https://github.com/llvm/llvm-project/commit/4b137e7446718973e209eb97402d9d06f90b8b0d
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
Log Message:
-----------
[lldb][NFC] Remove code dupl in favour of a named variable in UnwindAssemblyInstEmulation (#169369)
Commit: bc4143b27afaeee1fcf3e8f0024774f3adc1eef9
https://github.com/llvm/llvm-project/commit/bc4143b27afaeee1fcf3e8f0024774f3adc1eef9
Author: Ravil Dorozhinskii <ravil.aviva.com at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[DAG] SDPatternMatch - add m_SpecificFP matcher (#167438)
This patch introduces SpecificFP matcher for SelectionDAG nodes.
This includes:
Adding SpecificFP_match() in SDPatternMatch.h.
Adding test coverage in SelectionDAGPatternMatchTest.cpp.
Closes #165566
Commit: e1b08731e5d81a0483a91da5eb89b1087876b9c2
https://github.com/llvm/llvm-project/commit/e1b08731e5d81a0483a91da5eb89b1087876b9c2
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
R llvm/test/CodeGen/AArch64/pr151592.mir
R llvm/test/CodeGen/AArch64/pr151888.mir
R llvm/test/CodeGen/AArch64/pr164181-reduced.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
R llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
M llvm/test/CodeGen/PowerPC/combine-fneg.ll
M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
M llvm/test/CodeGen/PowerPC/frem.ll
M llvm/test/CodeGen/PowerPC/froundeven-legalization.ll
M llvm/test/CodeGen/PowerPC/half.ll
M llvm/test/CodeGen/PowerPC/ldexp.ll
M llvm/test/CodeGen/PowerPC/llvm.modf.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
R llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
R llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
R llvm/test/CodeGen/X86/pr76416.ll
M llvm/test/CodeGen/X86/subreg-fail.mir
R llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
Log Message:
-----------
Revert "Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG""
This reverts commit bb78728826ff57f3df859e79bfd857b5a175bb6d.
Commit: 51dd3ec13c51b0e399cbceafb84698b7241ed731
https://github.com/llvm/llvm-project/commit/51dd3ec13c51b0e399cbceafb84698b7241ed731
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[MLIR][OpenMP] Bail early in sortMapIndices if indices are the same (#169474)
If we are given the same index in the comparator callback, simply return
false. Otherwise we will end up adding invalid items to
occludedChildren, causing extra items to get removed that should not be,
resulting in failures that manifest in different forms (assertions, asan
failures, ubsan failures, etc.).
Commit: 68c2a8140f7b8a487b7a9d9a53c6568b7336ee62
https://github.com/llvm/llvm-project/commit/68c2a8140f7b8a487b7a9d9a53c6568b7336ee62
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/test/extensions/libcxx/odr_signature.exceptions.sh.cpp
M libcxx/test/extensions/libcxx/odr_signature.hardening.sh.cpp
Log Message:
-----------
[libc++][C++03] Fix ODR tests (#169349)
We don't really need to include `<__config>`. We just need to include a
public C++ header.
Commit: 105900ced185558633e2ca8aa812c8c6c39ef59b
https://github.com/llvm/llvm-project/commit/105900ced185558633e2ca8aa812c8c6c39ef59b
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/__config
M libcxx/include/__configuration/platform.h
M libcxx/include/__random/binomial_distribution.h
M libcxx/src/filesystem/operations.cpp
Log Message:
-----------
[libc++] Always define _LIBCPP_GLIBC_PREREQ (#169405)
Always defining the macro allows us to simplify the few places where
it's used.
Commit: d748c81218bee39dafb9cc0c00ed7831a3ed44c3
https://github.com/llvm/llvm-project/commit/d748c81218bee39dafb9cc0c00ed7831a3ed44c3
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/add_i1.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-entry.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/cse-convergent.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub_i1.ll
M llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
Log Message:
-----------
[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
The 16-bit immediate operand of s_waitcnt_depctr / s_wait_alu has some
unused bits. Previously codegen would set these bits to 1, but setting
them to 0 matches the SP3 assembler behaviour better, which in turn
means that we can print them using the human readable SP3 syntax:
s_wait_alu 0xfffd ; unused bits set to 1
s_wait_alu 0xff9d ; unused bits set to 0
s_wait_alu depctr_va_vcc(0) ; unused bits set to 0, human readable
Note that the set of unused bits changed between GFX10.1 and GFX10.3.
Commit: 17b19c50349053ed7721357f806233d633696bf0
https://github.com/llvm/llvm-project/commit/17b19c50349053ed7721357f806233d633696bf0
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/LoopUnrolling.cpp
M clang/test/Analysis/loop-unrolling.cpp
Log Message:
-----------
[analyzer] Unroll loops of compile-time upper-bounded loops (#169400)
Previously, only literal upper-bounded loops were recognized. This patch
relaxes this matching to accept any compile-time deducible constant
expression.
It would be better to rely on the SVals (values from the symbolic
domain), as those could potentially have more accurate answers, but this
one is much simpler.
Note that at the time we calculate this value, we have not evaluated the
sub-exprs of the condition, consequently, we can't just query the
Environment for the folded SVal.
Because of this, the next best tool in our toolbox is comp-time
evaluating the Expr.
rdar://165363923
Commit: 4e37526fdb37bb6e778a5445b05cb1be539fbda7
https://github.com/llvm/llvm-project/commit/4e37526fdb37bb6e778a5445b05cb1be539fbda7
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
Log Message:
-----------
[AMDGPU] Fix test after #169378
Commit: af3af8ea5a4a0102bfd3998d1898eef6d735b2e4
https://github.com/llvm/llvm-project/commit/af3af8ea5a4a0102bfd3998d1898eef6d735b2e4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/X86/setcc-wide-types.ll
Log Message:
-----------
[X86] setcc-wide-types.ll - cleanup check prefixes NFC (#169488)
Match typical prefixes used in x86 SSE/AVX tests
Commit: e06c148af7ed118ef2ff0774c8ad00838638bb2a
https://github.com/llvm/llvm-project/commit/e06c148af7ed118ef2ff0774c8ad00838638bb2a
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Analysis/IVDescriptors.cpp
Log Message:
-----------
[IVDesc] Use SCEVPatternMatch to improve code (NFC) (#168397)
Commit: 07ad928d92eac995e8d2fc48b0aafde511e9f3a0
https://github.com/llvm/llvm-project/commit/07ad928d92eac995e8d2fc48b0aafde511e9f3a0
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/fill_n.h
A libcxx/include/__algorithm/specialized_algorithms.h
M libcxx/include/__bit_reference
M libcxx/include/module.modulemap.in
Log Message:
-----------
[libc++] Introduce __specialized_algorithms (#167295)
Commit: 262716b35be1fc2c8de511b32d65f54448e0e204
https://github.com/llvm/llvm-project/commit/262716b35be1fc2c8de511b32d65f54448e0e204
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 07ad928d92ea
Commit: 4bc654d6497430c1dd5e4e25aaa84b3dec3e1113
https://github.com/llvm/llvm-project/commit/4bc654d6497430c1dd5e4e25aaa84b3dec3e1113
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
R cmake/Modules/GetToolchainDirs.cmake
M flang-rt/CMakeLists.txt
M flang-rt/cmake/modules/AddFlangRT.cmake
M flang-rt/cmake/modules/AddFlangRTOffload.cmake
R flang-rt/cmake/modules/FlangRTIntrospection.cmake
A flang-rt/cmake/modules/GetToolchainDirs.cmake
M flang-rt/lib/runtime/CMakeLists.txt
R flang-rt/lib/runtime/__cuda_builtins.f90
R flang-rt/lib/runtime/__cuda_device.f90
R flang-rt/lib/runtime/__fortran_builtins.f90
R flang-rt/lib/runtime/__fortran_ieee_exceptions.f90
R flang-rt/lib/runtime/__fortran_type_info.f90
R flang-rt/lib/runtime/__ppc_intrinsics.f90
R flang-rt/lib/runtime/__ppc_types.f90
R flang-rt/lib/runtime/cooperative_groups.f90
R flang-rt/lib/runtime/cudadevice.f90
R flang-rt/lib/runtime/ieee_arithmetic.f90
R flang-rt/lib/runtime/ieee_exceptions.f90
R flang-rt/lib/runtime/ieee_features.f90
R flang-rt/lib/runtime/iso_c_binding.f90
R flang-rt/lib/runtime/iso_fortran_env.f90
R flang-rt/lib/runtime/iso_fortran_env_impl.f90
R flang-rt/lib/runtime/mma.f90
M flang-rt/test/lit.site.cfg.py.in
M flang-rt/unittests/CMakeLists.txt
M flang/CMakeLists.txt
M flang/include/flang/Frontend/CompilerInvocation.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Semantics/semantics.cpp
A flang/module/.clang-format
A flang/module/__cuda_builtins.f90
A flang/module/__cuda_device.f90
A flang/module/__fortran_builtins.f90
A flang/module/__fortran_ieee_exceptions.f90
A flang/module/__fortran_type_info.f90
A flang/module/__ppc_intrinsics.f90
A flang/module/__ppc_types.f90
A flang/module/cooperative_groups.f90
A flang/module/cudadevice.f90
A flang/module/ieee_arithmetic.f90
A flang/module/ieee_exceptions.f90
A flang/module/ieee_features.f90
A flang/module/iso_c_binding.f90
A flang/module/iso_fortran_env.f90
A flang/module/iso_fortran_env_impl.f90
A flang/module/mma.f90
M flang/test/CMakeLists.txt
M flang/test/Driver/Inputs/ieee_arithmetic.mod
M flang/test/Driver/Inputs/iso_fortran_env.mod
R flang/test/Driver/intrinsic-module-path.F90
A flang/test/Driver/intrinsic-module-path.f90
M flang/test/Driver/lto-fatlto.f90
M flang/test/Driver/pp-fixed-form.f90
M flang/test/Lower/HLFIR/type-bound-call-mismatch.f90
M flang/test/Lower/OpenMP/simd_aarch64.f90
M flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90
M flang/test/Preprocessing/fixed-free.f
M flang/test/Preprocessing/no-pp-if.f90
M flang/test/Semantics/bug163242.f90
M flang/test/Semantics/bug164303.f90
M flang/test/lit.cfg.py
M flang/test/lit.site.cfg.py.in
M flang/tools/CMakeLists.txt
M flang/tools/bbc/bbc.cpp
A flang/tools/f18/CMakeLists.txt
A flang/tools/f18/dump.cpp
M llvm/runtimes/CMakeLists.txt
M openmp/CMakeLists.txt
M openmp/runtime/CMakeLists.txt
A openmp/runtime/cmake/LibompCheckFortranFlag.cmake
M openmp/runtime/cmake/LibompHandleFlags.cmake
M openmp/runtime/cmake/config-ix.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/test/lit.cfg
M openmp/runtime/test/lit.site.cfg.in
M runtimes/CMakeLists.txt
Log Message:
-----------
Revert "[Flang] Move builtin .mod generation into runtimes" (#169489)
Reverts llvm/llvm-project#137828
Buildbot error in
https://lab.llvm.org/staging/#/builders/105/builds/37275
Commit: 9e53ef3d8c18648517c7afb06bc0cd01ebbbdfa9
https://github.com/llvm/llvm-project/commit/9e53ef3d8c18648517c7afb06bc0cd01ebbbdfa9
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
A mlir/test/Target/LLVMIR/nvvm/mbar_arrive.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_arrive_drop.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_complete_tx.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_expect_tx.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_init.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_invalid.mlir
R mlir/test/Target/LLVMIR/nvvm/mbarriers.mlir
Log Message:
-----------
[MLIR][NVVM] Update mbarrier.arrive.* Op (#168758)
This patch updates the mbarrier.arrive.* family of Ops to include
all features added up-to Blackwell.
* Update the `mbarrier.arrive` Op to include shared_cluster
memory space, cta/cluster scope and an option to lower using
relaxed semantics.
* An `arrive_drop` variant is added for both the `arrive` and
`arrive.nocomplete` operations.
* Updates for expect_tx and complete_tx operations.
* Verifier checks are added wherever appropriate.
* lit tests are added to verify the lowering to the intrinsics.
TODO:
* Updates for the remaining mbarrier family will be done in
subsequent PRs. (mainly, arrive.expect-tx, test_wait and try_waits)
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 6bf3249fe9771c5732d993304ecee11f55927f9f
https://github.com/llvm/llvm-project/commit/6bf3249fe9771c5732d993304ecee11f55927f9f
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Sema/SemaARM.h
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
A clang/test/Sema/AArch64/builtin_vectorelements.c
Log Message:
-----------
[Clang][Sema] Emit diagnostic for __builtin_vectorelements(<SVEType>) when SVE is not available. (#168097)
As is done for other targets, I've moved the target type checking code
into SemaARM and migrated existing uses.
Fixes https://github.com/llvm/llvm-project/issues/155736
Commit: f0e0a2215827facf1f480753a96833f60ccbcb62
https://github.com/llvm/llvm-project/commit/f0e0a2215827facf1f480753a96833f60ccbcb62
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
Log Message:
-----------
[bazel] Delete redundant visibility (#169493)
default_visibility is already public.
Commit: 1919cd63223fdd6acd8a2c2d515f190160275226
https://github.com/llvm/llvm-project/commit/1919cd63223fdd6acd8a2c2d515f190160275226
Author: Colin Kinloch <colin at kinlo.ch>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/CheckerHelpers.cpp
A clang/test/Analysis/std-c-library-functions-eof-2-rad.c
Log Message:
-----------
[analyzer] Fix non decimal macro values in tryExpandAsInteger (#168632)
Values were parsed into an unsigned APInt with just enough of a bit
width to hold the number then interpreted as signed values. This
resulted in hex, octal and binary literals from being interpreted as
negative when the most significant bit is 1.
For example the `-0b11` would have a bit width of 2, would be
interpreted as -1, then negated to become 1.
Commit: 4e9b76e23b29a0576c0b950e06daa2f2a84c1b65
https://github.com/llvm/llvm-project/commit/4e9b76e23b29a0576c0b950e06daa2f2a84c1b65
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/lib/CIR/CodeGen/CIRGenOpenACCHelpers.h
M clang/test/CIR/CodeGenOpenACC/declare-create.cpp
M clang/test/CIR/CodeGenOpenACC/openacc-not-implemented-global.cpp
R clang/test/CIR/CodeGenOpenACC/openacc-not-implemented.cpp
Log Message:
-----------
[OpenACC][CIR] 'declare' lowering for globals/ns/struct-scopes (+create) (#169409)
This patch does the lowering for a 'declare' construct that is not a
function-local-scope. It also does the lowering for 'create', which has
an entry-op of create and exit-op of delete.
Global/NS/Struct scope 'declare's emit a single 'acc_ctor' and
'acc_dtor' (except in the case of 'link') per variable referenced. The
ctor is the entry op followed by a declare_enter. The dtor is a
get_device_ptr, followed by a declare_exit, followed by a delete(exit
op). This DOES include any necessary bounds.
This patch implements all of the above. We use a separate 'visitor' for
the clauses here since it is particularly different from the other uses,
AND there are only 4 valid clauses. Additionally, we had to split the
modifier conversion into its own 'helpers' file, which will hopefully
get some additional use in the future.
Commit: d54168013aa49876c21d53b9a4a39eec23953096
https://github.com/llvm/llvm-project/commit/d54168013aa49876c21d53b9a4a39eec23953096
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/Transforms/Utils/FunctionComparator.h
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
Log Message:
-----------
[LLVM] Use "syncscope" instead of "synchscope" in comments. NFC. (#134615)
This matches the spelling of the keyword in LLVM IR.
Commit: d615c14c22003522c16f7b82646542eb8e2dddca
https://github.com/llvm/llvm-project/commit/d615c14c22003522c16f7b82646542eb8e2dddca
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
Log Message:
-----------
[RISCV] Update SpacemiT-X60 vector floating-point instructions latencies (#150618)
This PR adds hardware-measured latencies for all instructions defined in
Section 13 of the RVV specification: "Vector Floating-Point
Instructions" to the SpacemiT-X60 scheduling model.
Commit: a7e715a1419ec977ff7d82f028a0449f9d20bf1c
https://github.com/llvm/llvm-project/commit/a7e715a1419ec977ff7d82f028a0449f9d20bf1c
Author: Paul Osmialowski <pawel.osmialowski at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/docs/Vectorizers.rst
Log Message:
-----------
[llvm][docs] Correct the list of the available -fveclib= options to match with the reality (#168205)
The command line reality is this:
$ clang -c prog.c -fveclib=accelerate
error: invalid value 'accelerate' in '-fveclib=accelerate'
$ clang -c prog.c -fveclib=Accelerate
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=libmvec
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=LIBMVEC
error: invalid value 'LIBMVEC' in '-fveclib=LIBMVEC'
$ clang -c prog.c -fveclib=massv
error: invalid value 'massv' in '-fveclib=massv'
$ clang -c prog.c -fveclib=MASSV
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=sleef
error: invalid value 'sleef' in '-fveclib=sleef'
$ clang -c prog.c -fveclib=sleefgnuabi
error: invalid value 'sleefgnuabi' in '-fveclib=sleefgnuabi'
$ clang -c prog.c -fveclib=SLEEF
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=darwin_libsystem_m
error: invalid value 'darwin' in '-fveclib=darwin_libsystem_m'
$ clang -c prog.c -fveclib=Darwin_libsystem_m
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=armpl
error: invalid value 'armpl' in '-fveclib=armpl'
$ clang -c prog.c -fveclib=ARMPL
error: invalid value 'ARMPL' in '-fveclib=ARMPL'
$ clang -c prog.c -fveclib=ArmPL
prog.c:1:2: warning: This is only a test [-W#warnings]
1 | #warning This is only a test
| ^
1 warning generated.
$ clang -c prog.c -fveclib=amdlibm
error: invalid value 'amdlibm' in '-fveclib=amdlibm'
$ clang -c prog.c -fveclib=AMDLIBM
clang: error: unsupported option 'AMDLIBM' for target 'aarch64'
Commit: b37b307715fd1c449698aabad1fcfd188b265f2c
https://github.com/llvm/llvm-project/commit/b37b307715fd1c449698aabad1fcfd188b265f2c
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/__functional/bind.h
M libcxx/include/__functional/bind_back.h
M libcxx/include/__functional/bind_front.h
M libcxx/include/__functional/function.h
M libcxx/include/__functional/mem_fn.h
M libcxx/include/__functional/reference_wrapper.h
M libcxx/test/libcxx/diagnostics/functional.nodiscard.verify.cpp
M libcxx/test/std/utilities/function.objects/refwrap/refwrap.invoke/robust_against_adl.pass.cpp
Log Message:
-----------
[libc++] Applied `[[nodiscard]]` to some general utilities (#169322)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
The following functions/classes have been annotated in this patch:
- [x] `bind_back`, `bind_front`, `bind`
- [x] `function`, `mem_fn`
- [x] `reference_wrapper`
Commit: 077a280cf586b29c6aa37a17637bcb6b91dc121c
https://github.com/llvm/llvm-project/commit/077a280cf586b29c6aa37a17637bcb6b91dc121c
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
A flang/test/Lower/OpenACC/acc-reduction-remapping.f90
Log Message:
-----------
[flang][acc] remap symbol appearing in reduction clause (#168876)
This patch is a follow-up of #162306 for the reduction clause.
Inside the compute region that carries the reduction clause, a new
hlfir.declare is generated for symbol appearing in the reduction clause.
The input of this hlfir.declare is the acc.reduction result. The related
semantics::Symbol is remapped to the hlfir.declare result so that any
reference to the symbol inside the compute region will use this SSA
value as the starting point instead of the SSA value for the host
address.
Commit: 5818435c437c654c8c17c7ba8b7eb8833b7c3229
https://github.com/llvm/llvm-project/commit/5818435c437c654c8c17c7ba8b7eb8833b7c3229
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/basic.ll
Log Message:
-----------
RuntimeLibcalls: Add a few libm entries from TargetLibraryInfo (#167049)
These are floating-point functions recorded in TargetLibraryInfo,
but missing from RuntimeLibcalls.
Commit: 7f8c43a24949e2aa33e5f03f75ac865bb2f11ad8
https://github.com/llvm/llvm-project/commit/7f8c43a24949e2aa33e5f03f75ac865bb2f11ad8
Author: GrumpyPigSkin <130710602+GrumpyPigSkin at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
A llvm/test/CodeGen/X86/GlobalISel/fp-bitcast.ll
Log Message:
-----------
[X86][GISel] Fix crash on bitcasting i16 <-> half with gisel enabled. (#168456)
Added missing checks for casting half to/from i16 with global-isel
enabled.
Fixes #166557
Commit: d8ae4d503ada5509fb526a782816540eb4d15012
https://github.com/llvm/llvm-project/commit/d8ae4d503ada5509fb526a782816540eb4d15012
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/basic.ll
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/ps.ll
Log Message:
-----------
RuntimeLibcalls: Add __memcpy_chk, __memmove_chk, __memset_chk (#167053)
These were in TargetLibraryInfo, but missing from RuntimeLibcalls.
This only adds the cases that already have the non-chk variants
already. Copies the enabled-by-default logic from TargetLibraryInfo,
which is probably overly permissive. Only isPS opts-out.
Commit: 25c95ebfa82e2f6a20cf1282aaef09d1cc598ee7
https://github.com/llvm/llvm-project/commit/25c95ebfa82e2f6a20cf1282aaef09d1cc598ee7
Author: Ming Yan <ming.yan at terapines.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/test/Fir/FirToSCF/do-loop.fir
Log Message:
-----------
[flang][fir] Convert `fir.do_loop` with the unordered attribute to `scf.parallel`. (#168510)
Refines the existing conversion to allow `fir.do_loop` annotated with
`unordered` to be lowered to `scf.parallel`, while other loops retain
their original lowering.
Commit: a51e2ef0fe73dd9ab6e608304ddf2b489c350cf4
https://github.com/llvm/llvm-project/commit/a51e2ef0fe73dd9ab6e608304ddf2b489c350cf4
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
Log Message:
-----------
[VPlan] Treat VPVector(End)PointerRecipe as single-scalar, if ops are. (#169249)
VPVector(End)PointerRecipes are single-scalar if all their operands are.
This should be effectively NFC currently, but it should re-enable cost
checking for some more VPWidenMemoryRecipe after
https://github.com/llvm/llvm-project/pull/157387 as discovered by
John Brawn.
Commit: eb5297e0ade96fe8a6297763f28219be97dfac76
https://github.com/llvm/llvm-project/commit/eb5297e0ade96fe8a6297763f28219be97dfac76
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/merge_attributes.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sincos_stret.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sleef.ll
Log Message:
-----------
RuntimeLibcalls: Add mustprogress to common function attributes (#167080)
Commit: be2dfce6472c65270900dce1754f5352a83c2e98
https://github.com/llvm/llvm-project/commit/be2dfce6472c65270900dce1754f5352a83c2e98
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copyin.cpp
Log Message:
-----------
[OpenACC][CIR] Global declare 'copyin' clause lowering (#169498)
JUST like the 'create' clause, except the entry op is copyin instead of
create. Most of this is the test.
Commit: 9007b36b4250dff51e1a22f0b1f4084d5ab4fd4a
https://github.com/llvm/llvm-project/commit/9007b36b4250dff51e1a22f0b1f4084d5ab4fd4a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
Log Message:
-----------
[RISCV] Add a InstRW to COPY in RISCVSchedSpacemitX60.td. (#169423)
This prevents the scheduler from thinking copy instructions are free. In
#167008, we saw cases where the scheduler moved ABI copies past other
instructions creating high register pressure that caused the register
allocator to run out of registers. They can't be spilled because the
physical register lifetime was increased, not the virtual register.
Ideally, we would detect what register class the COPY is for, but for now
I've just treated it as a scalar integer copy.
Commit: 4f5fb36ddba6f538ff859d494fe15f19691b88f1
https://github.com/llvm/llvm-project/commit/4f5fb36ddba6f538ff859d494fe15f19691b88f1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Use an enum class for AVL state ins RISCVInsertVSETVLI. NFC (#169455)
Commit: 3564870a9fbfe49b11b47136127b6f972fbac43b
https://github.com/llvm/llvm-project/commit/3564870a9fbfe49b11b47136127b6f972fbac43b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Initialize AltFmt and TWiden in the VSETVLIInfo default constructor. (#169457)
Commit: b3b83ac1e80e4a3f3e4241b2ae0ceabef369a5bf
https://github.com/llvm/llvm-project/commit/b3b83ac1e80e4a3f3e4241b2ae0ceabef369a5bf
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M offload/test/offloading/shared_lib_fp_mapping.c
M offload/test/offloading/static_linking.c
Log Message:
-----------
[offload][lit] Fix compilation of two offload tests (#169399)
These are C tests, not C++, so no function parameters means unspecified
number of parameters, not `void`.
These compile fine on the current tested offload targets because an
error is only
[thrown](https://github.com/llvm/llvm-project/blob/main/clang/lib/Sema/SemaDecl.cpp#L10695)
if the calling convention doesn't support variadic arguments, which they
happen to.
When compiling this test for other targets that do not support variadic
arguments, we get an error, which does not seem intentional.
Just add `void` to the parameter list.
---------
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 031d99836de51f2d6dfeb4f539e2d1af85f4f263
https://github.com/llvm/llvm-project/commit/031d99836de51f2d6dfeb4f539e2d1af85f4f263
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
A llvm/test/CodeGen/SPIRV/function/vararg.ll
Log Message:
-----------
[SPIRV] Error in backend for vararg functions (#169111)
SPIR-V doesn't support variadic functions, though we make an exception
for `printf`.
If we don't error, we generate invalid SPIR-V because the backend has no
idea how to codegen vararg functions as it is not described in the spec.
We get asm like this:
```
%27 = OpFunction %6 None %7
%28 = OpFunctionParameter %4
; -- End function
```
The above asm is totally invalid, there's no `OpFunctionEnd` and it
causes crashes in downstream tools like `spirv-as` and `spirv-link`.
We already have many `printf` tests locking down that this doesn't break
`printf`, it was already handled elsewhere at the time the error check
runs.
Note the SPIR-V Translator does the same thing, see
[here](https://github.com/KhronosGroup/SPIRV-LLVM-Translator/pull/2703).
---------
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: ccbd0d1a69eb71268bfa7066a962bbd37c9893b1
https://github.com/llvm/llvm-project/commit/ccbd0d1a69eb71268bfa7066a962bbd37c9893b1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Add assertions to VSETVLIInfo accessors. NFC (#169462)
Commit: 177e38286cd61a7b5a968636e1f147f128dd25a2
https://github.com/llvm/llvm-project/commit/177e38286cd61a7b5a968636e1f147f128dd25a2
Author: Sayan Saha <sayans at mathworks.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/Utils/QuantUtils.h
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Utils/QuantUtils.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/quant-test.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Get quantized element type with sign info. (#169387)
As mentioned in
https://github.com/llvm/llvm-project/blob/a27bb38ee6f5762e715803d8eb6ffc5a8dd09575/mlir/include/mlir/Dialect/Quant/IR/QuantTypes.h#L109
`QuantType::getStorageType` doesn't capture the sign information. This
lead to the following IR to fail during verification:
```
func.func @clamp(%arg0:tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>) -> (tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>) {
%0 = tosa.clamp %arg0 {max_val = 255 : ui8, min_val = 0 : ui8} : (tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>) -> tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>
return %0 : tensor<?x112x112x32x!quant.uniform<u8:f32, 0.023529412224888802:-128>>
}
```
with `'tosa.clamp' op min/max attributes types are incompatible with
input/output element types` error
since `getStorageType` was returning signed integer but the clamp
attributes were unsigned.
This PR updates the usage of `getStorageType` in tosa codebase to
correctly use the signed info for the quantized type.
Commit: 1c3b10f2e2d8f9600fedd5e579aef69d7d31fadc
https://github.com/llvm/llvm-project/commit/1c3b10f2e2d8f9600fedd5e579aef69d7d31fadc
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)
Since #142598 isKernelLDS has been a pointless wrapper around isKernel.
Commit: 02c9e8987a22753417c721eba5e5848f3fe33a24
https://github.com/llvm/llvm-project/commit/02c9e8987a22753417c721eba5e5848f3fe33a24
Author: Marco Elver <elver at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll
Log Message:
-----------
[InstCombine][MemProf] Preserve all metadata (#169242)
When rewriting operator new calls to their hot/cold variants for PGHO,
`!alloc_token` metadata was being dropped. This metadata is required by
the AllocToken pass to correctly instrument the optimized allocation.
Fix it by preserving all metadata.
Commit: b8ef25aa643761233dc5b74d9fb7c38a2064d9c7
https://github.com/llvm/llvm-project/commit/b8ef25aa643761233dc5b74d9fb7c38a2064d9c7
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Transforms/Utils/LoopUtils.cpp
A llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
M llvm/test/Verifier/llvm.loop.estimated_trip_count.ll
M llvm/unittests/Transforms/Utils/LoopUtilsTest.cpp
Log Message:
-----------
[PGO] Fix zeroed estimated trip count (#167792)
Before PR #152775, `llvm::getLoopEstimatedTripCount` never returned 0.
If `llvm::setLoopEstimatedTripCount` were called with 0, it would zero
branch weights, causing `llvm::getLoopEstimatedTripCount` to return
`std::nullopt`.
PR #152775 changed that behavior: if `llvm::setLoopEstimatedTripCount`
is called with 0, it sets `llvm.loop.estimated_trip_count` to 0, causing
`llvm::getLoopEstimatedTripCount` to return 0. However, it kept
documentation saying `llvm::getLoopEstimatedTripCount` returns a
positive count.
Some passes continue to assume `llvm::getLoopEstimatedTripCount` never
returns 0 and crash if it does, as reported in issue #164254. To restore
the behavior they expect, this patch changes
`llvm::getLoopEstimatedTripCount` to return `std::nullopt` when
`llvm.loop.estimated_trip_count` is 0.
Commit: c582688b6912c615da1d08630c178dd3d0072aeb
https://github.com/llvm/llvm-project/commit/c582688b6912c615da1d08630c178dd3d0072aeb
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
Log Message:
-----------
[MLIR][tensor] Simplify ExtractSliceOp::inferResultType (nfc) (#169313)
The `offsets` and `strides` arguments are neither used nor required -
removed them and simplify this hook.
Commit: 6d21ce8797317814ad6f2372d98d21c9900f0579
https://github.com/llvm/llvm-project/commit/6d21ce8797317814ad6f2372d98d21c9900f0579
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceresident.cpp
Log Message:
-----------
[OpenACC][CIR] device_resident lowering for NS/global/struct declare (#169507)
This is the same as create/copyin, except it uses
declare_device_resident for the entry op.
Commit: 7b5163d3001613e9c449f7603f4a0f7f521e79a1
https://github.com/llvm/llvm-project/commit/7b5163d3001613e9c449f7603f4a0f7f521e79a1
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
Log Message:
-----------
[lldb][NFC] use llvm::StringRef in `ExtractContextAndIdentifer` function (#169506)
this avoids allocation when checking if a method contains a path.
Commit: e04cca8561c65b9820f2c284eea164ab9fb7cdce
https://github.com/llvm/llvm-project/commit/e04cca8561c65b9820f2c284eea164ab9fb7cdce
Author: Marco Elver <elver at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A clang/test/CodeGen/memprof-pgho.cpp
Log Message:
-----------
[Clang][MemProf] Add end-to-end test for PGHO rewriting (#169243)
Add an end-to-end (non-LTO) test verifying that the optimization
pipeline is set up correctly for Profile Guided Heap Optimization (PGHO)
transforms. Ensure that both PGHO and AllocToken can stack, and the
AllocToken pass does not interfere with PGHO and vice versa.
Commit: 1a036732d210c2b78404067a1aa0b3a3bba3eaf8
https://github.com/llvm/llvm-project/commit/1a036732d210c2b78404067a1aa0b3a3bba3eaf8
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
A clang/test/Driver/hip-spirv-backend-bindings.c
A clang/test/Driver/hip-spirv-backend-opt.c
A clang/test/Driver/hip-spirv-backend-phases.c
Log Message:
-----------
[clang][Driver] Support for the SPIR-V backend when compiling HIP (#167543)
For HIP, the SPIR-V backend can be optionally activated with the -use-spirv-backend flag. This option uses the SPIR-V BE instead of the SPIR-V translator. These changes also ensure that -use-spirv-backend does not require external dependencies, such as spirv-as and spirv-link
Commit: 17852deda7fb9dabb41023e2673025c630b9369d
https://github.com/llvm/llvm-project/commit/17852deda7fb9dabb41023e2673025c630b9369d
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
M llvm/lib/Target/NVPTX/NVPTXTagInvariantLoads.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
M llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
A llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
A llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
A llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
Log Message:
-----------
[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)
This backend support will allow the LoadStoreVectorizer, in certain
cases, to fill in gaps when creating load/store vectors and generate
LLVM masked load/stores
(https://llvm.org/docs/LangRef.html#llvm-masked-store-intrinsics). To
accomplish this, changes are separated into two parts. This first part
has the backend lowering and TTI changes, and a follow up PR will have
the LSV generate these intrinsics:
https://github.com/llvm/llvm-project/pull/159388.
In this backend change, Masked Loads get lowered to PTX with `#pragma
"used_bytes_mask" [mask];`
(https://docs.nvidia.com/cuda/parallel-thread-execution/#pragma-strings-used-bytes-mask).
And Masked Stores get lowered to PTX using the new sink symbol syntax
(https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-st).
# TTI Changes
TTI changes are needed because NVPTX only supports masked loads/stores
with _constant_ masks. `ScalarizeMaskedMemIntrin.cpp` is adjusted to
check that the mask is constant and pass that result into the TTI check.
Behavior shouldn't change for non-NVPTX targets, which do not care
whether the mask is variable or constant when determining legality, but
all TTI files that implement these API need to be updated.
# Masked store lowering implementation details
If the masked stores make it to the NVPTX backend without being
scalarized, they are handled by the following:
* `NVPTXISelLowering.cpp` - Sets up a custom operation action and
handles it in lowerMSTORE. Similar handling to normal store vectors,
except we read the mask and place a sentinel register `$noreg` in each
position where the mask reads as false.
For example,
```
t10: v8i1 = BUILD_VECTOR Constant:i1<-1>, Constant:i1<0>, Constant:i1<0>, Constant:i1<-1>, Constant:i1<-1>, Constant:i1<0>, Constant:i1<0>, Constant:i1<-1>
t11: ch = masked_store<(store unknown-size into %ir.lsr.iv28, align 32, addrspace 1)> t5:1, t5, t7, undef:i64, t10
->
STV_i32_v8 killed %13:int32regs, $noreg, $noreg, killed %16:int32regs, killed %17:int32regs, $noreg, $noreg, killed %20:int32regs, 0, 0, 1, 8, 0, 32, %4:int64regs, 0, debug-location !18 :: (store unknown-size into %ir.lsr.iv28, align 32, addrspace 1);
```
* `NVPTXInstInfo.td` - changes the definition of store vectors to allow
for a mix of sink symbols and registers.
* `NVPXInstPrinter.h/.cpp` - Handles the `$noreg` case by printing "_".
# Masked load lowering implementation details
Masked loads are routed to normal PTX loads, with one difference: a
`#pragma "used_bytes_mask"` is emitted before the load instruction
(https://docs.nvidia.com/cuda/parallel-thread-execution/#pragma-strings-used-bytes-mask).
To accomplish this, a new operand is added to every NVPTXISD Load type
representing this mask.
* `NVPTXISelLowering.h/.cpp` - Masked loads are converted into normal
NVPTXISD loads with a mask operand in two ways. 1) In type legalization
through replaceLoadVector, which is the normal path, and 2) through
LowerMLOAD, to handle the legal vector types
(v2f16/v2bf16/v2i16/v4i8/v2f32) that will not be type legalized. Both
share the same convertMLOADToLoadWithUsedBytesMask helper. Both default
this operand to UINT32_MAX, representing all bytes on. For the latter,
we need a new `NVPTXISD::MLoadV1` type to represent that edge case
because we cannot put the used bytes mask operand on a generic
LoadSDNode.
* `NVPTXISelDAGToDAG.cpp` - Extract used bytes mask from loads, add them
to created machine instructions.
* `NVPTXInstPrinter.h/.cpp` - Print the pragma when the used bytes mask
isn't all ones.
* `NVPTXForwardParams.cpp`, `NVPTXReplaceImageHandles.cpp` - Update
manual indexing of load operands to account for new operand.
* `NVPTXInsrtInfo.td`, `NVPTXIntrinsics.td` - Add the used bytes mask to
the MI definitions.
* `NVPTXTagInvariantLoads.cpp` - Ensure that masked loads also get
tagged as invariant.
Some generic changes that are needed:
* `LegalizeVectorTypes.cpp` - Ensure flags are preserved when splitting
masked loads.
* `SelectionDAGBuilder.cpp` - Preserve `MD_invariant_load` on masked
load SDNode creation
Commit: 6a395fec1f7663e02c6607e8e10791838c949389
https://github.com/llvm/llvm-project/commit/6a395fec1f7663e02c6607e8e10791838c949389
Author: Guy David <guyda96 at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
Log Message:
-----------
[AArch64] Mark FMOVvXfY_ns as rematerializable, cheap (#169186)
Commit: b93bb69dfad5f94565d90575a92203a1a2f3395b
https://github.com/llvm/llvm-project/commit/b93bb69dfad5f94565d90575a92203a1a2f3395b
Author: Samira Bakon <bazuzi at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
Log Message:
-----------
[clang][dataflow] Use containers with deterministic iteration order. (#169512)
Commit: eb1ff56e26fdb48728642f7d26e47b337b7235ea
https://github.com/llvm/llvm-project/commit/eb1ff56e26fdb48728642f7d26e47b337b7235ea
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll
Log Message:
-----------
[SLP][NFC]Add a test for copyable operands, used multiple times, NFC
Commit: d69e70149636efa0293310303878fbf9a5f31433
https://github.com/llvm/llvm-project/commit/d69e70149636efa0293310303878fbf9a5f31433
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
Log Message:
-----------
[PGO] Add missing target datalayout in test (#169520)
The test was added by b8ef25aa643761233dc5b74d9fb7c38a2064d9c7. It
failed on at least the following bots, but the failure did not reproduce
on my test machines or in pre-commit CI:
- https://lab.llvm.org/buildbot/#/builders/190/builds/31638
- https://lab.llvm.org/buildbot/#/builders/190/builds/31638
This fix hopefully addresses at least the warnings there.
Commit: 5999cc8ceef3acef128e1baf8fcefd7164acc677
https://github.com/llvm/llvm-project/commit/5999cc8ceef3acef128e1baf8fcefd7164acc677
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M libcxx/include/stack
M libcxx/test/libcxx/diagnostics/stack.nodiscard.verify.cpp
Log Message:
-----------
[libc++][stack] Applied `[[nodiscard]]` (#169468)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 1c5b1501ca50e039ae39075465972761449013e9
https://github.com/llvm/llvm-project/commit/1c5b1501ca50e039ae39075465972761449013e9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/lib/CodeGen/LibcallLoweringInfo.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.h
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/Mips/Mips16ISelLowering.h
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.h
Log Message:
-----------
CodeGen: Move libcall lowering configuration to subtarget (#168621)
Previously libcall lowering decisions were made directly
in the TargetLowering constructor. Pull these into the subtarget
to facilitate turning LibcallLoweringInfo into a separate analysis
in the future.
Commit: 5017370a1ce5009aed2855b645194bc141f72a2d
https://github.com/llvm/llvm-project/commit/5017370a1ce5009aed2855b645194bc141f72a2d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/gws_agpr.ll
Log Message:
-----------
AMDGPU: Add baseline test for gws handling with AGPR inputs (#169372)
Commit: a860c8378f91d9b7713171888e76962b2747fe4e
https://github.com/llvm/llvm-project/commit/a860c8378f91d9b7713171888e76962b2747fe4e
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
R clang/test/Driver/hip-spirv-backend-bindings.c
R clang/test/Driver/hip-spirv-backend-opt.c
R clang/test/Driver/hip-spirv-backend-phases.c
Log Message:
-----------
Revert "[clang][Driver] Support for the SPIR-V backend when compiling HIP (#167543)" (#169528)
This reverts commit 1a036732d210c2b78404067a1aa0b3a3bba3eaf8.
Reverted due to a failure in hip-spirv-backend-opt.c for
fuchsia-x86_64-linux.
Commit: 53e5cfdf8b13e2427797ca6eeda1860f8aa190ef
https://github.com/llvm/llvm-project/commit/53e5cfdf8b13e2427797ca6eeda1860f8aa190ef
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/combined-copy.c
M clang/test/CIR/CodeGenOpenACC/compute-copy.c
M clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceptr.cpp
M clang/test/CIR/CodeGenOpenACC/declare-link.cpp
M clang/test/CIR/CodeGenOpenACC/declare-present.cpp
Log Message:
-----------
[OpenACC][CIR] link clause lowering for global declare (#169524)
The 'link' clause is like the rest of the global clauses (copyin,
create, device_resident), except it only has an entry op(thus no
dtor).
This patch also removes a bunch of now stales TODOs from the tests.
Commit: 8380a48aa0b62be28b653ba6b3d38198680b2bd9
https://github.com/llvm/llvm-project/commit/8380a48aa0b62be28b653ba6b3d38198680b2bd9
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
Log Message:
-----------
[PGO] Add REQUIRES to test (#169531)
The test was added by b8ef25aa643761233dc5b74d9fb7c38a2064d9c7. It
failed on at least the following bots, but the failure did not reproduce
on my test machines or in pre-commit CI:
- https://lab.llvm.org/buildbot/#/builders/190/builds/31643
- https://lab.llvm.org/buildbot/#/builders/65/builds/25949
- https://lab.llvm.org/buildbot/#/builders/154/builds/24417
d69e70149636efa0293310303878fbf9a5f31433 did not fix the failure.
Hopefully this will.
Commit: 1441f0458545243f9278cf87a35c4cb4e1cd62bd
https://github.com/llvm/llvm-project/commit/1441f0458545243f9278cf87a35c4cb4e1cd62bd
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/Address.h
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
A clang/test/CIR/CodeGen/placement-new.cpp
Log Message:
-----------
[CIR] Upstream reserved placement new handling (#169436)
This upstreams the code to support reserved placement new calls.
Commit: 45336992453c83d083ccadf62ae56626dfb0f761
https://github.com/llvm/llvm-project/commit/45336992453c83d083ccadf62ae56626dfb0f761
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
Log Message:
-----------
[BOLT][BTI] Add MCPlusBuilder::isBTILandingPad (#167306)
- takes both implicit and explicit BTIs into account
- fix related comment in
llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
Commit: 83d9c636b753ab37842a25606d95d800dce90398
https://github.com/llvm/llvm-project/commit/83d9c636b753ab37842a25606d95d800dce90398
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M utils/bazel/third_party_build/zlib-ng.BUILD
Log Message:
-----------
[bazel] Add alias for zlib-ng for WORKSPACE compat (#169530)
The consumer of zlib in third-party/BUILD.bazel expects zlib-ng from the
BCR, if you still load this version from your WORKSPACE / MODULE.bazel
you need to use this name instead.
Commit: 012721d3200ceed635495394fe96b17bbaa8653e
https://github.com/llvm/llvm-project/commit/012721d3200ceed635495394fe96b17bbaa8653e
Author: Benjamin Chetioui <3920784+bchetioui at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/test/python/ir/operation.py
Log Message:
-----------
[mlir][python] Propagate error diagnostics when an op couldn't be created. (#169499)
Commit: 4877c593a873657cd18a1ee0bd4a13f4b84c4d3b
https://github.com/llvm/llvm-project/commit/4877c593a873657cd18a1ee0bd4a13f4b84c4d3b
Author: Kaitlin Peng <kaitlinpeng at microsoft.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCombine.td
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h
A llvm/test/CodeGen/SPIRV/GlobalISel/InstCombine/prelegalizercombiner-select-to-faceforward.mir
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/faceforward.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward.ll
Log Message:
-----------
[SPIRV] Add PreLegalizer pattern matching for `faceforward` (#139959)
Tasks completed:
- Pattern match`select(fcmp(dot(p2, p3), 0), p1, -p1)` to
`faceforward(p1, p2, p3)`
- Add pattern matching tests to
`prelegalizercombiner-select-to-faceforward.mir` and `faceforward.ll`
- Add CL extension error test
`llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll`
- Add CL extension test for no pattern matching in
`llvm/test/CodeGen/SPIRV/opencl/faceforward.ll`
Closes #137255.
Commit: d125cab13f08eee4d02d02e46223d14285bb2353
https://github.com/llvm/llvm-project/commit/d125cab13f08eee4d02d02e46223d14285bb2353
Author: Valeriy Savchenko <vsavchenko at apple.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/Transforms/InstCombine/cast-mul-select.ll
M llvm/test/Transforms/InstCombine/cast.ll
M llvm/test/Transforms/InstCombine/catchswitch-phi.ll
M llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
M llvm/test/Transforms/InstCombine/known-bits-lerp-pattern.ll
M llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
M llvm/test/Transforms/InstCombine/logical-select.ll
Log Message:
-----------
[InstCombine] Support multi-use values in cast elimination transforms (#165877)
`canEvaluateTruncated` and `canEvaluateSExtd` previously rejected
multi-use values to avoid duplication. This was overly conservative, if
all users of a multi-use value are part of the transform, we can
evaluate it in a different type without duplication.
This change tracks visited values and defers decisions on multi-use
values until we verify all their users were visited.
`EvaluateInDifferentType` now memoizes multi-use values to avoid
creating duplicates.
Applied to truncation and sext. Zext unchanged due to its dual-return
nature.
Commit: 84df446af980f33f8014578856f8b1f8037888ee
https://github.com/llvm/llvm-project/commit/84df446af980f33f8014578856f8b1f8037888ee
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
Log Message:
-----------
AMDGPU: Remove DummyCGSCC use after buffer lowering passes (#169519)
The fixme the comment refers to was removed.
Commit: 44cffbe5d8de5947780288ca3c366bbd52650314
https://github.com/llvm/llvm-project/commit/44cffbe5d8de5947780288ca3c366bbd52650314
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/fma-combine.ll
Log Message:
-----------
[RISCV] Propagate SDNode flags when combining `(fmul (fneg X), ...)` (#169460)
In #157388, we turned `(fmul (fneg X), Y)` into `(fneg (fmul X, Y))`.
However, we forgot to propagate SDNode flags, specifically fast math
flags, from the original FMUL to the new one. This hinders some of the
subsequent (FMA) DAG combiner patterns that relied on the contraction
flag and as a consequence, missed some of the opportunities to generate
negation FMA instructions like `fnmadd`.
This patch fixes this issue by propagating the flags.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 6a6b99aa8010f16f4e74f78bca1f3c6ca9e94b9f
https://github.com/llvm/llvm-project/commit/6a6b99aa8010f16f4e74f78bca1f3c6ca9e94b9f
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCRecipeBufferization.cpp
M flang/test/Fir/OpenACC/recipe-bufferization.mlir
M flang/test/Lower/OpenACC/acc-firstprivate-derived-allocatable-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-pointer-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-user-assign.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction-remapping.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenACC/do-loops-to-acc-loops.f90
M flang/test/Transforms/OpenACC/acc-implicit-copy-reduction.fir
M flang/test/Transforms/OpenACC/acc-implicit-data-fortran.F90
M flang/test/Transforms/OpenACC/acc-implicit-data.fir
M flang/test/Transforms/OpenACC/acc-implicit-firstprivate.fir
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/test/Dialect/OpenACC/acc-implicit-data-reduction.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
M mlir/test/Dialect/OpenACC/invalid.mlir
M mlir/test/Dialect/OpenACC/legalize-data.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
Log Message:
-----------
[acc][flang][cir] Add recipes to data entry operations (#149210)
This patch refactors the OpenACC dialect to attach recipe symbols
directly to data operations (acc.private, acc.firstprivate,
acc.reduction)
rather than to compute constructs (acc.parallel, acc.serial, acc.loop).
Motivation:
The previous design required compute constructs to carry both the recipe
symbol and the variable reference, leading to complexity. Additionally,
recipes were required even when they could be generated automatically
through MappableType interfaces.
Changes:
- Data operations (acc.private, acc.firstprivate, acc.reduction) now
require a 'recipe' attribute referencing their respective recipe
operations
- Verifier enforces recipe attribute presence for non-MappableType
operands; MappableType operands can generate recipes on demand
- Compute constructs (acc.parallel, acc.serial, acc.loop) no longer
carry recipe symbols in their operands
- Updated flang lowering to attach recipes to data operations instead
of passing them to compute constructs
Format Migration:
Old format:
```
acc.parallel private(@recipe -> %var : !fir.ref<i32>) { ... }
```
New format:
```
%private = acc.private varPtr(%var : !fir.ref<i32>)
recipe(@recipe) -> !fir.ref<i32>
acc.parallel private(%private : !fir.ref<i32>) { ... }
```
Test Updates:
- Updated all CIR and Flang OpenACC tests to new format
- Fixed CHECK lines to verify recipe attributes on data operations
Commit: d5aa686636e0824f2d39ac333537d19bb4f8fc34
https://github.com/llvm/llvm-project/commit/d5aa686636e0824f2d39ac333537d19bb4f8fc34
Author: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
[GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`. (#166204)
`convert-vector-to-llvm` pass applies a set of vector transformation
patterns that are not included in the standard `convert-to-llvm` pass
interface. These additional transformations are required to properly
lower MLIR vector operations. Since not all vector ops have direct
`llvm` dialect lowering, many of them must first be progressively
rewritten into simpler or more canonical vector ops, which are then
lowered to `llvm`. Therefore, running `convert-vector-to-llvm` is
necessary to ensure a complete and correct lowering of vector operations
to the `llvm` dialect.
Commit: 4822f4986fae9bb212e2f35e29839bbd9fb26bea
https://github.com/llvm/llvm-project/commit/4822f4986fae9bb212e2f35e29839bbd9fb26bea
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Analysis/CFG.cpp
M clang/test/Analysis/lifetime-cfg-output.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/unittests/Analysis/FlowSensitive/LoggerTest.cpp
Log Message:
-----------
[LifetimeSafety] Add parameter lifetime tracking in CFG (#169320)
This PR enhances the CFG builder to properly handle function parameters
in lifetime analysis:
1. Added code to include parameters in the initial scope during CFG
construction for both `FunctionDecl` and `BlockDecl` types
2. Added a special case to skip reference parameters, as they don't need
automatic destruction
3. Fixed several test cases that were previously marked as "FIXME" due
to missing parameter lifetime tracking
Previously, Clang's lifetime analysis was not properly tracking the
lifetime of function parameters, causing it to miss important
use-after-return bugs when parameter values were returned by reference
or address. This change ensures that parameters are properly tracked in
the CFG, allowing the analyzer to correctly identify when stack memory
associated with parameters is returned.
Fixes https://github.com/llvm/llvm-project/issues/169014
Commit: f545c2cec12f77f1fb61ccf07393f434d456ad94
https://github.com/llvm/llvm-project/commit/f545c2cec12f77f1fb61ccf07393f434d456ad94
Author: David Stone <davidfromonline at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/Sema/SemaDeclCXX.cpp
Log Message:
-----------
[clang][NFC] Don't copy into a vector just to iterate in `IsInitListMemberExprInitialized` (#169385)
Commit: 0c9c62adf165ebf4128bcfe9863fa0c524b46b7b
https://github.com/llvm/llvm-project/commit/0c9c62adf165ebf4128bcfe9863fa0c524b46b7b
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
Log Message:
-----------
[PowerPC ]convert `(setcc (and X, 1), 0, eq)` to `XORI (and X, 1), 1` (#168384)
Convert `(setcc (and X, 1), 0, eq)` to `XORI (and X, 1), 1` , it will save one instruction.
Commit: d7dcc108fc3ada2330277424495b676d52de1765
https://github.com/llvm/llvm-project/commit/d7dcc108fc3ada2330277424495b676d52de1765
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/docs/DeveloperPolicy.rst
M llvm/utils/git/github-automation.py
Log Message:
-----------
[GitHub] Add review instructions for commit access requests (#168971)
As discussed in
https://discourse.llvm.org/t/clarification-on-how-to-accept-commit-access-requests/88728,
clarify reviewer instructions for how to accept commit access requests.
Commit: 1d30ae6e402a28018a5574b7c68d71aac14acd63
https://github.com/llvm/llvm-project/commit/1d30ae6e402a28018a5574b7c68d71aac14acd63
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
AMDGPU: Stop forcing RequiresCodeGenSCCOrder (#169522)
This hasn't been strictly necessary since c897c13dde.
Practically this makes little difference; we still enable IPRA
by default which implies this option. By removing this explicit
force, -enable-ipra=0 has the expected change in the pass pipeline
to remove the DummyCGSCC runs.
Commit: 8f1bb92bbfa45d49103953dad0d0a5dcfd388959
https://github.com/llvm/llvm-project/commit/8f1bb92bbfa45d49103953dad0d0a5dcfd388959
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
M llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
M llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
Log Message:
-----------
[NVPTX] Fix lit test issues from masked load/store implementation (#169535)
>From this commit:
https://github.com/llvm/llvm-project/commit/17852deda7fb9dabb41023e2673025c630b9369d,
Build was broken here:
https://lab.llvm.org/buildbot/#/builders/155/builds/15135/steps/7/logs/stdio.
I think this should fix things.
Commit: 6c8ff4f2bbae6fe29b0ef67edb70e6d73b47beb3
https://github.com/llvm/llvm-project/commit/6c8ff4f2bbae6fe29b0ef67edb70e6d73b47beb3
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Log Message:
-----------
[NVPTX] Fix maybe unused variable in 17852ded (#169542)
Commit: dce95b2ea41e8585cd1e3e2ce07f5d692a970949
https://github.com/llvm/llvm-project/commit/dce95b2ea41e8585cd1e3e2ce07f5d692a970949
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACCLoop.cpp
Log Message:
-----------
[OpenACC][CIR][NFC] Remove 'NYI' diagnostics, since we're done with t… (#169543)
…hese
We've finished all of the clauses/etc that we're going to use this
visitor for, so we can remove the SourceLocation we used just for that,
and replace all NYI with unreachables.
Commit: a8e0afe98853418e1367274e6f04f7ba255de199
https://github.com/llvm/llvm-project/commit/a8e0afe98853418e1367274e6f04f7ba255de199
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/test/CIR/CodeGen/vector-ext-element.cpp
Log Message:
-----------
[CIR] ArraySubscriptExpr on ExtVectorElementExpr (#169158)
Implement ArraySubscriptExpr support for ExtVectorElementExpr
Commit: 2d78b1409eeab558cfc1b64ab39211af00c5f35f
https://github.com/llvm/llvm-project/commit/2d78b1409eeab558cfc1b64ab39211af00c5f35f
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/OpenMPKinds.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/lib/Parse/ParseOpenMP.cpp
A clang/test/OpenMP/need_device_ptr_kind_ast_print.cpp
A clang/test/OpenMP/need_device_ptr_kind_messages.cpp
Log Message:
-----------
[OpenMP][Clang] Parsing/Sema support for `need_device_ptr(fb_nullify/fb_preserve)`. (#168905)
This patch adds parsing, semantic handling, and diagnostics for the
`OpenMP 6.1 fb_nullify` and` fb_preserve` fallback modifiers used with
the `need_device_ptr` map modifier.
Commit: 622dbb372bfefc135c3cdf967ae6f3b55ffa4a16
https://github.com/llvm/llvm-project/commit/622dbb372bfefc135c3cdf967ae6f3b55ffa4a16
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
Log Message:
-----------
AMDGPU: Add more tests for 32-bit constant address space (#168976)
The sub-dword cases just assert now, so comment those out.
Commit: 20ca85b69fc06feb75f67414d54f3830748bb456
https://github.com/llvm/llvm-project/commit/20ca85b69fc06feb75f67414d54f3830748bb456
Author: Jez Ng <me at jezng.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/InputFiles.cpp
M lld/test/MachO/x86-64-relocs.s
Log Message:
-----------
[lld] macho: Support section branch relocations, including the 1-byte form (#169062)
I noticed that we had a hardcoded value of 4 for the pcrel section
relocations, which seems like an issue given that we recently added
support for 1-byte branch relocations in
https://github.com/llvm/llvm-project/pull/164439. The code included an
assert that the relevant relocation had the BYTE4 attribute, but that is
actually not enough to use a hardcoded value of 4: we need to assert
that the *other* `BYTE<n>` attributes are not set either.
However, since we did not support local branch relocations, that doesn't
seem to have mattered in practice. That said, local branch relocations
can be emitted by compilers, and ld64 does handle the 4-byte version of
them, so I've added support for it here.
ld64 actually seems to reject 1-byte section relocations, so the
questionable code is actually probably fine (minus the incorrect
assert). So we have two options: add an equivalent check in LLD, or just
support 1-byte local branch relocations. Supporting it actually requires
less code, so I've gone with that option here.
Commit: 2ee12f191a005363259e3a95ccdf459d9044eadf
https://github.com/llvm/llvm-project/commit/2ee12f191a005363259e3a95ccdf459d9044eadf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/gws_agpr.ll
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
A llvm/test/MC/AMDGPU/ds_gws_sgpr_err.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
Log Message:
-----------
AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)
On targets that require even aligned 64-bit VGPRs, GWS operands
require even alignment of a 32-bit operand. Previously we had a hacky
post-processing which added an implicit operand to try to manage
the constraint. This would require special casing in other passes
to avoid breaking the operand constraint. This moves the handling
into the instruction definition, so other passes no longer need
to consider this edge case. MC still does need to special case this,
to print/parse as a 32-bit register. This also still ends up net
less work than introducing even aligned 32-bit register classes.
This also should be applied to the image special case.
Commit: 3a27fc48117ba7e062c3cfa0006badb64446ed69
https://github.com/llvm/llvm-project/commit/3a27fc48117ba7e062c3cfa0006badb64446ed69
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Omit VTYPE in VSETVLIInfo::print() when state is uninit or unknown. (#169459)
Commit: eab23e199aef18c2052c08171129633233ab98f5
https://github.com/llvm/llvm-project/commit/eab23e199aef18c2052c08171129633233ab98f5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Log Message:
-----------
[RISCV] Don't add Zilsd pairing hints if other part of the pair is reserved. (#169538)
Commit: ebe40066545fd0ad2e88c5e48b7751195d9a9eca
https://github.com/llvm/llvm-project/commit/ebe40066545fd0ad2e88c5e48b7751195d9a9eca
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/CMakeLists.txt
Log Message:
-----------
[mlir] Fix build failure with BUILD_SHARED_LIBS=ON
/usr/bin/ld: tools/mlir/lib/Dialect/GPU/Pipelines/CMakeFiles/obj.MLIRGP
UPipelines.dir/GPUToXeVMPipeline.cpp.o: in function `mlir::gpu::buildLo
werToXeVMPassPipeline(mlir::OpPassManager&, mlir::gpu::GPUToXeVMPipelin
eOptions const&)':
GPUToXeVMPipeline.cpp:(.text._ZN4mlir3gpu28buildLowerToXeVMPassPipeline
ERNS_13OpPassManagerERKNS0_24GPUToXeVMPipelineOptionsE+0x1293): undefin
ed reference to `mlir::createConvertVectorToLLVMPass()'
Commit: 6c48fbc1dcfbd44a47f126f21e575340b67aac06
https://github.com/llvm/llvm-project/commit/6c48fbc1dcfbd44a47f126f21e575340b67aac06
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M bolt/test/X86/lit.local.cfg
M bolt/test/lit.local.cfg
Log Message:
-----------
[BOLT][Tests] Use AT&T assembler syntax only for X86 tests (#169541)
Enabling AT&T syntax for all tests is broken when X86 target is not
enabled as reported in #167225.
Commit: 0917a38c694bd2558b79c2b6d51fee2308dd94dd
https://github.com/llvm/llvm-project/commit/0917a38c694bd2558b79c2b6d51fee2308dd94dd
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[PowerPC] Fix a warning
This patch fixes:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15676:17: error: unused
variable 'CC' [-Werror,-Wunused-variable]
Commit: af0fcf85c812867c1d03f390d5afbbbc5b7f1584
https://github.com/llvm/llvm-project/commit/af0fcf85c812867c1d03f390d5afbbbc5b7f1584
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/include/mlir/TableGen/Pattern.h
M mlir/lib/TableGen/Pattern.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
Log Message:
-----------
[mlir][tblgen] Don't echo absolute paths into rewrite pattern source (#168984)
Currently, the declarative pattern rewrite generator will always print
the [source]:[line](s) from which a pattern came. This is a useful
debugging hint, but it causes problem when absolute paths are used as
arguments to mlir-tblgen (which LLVM's build rules automatically do).
Specifially, it causes the source to be tied to the build location,
harning reproducability and our collective ability to get ccache hits
from, say, separate worktrees.
This commit resolves the issue by replacing absolute paths in thes
"Generated from:" comments with their filenames. (The alternative would
have been to implement an entire file-prefix-map the way the C compilers
do, but since this is an isolated incident, I chose to resolve it
locally.)
Commit: 36947982106686570383945c2bbf367f447d9edc
https://github.com/llvm/llvm-project/commit/36947982106686570383945c2bbf367f447d9edc
Author: Sergei Druzhkov <serzhdruzhok at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
Log Message:
-----------
[lldb-dap] Add format support for evaluate request (#169132)
This patch adds support for format option in the `evaluate` request
according to
[DAP](https://microsoft.github.io/debug-adapter-protocol/specification#Requests_Evaluate)
specification. Also, fixed typo in `LLDB_DAP_INVALID_VARRERF` constant.
Commit: 0f941f6866910e55e0e7cff30c48740477be0cd8
https://github.com/llvm/llvm-project/commit/0f941f6866910e55e0e7cff30c48740477be0cd8
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
Log Message:
-----------
[flang][cuda] Add support to allocate scalar character types (#169550)
Add support for character declared like:
```
subroutine sub1()
character*4, device :: b
end subroutine
```
Commit: ad3d9fb3cab7f2e9a7337ca3c1bd0018ff6c6158
https://github.com/llvm/llvm-project/commit/ad3d9fb3cab7f2e9a7337ca3c1bd0018ff6c6158
Author: Petr Penzin <ppenzin at tenstorrent.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
Log Message:
-----------
[RISCV] tt-ascalon-d8 vector scheduling (#167066)
Add the vector scheduling model for tt-ascalon-d8 and corresponding
llvm-mca tests.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 8d920725ca56930d301df1c7e090905423645a49
https://github.com/llvm/llvm-project/commit/8d920725ca56930d301df1c7e090905423645a49
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
Log Message:
-----------
[RISCV] Use FMV.D for moving GPRPairs on RV32_Zdinx (#169556)
This is noted by the specification, and should save a dynamic
instruction.
Code size should be no worse than before, as the pairs of moves can
usually be turned into two 16-bit moves, but `fmv.d` is always a 32-bit
instruction.
LLVM can look through a `FSGNJ_D_IN32X`, in
`RISCVInstrInfo::isCopyInstrImpl` which helps copy propagation.
Commit: dbcf5688cca37543ea3304be68516b3ac476eef3
https://github.com/llvm/llvm-project/commit/dbcf5688cca37543ea3304be68516b3ac476eef3
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
[AMDGPU] Simplify VT comparisons. NFC. (#169526)
Automated with `sed -i 's/\.Value//g' lib/Target/AMDGPU/*.td` plus a
tiny bit of manual reformatting.
Commit: 1c9368e01e6ed45e7dbc523d3bddfd900bb6e504
https://github.com/llvm/llvm-project/commit/1c9368e01e6ed45e7dbc523d3bddfd900bb6e504
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
A clang/test/CIR/CodeGen/copy-constructor.cpp
Log Message:
-----------
[CIR] Upstream non-record array init handling (#169429)
This upstreams the code to handle member initialization for non-record
arrays.
Commit: c475f8e5d809e2109a67c8523472eb28cd7bbb2a
https://github.com/llvm/llvm-project/commit/c475f8e5d809e2109a67c8523472eb28cd7bbb2a
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
A clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
Log Message:
-----------
[HLSL] Update vector swizzle elements individually (#169090)
When individual elements of a vector are updated via vector swizzle, it needs to be handled as separate store operations to the individual vector elements.
Clang treats vectors as one unit, so if a part of a vector needs to be updated, the whole vector is loaded, some elements modified, and then the whole vector is stored.
In HLSL vector elements are handled separately. We need to avoid this load/modify/store sequence to prevent overwriting other vector elements that might be getting updated in parallel.
Fixes #152815
Commit: 091aece72b0149bda6d465301fe3934ca570a592
https://github.com/llvm/llvm-project/commit/091aece72b0149bda6d465301fe3934ca570a592
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[VPlan] Remove redundant transferFlags call from replicateByVF (NFC).
Flags are now passed on construction/cloning. Remove unnecessary
transferFlags call, and make code independent of VPRecipeWithIRFlags, to
support additional recipes in the future.
Commit: 00ffc70ba154b8670fc37d1398ce4473bca3a516
https://github.com/llvm/llvm-project/commit/00ffc70ba154b8670fc37d1398ce4473bca3a516
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
Log Message:
-----------
[SLP][NFC]Add a test with commutative instruction with non-commutative op, NFC
Commit: 074d17e9c8cbc6f22e65ba1211787453ea629ccb
https://github.com/llvm/llvm-project/commit/074d17e9c8cbc6f22e65ba1211787453ea629ccb
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/tsd_shared.h
Log Message:
-----------
[scudo] Lock/unlock MutexTSDs in disable/enable. (#169440)
It is possible that a fork could occur while MutexTSDs is being held and
then cause a deadlock in a forked process when something attempts to
lock it again. Instead add it to the enable/disable list of mutexes.
Commit: e894654532a74b669b0b0830007cc6c979b35d56
https://github.com/llvm/llvm-project/commit/e894654532a74b669b0b0830007cc6c979b35d56
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/addrec-may-wrap-udiv-canonicalize.ll
Log Message:
-----------
[SCEV] Add tests for UDiv canonicalization of AddRecs that may wrap.
Add test cases for canonicalizing AddRecs that may wrap.
Commit: 9bf78ab8dd17ecbbecd4157c67e8fb4d95528194
https://github.com/llvm/llvm-project/commit/9bf78ab8dd17ecbbecd4157c67e8fb4d95528194
Author: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
Revert "[GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`." (#169570)
Reverts llvm/llvm-project#166204
There was a build issue due to a missing dependency.
Commit: 49828c23b59959ca9f2c0dc83aeb9ce7f84b5c31
https://github.com/llvm/llvm-project/commit/49828c23b59959ca9f2c0dc83aeb9ce7f84b5c31
Author: Haowei <haowei at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/cmake/caches/Fuchsia.cmake
Log Message:
-----------
[Fuchsia] Bump minimal OS X target to 11.0 (#169568)
libcxx requires minimal macOS 11 to build. This patch bumps the minimal
OS X target in Fuchsia's cmake cache file to 11.0 to satisfy this
requirement.
Commit: 4f39a4ff0ada92870ca1c2dccad382ea04947da8
https://github.com/llvm/llvm-project/commit/4f39a4ff0ada92870ca1c2dccad382ea04947da8
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCOpsInterfacesTest.cpp
Log Message:
-----------
[acc][flang] Add getInitRegion() to GlobalVariableOpInterface (#169569)
Some globals (e.g., fir.global) have initialization regions that may
transitively reference other globals or type descriptors. Add
getInitRegion() to GlobalVariableOpInterface to retrieve these regions,
returning Region* (nullptr if the global uses attributes for
initialization, as with memref.global).
Commit: 5f777b2c8faca3fe28079fc81a7aefbca1edb803
https://github.com/llvm/llvm-project/commit/5f777b2c8faca3fe28079fc81a7aefbca1edb803
Author: daniilavdeev <daniilavdeev237 at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M llvm/include/llvm/MC/MCSymbol.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/MC/MCSymbol.cpp
A llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
Log Message:
-----------
[dwarf] make dwarf fission compatible with RISCV relaxations 1/2 (#166597)
Currently, -gsplit-dwarf and -mrelax are incompatible options in Clang.
The issue is that .dwo files should not contain any relocations, as they
are not processed by the linker. However, relaxable code emits
relocations in DWARF for debug ranges that reside in the .dwo file when
DWARF fission is enabled.
This patch makes DWARF fission compatible with RISC-V relaxations. It
uses the StartxEndx DWARF forms in .debug_rnglists.dwo, which allow
referencing addresses from .debug_addr instead of using absolute
addresses. This approach eliminates relocations from .dwo files.
Commit: 97023fba5546f9d0e762ccbca89cbb8324a9131a
https://github.com/llvm/llvm-project/commit/97023fba5546f9d0e762ccbca89cbb8324a9131a
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/test/CIR/CodeGen/coro-task.cpp
Log Message:
-----------
[CIR] Emit ready and suspend branches for cir.await (#168814)
This PR adds codegen for `cir.await` ready and suspend. One notable
difference from the classic codegen is that, in the suspend branch, it
emits an `AwaitSuspendWrapper`(`.__await_suspend_wrapper__init`)
function that is always inlined. This function wraps the suspend logic
inside an internal wrapper that gets inlined. Example here:
https://godbolt.org/z/rWYGcaaG4
Commit: ebf5d9ef7de29b55fd9e9d504f83689b4013e0de
https://github.com/llvm/llvm-project/commit/ebf5d9ef7de29b55fd9e9d504f83689b4013e0de
Author: Alan Li <me at alanli.org>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-i8-gep.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-var-delta.ll
R llvm/test/Transforms/StraightLineStrengthReduce/path-compression.ll
R llvm/test/Transforms/StraightLineStrengthReduce/pick-candidate.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll
Log Message:
-----------
Revert "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169546)
This reverts commit f67409c3ec7cd45c55656c8159bc42b3918f1116.
cc @fiigii
Including us, several separate groups are experiencing regressions with
this change. This is the smallest reproducer pasted by @akuegel :
https://github.com/llvm/llvm-project/pull/162930#issuecomment-3574307330
Commit: 9534ed9f30043318798a9544461bc174e273e1f3
https://github.com/llvm/llvm-project/commit/9534ed9f30043318798a9544461bc174e273e1f3
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-26 (Wed, 26 Nov 2025)
Changed paths:
M orc-rt/include/orc-rt/Error.h
M orc-rt/unittests/ErrorTest.cpp
Log Message:
-----------
[orc-rt] Add ErrorAsOutParameter convenience constructor. (#169467)
Allows construction of ErrorAsOutParameters from Error references.
Commit: fd22706e937f7d2563cfa0e433dd735cc5284599
https://github.com/llvm/llvm-project/commit/fd22706e937f7d2563cfa0e433dd735cc5284599
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
A flang/test/Lower/OpenMP/compiler-directives-loop.f90
Log Message:
-----------
[flang][OpenMP] Skip compiler directives in getCollapsedLoopEval (#169565)
Use `getNestedDoConstruct` from Utils to get the nested DoConstructs.
Fixes https://github.com/llvm/llvm-project/issues/169532
Commit: f7a9fcad99e155fed32d98a2d41d1e3bfdeebf48
https://github.com/llvm/llvm-project/commit/f7a9fcad99e155fed32d98a2d41d1e3bfdeebf48
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/test/Lower/CUDA/cuda-atomicadd.cuf
Log Message:
-----------
[flang][cuda] Use PTX instruction for atomicAdd with 4xf32 (#169581)
Implementation similar to the clang one in
`clang/lib/Headers/__clang_cuda_intrinsics.h`
Commit: 1c034a372403d539700292cd564773ef3531a423
https://github.com/llvm/llvm-project/commit/1c034a372403d539700292cd564773ef3531a423
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
Log Message:
-----------
[compiler-rt] [UBsan] precommit test (#169579)
Commit: 60245f279f69d8844c5225a1ed44d880b5af0818
https://github.com/llvm/llvm-project/commit/60245f279f69d8844c5225a1ed44d880b5af0818
Author: Florian Mayer <fmayer at google.com>
Date: 2025-11-25 (Tue, 25 Nov 2025)
Changed paths:
M .gitattributes
M .github/workflows/bazel-checks.yml
M .github/workflows/build-ci-container-tooling.yml
M .github/workflows/build-ci-container-windows.yml
M .github/workflows/build-ci-container.yml
M .github/workflows/build-metrics-container.yml
M .github/workflows/check-ci.yml
M .github/workflows/ci-post-commit-analyzer.yml
M .github/workflows/commit-access-greeter.yml
M .github/workflows/commit-access-review.yml
M .github/workflows/docs.yml
M .github/workflows/email-check.yaml
M .github/workflows/gha-codeql.yml
M .github/workflows/hlsl-test-all.yaml
M .github/workflows/issue-release-workflow.yml
M .github/workflows/issue-subscriber.yml
M .github/workflows/issue-write.yml
M .github/workflows/libc-fullbuild-tests.yml
M .github/workflows/libc-overlay-tests.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/libclang-python-tests.yml
M .github/workflows/libcxx-build-and-test.yaml
M .github/workflows/libcxx-build-containers.yml
M .github/workflows/libcxx-check-generated-files.yml
M .github/workflows/libcxx-run-benchmarks.yml
M .github/workflows/llvm-abi-tests.yml
M .github/workflows/merged-prs.yml
M .github/workflows/mlir-spirv-tests.yml
M .github/workflows/new-prs.yml
M .github/workflows/pr-code-format.yml
M .github/workflows/pr-code-lint.yml
M .github/workflows/pr-request-release-note.yml
M .github/workflows/pr-subscriber.yml
M .github/workflows/premerge.yaml
M .github/workflows/release-asset-audit.yml
M .github/workflows/release-binaries.yml
M .github/workflows/release-documentation.yml
M .github/workflows/release-doxygen.yml
M .github/workflows/release-lit.yml
M .github/workflows/release-sources.yml
M .github/workflows/release-tasks.yml
M .github/workflows/scorecard.yml
M .github/workflows/spirv-tests.yml
M .github/workflows/test-unprivileged-download-artifact.yml
M .github/workflows/version-check.yml
M .gitignore
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/test/X86/lit.local.cfg
M bolt/test/lit.local.cfg
M bolt/unittests/Core/MCPlusBuilder.cpp
A clang/bindings/python/.git_archival.txt
A clang/bindings/python/.gitignore
A clang/bindings/python/pyproject.toml
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/cmake/caches/Fuchsia.cmake
M clang/docs/HIPSupport.rst
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/OpenMPKinds.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Basic/arm_mve_defs.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Sema/SemaARM.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/lib/Analysis/CFG.cpp
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets.cpp
M clang/lib/CIR/CodeGen/Address.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/lib/CIR/CodeGen/CIRGenOpenACCHelpers.h
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACCLoop.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/StaticAnalyzer/Core/CheckerHelpers.cpp
M clang/lib/StaticAnalyzer/Core/LoopUnrolling.cpp
M clang/test/Analysis/lifetime-cfg-output.cpp
M clang/test/Analysis/loop-unrolling.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
A clang/test/Analysis/std-c-library-functions-eof-2-rad.c
A clang/test/CIR/CodeGen/copy-constructor.cpp
M clang/test/CIR/CodeGen/coro-task.cpp
A clang/test/CIR/CodeGen/global-array-dtor.cpp
A clang/test/CIR/CodeGen/placement-new.cpp
M clang/test/CIR/CodeGen/vector-ext-element.cpp
M clang/test/CIR/CodeGenOpenACC/combined-copy.c
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-copy.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copyin.cpp
M clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
M clang/test/CIR/CodeGenOpenACC/declare-create.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceptr.cpp
M clang/test/CIR/CodeGenOpenACC/declare-deviceresident.cpp
M clang/test/CIR/CodeGenOpenACC/declare-link.cpp
M clang/test/CIR/CodeGenOpenACC/declare-present.cpp
M clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/openacc-not-implemented-global.cpp
R clang/test/CIR/CodeGenOpenACC/openacc-not-implemented.cpp
M clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
M clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
M clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
A clang/test/CodeGen/memprof-pgho.cpp
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
M clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
A clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
A clang/test/Misc/opencl-c-3.0.incorrect_define.cl
A clang/test/OpenMP/need_device_ptr_kind_ast_print.cpp
A clang/test/OpenMP/need_device_ptr_kind_messages.cpp
A clang/test/Sema/AArch64/builtin_vectorelements.c
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/unittests/Analysis/FlowSensitive/LoggerTest.cpp
M clang/utils/TableGen/MveEmitter.cpp
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
M compiler-rt/lib/scudo/standalone/tests/quarantine_test.cpp
M compiler-rt/lib/scudo/standalone/tests/size_class_map_test.cpp
M compiler-rt/lib/scudo/standalone/tsd_shared.h
M compiler-rt/test/lit.common.cfg.py
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Reduction.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCRecipeBufferization.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/module/cooperative_groups.f90
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/FirToSCF/do-loop.fir
M flang/test/Fir/OpenACC/recipe-bufferization.mlir
M flang/test/Lower/CUDA/cuda-atomicadd.cuf
A flang/test/Lower/CUDA/cuda-cluster.cuf
M flang/test/Lower/OpenACC/acc-firstprivate-derived-allocatable-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-pointer-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-user-assign.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
A flang/test/Lower/OpenACC/acc-reduction-remapping.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenACC/do-loops-to-acc-loops.f90
A flang/test/Lower/OpenMP/compiler-directives-loop.f90
M flang/test/Lower/identical-block-merge-disable.f90
M flang/test/Lower/implicit-interface.f90
M flang/test/Lower/inline_directive.f90
M flang/test/Lower/io-statement-1.f90
M flang/test/Lower/io-write.f90
M flang/test/Lower/location.f90
M flang/test/Lower/module_definition.f90
M flang/test/Lower/module_use.f90
M flang/test/Lower/module_use_in_same_file.f90
M flang/test/Lower/namelist-common-block.f90
M flang/test/Lower/nested-where.f90
M flang/test/Lower/nullify-polymorphic.f90
M flang/test/Lower/pointer-association-polymorphic.f90
M flang/test/Lower/pointer-disassociate.f90
M flang/test/Lower/polymorphic-temp.f90
M flang/test/Lower/polymorphic-types.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/procedure-declarations.f90
M flang/test/Lower/read-write-buffer.f90
M flang/test/Lower/select-type.f90
M flang/test/Lower/statement-function.f90
M flang/test/Lower/variable.f90
M flang/test/Lower/volatile-allocatable.f90
M flang/test/Lower/volatile-openmp1.f90
A flang/test/Semantics/OpenMP/compiler-directives-loop.f90
M flang/test/Semantics/OpenMP/loop-association.f90
A flang/test/Semantics/OpenMP/target-teams-nesting.f90
M flang/test/Transforms/OpenACC/acc-implicit-copy-reduction.fir
M flang/test/Transforms/OpenACC/acc-implicit-data-fortran.F90
M flang/test/Transforms/OpenACC/acc-implicit-data.fir
M flang/test/Transforms/OpenACC/acc-implicit-firstprivate.fir
A libclc/clc/include/clc/atomic/clc_atomic_flag_clear.h
A libclc/clc/include/clc/atomic/clc_atomic_flag_test_and_set.h
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/atomic/clc_atomic_flag_clear.cl
A libclc/clc/lib/generic/atomic/clc_atomic_flag_test_and_set.cl
A libclc/opencl/include/clc/opencl/atomic/atomic_flag_clear.h
A libclc/opencl/include/clc/opencl/atomic/atomic_flag_test_and_set.h
A libclc/opencl/include/clc/opencl/atomic/atomic_init.h
A libclc/opencl/include/clc/opencl/atomic/atomic_init.inc
A libclc/opencl/include/clc/opencl/types.h
A libclc/opencl/include/clc/opencl/utils.h
M libclc/opencl/lib/generic/SOURCES
A libclc/opencl/lib/generic/atomic/atomic_flag_clear.cl
A libclc/opencl/lib/generic/atomic/atomic_flag_test_and_set.cl
A libclc/opencl/lib/generic/atomic/atomic_init.cl
A libclc/opencl/lib/generic/atomic/atomic_init.inc
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/fill_n.h
A libcxx/include/__algorithm/specialized_algorithms.h
M libcxx/include/__bit_reference
M libcxx/include/__config
M libcxx/include/__configuration/platform.h
M libcxx/include/__functional/bind.h
M libcxx/include/__functional/bind_back.h
M libcxx/include/__functional/bind_front.h
M libcxx/include/__functional/function.h
M libcxx/include/__functional/mem_fn.h
M libcxx/include/__functional/reference_wrapper.h
M libcxx/include/__random/binomial_distribution.h
M libcxx/include/module.modulemap.in
M libcxx/include/stack
M libcxx/include/string
M libcxx/src/filesystem/operations.cpp
M libcxx/src/new.cpp
M libcxx/test/extensions/libcxx/odr_signature.exceptions.sh.cpp
M libcxx/test/extensions/libcxx/odr_signature.hardening.sh.cpp
M libcxx/test/libcxx/diagnostics/functional.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/stack.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/string.nodiscard.verify.cpp
M libcxx/test/std/utilities/function.objects/refwrap/refwrap.invoke/robust_against_adl.pass.cpp
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/InputFiles.cpp
M lld/test/MachO/x86-64-relocs.s
M lldb/include/lldb/API/SBStructuredData.h
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
M llvm/docs/DeveloperPolicy.rst
M llvm/docs/LangRef.rst
M llvm/docs/Vectorizers.rst
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
M llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/MC/MCSymbol.h
M llvm/include/llvm/Transforms/Utils/FunctionComparator.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/LibcallLoweringInfo.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
M llvm/lib/IR/CMakeLists.txt
A llvm/lib/IR/NVVMIntrinsicUtils.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/MC/MCSymbol.cpp
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchSelectionDAGInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchSelectionDAGInfo.h
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.h
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/Mips/Mips16ISelLowering.h
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsInstrFPU.td
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
M llvm/lib/Target/NVPTX/NVPTXTagInvariantLoads.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVCombine.td
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.cpp
M llvm/lib/Target/Sparc/SparcSubtarget.h
M llvm/lib/Target/VE/VETargetTransformInfo.h
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
A llvm/test/Analysis/ScalarEvolution/addrec-may-wrap-udiv-canonicalize.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/combine-sdiv.ll
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
R llvm/test/CodeGen/AArch64/pr151592.mir
R llvm/test/CodeGen/AArch64/pr151888.mir
R llvm/test/CodeGen/AArch64/pr164181-reduced.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
R llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/AArch64/rem-by-const.ll
A llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
M llvm/test/CodeGen/AArch64/sme-zt0-state.ll
M llvm/test/CodeGen/AArch64/srem-lkk.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/add_i1.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-entry.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/cse-convergent.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
A llvm/test/CodeGen/AMDGPU/gws_agpr.ll
M llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
A llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
M llvm/test/CodeGen/AMDGPU/spillv16.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub_i1.ll
M llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
M llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
M llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
A llvm/test/CodeGen/Mips/fp-intrinsics.ll
A llvm/test/CodeGen/Mips/fp-strict-fcmp.ll
M llvm/test/CodeGen/NVPTX/bswap.ll
M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
M llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
A llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
A llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
A llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
M llvm/test/CodeGen/PowerPC/combine-fneg.ll
M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
M llvm/test/CodeGen/PowerPC/frem.ll
M llvm/test/CodeGen/PowerPC/froundeven-legalization.ll
M llvm/test/CodeGen/PowerPC/half.ll
M llvm/test/CodeGen/PowerPC/ldexp.ll
M llvm/test/CodeGen/PowerPC/llvm.modf.ll
M llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
A llvm/test/CodeGen/RISCV/fma-combine.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
A llvm/test/CodeGen/SPIRV/GlobalISel/InstCombine/prelegalizercombiner-select-to-faceforward.mir
A llvm/test/CodeGen/SPIRV/function/vararg.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/faceforward.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll
A llvm/test/CodeGen/SPIRV/opencl/faceforward.ll
A llvm/test/CodeGen/Thumb2/mve-intrinsics/strict-intrinsics.ll
M llvm/test/CodeGen/Thumb2/mve-intrinsics/vabdq.ll
M llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
A llvm/test/CodeGen/X86/GlobalISel/fp-bitcast.ll
M llvm/test/CodeGen/X86/bitcnt-big-integer.ll
R llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
R llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
R llvm/test/CodeGen/X86/pr76416.ll
M llvm/test/CodeGen/X86/setcc-wide-types.ll
M llvm/test/CodeGen/X86/subreg-fail.mir
R llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
A llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
A llvm/test/MC/AMDGPU/ds_gws_sgpr_err.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
M llvm/test/TableGen/CPtrWildcard.td
A llvm/test/TableGen/ValueTypeByHwModeMissingRegInfo.td
M llvm/test/Transforms/InstCombine/cast-mul-select.ll
M llvm/test/Transforms/InstCombine/cast.ll
M llvm/test/Transforms/InstCombine/catchswitch-phi.ll
M llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
M llvm/test/Transforms/InstCombine/known-bits-lerp-pattern.ll
M llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
M llvm/test/Transforms/InstCombine/logical-select.ll
M llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll
M llvm/test/Transforms/LoopVectorize/AArch64/mul-simplification.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
M llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-cond-poison.ll
M llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
A llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
M llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-struct-return.ll
A llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll
A llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-i8-gep.ll
R llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-var-delta.ll
R llvm/test/Transforms/StraightLineStrengthReduce/path-compression.ll
R llvm/test/Transforms/StraightLineStrengthReduce/pick-candidate.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/basic.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/merge_attributes.ll
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/ps.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sincos_stret.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sleef.ll
M llvm/test/Verifier/llvm.loop.estimated_trip_count.ll
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
M llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/Transforms/Utils/LoopUtilsTest.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/git/github-automation.py
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
M mlir/include/mlir/Analysis/DataFlow/IntegerRangeAnalysis.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/include/mlir/Dialect/Tosa/Utils/QuantUtils.h
M mlir/include/mlir/TableGen/Pattern.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Conversion/ArithToAPFloat/ArithToAPFloat.cpp
M mlir/lib/Dialect/GPU/Pipelines/CMakeLists.txt
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Utils/QuantUtils.cpp
M mlir/lib/ExecutionEngine/APFloatWrappers.cpp
M mlir/lib/TableGen/Pattern.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Conversion/ArithToApfloat/arith-to-apfloat.mlir
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-data-reduction.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
M mlir/test/Dialect/OpenACC/invalid.mlir
M mlir/test/Dialect/OpenACC/legalize-data.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/quant-test.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
M mlir/test/Integration/Dialect/Arith/CPU/test-apfloat-emulation.mlir
A mlir/test/Target/LLVMIR/anonymous-tbaa.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_arrive.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_arrive_drop.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_complete_tx.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_expect_tx.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_init.mlir
A mlir/test/Target/LLVMIR/nvvm/mbar_invalid.mlir
R mlir/test/Target/LLVMIR/nvvm/mbarriers.mlir
M mlir/test/python/ir/operation.py
M mlir/tools/mlir-tblgen/RewriterGen.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCOpsInterfacesTest.cpp
A offload/test/mapping/use_device_addr/target_data_use_device_addr_arrsec_fallback.c
A offload/test/mapping/use_device_addr/target_data_use_device_addr_var_fallback.c
A offload/test/mapping/use_device_ptr/target_data_use_device_ptr_var_fallback.c
M offload/test/offloading/shared_lib_fp_mapping.c
M offload/test/offloading/static_linking.c
M orc-rt/include/orc-rt/Error.h
M orc-rt/unittests/ErrorTest.cpp
M orc-rt/unittests/SessionTest.cpp
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/extensions.bzl
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
A utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
A utils/bazel/llvm-project-overlay/third-party/cc_library_wrapper.bzl
M utils/bazel/third_party_build/zlib-ng.BUILD
M utils/bazel/third_party_build/zstd.BUILD
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/6ca0a10c950b...60245f279f69
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