[all-commits] [llvm/llvm-project] 2ee12f: AMDGPU: Use RegClassByHwMode to manage GWS operand...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ee12f191a005363259e3a95ccdf459d9044eadf
      https://github.com/llvm/llvm-project/commit/2ee12f191a005363259e3a95ccdf459d9044eadf
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-11-25 (Tue, 25 Nov 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/DSInstructions.td
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/gws_agpr.ll
    M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
    A llvm/test/MC/AMDGPU/ds_gws_sgpr_err.s
    M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s

  Log Message:
  -----------
  AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)

On targets that require even aligned 64-bit VGPRs, GWS operands
require even alignment of a 32-bit operand. Previously we had a hacky
post-processing which added an implicit operand to try to manage
the constraint. This would require special casing in other passes
to avoid breaking the operand constraint. This moves the handling
into the instruction definition, so other passes no longer need
to consider this edge case. MC still does need to special case this,
to print/parse as a 32-bit register. This also still ends up net
less work than introducing even aligned 32-bit register classes.

This also should be applied to the image special case.



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