[all-commits] [llvm/llvm-project] f287ab: [DAG][X86] Improve custom i256/i512 AVX512 CTLZ/CT...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f287abd53e03bf0fda9099c0845b25a340a20102
      https://github.com/llvm/llvm-project/commit/f287abd53e03bf0fda9099c0845b25a340a20102
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-11-25 (Tue, 25 Nov 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/ValueTypes.td
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/bitcnt-big-integer.ll
    M llvm/test/TableGen/CPtrWildcard.td

  Log Message:
  -----------
  [DAG][X86] Improve custom i256/i512 AVX512 CTLZ/CTTZ Handling with MVT::i256/i512 (#168860)

This patch proposes to move the AVX512 CTLZ/CTTZ i256/i512 codegen to
ReplaceNodeResults to allow them to be declared as custom lowering -
this allows expansion of larger int types (e.g. i1024) to fallback to
them during their expansion.

However to declare these i256/i512 ops as custom, we need to add
MVT::i256/i512 simple types - I'm intending to add further large integer
handling in the future, some of which will use vector register
instructions, and its going to be much easier if this can be handled
with i128/i256/i512 types that match the vector register sizes.

This exposed a regression in NVPTX due to their use of EVT::isSimple()
to match their upper integer size bounds.



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