[all-commits] [llvm/llvm-project] d40c8d: [Clang][OpenMP] Make test use clang_cc1 (#169233)
Marco Elver via All-commits
all-commits at lists.llvm.org
Mon Nov 24 08:36:44 PST 2025
Branch: refs/heads/users/melver/spr/instcombinememprof-preserve-alloc_token-metadata
Home: https://github.com/llvm/llvm-project
Commit: d40c8dccff70c0ffd4a6120334e4fcd472d2fd91
https://github.com/llvm/llvm-project/commit/d40c8dccff70c0ffd4a6120334e4fcd472d2fd91
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang/test/OpenMP/parallel_default_variableCategory_codegen.cpp
Log Message:
-----------
[Clang][OpenMP] Make test use clang_cc1 (#169233)
This test does not actually need to use the clang driver. Using the
driver means that the environment plays much more into the tests
results. We ran into a situation where the driver decided not to pass
-fopenmp to the cc1 invocation, causing the test to fail.
This also makes the test more consistent with the other OpenMP tests and
should make it slightly faster (no subprocess invocation).
Commit: c543615744d61e0967b956c402e310946d741570
https://github.com/llvm/llvm-project/commit/c543615744d61e0967b956c402e310946d741570
Author: Owen Anderson <resistor at mac.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Add myself to the former maintainers list. (#169201)
I was the SelectionDAG maintainer (then called code owner) from
aebfacb008246b912e2fc5a454939a3de942303b (requested to take it up by
Evan Cheng) and yielded the role to Justin Bogner as of
d8ed65dda0b10b5d9fa6ebd2da46e733fbde5512.
Commit: bbd99aa1f699071894ca7e5c86fb61ece0a96db5
https://github.com/llvm/llvm-project/commit/bbd99aa1f699071894ca7e5c86fb61ece0a96db5
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M lldb/unittests/Expression/DWARFExpressionTest.cpp
Log Message:
-----------
Fix #168467 (r598213) (#169232)
Co-authored-by: Aiden Grossman <agrossman154 at yahoo.com>
Commit: 996213c6ea0dc2e47624c6b06c0833a882c1c1f7
https://github.com/llvm/llvm-project/commit/996213c6ea0dc2e47624c6b06c0833a882c1c1f7
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanSLP.cpp
Log Message:
-----------
[VPlan] Refine mayRead/WriteFromMemory for VPInst, fix VPlan SLP check.
Fix VPlan SLP check incorrectly bailing out for non-VPInstructions.
Starting from the beginning of the block will include canonical IVs,
which in turn are not VPInstructions. If we hit a non-VPInstruction, we
should conservatively treat is as potentially unvectorizable.
To keep the tests working as expected, refine mayRead/WriteFromMemory
for Load and GEP VPInstructions.
Commit: f7ed15b9e734e63ab062a1f9a1b50588776a653d
https://github.com/llvm/llvm-project/commit/f7ed15b9e734e63ab062a1f9a1b50588776a653d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[bazel] Fully port 3773bbe9e7916ec89fb3e3cd02e29c54cabac82b (#169247)
e5edb512072bc040face27ed6c9e92f4a5f1e910 attempted to port this, but
seemed to miss a couple things that still showed up on CI. This patch
fixes up the missing pieces.
Commit: 4996645594cf9e2e318c0e693d9ec30d0aac5762
https://github.com/llvm/llvm-project/commit/4996645594cf9e2e318c0e693d9ec30d0aac5762
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang-tools-extra/clang-tidy/objc/AssertEqualsCheck.cpp
M clang/docs/LibASTMatchersReference.html
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
Log Message:
-----------
Revert "[ASTMatchers] Make isExpandedFromMacro accept llvm::StringRef… (#167060)" (#169238)
This reverts commit a52e1af7f766e26a78d10d31da98af041dd66410.
That commit reverted a change (making isExpandedFromMacro take a
std::string) that was explicitly added to avoid lifetime issues. We ran
into issues with some internal matchers due to this, and it probably is
not an uncommon downstream use case. This patch restroes the original
functionality and adds a test to ensure that the functionality is
preserved.
https://reviews.llvm.org/D90303 contains more discussion.
Commit: ded1311a28021c86814df34a00c8432bad02cc30
https://github.com/llvm/llvm-project/commit/ded1311a28021c86814df34a00c8432bad02cc30
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
Log Message:
-----------
[ORC] Fix typo in comment.
Commit: b73a281f026ca31330ee99dfb6e16a62363fe442
https://github.com/llvm/llvm-project/commit/b73a281f026ca31330ee99dfb6e16a62363fe442
Author: Nico Weber <thakis at chromium.org>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/LoongArch/BUILD.gn
Log Message:
-----------
[gn] port b5812c0cf789aa4cb (LoongArch SDNodeInfo)
Commit: 3c3e2a295254603c5fef271135cbe733139e78eb
https://github.com/llvm/llvm-project/commit/3c3e2a295254603c5fef271135cbe733139e78eb
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M orc-rt/include/orc-rt/WrapperFunction.h
M orc-rt/unittests/DirectCaller.h
Log Message:
-----------
[orc-rt] Remove unused Session argument from WrapperFunction::call. (#169255)
Commit: 28eee722aab153aaa8a257c935170aff3346d110
https://github.com/llvm/llvm-project/commit/28eee722aab153aaa8a257c935170aff3346d110
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
A llvm/test/Transforms/GlobalOpt/X86/apx.ll
Log Message:
-----------
[GlobalOpt] Add TTI interface useFastCCForInternalCall for FASTCC (#164768)
Background: X86 APX feature adds 16 registers within the same 64-bit
mode. PR #164638 is trying to extend such registers for FASTCC. However,
a blocker issue is calling convention cannot be changeable with or
without a feature.
The solution is to disable FASTCC if APX is not ready. This is an NFC
change to the final code generation, becasue X86 doesn't define an
alternative ABI for FASTCC in 64-bit mode. We can solve the potential
compatibility issue of #164638 with this patch.
Commit: a6cec3f3e5234d2646bc1a53715cda8324445ed2
https://github.com/llvm/llvm-project/commit/a6cec3f3e5234d2646bc1a53715cda8324445ed2
Author: hstk30-hw <hanwei62 at huawei.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
M llvm/test/CodeGen/AArch64/machine-sink-kill-flags.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/CodeGen/Hexagon/swp-stages5.ll
M llvm/test/CodeGen/NVPTX/atomics-b128.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll
M llvm/test/CodeGen/PowerPC/licm-xxsplti.ll
M llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
M llvm/test/CodeGen/PowerPC/sink-side-effect.ll
M llvm/test/CodeGen/PowerPC/sms-phi-1.ll
M llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/remat.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-reduct.ll
M llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
M llvm/test/CodeGen/WebAssembly/simd-shift-in-loop.ll
M llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
M llvm/test/CodeGen/X86/i128-mul.ll
M llvm/test/CodeGen/X86/loop-strength-reduce5.ll
M llvm/test/CodeGen/X86/madd.ll
M llvm/test/CodeGen/X86/pr49451.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
M llvm/test/CodeGen/X86/xor.ll
Log Message:
-----------
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" (#169219)
Reland d5f3ab8ec97786476a077b0c8e35c7c337dfddf2, fix testcases.
Commit: 25c2cc4b98092e8dccc8ff46162bea65e9a63bbc
https://github.com/llvm/llvm-project/commit/25c2cc4b98092e8dccc8ff46162bea65e9a63bbc
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/test/Transforms/GlobalOpt/X86/apx.ll
Log Message:
-----------
[GlobalOpt] Use `target triple` to fix Buildbot failures, NFCI (#169260)
This supposes to fix LLVM Buildbot failures after #164768. I don't have
the environment to verify though.
Commit: fe56f5c3d315bf3282a54a3b323cc462ce755136
https://github.com/llvm/llvm-project/commit/fe56f5c3d315bf3282a54a3b323cc462ce755136
Author: Matthias Springer <me at m-sp.org>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/include/mlir/Pass/Pass.h
M mlir/lib/Pass/Pass.cpp
M mlir/test/Dialect/Transform/test-pass-application.mlir
A mlir/test/Pass/invalid-unsupported-operation.mlir
M mlir/test/Pass/pipeline-invalid.mlir
Log Message:
-----------
[mlir][Pass] Fix crash when applying a pass to an optional interface (#169262)
Interfaces can be optional: whether an op implements an interface or not
can depend on the state of the operation.
```
// An optional code block for adding additional "classof" logic. This can
// be used to better enable "optional" interfaces, where an entity only
// implements the interface if some dynamic characteristic holds.
// `$_attr`/`$_op`/`$_type` may be used to refer to an instance of the
// interface instance being checked.
code extraClassOf = "";
```
The current `Pass::canScheduleOn(RegisteredOperationName)` is
insufficient. This commit adds an additional overload to inspect
`Operation *`.
This commit fixes a crash when scheduling an `InterfacePass` for an
optional interface on an operation that does not actually implement the
interface.
This is a re-upload of #168499, which was reverted.
Commit: c4254cd9bb52fb8ef101dcfbcec048447e6c99bb
https://github.com/llvm/llvm-project/commit/c4254cd9bb52fb8ef101dcfbcec048447e6c99bb
Author: Wenju He <wenju.he at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/Basic/Targets/SPIR.h
A clang/test/CodeGenOpenCL/__bf16.cl
M clang/test/SemaSYCL/bf16.cpp
Log Message:
-----------
[Clang] Support __bf16 type for SPIR/SPIR-V (#169012)
SPIR/SPIR-V are generic targets. Assume they support __bf16.
Commit: e71f243a8d0ed1a5089a4f56dcb90be972dfa061
https://github.com/llvm/llvm-project/commit/e71f243a8d0ed1a5089a4f56dcb90be972dfa061
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
Log Message:
-----------
[TableGen] Simplify MachineValueTypeSet::iterator::find_from_pos. NFC (#169227)
Merge the SkipBits!=0 handling into the first iteration of the word
loop. This is the same code structure used by BitVector::find_first_in.
Commit: c33e50bdc73522ed07a6d636dad66bbd1677daec
https://github.com/llvm/llvm-project/commit/c33e50bdc73522ed07a6d636dad66bbd1677daec
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/test/Transforms/GlobalOpt/X86/apx.ll
Log Message:
-----------
[GlobalOpt] Use `x86-registered-target` to fix Buildbot failures, 2nd try (#169266)
Commit: acab67baa72c9def53ac8fcd57cbb3b386903405
https://github.com/llvm/llvm-project/commit/acab67baa72c9def53ac8fcd57cbb3b386903405
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M compiler-rt/cmake/builtin-config-ix.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
[M68k][compiler-rt] Allow compiler-rt builtins to be built for M68k (#169256)
I've tested this locally, and the builtins build proceeds without a
hitch for m68k-none-none. This is part of a larger effort to establish a
working m68k baremetal toolchain.
Commit: ee4f6478babbcc746ef610e4bc0cf3859714b1e2
https://github.com/llvm/llvm-project/commit/ee4f6478babbcc746ef610e4bc0cf3859714b1e2
Author: Leon Clark <Leon4116 at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll
Log Message:
-----------
[AMDGPU] Propagate AA info in vector load/store splitting. (#168871)
Fixes a bug in `AMDGPUISelLowering` where alias analysis info is not
propagated to split loads and stores.
This is required for #161375
---------
Co-authored-by: Leon Clark <leoclark at amd.com>
Commit: 7851b8a65c5481bdf4a56f61a2c9603c2880dbc2
https://github.com/llvm/llvm-project/commit/7851b8a65c5481bdf4a56f61a2c9603c2880dbc2
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vector-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
Log Message:
-----------
[RISCV] Combine vslide{up,down} x, poison -> x (#169013)
The motivation for this is that it would be useful to express a
vslideup/vslidedown in a target independent way e.g. from the loop
vectorizer.
We can do this today with @llvm.vector.splice by setting one operand to
poison:
- A slide down can be achieved with @llvm.vector.splice(%x, poison,
slideamt)
- A slide up can be done by @llvm.vector.splice(poison, %x, -slideamt)
E.g.:
splice(<a,b,c,d>, poison, 3) = <d,poison,poison,poison>
splice(poison, <a,b,c,d>, -3) = <poison,poison,poison,a>
These splices get lowered to a vslideup + vslidedown pair with one of
the vs2s being poison. We can optimize this away so that we are just
left with a single slideup/slidedown.
Commit: 202d7840ff965400804972454e9de39e7d30e0b5
https://github.com/llvm/llvm-project/commit/202d7840ff965400804972454e9de39e7d30e0b5
Author: Twice <twice at apache.org>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Dialect/IRDL/IRDLLoading.cpp
M mlir/test/Dialect/IRDL/variadics.mlir
Log Message:
-----------
[MLIR][IRDL] Support camelCase segment size attributes in IRDL verifier (#168836)
Two years ago, `operand_segment_sizes` and `result_segment_sizes` were
renamed to `operandSegmentSizes` and `resultSegmentSizes` (check related
commits, e.g.
https://github.com/llvm/llvm-project/commit/363b655920c49a4bcb0869f820ed40aac834eebd).
However, the op verifiers in IRDL loading phase is still using old
attributes like `operand_segment_sizes` and `result_segment_sizes`,
which causes some conflict, e.g. it is not compatible with the OpView
builder in MLIR python bindings (which generates camelCase segment
attributes).
This PR is to support to use camelCase segment size attributes in IRDL
verifier. Note that support of `operand_segment_sizes` and
`result_segment_sizes` is dropped.
I found this issue since I'm working on a new IRDL wrapper in the MLIR
python bindings.
Commit: 13a39eaa0bcf6c439e8b59571f4afe593d658623
https://github.com/llvm/llvm-project/commit/13a39eaa0bcf6c439e8b59571f4afe593d658623
Author: hstk30-hw <hanwei62 at huawei.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[Sema] Fix Wunused-but-set-variable warning(NFC) (#169220)
Fix warning:
llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp:1455:23: warning:
variable 'Store' set but not used [-Wunused-but-set-variable]
Commit: b53e46f71af06e0338ddff8d6d3c87230d4b441d
https://github.com/llvm/llvm-project/commit/b53e46f71af06e0338ddff8d6d3c87230d4b441d
Author: Arun Thangamani <arun.thangamani at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/include/mlir/Dialect/X86Vector/CMakeLists.txt
A mlir/include/mlir/Dialect/X86Vector/TransformOps/CMakeLists.txt
A mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.h
A mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
M mlir/include/mlir/Dialect/X86Vector/Transforms.h
M mlir/lib/Dialect/X86Vector/CMakeLists.txt
A mlir/lib/Dialect/X86Vector/TransformOps/CMakeLists.txt
A mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
M mlir/lib/Dialect/X86Vector/Transforms/CMakeLists.txt
A mlir/lib/Dialect/X86Vector/Transforms/VectorContractToFMA.cpp
A mlir/lib/Dialect/X86Vector/Transforms/VectorContractToPackedTypeDotProduct.cpp
M mlir/lib/RegisterAllExtensions.cpp
A mlir/test/Dialect/X86Vector/vector-contract-to-fma.mlir
A mlir/test/Dialect/X86Vector/vector-contract-to-packed-type-dotproduct.mlir
Log Message:
-----------
[mlir][x86vector] Lower vector.contract to FMA or packed type dot-product (#168074)
A `transform` pass to lower `vector.contract` to (a) `vector.fma` for
`F32`, (b) `x86vector.avx512.dot` for `BF16`, (c) `x86vector.avx.dot.i8`
for `Int8` packed types.
The lowering works on condition with `m`, `batch`, `k` dims to be `one`
and `vnni` dim should be `2` for `bf16`; `4` for `int8`.
**The lowering pattern**: `batch_reduce.matmul` (input) ->
register-tiling(M, N) -> Vectorization (to `vector.contract`) ->
`unroll` vector.contract (`unit` dims) -> `hoisting` transformation
(move `C` loads/store outside batch/k loop) -> apply `licm`,
`canonicalization`, and `bufferize`.
Commit: 76e7e9fa109e424c18edc2b89e991dac99979599
https://github.com/llvm/llvm-project/commit/76e7e9fa109e424c18edc2b89e991dac99979599
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll
M llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll
Log Message:
-----------
[LoongArch][NFC] Add tests for combining vand(vnot) (#160830)
Commit: d124675e27a6abbce0bfea6a25ab9dfe66e9d657
https://github.com/llvm/llvm-project/commit/d124675e27a6abbce0bfea6a25ab9dfe66e9d657
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Dialect/X86Vector/Transforms/CMakeLists.txt
Log Message:
-----------
[mlir][x86vector] Add missing Linalg dependency (#169280)
Adds required dependency for `inferContractionDims`.
Fixes #168074
Commit: 54db657b9ebdbce70f902313e6b303d85d68a4dc
https://github.com/llvm/llvm-project/commit/54db657b9ebdbce70f902313e6b303d85d68a4dc
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/SarifDiagnostics.cpp
Log Message:
-----------
[StaticAnalyzer] Use llvm::find_if (NFC) (#169237)
Identified with llvm-use-ranges.
Commit: 67391fc039b27f4e82624a6de4493cdd0907878b
https://github.com/llvm/llvm-project/commit/67391fc039b27f4e82624a6de4493cdd0907878b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
Log Message:
-----------
[mlir] Construct SmallVector with initial values (NFC) (#169239)
Identified with llvm-use-ranges.
Commit: 2b81e9e8fea0cdb2eac1537c1f882b695615b141
https://github.com/llvm/llvm-project/commit/2b81e9e8fea0cdb2eac1537c1f882b695615b141
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Core.cpp
Log Message:
-----------
[Orc] Use a range-based for loop (NFC) (#169240)
Identified with modernize-loop-convert.
Commit: 7dd531f428614a310b6715fe9181432393d9095b
https://github.com/llvm/llvm-project/commit/7dd531f428614a310b6715fe9181432393d9095b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
Log Message:
-----------
[SPIRV] Use range-based for loops (NFC) (#169241)
Identified with modernize-loop-convert.
Commit: 9ce6fadbcaf60ed88302617b6301f68989d44e3e
https://github.com/llvm/llvm-project/commit/9ce6fadbcaf60ed88302617b6301f68989d44e3e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-11-23 (Sun, 23 Nov 2025)
Changed paths:
M clang/include/clang/AST/OpenMPClause.h
Log Message:
-----------
[AST] Construct iterator_range with the conversion constructor (NFC) (#169245)
This patch simplifies iterator_range construction with the conversion
constructor.
Commit: 95f0fab7fab48bbf37d3c02c0ea8b01ca73c30dd
https://github.com/llvm/llvm-project/commit/95f0fab7fab48bbf37d3c02c0ea8b01ca73c30dd
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/test/AST/ByteCode/cxx23.cpp
Log Message:
-----------
[clang][bytecode] Fix conditional operator scoping wrt. local variables (#169030)
We used to create a scope for the true- and false expression of a
conditional operator. This was done so e.g. in this example:
```c++
struct A { constexpr A(){}; ~A(); constexpr int get() { return 10; } }; // all-note 2{{declared here}}
static_assert( (false ? A().get() : 1) == 1);
```
we did _not_ evaluate the true branch at all, meaning we did not
register the local variable for the temporary of type `A`, which means
we also didn't call it destructor.
However, this breaks the case where the temporary needs to outlive the
conditional operator and instead be destroyed via the surrounding
`ExprWithCleanups`:
```
constexpr bool test2(bool b) {
unsigned long __ms = b ? (const unsigned long &)0 : __ms;
return true;
}
static_assert(test2(true));
```
Before this patch, we diagnosed this example:
```console
./array.cpp:180:15: error: static assertion expression is not an integral constant expression
180 | static_assert(test2(true));
| ^~~~~~~~~~~
./array.cpp:177:24: note: read of temporary whose lifetime has ended
177 | unsigned long __ms = b ? (const unsigned long &)0 : __ms;
| ^
./array.cpp:180:15: note: in call to 'test2(true)'
180 | static_assert(test2(true));
| ^~~~~~~~~~~
./array.cpp:177:51: note: temporary created here
177 | unsigned long __ms = b ? (const unsigned long &)0 : __ms;
| ^
1 error generated.
```
because the temporary created for the true branch got immediately
destroyed.
The problem in essence is that since the conditional operator doesn't
create a scope at all, we register the local variables for both its
branches, but we later only execute one of them, which means we should
also only destroy the locals of one of the branches.
We fix this similar to clang codgen's `is_active` flag: In the case of a
conditional operator (which is so far the only case where this is
problematic, and this also helps minimize the performance impact of this
change), we make local variables as disabled-by-default and then emit a
`EnableLocal` opcode later, which marks them as enabled. The code
calling their destructors checks whether the local was enabled at all.
Commit: f5cae7b805946337f30437871ea6e13844507775
https://github.com/llvm/llvm-project/commit/f5cae7b805946337f30437871ea6e13844507775
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/unittests/ExecutionEngine/Orc/WaitingOnGraphTest.cpp
Log Message:
-----------
[ORC] Add unit test for simple cycle in WaitingOnGraph::emit. (#169281)
WaitingOnGraphTests.Emit_SingleContainerSimpleCycle tests a pair of emit
operations where the second completes a simple cycle (1: A -> B, 2: B ->
A).
We already had a test of WaitingOnGraph::simplify's behavior in this
case, but did not have one for WaitingOnGraph::emit.
Commit: 02a997cf365d7cf9759ee732f27241f1242a84b3
https://github.com/llvm/llvm-project/commit/02a997cf365d7cf9759ee732f27241f1242a84b3
Author: owenca <owenpiano at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Handle `import` when used as template function name (#169279)
Fixes #149960
Commit: c15a6cc00b1a0e3a47d99172b839ec45c72168ae
https://github.com/llvm/llvm-project/commit/c15a6cc00b1a0e3a47d99172b839ec45c72168ae
Author: ganenkokb-yandex <160136233+ganenkokb-yandex at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/include/clang/AST/ASTImporter.h
M clang/lib/AST/ASTImporter.cpp
M clang/unittests/AST/ASTImporterTest.cpp
Log Message:
-----------
[Clang][ASTImporter] Fix cycle in importing template specialization on auto type with typename (#162514)
ASTImporter on importing template specialization with auto return type
faces cycle when return type is not nested one, but typename from
template arguments and other template.
There is code, that prevents cycle to auto return types when nested type
declared. Solved case differs somehow from nested types, but have same
solution with UsedDifferentProtoType - with delayed return type
determining.
Commit: e888cf863d5c0a83933f97cac04ae5dc5010e1a1
https://github.com/llvm/llvm-project/commit/e888cf863d5c0a83933f97cac04ae5dc5010e1a1
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
Log Message:
-----------
[AMDGPU] Add wave reduce intrinsics for float types - 2 (#168859)
Supported Ops: `fadd`, `fsub`
Commit: 1abb055c57c977f98267bdb89c856adfaa71e892
https://github.com/llvm/llvm-project/commit/1abb055c57c977f98267bdb89c856adfaa71e892
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[IVDesc] Make getCastInsts return an ArrayRef (NFC) (#169021)
To make it clear that the return value is immutable.
Commit: ce70d4b5b5130f2ac8586c3dd2198dc91771f534
https://github.com/llvm/llvm-project/commit/ce70d4b5b5130f2ac8586c3dd2198dc91771f534
Author: Gil Rapaport <gil.rapaport at mobileye.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
Log Message:
-----------
[mlir][emitc] Refactor getEmittedExpression (NFC) (#168361)
This method returns the current expression being emitted, but is only
used testing whether an expression is being emitted or not. This patch
therefore replaces it with a boolean isEmittingExpression() method.
Commit: f21857313dfab543e66ef43b1aed43b685794a7c
https://github.com/llvm/llvm-project/commit/f21857313dfab543e66ef43b1aed43b685794a7c
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/CAS/OnDiskGraphDB.cpp
Log Message:
-----------
[llvm][CAS] Remove unused functions (#168856)
Building with GCC I got:
```
<...>/OnDiskGraphDB.cpp:624:18: warning: ‘static {anonymous}::DataRecordHandle {anonymous}::DataRecordHandle::construct(char*, const {anonymous}::DataRecordHandle::Input&)’ defined but not used [-Wunused-function]
624 | DataRecordHandle DataRecordHandle::construct(char *Mem, const Input &I) {
| ^~~~~~~~~~~~~~~~
<...>/OnDiskGraphDB.cpp:456:1: warning: ‘static {anonymous}::DataRecordHandle {anonymous}::DataRecordHandle::create(llvm::function_ref<char*(long unsigned int)>, const {anonymous}::DataRecordHandle::Input&)’ defined but not used [-Wunused-function]
456 | DataRecordHandle::create(function_ref<char *(size_t Size)> Alloc,
| ^~~~~~~~~~~~~~~~
```
These implement parts of a class that is defined in an anonymous
namespace. All llvm tests passed with them removed.
Commit: c745a512dcfaa550c58b42bedd06464b7f593a26
https://github.com/llvm/llvm-project/commit/c745a512dcfaa550c58b42bedd06464b7f593a26
Author: Ingo Müller <ingomueller at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir:x86vector:transform] Fix bazel build after #168074. (#169294)
This PR fixes the bazel build that went out of sync with the changes
introduced in #168074.
Signed-off-by: Ingo Müller <ingomueller at google.com>
Commit: 6413e5a2df8ca75c4b54b2577bbec9a9d31911b0
https://github.com/llvm/llvm-project/commit/6413e5a2df8ca75c4b54b2577bbec9a9d31911b0
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/SemanticSelection.cpp
M clang-tools-extra/clangd/unittests/SemanticSelectionTests.cpp
Log Message:
-----------
[clangd] Implement fold range for #pragma region (#168177)
The implementation is based on the directive tree.
Fixes https://github.com/clangd/clangd/issues/1623
Commit: 30b1d1422733c012c274f173a3f4986615f7c1c7
https://github.com/llvm/llvm-project/commit/30b1d1422733c012c274f173a3f4986615f7c1c7
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/test/Analysis/stackaddrleak.c
Log Message:
-----------
[analyzer] Fix inf recursion in StackAddrEscapeChecker for self referencing blocks (#169208)
Objective-C blocks are like lambdas. They have captures, just like lambdas.
However, they can also implicitly capture themselves unlike lambdas.
This means that when walking the captures of a block, we may end up in
infinite recursion. This is not possible with lambdas, but happened in
practice with blocks downstream.
In this patch, I just use a set to keep track of the visited MemRegions.
Note that theoretically, there is nothing preventing usual lambdas or
functors from falling for the same trap, but probably slightly more
difficult to do so. You would likely need a pointer to itself, etc. I'll
not speculate here.
This inf recursion was likely caused by #126620, released in clang-21.
rdar://162215172
Commit: 4604762cc336317b0f02f7d8c1576f6205f4ea61
https://github.com/llvm/llvm-project/commit/4604762cc336317b0f02f7d8c1576f6205f4ea61
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
Log Message:
-----------
[AMDGPU] Add builtins for wave reduction intrinsics (#161816)
Commit: 4b65cafa182a9b91131bfce986e815c9a4ab6ae5
https://github.com/llvm/llvm-project/commit/4b65cafa182a9b91131bfce986e815c9a4ab6ae5
Author: Benjamin Maxwell <macdue at dueutil.tech>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/sve-bf16-arith.ll
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
Log Message:
-----------
[AArch64][SVE] Add custom lowering for bfloat FMUL (with +bf16) (#167502)
This lowers an SVE FMUL of bf16 using the BFMLAL top/bottom instructions
rather than extending to an f32 mul. This does require zeroing the
accumulator, but requires fewer extends/unpacking.
Commit: 121e2e9e377c1db6b5cb536e7fd0b78244c0ce04
https://github.com/llvm/llvm-project/commit/121e2e9e377c1db6b5cb536e7fd0b78244c0ce04
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/string
Log Message:
-----------
[libc++] Introduce basic_string::__allocate_long_buffer_for_growing (#162633)
Introducing this utility makes the `__grow_by{,_and_replace}`
significantly easier to understand and allows us to migrate away from
these functions in the future.
Commit: f3ce5dec690e11645e0b838132d3306b56c0ec97
https://github.com/llvm/llvm-project/commit/f3ce5dec690e11645e0b838132d3306b56c0ec97
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/__algorithm/all_of.h
M libcxx/include/__algorithm/none_of.h
A libcxx/test/std/algorithms/robust_against_nonbool.compile.pass.cpp
Log Message:
-----------
[libc++] Forward std::all_of and std::none_of to std::any_of (#167670)
This allows propagating optimizations to different algorithms by just
optimizing the lowest one. This is especially relevant now that we start
optimizing how we're iterating through ranges (e.g. the segmented
iterator optimizations) and adding assumptions so the compier can better
leverage semantics guaranteed by the standard (e.g.
`__builtin_assume_dereferenceable`).
Commit: 4b35ff583fbc61074bdf7b1ebf908d31e578f5ac
https://github.com/llvm/llvm-project/commit/4b35ff583fbc61074bdf7b1ebf908d31e578f5ac
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/remat.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
Log Message:
-----------
[RISCV] Enable rematerialization for scalar loads (#166774)
In some workloads we see an argument passed on the stack where it is
loaded, only for it to be immediately spilled to a different slot on the
stack and then reloaded from that spill slot later on.
We can avoid the unnecessary spill by marking loads as rematerializable
and just directly loading from where the argument was originally passed
on the stack. TargetTransformInfo::isReMaterializableImpl checks to make
sure that any loads are `MI.isDereferenceableInvariantLoad()`, so we
should be able to move the load down to the remat site.
This gives a 14.8% reduction in spills in 544.nab_r on rva23u64 -O3, and
a few other smaller reductions on llvm-test-suite. I didn't find any
benchmarks where the number of spills/reloads increased.
Related: #165761
Commit: 9be30e50c2bf878bd15ac8ed1270f1714c32b30f
https://github.com/llvm/llvm-project/commit/9be30e50c2bf878bd15ac8ed1270f1714c32b30f
Author: hev <wangrui at loongson.cn>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsLoongArchLASX.def
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Headers/lasxintrin.h
M clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
M clang/test/CodeGen/LoongArch/lasx/builtin.c
M clang/test/Preprocessor/init-loongarch.c
Log Message:
-----------
[clang][LoongArch] Introduce LASX and LSX conversion intrinsics (#157819)
This patch introduces the LASX and LSX conversion intrinsics:
- __m256 __lasx_cast_128_s (__m128)
- __m256d __lasx_cast_128_d (__m128d)
- __m256i __lasx_cast_128 (__m128i)
- __m256 __lasx_concat_128_s (__m128, __m128)
- __m256d __lasx_concat_128_d (__m128, __m128d)
- __m256i __lasx_concat_128 (__m128, __m128i)
- __m128 __lasx_extract_128_lo_s (__m256)
- __m128d __lasx_extract_128_lo_d (__m256d)
- __m128i __lasx_extract_128_lo (__m256i)
- __m128 __lasx_extract_128_hi_s (__m256)
- __m128d __lasx_extract_128_hi_d (__m256d)
- __m128i __lasx_extract_128_hi (__m256i)
- __m256 __lasx_insert_128_lo_s (__m256, __m128)
- __m256d __lasx_insert_128_lo_d (__m256d, __m128d)
- __m256i __lasx_insert_128_lo (__m256i, __m128i)
- __m256 __lasx_insert_128_hi_s (__m256, __m128)
- __m256d __lasx_insert_128_hi_d (__m256d, __m128d)
- __m256i __lasx_insert_128_hi (__m256i, __m128i)
Relevant GCC patch:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c2013267642fea4a6e89b826940c8aa80a76089d
Commit: 8c6ec1212720ebbbd7dc10e1fea2602a5d58eef5
https://github.com/llvm/llvm-project/commit/8c6ec1212720ebbbd7dc10e1fea2602a5d58eef5
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/array
M libcxx/test/libcxx/diagnostics/array.nodiscard.verify.cpp
M libcxx/test/std/containers/sequences/array/array.creation/to_array.verify.cpp
Log Message:
-----------
[libc++][array] Applied `[[nodiscard]]` (#168829)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: 4c4cf71095c4e2e2063793d889db3ca984dd375e
https://github.com/llvm/llvm-project/commit/4c4cf71095c4e2e2063793d889db3ca984dd375e
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/list
M libcxx/test/libcxx/diagnostics/list.nodiscard.verify.cpp
Log Message:
-----------
[libc++][list] Applied `[[nodiscard]]` (#169015)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 74a62b12b0461cf051dbb4c3842fdccad305411b
https://github.com/llvm/llvm-project/commit/74a62b12b0461cf051dbb4c3842fdccad305411b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/test/CodeGen/X86/avx2-builtins.c
Log Message:
-----------
[X86] avx2-builtins.c - add constexpr test coverage for _mm256_bslli_epi128/_mm256_bsrli_epi128 intrinsics (#169309)
Commit: d44d329c0b2f13bd1c259c822f5c4fc47d1240d5
https://github.com/llvm/llvm-project/commit/d44d329c0b2f13bd1c259c822f5c4fc47d1240d5
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/test/AST/ByteCode/intap.cpp
Log Message:
-----------
[clang][bytecode] Fix compound assign operators for IntAP(S) (#169303)
We didn't take `IntAP`/`IntAPS` into account when casting to and from
the computation LHS type. This broke the
`std/ranges/range.factories/range.iota.view/end.pass.cpp` test.
Commit: c73de9777e67df4411020a7909f0eadbbf1de08b
https://github.com/llvm/llvm-project/commit/c73de9777e67df4411020a7909f0eadbbf1de08b
Author: Julian Nagele <j.nagele at apple.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/test/Transforms/LoopUnroll/partial-unroll-reductions.ll
M llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
Log Message:
-----------
[IVDesciptors] Support detecting reductions with vector instructions. (#166353)
In combination with https://github.com/llvm/llvm-project/pull/149470
this will introduce parallel accumulators when unrolling reductions with
vector instructions. See also
https://github.com/llvm/llvm-project/pull/166630, which aims to
introduce parallel accumulators for FP reductions.
Commit: 840a43bbe3a7361f99e9444dfcfd9eefe60ba487
https://github.com/llvm/llvm-project/commit/840a43bbe3a7361f99e9444dfcfd9eefe60ba487
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/utils/ci/buildkite-pipeline.yml
Log Message:
-----------
[libcxx][ci] Temporarily disable ARM jobs (#169318)
Linaro is doing network maintenance and I don't have an estimated time
these will be back online.
Commit: fe9c8e4f10c74990a06f8837e4a45c56f725cb65
https://github.com/llvm/llvm-project/commit/fe9c8e4f10c74990a06f8837e4a45c56f725cb65
Author: Ingo Müller <ingomueller at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir:x86vector:transform] Fix bazel build (again) after #168074. (#169316)
This is a second attempt to fix the bazel build (after the first in
#169294, which was accidentally merged before CI passed). In the first
attempt, not all bazel dependencies had been added; this PR should add
them all and make CI pass.
Signed-off-by: Ingo Müller <ingomueller at google.com>
Commit: 5d2fc9408e99201a32f090ba263de05a362dfa2b
https://github.com/llvm/llvm-project/commit/5d2fc9408e99201a32f090ba263de05a362dfa2b
Author: Meredith Julian <35236176+mjulian31 at users.noreply.github.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/test/Transforms/InstCombine/scalarization.ll
Log Message:
-----------
[InstCombine] Fix phi scalarization with binop (#169120)
InstCombine phi scalarization would always create a new binary op with
the phi as the first operand, which is not correct for non-commutable
binary ops such as sub. This fix preserves the original binary op
ordering in the new binary op and adds a test for this behavior.
Currently, this transformation can produce silently incorrect IR, and in
the case of the added test, would optimize it out entirely.
Commit: d162c91c01a66e4af0af190044961e60db0eeb3d
https://github.com/llvm/llvm-project/commit/d162c91c01a66e4af0af190044961e60db0eeb3d
Author: Lang Hames <lhames at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
Log Message:
-----------
[ORC] Avoid self-dependence in SuperNode dependence graph. (#169286)
Avoid adding any given SuperNode SN to its own SuperNode-deps set. This
saves us from trying to redundantly merge its dependencies back into
itself (a no-op, but a potentially expensive one).
Commit: 1dc6ad008164353e05bfe857f905028827834dbb
https://github.com/llvm/llvm-project/commit/1dc6ad008164353e05bfe857f905028827834dbb
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M lldb/include/lldb/Target/UnixSignals.h
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Target/UnixSignals.cpp
M lldb/unittests/Signals/UnixSignalsTest.cpp
Log Message:
-----------
[lldb] Show signal number description (#164176)
show information about the signal when the user presses `process handle
<unix-signal>` i.e
```sh
(lldb) process handle SIGWINCH
NAME PASS STOP NOTIFY DESCRIPTION
=========== ===== ===== ====== ===================
SIGWINCH true false false window size changes
```
Wanted to use the existing `GetSignalDescription` but it is expected
behaviour to return the signal name if no signal code is passed. It is
used in stop info.
https://github.com/llvm/llvm-project/blob/65c895dfe084860847e9e220ff9f1b283ebcb289/lldb/source/Target/StopInfo.cpp#L1192-L1195
Commit: d41628941743b778432e30d93f25028ffb375fbc
https://github.com/llvm/llvm-project/commit/d41628941743b778432e30d93f25028ffb375fbc
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
Log Message:
-----------
[TableGen] Eliminate the dependency on SDNode definition order (#168745)
Fix the dependency of `CodeGenDAGPatterns::ParseDefaultOperands()` on
the particular order of SDNode definitions. Implicit usage of the first
definition as a placeholder makes `llvm-tblgen -gen-dag-isel` fail if
that SDNode is not usable as an output pattern operator and an instance
of `OperandWithDefaultOps` is used in a pattern.
Presently, each `OperandWithDefaultOps` record is processed by
constructing an instance of TreePattern from its `DefaultOps` argument
that has the form `(ops ...)`. Even though the result of processing the
root operator of that DAG is not inspected by `ParseDefaultOperands()`
function itself, that operator has to be supported by the underlying
`TreePattern::ParseTreePattern()` function. For that reason, a temporary
DAG is created by replacing the root operator of `DefaultOps` argument
with the first SDNode defined, which is usually `def imm : ...` defined
in `TargetSelectionDAG.td` file.
This results in misleading errors being reported when implementing new
`SDNode` types, if the new definition happens to be added before the
`def imm : ...` line. The error is reported by several test cases
executed by `check-llvm` target, as well as by the regular build, if one
of the enabled targets inherit one of its operand types from
`OperandWithDefaultOps`:
OptionalIntOperand: ../llvm/test/TableGen/DAGDefaultOps.td:28:5: error: In OptionalIntOperand: Cannot use 'unexpected_node' in an output pattern!
def OptionalIntOperand: OperandWithDefaultOps<i32, (ops (i32 0))>;
This commit implements a dedicated constructor of `TreePattern` to be
used if the caller does not care about the particular root operator of
the pattern being processed.
Commit: d90bc3bc609d3ef2254e85cfcd435a99eb2b019b
https://github.com/llvm/llvm-project/commit/d90bc3bc609d3ef2254e85cfcd435a99eb2b019b
Author: Dmitry Chigarev <dmitry.chigarev at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
Log Message:
-----------
[mlir][XeGPU][VectorToXeGPU] Use 'xegpu.load' to lower 1D 'vector.transfer_read' for PVC & BMG (#168910)
The PR changes the `TransferReadLowering` to always use `xegpu.load`
(and not `xegpu.load_nd`) for 1D cases as it has more developed
interface (e.g. layouts capabilites).
Signed-off-by: dchigarev <dmitry.chigarev at intel.com>
Commit: 72bfa28c07c810112da0778f504b91e87ab63600
https://github.com/llvm/llvm-project/commit/72bfa28c07c810112da0778f504b91e87ab63600
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/test/CodeGen/X86/avx2-builtins.c
Log Message:
-----------
[X86] avx2-builtins.c - fix copy+paste typo in _mm256_cmpeq_epi8 constexpr test - still tested _mm_cmpeq_epi8 (#169311)
Commit: 74f5548bbc916a6c23731561f3808e64633760c7
https://github.com/llvm/llvm-project/commit/74f5548bbc916a6c23731561f3808e64633760c7
Author: Nathan Gauër <brioche at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/AST/HLSL/semantic-input-struct-shadow.hlsl
A clang/test/AST/HLSL/semantic-input-struct.hlsl
A clang/test/AST/HLSL/semantic-input.hlsl
A clang/test/AST/HLSL/semantic-output-struct-shadow.hlsl
A clang/test/AST/HLSL/semantic-output-struct.hlsl
A clang/test/AST/HLSL/semantic-output.hlsl
M clang/test/CodeGenHLSL/semantics/SV_Position.ps.hlsl
A clang/test/CodeGenHLSL/semantics/SV_Position.vs.hlsl
M clang/test/SemaHLSL/Semantics/position.ps.hlsl
R clang/test/SemaHLSL/Semantics/position.vs.hlsl
A llvm/test/CodeGen/SPIRV/semantics/position.ps.ll
A llvm/test/CodeGen/SPIRV/semantics/position.vs.ll
Log Message:
-----------
[HLSL][SPIR-V] Implements SV_Position for VS/PS I/O (#168735)
Current implementation for SV_Position was very basic to allow
implementing/testing some semantics. Now that semantic support is more
robust, I can move forward and implement the whole semantic logic.
DX part is still a bit placeholder.
Commit: e4cff3c687fe909a2ff291576872aa06a55277ce
https://github.com/llvm/llvm-project/commit/e4cff3c687fe909a2ff291576872aa06a55277ce
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/ScalableValueBoundsConstraintSet.cpp
Log Message:
-----------
[mlir] Avoid else after return in ScalableValueBounds (NFC) (#169211)
Commit: 65fd9f1f891bcc4bc1a27a00a45a4c1d9670ae63
https://github.com/llvm/llvm-project/commit/65fd9f1f891bcc4bc1a27a00a45a4c1d9670ae63
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/test/Transforms/Attributor/dereferenceable-1.ll
M llvm/test/Transforms/Attributor/nonnull.ll
M llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
M llvm/test/Transforms/Attributor/willreturn.ll
M llvm/test/Transforms/FunctionAttrs/nonnull.ll
Log Message:
-----------
[Attributor] Support nested conditional branches (#168532)
The attributor can infer the alignment of %p at the call-site in this
example [1]:
```
define void @f(ptr align 8 %p, i1 %c1, i1 %c2) {
entry:
br i1 %c1, label %bb.1, label %exit
bb.1:
call void (...) @llvm.fake.use(ptr %p)
br label %exit
exit:
ret void
}
```
but not when there's an additional conditional branch:
```
define void @f(ptr align 8 %p, i1 %c1, i1 %c2) {
entry:
br i1 %c1, label %bb.1, label %exit
bb.1:
br i1 %c2, label %bb.2, label %exit
bb.2:
call void (...) @llvm.fake.use(ptr %p)
br label %exit
exit:
ret void
}
```
unless `-attributor-annotate-decl-cs` is enabled. This patch extends
`followUsesInMBEC` to handle such recursive branches.
n.b. admittedly I wrote this patch before discovering inferring the
alignment in this example is already possible with
`-attributor-annotate-decl-cs`, I came to realise this once writing the
tests, but this seems like a gap regardless looking at existing FIXMEs,
plus the alignment can now be inferred in this particular example
without the flag.
[1] https://godbolt.org/z/aKoc75so5
Commit: 999deef63df5a057350a1e3bf211e536d5cfbc82
https://github.com/llvm/llvm-project/commit/999deef63df5a057350a1e3bf211e536d5cfbc82
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGExprComplex.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/test/CodeGen/promoted-complex-div.c
Log Message:
-----------
Desugar complex element types for promoted complex division (#168943)
This patch fixes a crash in Clang that occurs when the compiler
retrieves the element type of a complex type but receives a sugared
type. See example here: https://godbolt.org/z/cdbdeMcaT
This patch fixes the crash.
Commit: e5755395417ceaa9cd049e69593cb0dcc7d0e65c
https://github.com/llvm/llvm-project/commit/e5755395417ceaa9cd049e69593cb0dcc7d0e65c
Author: Jack Frankland <jack.frankland at arm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
Log Message:
-----------
[milr][memref]: Fold expand_shape + transfer_read (#167679)
Extend the load of a expand shape rewrite pattern to support folding a
`memref.expand_shape` and `vector.transfer_read` when the permutation
map on `vector.transfer_read` is a minor identity.
---------
Signed-off-by: Jack Frankland <jack.frankland at arm.com>
Commit: a27842ce0698299eed4fbe076560b8d785d50444
https://github.com/llvm/llvm-project/commit/a27842ce0698299eed4fbe076560b8d785d50444
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/test/CodeGen/X86/apx/no-rex2-general.ll
M llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll
M llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll
M llvm/test/CodeGen/X86/apx/no-rex2-special.ll
Log Message:
-----------
[X86][NFC] Add `-show-mc-encoding` to check register misuse (#169264)
Commit: d14840779bf9e4ba80e8955b0e846d112106f287
https://github.com/llvm/llvm-project/commit/d14840779bf9e4ba80e8955b0e846d112106f287
Author: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
A llvm/test/CodeGen/X86/avx512-i386-setallones-pseudo.mir
A llvm/test/CodeGen/X86/avx512-setallones-pseudo.mir
M llvm/test/CodeGen/X86/eq-or-eq-range-of-2.ll
Log Message:
-----------
[X86][AVX512] Add pseudos for `AVX512_*_SETALLONES` (#169009)
Introduce `AVX512_128_SETALLONES`, `AVX512_256_SETALLONES` pseudos to
generate all-ones vectors.
Post-RA expansion:
- Use VEX vpcmpeqd for XMM/YMM0–15 when available (matches current
codegen as `AVX512_128/256_SETALLONES` will be preferred over
`AVX1/2_SETALLONES` for AVX512VL target).
- Use EVEX `vpternlogd imm=0xFF` for high regs.
Includes MIR tests for both VEX and EVEX paths.
Commit: 83765f435d1ca1ffc29ebe0ad979bfb70a22ff70
https://github.com/llvm/llvm-project/commit/83765f435d1ca1ffc29ebe0ad979bfb70a22ff70
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu-templates.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu-templates.s.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-templates.test
M llvm/utils/update_mc_test_checks.py
Log Message:
-----------
[Utils][update_mc_test_checks] Support generating asm tests from templates. (#168946)
Reduces the pain of manual editing tests applying the same
changes over multiple instructions and keeping them consistent.
Commit: d5927a6172ab9b95f7f533bfdff865c1ce2aad5b
https://github.com/llvm/llvm-project/commit/d5927a6172ab9b95f7f533bfdff865c1ce2aad5b
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M lldb/docs/dil-expr-lang.ebnf
M lldb/include/lldb/Symbol/TypeSystem.h
M lldb/include/lldb/ValueObject/DILAST.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
M lldb/source/Symbol/CompilerType.cpp
M lldb/source/Symbol/TypeSystem.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILParser.cpp
A lldb/test/API/commands/frame/var-dil/expr/Arithmetic/Makefile
A lldb/test/API/commands/frame/var-dil/expr/Arithmetic/TestFrameVarDILArithmetic.py
A lldb/test/API/commands/frame/var-dil/expr/Arithmetic/main.cpp
A lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/Makefile
A lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/TestFrameVarDILPointerArithmetic.py
A lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/main.cpp
Log Message:
-----------
[LLDB] Add unary plus and minus to DIL (#155617)
This patch adds unary nodes plus and minus, introduces unary type
conversions, and adds integral promotion to the type system.
Commit: cd13d9f9e5af7dad1b389f70bb01854134cb9df5
https://github.com/llvm/llvm-project/commit/cd13d9f9e5af7dad1b389f70bb01854134cb9df5
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
Log Message:
-----------
[lldb] Add test showing UnwindAssemblyInstEmulation can't handle backwards branches (#168398)
If we have a conditional branch, followed by an epilogue, followed by
more code, LLDB will incorrectly compute unwind information through
instruction emulation. Consider this:
```
// ...
<+16>: b.ne ; <+52> DO_SOMETHING_AND_GOTO_AFTER_EPILOGUE
// epilogue start
<+20>: ldp x29, x30, [sp, #0x20]
<+24>: add sp, sp, #0x30
<+28>: ret
// epilogue end
AFTER_EPILOGUE:
<+32>: do something
// ...
<+48>: ret
DO_SOMETHING_AND_GOTO_AFTER_EPILOGUE:
<+52>: stp x22, x23, [sp, #0x10]
<+56>: mov x22, #0x1
<+64>: b ; <+32> AFTER_EPILOGUE
```
LLDB will think that the unwind state of +32 is the same as +28. This is
false, as +32 _never_ executes after +28.
The root cause of the problem is the order in which instructions are
visited; they are visited in the order they appear in the text, with
unwind state always being forwarded to positive branch offsets, but
never to negative offsets.
In the example above, `AFTER_EPILOGUE` should inherit the state of the
branch in +64, but it doesn't because `AFTER_EPILOGUE` is visited right
after the `ret` in +28.
Fixing this should be simple: maintain a stack of instructions to visit.
While the stack is not empty, take the next instruction on stack and
visit it.
* After visiting a non-branching instruction, push the next instruction
and forward unwind state to it.
* After visiting a branch with one or more known targets, push the known
branch targets and forward state to them.
* In all other cases (ret, or branch to register), don't push nor
forward anything.
Never push an instruction already on the stack. Like the algorithm
today, this new algorithm also assumes that, if two instructions branch
to the same target, the unwind state in both better be the same.
(Note: yes, branch to register is also handled incorrectly today, and
will still be incorrect).
Commit: 4a567e3e7c35257e47ee2fb6de61c2c4fb0d4af0
https://github.com/llvm/llvm-project/commit/4a567e3e7c35257e47ee2fb6de61c2c4fb0d4af0
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/utils/lit/examples/many-tests/ManyTests.py
Log Message:
-----------
[llvm][utils][lit] Fix imports in ManyTests.py example (#169328)
Fixes #169297
Commit: 24abb0603a5f491943d05ea3a2b6513238d9937e
https://github.com/llvm/llvm-project/commit/24abb0603a5f491943d05ea3a2b6513238d9937e
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
Log Message:
-----------
[OpenAC][CIR] func-local-declare 'copy' clause lowering (#169115)
This patch implements the lowering for the 'copy' clause for a
function-local declare directive.
This is the first of the clauses that requires a 'cleanup' step, so it
also includes some basic infrastructure for that. Fortunately there are
only 8 clauses (only 6 of which require cleanup), so the if/else chain
won't get too long.
Also fortunately, we don't have to include any of the AST components, as
it is possible to tell all the required details from the entry operation
itself.
Commit: ceea07daa8a41562fdd884a224afbac1d7346e3e
https://github.com/llvm/llvm-project/commit/ceea07daa8a41562fdd884a224afbac1d7346e3e
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/forward_list
M libcxx/test/libcxx/diagnostics/forward_list.nodiscard.verify.cpp
Log Message:
-----------
[libc++][forward_list] Applied `[[nodiscard]]` (#169019)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Commit: 456b0512c927e37640fbdb9f6627466948f64305
https://github.com/llvm/llvm-project/commit/456b0512c927e37640fbdb9f6627466948f64305
Author: Luke Lau <luke at igalia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-cond-poison.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll
Log Message:
-----------
[VPlan] Set ZeroIsPoison=false for FirstActiveLane (#169298)
When interleaving a loop with an early exit, the parts before the active
lane will be all zero. Currently we emit @llvm.experimental.cttz.elts
with ZeroIsPoison=true for these parts, which means that they will
produce poison.
We don't see any miscompiles today on AArch64 because it has the same
lowering for cttz.elts regardless of ZeroIsPoison, but this may cause
issues on RISC-V when interleaving. This fixes it by setting
ZeroIsPoison=false.
The codegen is slightly worse on RISC-V when ZeroIsPoison=false and we
could potentially recover it by enabling it again when UF=1, but this is
left to another PR.
This is split off from #168738, where LastActiveLane can get expanded to
a FirstActiveLane with an all-zeroes mask.
Commit: 1580f4b038c9945bf73d33b25459bece2f67ace7
https://github.com/llvm/llvm-project/commit/1580f4b038c9945bf73d33b25459bece2f67ace7
Author: David Green <david.green at arm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
Log Message:
-----------
[AArch64] Update costs for fshl/r and add rotr/l variants. NFC
Commit: ad0acf4af001a3781b41b572788adcd7d652d18a
https://github.com/llvm/llvm-project/commit/ad0acf4af001a3781b41b572788adcd7d652d18a
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
Log Message:
-----------
AMDGPU/GlobalISel: Combine S16 copy-trunc-readanylane-anyext (#168410)
Commit: 71952df1f52c8d54ea00a9e836184ba0ece7c6c3
https://github.com/llvm/llvm-project/commit/71952df1f52c8d54ea00a9e836184ba0ece7c6c3
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CodeGen/CGException.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
A clang/test/OpenMP/spirv_target_codegen_noexceptions.cpp
Log Message:
-----------
[OpenMP][SPIRV] Disable exceptions for OpenMP SPIR-V (#169094)
More missed target checks.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: d542dce0e6e65d8943c31fc99391572c0287128a
https://github.com/llvm/llvm-project/commit/d542dce0e6e65d8943c31fc99391572c0287128a
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/test/CIR/CodeGenOpenACC/declare-copyin.cpp
Log Message:
-----------
[OpenACC][CIR] copyin lowering for func-local- declare (#169336)
This is exactly like the 'copy', except the exit operation is a 'delete'
instead of a 'copyout'. Also, creating the 'delete' op has one less
argument to it, so we have to do some special handling when creating
that.
Commit: f4ba8e38ee0a3a2789b50d50e724fb90b1527708
https://github.com/llvm/llvm-project/commit/f4ba8e38ee0a3a2789b50d50e724fb90b1527708
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for G_FABS and G_FNEG (#168411)
Commit: 29cfef188088cb0101b3ec70b13d68c06a2d49d6
https://github.com/llvm/llvm-project/commit/29cfef188088cb0101b3ec70b13d68c06a2d49d6
Author: Mirko <mirkomueller97 at live.de>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/DebugInfo/PDB/Native/NativeSession.cpp
M llvm/unittests/DebugInfo/PDB/NativeSessionTest.cpp
Log Message:
-----------
[PDB][NativeSession] Use better error code for invalid format (#167885)
Replaces the default "Success" std::error_code with a more meaningful
one if `Magic != file_magic::pdb`.
Commit: 2bdd1357c826afe681ab0d6ddfa8fb814b2cef6a
https://github.com/llvm/llvm-project/commit/2bdd1357c826afe681ab0d6ddfa8fb814b2cef6a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/simd_utils.h
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_fallbacks.h
M libcxx/include/__locale_dir/locale_base_api/ibm.h
R libcxx/include/__locale_dir/locale_base_api/musl.h
M libcxx/include/__locale_dir/num.h
M libcxx/include/__locale_dir/support/bsd_like.h
M libcxx/include/__locale_dir/support/fuchsia.h
M libcxx/include/__locale_dir/support/linux.h
M libcxx/include/__locale_dir/support/no_locale/strtonum.h
M libcxx/include/__locale_dir/support/windows.h
M libcxx/include/__support/xlocale/__strtonum_fallback.h
M libcxx/include/module.modulemap.in
M libcxx/src/locale.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_long.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_int.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_long.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_long_long.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_short.pass.cpp
Log Message:
-----------
[libc++] Optimize num_get integral functions (#121795)
```
---------------------------------------------------
Benchmark old new
---------------------------------------------------
BM_num_get<bool> 86.5 ns 32.3 ns
BM_num_get<long> 82.1 ns 30.3 ns
BM_num_get<long long> 85.2 ns 33.4 ns
BM_num_get<unsigned short> 85.3 ns 31.2 ns
BM_num_get<unsigned int> 84.2 ns 31.1 ns
BM_num_get<unsigned long> 83.6 ns 31.9 ns
BM_num_get<unsigned long long> 87.7 ns 31.5 ns
BM_num_get<float> 116 ns 114 ns
BM_num_get<double> 114 ns 114 ns
BM_num_get<long double> 113 ns 114 ns
BM_num_get<void*> 151 ns 144 ns
```
This patch applies multiple optimizations:
- Stages two and three of do_get are merged and a custom integer parser
has been implemented
This avoids allocations, removes the need for strto{,u}ll and avoids
__stage2_int_loop (avoiding extra writes to memory)
- std::find has been replaced with __atoms_offset, which uses vector
instructions to look for a character
Fixes #158100
Fixes #158102
Commit: bb78728826ff57f3df859e79bfd857b5a175bb6d
https://github.com/llvm/llvm-project/commit/bb78728826ff57f3df859e79bfd857b5a175bb6d
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
A llvm/test/CodeGen/AArch64/pr151592.mir
A llvm/test/CodeGen/AArch64/pr151888.mir
A llvm/test/CodeGen/AArch64/pr164181-reduced.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
A llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
M llvm/test/CodeGen/PowerPC/combine-fneg.ll
M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
M llvm/test/CodeGen/PowerPC/frem.ll
M llvm/test/CodeGen/PowerPC/froundeven-legalization.ll
M llvm/test/CodeGen/PowerPC/half.ll
M llvm/test/CodeGen/PowerPC/ldexp.ll
M llvm/test/CodeGen/PowerPC/llvm.modf.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
A llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
A llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
A llvm/test/CodeGen/X86/pr76416.ll
M llvm/test/CodeGen/X86/subreg-fail.mir
A llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
Log Message:
-----------
Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG"
A SUBREG_TO_REG instruction expresses that the top bits of the result
register are set to a certain value (e.g. 0).
The example below expresses that the result of %1 will have the top 32
bits zeroed and the lower 32bits being equal to the result of INSTR.
```
%0:gpr32 = INSTR
%1:gpr64 = SUBREG_TO_REG 0, %0, sub32
```
When the RegisterCoalescer tries to remove SUBREG_TO_REG instructions by
coalescing %0 into %1, it must keep the same semantics. Currently
however, the RegisterCoalescer would emit:
```
%1.sub32:gpr64 = INSTR
```
which no longer expresses that the top 32-bits of the register are
defined (zeroed) by INSTR.
This may cause issues with e.g. machine copy propagation where the pass
may think it can remove a COPY-like instruction because the MIR says
only the bottom 32-bits are defined/used, even though other uses of the
register rely on the top 32-bits being zeroed by the COPY-like
instruction.
This PR changes the RegisterCoalescer to instead emit:
```
undef %1.sub32:gpr64 = MOVimm32 42, implicit-def %1
```
to express that the entire contents of %1:gpr64 are defined by the
instruction.
This tries to reland #134408 which had to be reverted due to a few reported
failures.
Commit: ccd2c3e3202d25f39775a39d1565522481a14565
https://github.com/llvm/llvm-project/commit/ccd2c3e3202d25f39775a39d1565522481a14565
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/utils/ci/buildkite-pipeline.yml
Log Message:
-----------
Revert "[libcxx][ci] Temporarily disable ARM jobs" (#169352)
Reverts llvm/llvm-project#169318
Our builders are back online. I see them picking up existing jobs.
Commit: e442c67a2c98a3e1e3bfcf90aaa82ba70fb92760
https://github.com/llvm/llvm-project/commit/e442c67a2c98a3e1e3bfcf90aaa82ba70fb92760
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang-tools-extra/clangd/SemanticSelection.cpp
Log Message:
-----------
[clangd] Fix C++20 build failure
Commit: dc39fa34c3e27650bd111357d77247592b14baef
https://github.com/llvm/llvm-project/commit/dc39fa34c3e27650bd111357d77247592b14baef
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
A clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
Log Message:
-----------
[OpenACC][CIR] copyout clause lowering on func-local declare (#169350)
This is identical to 'copy' and 'copyin', except it uses 'create' and
'copyout' as its entry/exit op. This patch adds the same tests, and
similar code for all of it.
Commit: 870f581f702e6bb85c59670492c9998aacc3dacf
https://github.com/llvm/llvm-project/commit/870f581f702e6bb85c59670492c9998aacc3dacf
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M libcxx/include/__config
M libcxx/test/std/depr/depr.cpp.headers/ccomplex.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/ciso646.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/cstdalign.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/cstdbool.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/ctgmath.verify.cpp
Log Message:
-----------
[libc++] Disable header deprecations until #168041 is landed (#169305)
The `#warning` causes diagnostics if system headers include deprecated
headers. #168041 will add a way to deprecated headers properly, which
then also interacts nicely with system header suppression.
Commit: ab7145231b9d6a87d528a344456a77793c75614d
https://github.com/llvm/llvm-project/commit/ab7145231b9d6a87d528a344456a77793c75614d
Author: Marco Elver <elver at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M llvm/lib/Support/AllocToken.cpp
Log Message:
-----------
[Support] Permit "default" string in AllocToken mode parsing (#169351)
Update getAllocTokenModeFromString() to recognize "default" as a valid
mode string, mapping it to `DefaultAllocTokenMode`.
Commit: d49d06989eb05d1309dedffa35a37a5edf52c5f4
https://github.com/llvm/llvm-project/commit/d49d06989eb05d1309dedffa35a37a5edf52c5f4
Author: Marco Elver <elver at google.com>
Date: 2025-11-24 (Mon, 24 Nov 2025)
Changed paths:
M clang-tools-extra/clang-tidy/objc/AssertEqualsCheck.cpp
M clang-tools-extra/clangd/SemanticSelection.cpp
M clang-tools-extra/clangd/unittests/SemanticSelectionTests.cpp
M clang/docs/LibASTMatchersReference.html
M clang/include/clang/AST/ASTImporter.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/BuiltinsLoongArchLASX.def
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
M clang/lib/CodeGen/CGException.cpp
M clang/lib/CodeGen/CGExprComplex.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Headers/lasxintrin.h
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/lib/StaticAnalyzer/Core/SarifDiagnostics.cpp
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/intap.cpp
A clang/test/AST/HLSL/semantic-input-struct-shadow.hlsl
A clang/test/AST/HLSL/semantic-input-struct.hlsl
A clang/test/AST/HLSL/semantic-input.hlsl
A clang/test/AST/HLSL/semantic-output-struct-shadow.hlsl
A clang/test/AST/HLSL/semantic-output-struct.hlsl
A clang/test/AST/HLSL/semantic-output.hlsl
M clang/test/Analysis/stackaddrleak.c
A clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
A clang/test/CIR/CodeGenOpenACC/declare-copyin.cpp
A clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
M clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
M clang/test/CodeGen/LoongArch/lasx/builtin.c
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/promoted-complex-div.c
M clang/test/CodeGenHLSL/semantics/SV_Position.ps.hlsl
A clang/test/CodeGenHLSL/semantics/SV_Position.vs.hlsl
A clang/test/CodeGenOpenCL/__bf16.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M clang/test/OpenMP/parallel_default_variableCategory_codegen.cpp
A clang/test/OpenMP/spirv_target_codegen_noexceptions.cpp
M clang/test/Preprocessor/init-loongarch.c
M clang/test/SemaHLSL/Semantics/position.ps.hlsl
R clang/test/SemaHLSL/Semantics/position.vs.hlsl
M clang/test/SemaSYCL/bf16.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
M clang/unittests/Format/FormatTest.cpp
M compiler-rt/cmake/builtin-config-ix.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/all_of.h
M libcxx/include/__algorithm/none_of.h
M libcxx/include/__algorithm/simd_utils.h
M libcxx/include/__config
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_fallbacks.h
M libcxx/include/__locale_dir/locale_base_api/ibm.h
R libcxx/include/__locale_dir/locale_base_api/musl.h
M libcxx/include/__locale_dir/num.h
M libcxx/include/__locale_dir/support/bsd_like.h
M libcxx/include/__locale_dir/support/fuchsia.h
M libcxx/include/__locale_dir/support/linux.h
M libcxx/include/__locale_dir/support/no_locale/strtonum.h
M libcxx/include/__locale_dir/support/windows.h
M libcxx/include/__support/xlocale/__strtonum_fallback.h
M libcxx/include/array
M libcxx/include/forward_list
M libcxx/include/list
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/src/locale.cpp
M libcxx/test/libcxx/diagnostics/array.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/forward_list.nodiscard.verify.cpp
M libcxx/test/libcxx/diagnostics/list.nodiscard.verify.cpp
A libcxx/test/std/algorithms/robust_against_nonbool.compile.pass.cpp
M libcxx/test/std/containers/sequences/array/array.creation/to_array.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/ccomplex.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/ciso646.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/cstdalign.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/cstdbool.verify.cpp
M libcxx/test/std/depr/depr.cpp.headers/ctgmath.verify.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_long.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_int.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_long.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_long_long.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_unsigned_short.pass.cpp
M lldb/docs/dil-expr-lang.ebnf
M lldb/include/lldb/Symbol/TypeSystem.h
M lldb/include/lldb/Target/UnixSignals.h
M lldb/include/lldb/ValueObject/DILAST.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
M lldb/source/Symbol/CompilerType.cpp
M lldb/source/Symbol/TypeSystem.cpp
M lldb/source/Target/UnixSignals.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILParser.cpp
A lldb/test/API/commands/frame/var-dil/expr/Arithmetic/Makefile
A lldb/test/API/commands/frame/var-dil/expr/Arithmetic/TestFrameVarDILArithmetic.py
A lldb/test/API/commands/frame/var-dil/expr/Arithmetic/main.cpp
A lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/Makefile
A lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/TestFrameVarDILPointerArithmetic.py
A lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/main.cpp
M lldb/unittests/Expression/DWARFExpressionTest.cpp
M lldb/unittests/Signals/UnixSignalsTest.cpp
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
M llvm/Maintainers.md
M llvm/docs/LangRef.rst
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CAS/OnDiskGraphDB.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/DebugInfo/PDB/Native/NativeSession.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/Support/AllocToken.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanSLP.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
M llvm/test/CodeGen/AArch64/machine-sink-kill-flags.ll
A llvm/test/CodeGen/AArch64/pr151592.mir
A llvm/test/CodeGen/AArch64/pr151888.mir
A llvm/test/CodeGen/AArch64/pr164181-reduced.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
A llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/AArch64/sve-bf16-arith.ll
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
A llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/CodeGen/Hexagon/swp-stages5.ll
M llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
M llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll
M llvm/test/CodeGen/NVPTX/atomics-b128.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
M llvm/test/CodeGen/PowerPC/combine-fneg.ll
M llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll
M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
M llvm/test/CodeGen/PowerPC/frem.ll
M llvm/test/CodeGen/PowerPC/froundeven-legalization.ll
M llvm/test/CodeGen/PowerPC/half.ll
M llvm/test/CodeGen/PowerPC/ldexp.ll
M llvm/test/CodeGen/PowerPC/licm-xxsplti.ll
M llvm/test/CodeGen/PowerPC/llvm.modf.ll
M llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
M llvm/test/CodeGen/PowerPC/sink-side-effect.ll
M llvm/test/CodeGen/PowerPC/sms-phi-1.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/CodeGen/RISCV/remat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vector-splice.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/remat.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
A llvm/test/CodeGen/SPIRV/semantics/position.ps.ll
A llvm/test/CodeGen/SPIRV/semantics/position.vs.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-reduct.ll
M llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
M llvm/test/CodeGen/WebAssembly/simd-shift-in-loop.ll
M llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
M llvm/test/CodeGen/X86/apx/no-rex2-general.ll
M llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll
M llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll
M llvm/test/CodeGen/X86/apx/no-rex2-special.ll
A llvm/test/CodeGen/X86/avx512-i386-setallones-pseudo.mir
A llvm/test/CodeGen/X86/avx512-setallones-pseudo.mir
A llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
A llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
M llvm/test/CodeGen/X86/eq-or-eq-range-of-2.ll
M llvm/test/CodeGen/X86/i128-mul.ll
M llvm/test/CodeGen/X86/loop-strength-reduce5.ll
M llvm/test/CodeGen/X86/madd.ll
M llvm/test/CodeGen/X86/pr49451.ll
A llvm/test/CodeGen/X86/pr76416.ll
M llvm/test/CodeGen/X86/subreg-fail.mir
A llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
M llvm/test/CodeGen/X86/xor.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
M llvm/test/Transforms/Attributor/dereferenceable-1.ll
M llvm/test/Transforms/Attributor/nonnull.ll
M llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
M llvm/test/Transforms/Attributor/willreturn.ll
M llvm/test/Transforms/FunctionAttrs/nonnull.ll
A llvm/test/Transforms/GlobalOpt/X86/apx.ll
M llvm/test/Transforms/InstCombine/scalarization.ll
M llvm/test/Transforms/LoopUnroll/partial-unroll-reductions.ll
M llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-cond-poison.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu-templates.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu-templates.s.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-templates.test
M llvm/unittests/DebugInfo/PDB/NativeSessionTest.cpp
M llvm/unittests/ExecutionEngine/Orc/WaitingOnGraphTest.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/gn/secondary/llvm/lib/Target/LoongArch/BUILD.gn
M llvm/utils/lit/examples/many-tests/ManyTests.py
M llvm/utils/update_mc_test_checks.py
M mlir/include/mlir/Dialect/X86Vector/CMakeLists.txt
A mlir/include/mlir/Dialect/X86Vector/TransformOps/CMakeLists.txt
A mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.h
A mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
M mlir/include/mlir/Dialect/X86Vector/Transforms.h
M mlir/include/mlir/Pass/Pass.h
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/lib/Dialect/IRDL/IRDLLoading.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/Vector/IR/ScalableValueBoundsConstraintSet.cpp
M mlir/lib/Dialect/X86Vector/CMakeLists.txt
A mlir/lib/Dialect/X86Vector/TransformOps/CMakeLists.txt
A mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
M mlir/lib/Dialect/X86Vector/Transforms/CMakeLists.txt
A mlir/lib/Dialect/X86Vector/Transforms/VectorContractToFMA.cpp
A mlir/lib/Dialect/X86Vector/Transforms/VectorContractToPackedTypeDotProduct.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/lib/Pass/Pass.cpp
M mlir/lib/RegisterAllExtensions.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
M mlir/test/Dialect/IRDL/variadics.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/Transform/test-pass-application.mlir
A mlir/test/Dialect/X86Vector/vector-contract-to-fma.mlir
A mlir/test/Dialect/X86Vector/vector-contract-to-packed-type-dotproduct.mlir
A mlir/test/Pass/invalid-unsupported-operation.mlir
M mlir/test/Pass/pipeline-invalid.mlir
M orc-rt/include/orc-rt/WrapperFunction.h
M orc-rt/unittests/DirectCaller.h
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
rebase
Created using spr 1.3.8-beta.1
Compare: https://github.com/llvm/llvm-project/compare/ca9a341ab49d...d49d06989eb0
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