[all-commits] [llvm/llvm-project] e4a4bb: [PowerPC] Replace vspltisw+vadduwm instructions wi...

[Himadhith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e4a4bb0f6d3b3b9f3ccba79202a9074415b7dd71
      https://github.com/llvm/llvm-project/commit/e4a4bb0f6d3b3b9f3ccba79202a9074415b7dd71
  Author: Himadhith <79003240+Himadhith at users.noreply.github.com>
  Date:   2025-11-21 (Fri, 21 Nov 2025)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/test/CodeGen/PowerPC/addition-vector-all-ones.ll
    M llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll

  Log Message:
  -----------
  [PowerPC] Replace vspltisw+vadduwm instructions with xxleqv+vsubuwm for adding the vector {1, 1, 1, 1} (#160882)

This patch optimizes vector addition operations involving **`all-ones`**
vectors by leveraging the generation of vectors of -1s(using `xxleqv`,
which is cheaper than generating vectors of 1s(`vspltisw`). These are
the respective vector types.
`v2i64`: **`A + vector {1, 1}`**
`v4i32`: **`A + vector {1, 1, 1, 1}`**
`v8i16`: **`A + vector {1, 1, 1, 1, 1, 1, 1, 1}`**
`v16i8`: **`A + vector {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1}`**

The optimized version replaces `vspltisw (4 cycles)` with `xxleqv (2
cycles)` using the following identity:
`A - (-1) = A + 1`.

---------

Co-authored-by: himadhith <himadhith.v at ibm.com>
Co-authored-by: Tony Varghese <tonypalampalliyil at gmail.com>



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