[all-commits] [llvm/llvm-project] 645e0d: [llvm][RISCV] Implement Zilsd load/store pair opti...

[Brandon Wu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 645e0dcbff33248bd2cdc4ac258420de9b5936b1
      https://github.com/llvm/llvm-project/commit/645e0dcbff33248bd2cdc4ac258420de9b5936b1
  Author: Brandon Wu <songwu0813 at gmail.com>
  Date:   2025-11-21 (Fri, 21 Nov 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/CMakeLists.txt
    M llvm/lib/Target/RISCV/RISCV.h
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td
    M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    A llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/features-info.ll
    A llvm/test/CodeGen/RISCV/zilsd-ldst-opt-postra.mir
    A llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir
    A llvm/test/CodeGen/RISCV/zilsd-regalloc-hints.mir

  Log Message:
  -----------
  [llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)

This commit implements a complete load/store optimization pass for the
RISC-V Zilsd extension, which combines pairs of 32-bit load/store
instructions into single 64-bit LD/SD instructions when possible.
Default alignment is 8, it also provide zilsd-4byte-align feature for
looser condition.

Related work: https://reviews.llvm.org/D144002

---------

Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>



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