[all-commits] [llvm/llvm-project] fbc093: [RISCV] Only add v2i32 to GPR regclass in the RV64...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fbc093588f654ba771dfc055687676edf4d76884
      https://github.com/llvm/llvm-project/commit/fbc093588f654ba771dfc055687676edf4d76884
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-11-20 (Thu, 20 Nov 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Only add v2i32 to GPR regclass in the RV64 hardware mode. (#168930)

Removes about 200 bytes of unneeded patterns from RISCVGenDAGISel.inc



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