[all-commits] [llvm/llvm-project] b8059e: [X86] Avoid extra (PMADDUBSW(X, AND(Y)) in <X x i8>...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b8059e757fb95b1d3cd9b657e540bf2cd47dad82
      https://github.com/llvm/llvm-project/commit/b8059e757fb95b1d3cd9b657e540bf2cd47dad82
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-11-16 (Sun, 16 Nov 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/avx2-arith.ll
    M llvm/test/CodeGen/X86/combine-mul.ll
    M llvm/test/CodeGen/X86/gfni-shifts.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
    M llvm/test/CodeGen/X86/min-legal-vector-width.ll
    M llvm/test/CodeGen/X86/pmul.ll
    M llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll
    M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/X86/vector-fshr-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-512.ll
    M llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
    M llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
    M llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
    M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
    M llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
    M llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
    M llvm/test/CodeGen/X86/vector-mul.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-512.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll

  Log Message:
  -----------
  [X86] Avoid extra (PMADDUBSW(X,AND(Y)) in <X x i8> multiplication (#168262)

On SSSE3 targets we use PMADDUBSW of odd/even with suitable masking to
avoid having to extend/truncate with `<X x i16>` types and avoid
additional Port0/5 pressure.

However, lower i8 elements in the pair can safely use PMULLW directly
without any pre-masking as we will only use the lower i8 bits of the
result which is only affected by the lower i8 of the inputs.



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