[all-commits] [llvm/llvm-project] 7b12a0: [AArch64] Allow peephole to optimize AND + signed ...

[AZero13 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7b12a08f5e0d5e615dee2b62f9a68a03e68b6c93
      https://github.com/llvm/llvm-project/commit/7b12a08f5e0d5e615dee2b62f9a68a03e68b6c93
  Author: AZero13 <gfunni234 at gmail.com>
  Date:   2025-11-10 (Mon, 10 Nov 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    A llvm/test/CodeGen/AArch64/arm64-regress-opt-cmp-signed.mir
    M llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll

  Log Message:
  -----------
  [AArch64] Allow peephole to optimize AND + signed compare with 0 (#153608)

This should be the peephole's job. Because and sets V flag to 0, this is
why signed comparisons with 0 are okay to replace with tst. Note this is
only for AArch64, because ANDS on ARM leaves the V flag the same.

Fixes: https://github.com/llvm/llvm-project/issues/154387



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