[all-commits] [llvm/llvm-project] 16c1de: [AMDGPU] Verify dominance when rewriting spills to...

[Austin Kerbow via All-commits]

  Branch: refs/heads/users/kerbowa/rewrite-agpr-copy-crash
  Home:   https://github.com/llvm/llvm-project
  Commit: 16c1de0b058f6e28081e1f82f88e3998228d2ab5
      https://github.com/llvm/llvm-project/commit/16c1de0b058f6e28081e1f82f88e3998228d2ab5
  Author: Austin Kerbow <Austin.Kerbow at amd.com>
  Date:   2025-11-10 (Mon, 10 Nov 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
    A llvm/test/CodeGen/AMDGPU/rewrite-agpr-spill-multi-store-crash.ll

  Log Message:
  -----------
  [AMDGPU] Verify dominance when rewriting spills to registers

When performing spill elimination in the AGPR copy rewrite pass it was
possible to see spill reloads that were not dominated by any store. This
caused invalid MIR to be generated where vreg uses were not dominated by
defs. This patch adds a dominance check before rewriting spills.



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