[all-commits] [llvm/llvm-project] 1fd49d: [SelectionDAG] Fix bug related to demanded bits/el...

Mon Nov 10 03:57:58 PST 2025

  Branch: refs/heads/users/bjope/demandedbits_bitcast_1
  Home:   https://github.com/llvm/llvm-project
  Commit: 1fd49d8f7f4c28b28985e5443f455a3bbadfef39
      https://github.com/llvm/llvm-project/commit/1fd49d8f7f4c28b28985e5443f455a3bbadfef39
  Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2025-11-10 (Mon, 10 Nov 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/reduce-or.ll
    M llvm/test/CodeGen/AArch64/reduce-xor.ll
    M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
    M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
    M llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
    M llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll
    M llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
    M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
    M llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
    M llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
    M llvm/test/CodeGen/X86/avx512fp16-mov.ll
    M llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
    M llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
    M llvm/test/CodeGen/X86/bitcast-and-setcc-128.ll
    M llvm/test/CodeGen/X86/bitcast-setcc-128.ll
    M llvm/test/CodeGen/X86/bitcast-setcc-512.ll
    M llvm/test/CodeGen/X86/bitcast-vector-bool.ll
    M llvm/test/CodeGen/X86/buildvec-widen-dotproduct.ll
    M llvm/test/CodeGen/X86/combine-multiplies.ll
    M llvm/test/CodeGen/X86/combine-pmuldq.ll
    M llvm/test/CodeGen/X86/combine-rotates.ll
    M llvm/test/CodeGen/X86/combine-sdiv.ll
    M llvm/test/CodeGen/X86/combine-shl.ll
    M llvm/test/CodeGen/X86/combine-sra.ll
    M llvm/test/CodeGen/X86/combine-storetomstore.ll
    M llvm/test/CodeGen/X86/combine-udiv.ll
    M llvm/test/CodeGen/X86/dagcombine-shifts.ll
    M llvm/test/CodeGen/X86/f16c-intrinsics-fast-isel.ll
    M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
    M llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
    M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/X86/funnel-shift.ll
    M llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
    M llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
    M llvm/test/CodeGen/X86/ifma-combine-vpmadd52.ll
    M llvm/test/CodeGen/X86/known-never-zero.ll
    M llvm/test/CodeGen/X86/known-pow2.ll
    M llvm/test/CodeGen/X86/known-signbits-shl.ll
    M llvm/test/CodeGen/X86/known-signbits-vector.ll
    M llvm/test/CodeGen/X86/madd.ll
    M llvm/test/CodeGen/X86/masked_store.ll
    M llvm/test/CodeGen/X86/movmsk-cmp.ll
    M llvm/test/CodeGen/X86/mulvi32.ll
    M llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
    M llvm/test/CodeGen/X86/pmul.ll
    M llvm/test/CodeGen/X86/pmulh.ll
    M llvm/test/CodeGen/X86/pr107423.ll
    M llvm/test/CodeGen/X86/pr35918.ll
    M llvm/test/CodeGen/X86/pr41619.ll
    M llvm/test/CodeGen/X86/pr42727.ll
    M llvm/test/CodeGen/X86/pr45563-2.ll
    M llvm/test/CodeGen/X86/pr45833.ll
    M llvm/test/CodeGen/X86/pr77459.ll
    M llvm/test/CodeGen/X86/promote-cmp.ll
    M llvm/test/CodeGen/X86/promote-vec3.ll
    M llvm/test/CodeGen/X86/psubus.ll
    M llvm/test/CodeGen/X86/rotate-extract-vector.ll
    M llvm/test/CodeGen/X86/sadd_sat_vec.ll
    M llvm/test/CodeGen/X86/sat-add.ll
    M llvm/test/CodeGen/X86/sdiv-exact.ll
    M llvm/test/CodeGen/X86/shrink_vmul.ll
    M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/X86/sshl_sat_vec.ll
    M llvm/test/CodeGen/X86/ssub_sat_vec.ll
    M llvm/test/CodeGen/X86/test-shrink-bug.ll
    M llvm/test/CodeGen/X86/ucmp.ll
    M llvm/test/CodeGen/X86/udiv-exact.ll
    M llvm/test/CodeGen/X86/undo-mul-and.ll
    M llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll
    M llvm/test/CodeGen/X86/ushl_sat_vec.ll
    M llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll
    M llvm/test/CodeGen/X86/vec_int_to_fp.ll
    M llvm/test/CodeGen/X86/vec_minmax_sint.ll
    M llvm/test/CodeGen/X86/vec_minmax_uint.ll
    M llvm/test/CodeGen/X86/vec_smulo.ll
    M llvm/test/CodeGen/X86/vec_umulo.ll
    M llvm/test/CodeGen/X86/vector-compare-all_of.ll
    M llvm/test/CodeGen/X86/vector-compare-any_of.ll
    M llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
    M llvm/test/CodeGen/X86/vector-fshl-128.ll
    M llvm/test/CodeGen/X86/vector-fshl-256.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
    M llvm/test/CodeGen/X86/vector-fshl-sub128.ll
    M llvm/test/CodeGen/X86/vector-fshr-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
    M llvm/test/CodeGen/X86/vector-mul.ll
    M llvm/test/CodeGen/X86/vector-pcmp.ll
    M llvm/test/CodeGen/X86/vector-reduce-fmaximum.ll
    M llvm/test/CodeGen/X86/vector-reduce-mul.ll
    M llvm/test/CodeGen/X86/vector-reduce-smax.ll
    M llvm/test/CodeGen/X86/vector-reduce-smin.ll
    M llvm/test/CodeGen/X86/vector-reduce-umax.ll
    M llvm/test/CodeGen/X86/vector-reduce-umin.ll
    M llvm/test/CodeGen/X86/vector-rotate-128.ll
    M llvm/test/CodeGen/X86/vector-rotate-256.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
    M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
    M llvm/test/CodeGen/X86/vector-trunc-math.ll
    M llvm/test/CodeGen/X86/vector-trunc-packus.ll
    M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
    M llvm/test/CodeGen/X86/vector-trunc-usat.ll
    M llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
    M llvm/test/CodeGen/X86/vselect.ll

  Log Message:
  -----------
  [SelectionDAG] Fix bug related to demanded bits/elts for BITCAST

When we have a BITCAST and the source type is a vector with smaller
elements compared to the destination type, then we need to demand
all the source elements that make up the demanded elts for the
result when doing recursive calls to SimplifyDemandedBits,
SimplifyDemandedVectorElts and SimplifyMultipleUseDemandedBits.
Problem is that those simplifications are allowed to turn non-demanded
elements of a vector into POISON, so unless we demand all source
elements that make up the result there is a risk that the result
would be more poisonous (even for demanded elts) after the
simplification.

The patch fixes some bugs in SimplifyMultipleUseDemandedBits and
SimplifyDemandedBits for situations when we did not consider the
problem described above. Now we make sure that we also demand vector
elements that "must not be turned into poison" even if those elements
correspond to bits that does not need to be defined according to
the DemandedBits mask.

Fixes #138513

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