[all-commits] [llvm/llvm-project] 324115: [AArch64][SVE] Avoid movprfx by reusing register f...

[Sander de Smalen via All-commits]

  Branch: refs/heads/users/sdesmalen-arm/avoid-movprfx-with-predicated-undef-pseudos
  Home:   https://github.com/llvm/llvm-project
  Commit: 3241156fa8ac76a46cc555ba5def32720429e06c
      https://github.com/llvm/llvm-project/commit/3241156fa8ac76a46cc555ba5def32720429e06c
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2025-11-07 (Fri, 07 Nov 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-abd.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
    M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
    M llvm/test/CodeGen/AArch64/sve2-xar.ll

  Log Message:
  -----------
  [AArch64][SVE] Avoid movprfx by reusing register for _UNDEF pseudos.

For predicated SVE instructions where we know that the inactive
lanes are undef, it is better to pick a destination register that
is not unique. This avoids introducing a movprfx to copy a unique
register to the destination operand, which would be needed to comply
with the tied operand constraints.

For example:

  %src1 = COPY $z1
  %src2 = COPY $z2
  %dst = SDIV_ZPZZ_S_UNDEF %p, %src1, %src2

Here it is beneficial to pick $z1 or $z2 as the destination register,
because if it would have chosen a unique register (e.g. $z0) then
the pseudo expand pass would need to insert a MOVPRFX to expand
the operation into:

  $z0 = SDIV_ZPZZ_S_UNDEF $p0, $z1, $z2

  ->

  $z0 = MOVPRFX $z1
  $z0 = SDIV_ZPmZ_S $p0, $z0, $z2

By picking $z1 directly, we'd get:

  $z1 = SDIV_ZPmZ_S, $p0 $z1, $z2



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