[all-commits] [llvm/llvm-project] 19a683: [LLVM][ARM] Add native ct.select support for ARM32...

[Julius Alexandre via All-commits]

  Branch: refs/heads/users/wizardengineer/ct-select-arm
  Home:   https://github.com/llvm/llvm-project
  Commit: 19a683ea275b7a93065c4d171c1c931f85594296
      https://github.com/llvm/llvm-project/commit/19a683ea275b7a93065c4d171c1c931f85594296
  Author: wizardengineer <juliuswoosebert at gmail.com>
  Date:   2025-11-05 (Wed, 05 Nov 2025)

  Changed paths:
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMTargetMachine.cpp
    A llvm/test/CodeGen/ARM/ctselect-half.ll
    A llvm/test/CodeGen/ARM/ctselect-vector.ll
    A llvm/test/CodeGen/ARM/ctselect.ll

  Log Message:
  -----------
  [LLVM][ARM] Add native ct.select support for ARM32 and Thumb

This patch implements architecture-specific lowering for ct.select on ARM
(both ARM32 and Thumb modes) using conditional move instructions and
bitwise operations for constant-time selection.

Implementation details:
- Uses pseudo-instructions that are expanded Post-RA to bitwise operations
- Post-RA expansion in ARMBaseInstrInfo for BUNDLE pseudo-instructions
- Handles scalar integer types, floating-point, and half-precision types
- Handles vector types with NEON when available
- Support for both ARM and Thumb instruction sets (Thumb1 and Thumb2)
- Special handling for Thumb1 which lacks conditional execution
- Comprehensive test coverage including half-precision and vectors

The implementation includes:
- ISelLowering: Custom lowering to CTSELECT pseudo-instructions
- ISelDAGToDAG: Selection of appropriate pseudo-instructions
- BaseInstrInfo: Post-RA expansion of BUNDLE to bitwise instruction sequences
- InstrInfo.td: Pseudo-instruction definitions for different types
- TargetMachine: Registration of Post-RA expansion pass
- Proper handling of condition codes and register allocation constraints



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