[all-commits] [llvm/llvm-project] 43177b: [clang-format] Recognize Verilog followed-by opera...

[sstwcw via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 43177bf777f6a44c058277e9b504687bdc0370cc
      https://github.com/llvm/llvm-project/commit/43177bf777f6a44c058277e9b504687bdc0370cc
  Author: sstwcw <su3e8a96kzlver at posteo.net>
  Date:   2025-11-03 (Mon, 03 Nov 2025)

  Changed paths:
    M clang/lib/Format/FormatTokenLexer.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp

  Log Message:
  -----------
  [clang-format] Recognize Verilog followed-by operators (#165594)

When formatting Verilog code, the program changes the hash to
`kw_verilogHash` and the backtick to `tok::hash`. The developer did not
take that into account when writing the part for recognizing the `#-#`
and `#=#` operators. The part did not work. The program would add a
space within the operator.

after

```SystemVerilog
##[0 : 5] done #-# always !rst;
```

before

```SystemVerilog
##[0 : 5] done #- #always !rst;
```



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications