[all-commits] [llvm/llvm-project] 24af13: CodeGen: Remove TRI argument from getRegClass

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/codgen/remove-tri-argument-getRegClass
  Home:   https://github.com/llvm/llvm-project
  Commit: 24af138c9bae7002f7df7c51d59d1da71d483bac
      https://github.com/llvm/llvm-project/commit/24af138c9bae7002f7df7c51d59d1da71d483bac
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-10-30 (Thu, 30 Oct 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
    M llvm/lib/CodeGen/BreakFalseDeps.cpp
    M llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
    M llvm/lib/CodeGen/GlobalISel/Utils.cpp
    M llvm/lib/CodeGen/InitUndef.cpp
    M llvm/lib/CodeGen/MachineInstr.cpp
    M llvm/lib/CodeGen/MachineLICM.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
    M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    M llvm/lib/CodeGen/TargetInstrInfo.cpp
    M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
    M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
    M llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    M llvm/lib/Target/ARM/ARMFrameLowering.cpp
    M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    M llvm/lib/Target/ARM/MLxExpansionPass.cpp
    M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
    M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp
    M llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
    M llvm/lib/Target/LoongArch/LoongArchDeadRegisterDefinitions.cpp
    M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    M llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp
    M llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
    M llvm/lib/Target/X86/X86DomainReassignment.cpp
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstrInfo.h
    M llvm/lib/Target/X86/X86OptimizeLEAs.cpp
    M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

  Log Message:
  -----------
  CodeGen: Remove TRI argument from getRegClass

TargetInstrInfo now directly holds a reference to TargetRegisterInfo
and does not need TRI passed in anywhere.



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