[all-commits] [llvm/llvm-project] 53e744: [LSR] Don't count conditional loads/store as enabl...

[John Brawn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 53e7443e0c0db82fa82d7b9009bbc5cdac1c9fac
      https://github.com/llvm/llvm-project/commit/53e7443e0c0db82fa82d7b9009bbc5cdac1c9fac
  Author: John Brawn <john.brawn at arm.com>
  Date:   2025-10-30 (Thu, 30 Oct 2025)

  Changed paths:
    M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/minloop.ll
    M llvm/test/Transforms/LoopStrengthReduce/AArch64/prefer-all.ll

  Log Message:
  -----------
  [LSR] Don't count conditional loads/store as enabling pre/post-index (#159573)

When a load/store is conditionally executed in a loop it isn't a
candidate for pre/post-index addressing, as the increment of the address
would only happen on those loop iterations where the load/store is
executed.

Detect this and only discount the AddRec cost when the load/store is
unconditional.



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