[all-commits] [llvm/llvm-project] e68cf1: [GitHub][CI] Remove 'Set Safe Directory' step (#16...
Maksim Levental via All-commits
all-commits at lists.llvm.org
Sat Oct 25 11:01:55 PDT 2025
Branch: refs/heads/users/makslevental/fix-getOwner
Home: https://github.com/llvm/llvm-project
Commit: e68cf1ebcf8a059ea5f373340a854c15146a20dd
https://github.com/llvm/llvm-project/commit/e68cf1ebcf8a059ea5f373340a854c15146a20dd
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M .github/workflows/pr-code-format.yml
M .github/workflows/pr-code-lint.yml
Log Message:
-----------
[GitHub][CI] Remove 'Set Safe Directory' step (#165052)
Commit: 409c6544435395ac24d3efb92fd51841e9223315
https://github.com/llvm/llvm-project/commit/409c6544435395ac24d3efb92fd51841e9223315
Author: cmtice <cmtice at google.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M .ci/monolithic-windows.sh
Log Message:
-----------
[CI] Update Windows premerge testing to use clang-cl.exe (#164900)
Now that the Windows container contains clang, use it for building the
premerge tests. Measurements show this is significantly faster than
using msvc cl. Note we had to disable four warnings -Wc++98-compat,
-Wc++14-compat, -Wunsafe-buffer-usage, and -Wold-style-cast to make
this work with 'check-mlir' on Windows (clang generates a lot of warnings
that msvc cl does not).
Commit: 10a975be0f4c6337fe981c4086d90c582a970010
https://github.com/llvm/llvm-project/commit/10a975be0f4c6337fe981c4086d90c582a970010
Author: Julian Lettner <yln at users.noreply.github.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M lldb/include/lldb/Target/Target.h
M lldb/source/Commands/CommandCompletions.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Commands/Options.td
M lldb/source/Target/Target.cpp
A lldb/test/Shell/ExecControl/StopHook/stop-hook-list.test
Log Message:
-----------
[lldb] Introduce internal stop hooks (#164506)
Introduce the concept of internal stop hooks.
These are similar to LLDB's internal breakpoints:
LLDB itself will add them and users of LLDB will
not be able to add or remove them.
This change adds the following 3
independently-useful concepts:
* Maintain a list of internal stop hooks that will be populated by LLDB
and cannot be added to or removed from by users. They are managed in a
separate list in `Target::m_internal_stop_hooks`.
* `StopHookKind:CodeBased` and `StopHookCoded` represent a stop hook
defined by a C++ code callback (instead of command line expressions or a
Python class).
* Stop hooks that do not print any output can now also suppress the
printing of their header and description when they are hit via
`StopHook::GetSuppressOutput`.
Combining these 3 concepts we can model "internal
stop hooks" which serve the same function as
LLDB's internal breakpoints: executing built-in,
LLDB-defined behavior, leveraging the existing
mechanism of stop hooks.
This change also simplifies
`Target::RunStopHooks`. We already have to
materialize a new list for combining internal and
user stop hooks. Filter and only add active hooks to this list to avoid
the need for "isActive?"
checks later on.
Commit: 3a59407689da7a3f2f934a841ed32ffcbfaf24dc
https://github.com/llvm/llvm-project/commit/3a59407689da7a3f2f934a841ed32ffcbfaf24dc
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M .ci/utils.sh
Log Message:
-----------
[CI] Make Postcommit Testing Pass In Correct Flags to Premerge Advisor
Before this patch we were passing in the previous commit rather than the
current commit due to a copy and paste adjustment failure from the PR
flow. We want the base SHA to just be the commit SHA for postcommit. We
also were not attaching the run number which made the source ID the
first JUnit XML file rather than the buildbot run number.
Commit: 5fda2a5d9c1a0f90da5d0afc412c9ad613702823
https://github.com/llvm/llvm-project/commit/5fda2a5d9c1a0f90da5d0afc412c9ad613702823
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/docs/ProgrammersManual.rst
A llvm/include/llvm/ADT/RadixTree.h
M llvm/unittests/ADT/CMakeLists.txt
A llvm/unittests/ADT/RadixTreeTest.cpp
Log Message:
-----------
[NFC][ADT] Add RadixTree (#164524)
This commit introduces a RadixTree implementation to LLVM.
RadixTree, as a Trie, is very efficient by searching for prefixes.
A Radix Tree is more efficient implementation of Trie.
The tree will be used to optimize Glob matching in SpecialCaseList:
* https://github.com/llvm/llvm-project/pull/164531
* https://github.com/llvm/llvm-project/pull/164543
* https://github.com/llvm/llvm-project/pull/164545
---------
Co-authored-by: Kazu Hirata <kazu at google.com>
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: cc4f462ba46c288dc26aa155775444cd9a7c4d0e
https://github.com/llvm/llvm-project/commit/cc4f462ba46c288dc26aa155775444cd9a7c4d0e
Author: Yi-Chi Lee <55395582+yichi170 at users.noreply.github.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
A llvm/test/CodeGen/X86/issue163738.ll
Log Message:
-----------
[X86][ISel] Improve VPTERNLOG matching for negated logic trees (#164863)
This patch extends VPTERNLOG pattern matching to handle cases where an
outer NOT wraps a pure logical tree, such as `~(A | B | C)`. By
recognizing these negated logic trees, the instruction selector can now
emit a single vpternlog instruction.
The change preserves the match for patterns like `(x != C1) & (x !=
C2)`, which also have the xor-with-all-ones pattern outside. The patch
conservatively peels the outer XOR-with-all-ones only when it directly
wraps a foldable logical operator (AND, OR, XOR, or ANDNP).
Resolves #163738
Commit: 9161760123cd8b10694483a8f27d72ed134173b2
https://github.com/llvm/llvm-project/commit/9161760123cd8b10694483a8f27d72ed134173b2
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M .ci/premerge_advisor_upload.py
Log Message:
-----------
[CI] Make Premerge Advisor Upload to Both Advisor Instances
So that we do not have to worry about synchronizing data between the two
clusters. This also enables this script to work on AArch64, although
we'll look at enabling that later.
Reviewers: cmtice
Reviewed By: cmtice
Pull Request: https://github.com/llvm/llvm-project/pull/165058
Commit: c9a45d3fd777997f669ff6af9c1f27e60a0fa23f
https://github.com/llvm/llvm-project/commit/c9a45d3fd777997f669ff6af9c1f27e60a0fa23f
Author: Kees Cook <kees at kernel.org>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMInstrInfo.td
Log Message:
-----------
[ARM][KCFI] Fix bundle sizes to reflect worst-case expansion (#164917)
The KCFI_CHECK pseudo-instruction size for ARM got miscalculated. These
should represent worst-case expansion to ensure correct branch range
calculations and code layout.
Update the Size field for each ARM sub-architecture:
- ARM: 28 → 40 bytes (10 instructions @ 4 bytes when r3 spill needed)
- Thumb2: 32 → 34 bytes (mixed 16/32-bit instructions with r3 spill)
- Thumb1: 50 → 38 bytes (19 instructions @ 2 bytes with r2+r3 spills)
The ARM and Thumb2 sizes were underestimating the case where the target
register is r12, requiring r3 to be used as scratch and
spilled/restored. The Thumb1 size was overestimated and has been
corrected to the actual worst-case of 19 instructions.
Commit: a7c38b8a9c7feb94dc7f500e62c4197b8089da05
https://github.com/llvm/llvm-project/commit/a7c38b8a9c7feb94dc7f500e62c4197b8089da05
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/RadixTree.h
Log Message:
-----------
[ADT][NFC] Add missing #include <vector> (#165068)
Added in #164524. Fails when using libc++ in a mode that prunes
transitive headers.
Commit: 30f9ce14b439ddb14a9624705ac573d7597d6ce2
https://github.com/llvm/llvm-project/commit/30f9ce14b439ddb14a9624705ac573d7597d6ce2
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M libc/include/llvm-libc-macros/gpu/signal-macros.h
M libc/include/llvm-libc-macros/linux/signal-macros.h
Log Message:
-----------
[libc] add SIG_HOLD for linux/gpu (#165007)
Commit: 2afbd3df2ae6959b6bf5cbf22db22b57247f36ac
https://github.com/llvm/llvm-project/commit/2afbd3df2ae6959b6bf5cbf22db22b57247f36ac
Author: SahilPatidar <sahilpatidar60 at gmail.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
R llvm/include/llvm/ExecutionEngine/Orc/Shared/SymbolFilter.h
R llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/LibraryResolver.h
R llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/LibraryScanner.h
M llvm/lib/ExecutionEngine/Orc/TargetProcess/CMakeLists.txt
R llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryResolver.cpp
R llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryScanner.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
R llvm/unittests/ExecutionEngine/Orc/Inputs/A/A_linux.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/A/A_macho.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/B/B_linux.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/B/B_macho.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/C/C_linux.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/C/C_macho.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/D/D_linux.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/D/D_macho.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/Z/Z_linux.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/Z/Z_macho.yaml
R llvm/unittests/ExecutionEngine/Orc/LibraryResolverTest.cpp
Log Message:
-----------
Revert "REAPPLY [ORC] Add automatic shared library resolver for unresolved symbols. #148410" (#165069)
Reverting llvm/llvm-project#164551 due to persistent build bot failure
caused by a path difference issue.
Commit: 351dc85e006ffc81ea63ad19490ce9158b25d37b
https://github.com/llvm/llvm-project/commit/351dc85e006ffc81ea63ad19490ce9158b25d37b
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
M llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
M llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
M llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
M llvm/test/CodeGen/Mips/beqzc.ll
M llvm/test/CodeGen/Mips/beqzc1.ll
M llvm/test/CodeGen/Mips/brsize3.ll
M llvm/test/CodeGen/Mips/brsize3a.ll
M llvm/test/CodeGen/Mips/ci2.ll
M llvm/test/CodeGen/Mips/cmplarge.ll
M llvm/test/CodeGen/Mips/const1.ll
M llvm/test/CodeGen/Mips/const4a.ll
M llvm/test/CodeGen/Mips/const6.ll
M llvm/test/CodeGen/Mips/const6a.ll
M llvm/test/CodeGen/Mips/ctlz.ll
M llvm/test/CodeGen/Mips/delay-slot-fill-forward.ll
M llvm/test/CodeGen/Mips/f16abs.ll
M llvm/test/CodeGen/Mips/fp16instrinsmc.ll
M llvm/test/CodeGen/Mips/fpneeded.ll
M llvm/test/CodeGen/Mips/fpnotneeded.ll
M llvm/test/CodeGen/Mips/hf16call32.ll
M llvm/test/CodeGen/Mips/hf16call32_body.ll
M llvm/test/CodeGen/Mips/hfptrcall.ll
M llvm/test/CodeGen/Mips/l3mc.ll
M llvm/test/CodeGen/Mips/lcb2.ll
M llvm/test/CodeGen/Mips/lcb3c.ll
M llvm/test/CodeGen/Mips/lcb4a.ll
M llvm/test/CodeGen/Mips/lcb5.ll
M llvm/test/CodeGen/Mips/mbrsize4a.ll
M llvm/test/CodeGen/Mips/micromips-attr.ll
M llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll
M llvm/test/CodeGen/Mips/mips16-hf-attr.ll
M llvm/test/CodeGen/Mips/mips16_32_1.ll
M llvm/test/CodeGen/Mips/mips16_32_10.ll
M llvm/test/CodeGen/Mips/mips16_32_3.ll
M llvm/test/CodeGen/Mips/mips16_32_4.ll
M llvm/test/CodeGen/Mips/mips16_32_5.ll
M llvm/test/CodeGen/Mips/mips16_32_6.ll
M llvm/test/CodeGen/Mips/mips16_32_7.ll
M llvm/test/CodeGen/Mips/mips16_32_8.ll
M llvm/test/CodeGen/Mips/mips16_32_9.ll
M llvm/test/CodeGen/Mips/nomips16.ll
M llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll
M llvm/test/CodeGen/Mips/powif64_16.ll
M llvm/test/CodeGen/Mips/s2rem.ll
M llvm/test/CodeGen/Mips/sel1c.ll
M llvm/test/CodeGen/Mips/sel2c.ll
M llvm/test/CodeGen/Mips/simplebr.ll
M llvm/test/CodeGen/Mips/sr1.ll
M llvm/test/CodeGen/Mips/tnaked.ll
Log Message:
-----------
[test][MIPS] Remove unsafe-fp-math uses (NFC) (#164790)
Post cleanup for #164534.
Commit: 168db5eca0da25b92a105c8df5c55ed7fd2d4cfc
https://github.com/llvm/llvm-project/commit/168db5eca0da25b92a105c8df5c55ed7fd2d4cfc
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/Support/SpecialCaseList.h
M llvm/lib/Support/SpecialCaseList.cpp
Log Message:
-----------
[SpecialCaseList] Filtering Globs with matching prefix (#164531)
This commit optimizes `SpecialCaseList` by using a `RadixTree` to filter
glob patterns based on their prefixes. When matching a query, the
`RadixTree` quickly identifies all glob patterns whose prefixes match
the query's prefix. This significantly reduces the number of glob
patterns that need to be fully evaluated, leading to performance
improvements, especially when dealing with a large number of patterns.
According to SpecialCaseListBM:
Lookup benchmarks (significant improvements):
```
OVERALL_GEOMEAN -0.8177
```
Lookup like `prefix*` benchmarks (huge improvements):
```
OVERALL_GEOMEAN -0.9819
```
https://gist.github.com/vitalybuka/824884bcbc1713e815068c279159dafe
---------
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: 44601d1a7a8a9df879998ae0a193ccab851d4131
https://github.com/llvm/llvm-project/commit/44601d1a7a8a9df879998ae0a193ccab851d4131
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
Reapply "Reapply "[clang-format] Annotate ::operator and Foo::operator… (#165038)
This reverts commit bd27abcceedfc60f4598124aa022cd0b766da3d8.
See https://github.com/llvm/llvm-project/pull/164670#issuecomment-3445926724
Commit: f7585adc94e87e0e32161be5a07d03927b6ce1a7
https://github.com/llvm/llvm-project/commit/f7585adc94e87e0e32161be5a07d03927b6ce1a7
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir
M llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
Log Message:
-----------
[AArch64] Widen GPR32 zero cycle zeroing (#164244)
Given a GPR32 zeroing instruction, if the target supports zero cycle
zeroing for GPR64 but not for GPR32, widen the instruction to 64 bit
`$xn = MOVZXi 0, 0` instead of writing to `$wn` to exploit zero cycle
zeroing.
It also aligns naming in the generic zeroing test.
Commit: 7be3cac735b272ffa9b89e36c8c7b7a5d333cf40
https://github.com/llvm/llvm-project/commit/7be3cac735b272ffa9b89e36c8c7b7a5d333cf40
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/CodeGen/Passes.h
M llvm/lib/Target/X86/X86.h
Log Message:
-----------
[X86] Move x86 specific create*Pass Functions to X86.h
There are no other target specific passes in Passes.h and these really
belong inside x86.h to be consistent with other targets.
Reviewers: arsenm, phoebewang, RKSimon, topperc
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/165075
Commit: 59e601a3d5e7669fdf809b9c6494e6f877ea5cd8
https://github.com/llvm/llvm-project/commit/59e601a3d5e7669fdf809b9c6494e6f877ea5cd8
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll
Log Message:
-----------
[CodeGenPrepare] Don't simplify incomplete expression tree in AddrModeCombine (#164628)
Since new select/phi instructions may construct loops, the expression
tree to be simplified may still be incomplete (i.e., it may contain
select with dummy values or phi without incoming values). This patch
removes the call to simplifyInstruction for now, as it doesn't break
existing tests.
Original PR: https://reviews.llvm.org/D36073
Fix the crash reported in
https://github.com/llvm/llvm-project/pull/163453#issuecomment-3429922732.
Commit: f248010a5233e726f6ab1767c09cd582057a6413
https://github.com/llvm/llvm-project/commit/f248010a5233e726f6ab1767c09cd582057a6413
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
Log Message:
-----------
[mlir][amdgpu] Update mfma assembly format with intrinsic shape (#165037)
Use the same format as introduced for wmma by
https://github.com/llvm/llvm-project/pull/164920.
Also make `blocks` default to 1.
Commit: 51fcb9d4daa73f7b62b065af4b4b23b6e8ceb090
https://github.com/llvm/llvm-project/commit/51fcb9d4daa73f7b62b065af4b4b23b6e8ceb090
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/test/CIR/CodeGen/complex.cpp
Log Message:
-----------
[CIR] Upstream CallOp with ComplexType as return type (#164980)
Upstream support calling function that returns ComplexType
Issue https://github.com/llvm/llvm-project/issues/141365
Commit: b0658b1151a7dce63e7bc29b69037462c07c355e
https://github.com/llvm/llvm-project/commit/b0658b1151a7dce63e7bc29b69037462c07c355e
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCleanup.h
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
Log Message:
-----------
[CIR][NFC] Upstream EHPersonality for function (#164883)
Upstream the EHPersonality class for a function as a prerequisite for
working with the handlers
Issue #154992
Commit: f58aa0ec8b3523f3bdaa73964b809d6d54c42768
https://github.com/llvm/llvm-project/commit/f58aa0ec8b3523f3bdaa73964b809d6d54c42768
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/lib/ExecutionEngine/Orc/Core.cpp
Log Message:
-----------
[ORC] Fix race when checking isComplete (#165063)
After #164340 there is a tsan race on `OutstandingSymbolsCount` when
decrementing it in `notifySymbolMetRequiredState` vs reading it in
`isComplete()`. Fix this by having `IL_emit` filter out non-completed
queries when it has the lock to do so, and that way we avoid needing to
call `isComplete()` later.
Commit: bbe92096bbcdfe9bdb47bf7ca42b17992ad94e74
https://github.com/llvm/llvm-project/commit/bbe92096bbcdfe9bdb47bf7ca42b17992ad94e74
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Dialect/AMDGPU/canonicalize.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
Log Message:
-----------
[mlir][amdgpu] Update scaled_mfma assembly format with intrinsic shape (#165044)
Use the same format as introduced for wmma by
https://github.com/llvm/llvm-project/pull/164920 and for mfma by
https://github.com/llvm/llvm-project/pull/165037.
Commit: 9a0a1fadef0880e19c1c278486b4e79aa04e580f
https://github.com/llvm/llvm-project/commit/9a0a1fadef0880e19c1c278486b4e79aa04e580f
Author: Luo Yuanke <lyk_03 at hotmail.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Log Message:
-----------
[ISel] Use CallBase instead of CallInst (#164769)
This is to follow the discussion in
https://github.com/llvm/llvm-project/pull/164565
CallBase can cover more call-like instructions which carry caling
convention flag.
Co-authored-by: Yuanke Luo <ykluo at birentech.com>
Commit: 1d661a97a53b8f701fec8d3056f692c39ed12f6a
https://github.com/llvm/llvm-project/commit/1d661a97a53b8f701fec8d3056f692c39ed12f6a
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
Add Codegen/Hexagon/masked_gather.ll to profcheck-xfail (#165093)
Commit: b97835d09df36e91434c82db28cad7bbdd5b37b8
https://github.com/llvm/llvm-project/commit/b97835d09df36e91434c82db28cad7bbdd5b37b8
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
Add new MemorySanitizer test cases for AArch64 (#165094)
Commit: 881b001b07cc761dd9e92c0958f0231ea56298d8
https://github.com/llvm/llvm-project/commit/881b001b07cc761dd9e92c0958f0231ea56298d8
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
M llvm/lib/CodeGen/RegisterUsageInfo.cpp
Log Message:
-----------
[ADT] Make internal methods of DenseMap/SmallDenseMap private (NFC) (#165079)
This patch moves the init, copyFrom, and grow methods in DenseMap and
SmallDenseMap from public to private to hide implementation details.
The only problem is that PhysicalRegisterUsageInfo calls
DenseMap::grow instead of DenseMap::reserve, which I don't think is
intended. This patch updates the call to reserve.
Commit: d4612449e207e7841e3fd65c21443a6e24edd4c7
https://github.com/llvm/llvm-project/commit/d4612449e207e7841e3fd65c21443a6e24edd4c7
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
M llvm/unittests/ADT/DenseMapTest.cpp
Log Message:
-----------
[ADT] Skip DenseMapBase::destroyAll on trivially destructible types (#165080)
DenseMap::destroyAll currently iterates through the entire bucket
array to call destructors keys and values. We don't need to do that
if we know that both key and value types are trivially destructible,
meaning that the destructors are no-ops.
This patch introduces "constexpr if" at the beginning of destroyAll to
skip the rest of the function if both key and value types are
trivially destructible.
Commit: 7379100be637eeb72d732d8f174a3b01d22532e3
https://github.com/llvm/llvm-project/commit/7379100be637eeb72d732d8f174a3b01d22532e3
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/Support/Recycler.h
Log Message:
-----------
[Support] Consolidate the two implementations of Recycler::clear (NFC) (#165081)
This patch consolidates the two implementations of Recycler::clear
with "if constexpr" for simplicity.
Commit: 84857775b76f7e27096d9ac311b378f99a8442c7
https://github.com/llvm/llvm-project/commit/84857775b76f7e27096d9ac311b378f99a8442c7
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
M llvm/lib/Target/AMDGPU/AMDGPUMIRFormatter.h
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.h
M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
M llvm/lib/Target/BPF/BPFTargetLoweringObjectFile.h
M llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h
M llvm/lib/Target/RISCV/RISCVConstantPoolValue.h
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
M llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
M llvm/lib/Target/SystemZ/SystemZMachineScheduler.h
M llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
M llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
M llvm/lib/Target/X86/MCA/X86CustomBehaviour.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86MachineFunctionInfo.h
Log Message:
-----------
[Target] Add "override" where appropriate (NFC) (#165083)
Note that "override" makes "virtual" redundant.
Identified with modernize-use-override.
Commit: 09eea2256e5305e7527df61b2fc35f16410b63be
https://github.com/llvm/llvm-project/commit/09eea2256e5305e7527df61b2fc35f16410b63be
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/Transforms/IPO/Attributor.cpp
A llvm/test/Transforms/Attributor/range-and-constant-fold.ll
Log Message:
-----------
[Attributor] Check range size before constant fold load (#151359)
If the range size doesn't match the type size, it might read wrong data.
Commit: 059d90d08f610d5919c42646f267bbab77f7bee4
https://github.com/llvm/llvm-project/commit/059d90d08f610d5919c42646f267bbab77f7bee4
Author: Yunqing Yu <yunqingy at nvidia.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
Log Message:
-----------
[Legalizer] Cache extracted element when lowering G_SHUFFLE_VECTOR. (#163893)
Cache extracted elements in lowerShuffleVector(). For example, when
lowering
```
%0:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
%2:_(<N x s32>) = G_SHUFFLE_VECTOR %1, shufflemask(0, 0, 0, 0 ... x N )
```
Currently, we generate `N` `G_EXTRACT_VECTOR_ELT` for each element in
shufflemask. This is undesirable and bloats the code, especially for
larger vectors.
With this change, we only generate one `G_EXTRACT_VECTOR_ELT` from `%0`
and reuse it for all four result elements.
Commit: 05c495de132f7609537686f60f312059ea70b4a6
https://github.com/llvm/llvm-project/commit/05c495de132f7609537686f60f312059ea70b4a6
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/Support/SpecialCaseList.h
M llvm/lib/Support/SpecialCaseList.cpp
Log Message:
-----------
[SpecialCaseList] Filtering Globs with matching prefix and suffix (#164543)
This commit enhances the `SpecialCaseList::GlobMatcher` to filter globs
more efficiently by considering both prefixes and suffixes.
Previously, the `GlobMatcher` used a `RadixTree` to store globs based
on their prefixes. This allowed for quick lookup of potential matches
by matching the query string's prefix against the stored prefixes.
However, for globs with common prefixes but different suffixes,
unnecessary glob matching attempts could still occur.
This change introduces a nested `RadixTree` structure:
`PrefixSuffixToGlob: RadixTree<Prefix, RadixTree<Suffix, Globs>>`.
Now, when a query string is matched, it first finds matching prefixes,
and then within those prefix matches, it further filters by matching
the reversed suffix of the query string against the reversed suffixes
of the globs. This significantly reduces the number of `Glob::match`
calls, especially for large special case lists with many globs sharing
common prefixes but differing in their suffixes.
According to SpecialCaseListBM:
Lookup benchmarks (significant improvements):
```
OVERALL_GEOMEAN -0.5815
```
Lookup `*suffix` and `prefix*suffix` like benchmarks (huge
improvements):
```
OVERALL_GEOMEAN -0.9316
```
https://gist.github.com/vitalybuka/e586751902760ced6beefcdf0d7b26fd
Commit: 5113ca0f43a5ce071b462e9f62ebedfa728525be
https://github.com/llvm/llvm-project/commit/5113ca0f43a5ce071b462e9f62ebedfa728525be
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
Log Message:
-----------
[clang] Proofread LanguageExtensions.rst (#165082)
Commit: 7b9cf0fe8d7bd77cd5d6747cfed6ecdded64fca3
https://github.com/llvm/llvm-project/commit/7b9cf0fe8d7bd77cd5d6747cfed6ecdded64fca3
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/Bitfields.h
Log Message:
-----------
[ADT] Tighten static_assert in Bitfields (#165099)
This patch tightens the static_assert. FirstBit and LastBit are
0-based bit indices of a bitfield, so they must be strictly less than
StorageBits.
Commit: e510797700fb53d114371ad18084bce11fdfafc0
https://github.com/llvm/llvm-project/commit/e510797700fb53d114371ad18084bce11fdfafc0
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/ConcurrentHashtable.h
Log Message:
-----------
[ADT] Use std::scoped_lock in ConcurrentHashtable (NFC) (#165100)
This patch uses std::scoped_lock to ensure the mutex is released via
RAII, improving robustness.
Commit: c3a4093dae316c0c4cf71bf965c3f6a99a8476d8
https://github.com/llvm/llvm-project/commit/c3a4093dae316c0c4cf71bf965c3f6a99a8476d8
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
Log Message:
-----------
[ADT] Consolidate copyFrom in DenseMap.h (NFC) (#165101)
DenseMap.h has:
- DenseMapBase::copyFrom
- DenseMap::copyFrom
- SmallDenseMap::copyFrom
The latter two clear and set up the storage again before delegating
DenseMapBase::copyFrom to do the actual work of copying buckets.
This patch consolidates all these into DenseMapBase::copyFrom while
eliminating name shadowing concerns. Note that DenseMap::copyFrom and
SmallDenseMap::copyFrom are nearly identical, and they can be made
identical with small adjustments:
- Set NumEntries and NumTombstones to 0 unconditionally.
- Teach SmallDenseMap::allocateBuckets to always return true.
This patch essentially applies these adjustments and then "inlines"
the identical function body to the beginning of
DenseMapBase::copyFrom.
This patch de-templatizes DenseMapBase::copyFrom because nobody calls
it with any type other than DerivedT.
Commit: e4909203feb2f6f4eccb42ed148cc39cedd5b524
https://github.com/llvm/llvm-project/commit/e4909203feb2f6f4eccb42ed148cc39cedd5b524
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
Log Message:
-----------
[ADT] Remove KeyInfoT forwarders in DenseMap.h (NFC) (#165102)
This patch removes getEmptyKey, getTombstoneKey, and getHashValue from
DenseMapBase. These forwarder methods do not really encapsulate
KeyInfoT. Many of their callers already mention KeyInfoT::isEqual for
example.
An existing static_assert is moved to another method. Note that it
must live in a method for type completeness reasons.
Commit: 9458ecd298a6d445ade80e750cbbfb89da0e0d5f
https://github.com/llvm/llvm-project/commit/9458ecd298a6d445ade80e750cbbfb89da0e0d5f
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
Log Message:
-----------
[ADT] Move shrink_and_clear to DenseMapBase (NFC) (#165103)
Without this patch, DenseMap and SmallDenseMap have distinct
implementations of shrink_and_clear. These implementations mix a
common high-level algorithm with class-specific logic.
This patch moves the common algorithm into
DenseMapBase::shrink_and_clear. A new private helper,
planShrinkAndClear, now handles the class-specific logic for deciding
whether to shrink the buffer. The base class method now serves as the
single public entry point.
Commit: fd804f076d117bc1d0a8751ef7ad44132a03453e
https://github.com/llvm/llvm-project/commit/fd804f076d117bc1d0a8751ef7ad44132a03453e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/docs/CIBestPractices.rst
Log Message:
-----------
[CI][Github] Add Fully Qualified Container Names to Best Practices (#165067)
Based on some recent discussion in #162007. Documenting this in the best
practices page so we have something easy to point to in code
review/reference for ourselves now that the repository has been cleaned
up.
Commit: 5d0f1591f8b91ac7919910c4e3e9614a8804c02a
https://github.com/llvm/llvm-project/commit/5d0f1591f8b91ac7919910c4e3e9614a8804c02a
Author: AZero13 <gfunni234 at gmail.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/ARM/load-combine-big-endian.ll
M llvm/test/CodeGen/ARM/load-combine.ll
Log Message:
-----------
[DAGCombine] Improve bswap lowering for machines that support bit rotates (#164848)
Source: Hacker's delight.
Commit: 6d94364c45f3ee2f94806bdbedb9da3f279b8052
https://github.com/llvm/llvm-project/commit/6d94364c45f3ee2f94806bdbedb9da3f279b8052
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M .ci/monolithic-windows.sh
M .ci/premerge_advisor_upload.py
M .ci/utils.sh
M .github/workflows/pr-code-format.yml
M .github/workflows/pr-code-lint.yml
M clang/docs/LanguageExtensions.rst
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenCleanup.h
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/test/CIR/CodeGen/complex.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M libc/include/llvm-libc-macros/gpu/signal-macros.h
M libc/include/llvm-libc-macros/linux/signal-macros.h
M lldb/include/lldb/Target/Target.h
M lldb/source/Commands/CommandCompletions.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Commands/Options.td
M lldb/source/Target/Target.cpp
A lldb/test/Shell/ExecControl/StopHook/stop-hook-list.test
M llvm/docs/CIBestPractices.rst
M llvm/docs/ProgrammersManual.rst
M llvm/include/llvm/ADT/Bitfields.h
M llvm/include/llvm/ADT/ConcurrentHashtable.h
M llvm/include/llvm/ADT/DenseMap.h
A llvm/include/llvm/ADT/RadixTree.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
R llvm/include/llvm/ExecutionEngine/Orc/Shared/SymbolFilter.h
R llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/LibraryResolver.h
R llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/LibraryScanner.h
M llvm/include/llvm/Support/Recycler.h
M llvm/include/llvm/Support/SpecialCaseList.h
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/RegisterUsageInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/CMakeLists.txt
R llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryResolver.cpp
R llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryScanner.cpp
M llvm/lib/Support/SpecialCaseList.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
M llvm/lib/Target/AMDGPU/AMDGPUMIRFormatter.h
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.h
M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
M llvm/lib/Target/BPF/BPFTargetLoweringObjectFile.h
M llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h
M llvm/lib/Target/RISCV/RISCVConstantPoolValue.h
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
M llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
M llvm/lib/Target/SystemZ/SystemZMachineScheduler.h
M llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
M llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
M llvm/lib/Target/X86/MCA/X86CustomBehaviour.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86.h
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86MachineFunctionInfo.h
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir
M llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/ARM/load-combine-big-endian.ll
M llvm/test/CodeGen/ARM/load-combine.ll
M llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
M llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
M llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
M llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
M llvm/test/CodeGen/Mips/beqzc.ll
M llvm/test/CodeGen/Mips/beqzc1.ll
M llvm/test/CodeGen/Mips/brsize3.ll
M llvm/test/CodeGen/Mips/brsize3a.ll
M llvm/test/CodeGen/Mips/ci2.ll
M llvm/test/CodeGen/Mips/cmplarge.ll
M llvm/test/CodeGen/Mips/const1.ll
M llvm/test/CodeGen/Mips/const4a.ll
M llvm/test/CodeGen/Mips/const6.ll
M llvm/test/CodeGen/Mips/const6a.ll
M llvm/test/CodeGen/Mips/ctlz.ll
M llvm/test/CodeGen/Mips/delay-slot-fill-forward.ll
M llvm/test/CodeGen/Mips/f16abs.ll
M llvm/test/CodeGen/Mips/fp16instrinsmc.ll
M llvm/test/CodeGen/Mips/fpneeded.ll
M llvm/test/CodeGen/Mips/fpnotneeded.ll
M llvm/test/CodeGen/Mips/hf16call32.ll
M llvm/test/CodeGen/Mips/hf16call32_body.ll
M llvm/test/CodeGen/Mips/hfptrcall.ll
M llvm/test/CodeGen/Mips/l3mc.ll
M llvm/test/CodeGen/Mips/lcb2.ll
M llvm/test/CodeGen/Mips/lcb3c.ll
M llvm/test/CodeGen/Mips/lcb4a.ll
M llvm/test/CodeGen/Mips/lcb5.ll
M llvm/test/CodeGen/Mips/mbrsize4a.ll
M llvm/test/CodeGen/Mips/micromips-attr.ll
M llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll
M llvm/test/CodeGen/Mips/mips16-hf-attr.ll
M llvm/test/CodeGen/Mips/mips16_32_1.ll
M llvm/test/CodeGen/Mips/mips16_32_10.ll
M llvm/test/CodeGen/Mips/mips16_32_3.ll
M llvm/test/CodeGen/Mips/mips16_32_4.ll
M llvm/test/CodeGen/Mips/mips16_32_5.ll
M llvm/test/CodeGen/Mips/mips16_32_6.ll
M llvm/test/CodeGen/Mips/mips16_32_7.ll
M llvm/test/CodeGen/Mips/mips16_32_8.ll
M llvm/test/CodeGen/Mips/mips16_32_9.ll
M llvm/test/CodeGen/Mips/nomips16.ll
M llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll
M llvm/test/CodeGen/Mips/powif64_16.ll
M llvm/test/CodeGen/Mips/s2rem.ll
M llvm/test/CodeGen/Mips/sel1c.ll
M llvm/test/CodeGen/Mips/sel2c.ll
M llvm/test/CodeGen/Mips/simplebr.ll
M llvm/test/CodeGen/Mips/sr1.ll
M llvm/test/CodeGen/Mips/tnaked.ll
A llvm/test/CodeGen/X86/issue163738.ll
A llvm/test/Transforms/Attributor/range-and-constant-fold.ll
M llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll
M llvm/unittests/ADT/CMakeLists.txt
M llvm/unittests/ADT/DenseMapTest.cpp
A llvm/unittests/ADT/RadixTreeTest.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
R llvm/unittests/ExecutionEngine/Orc/Inputs/A/A_linux.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/A/A_macho.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/B/B_linux.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/B/B_macho.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/C/C_linux.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/C/C_macho.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/D/D_linux.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/D/D_macho.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/Z/Z_linux.yaml
R llvm/unittests/ExecutionEngine/Orc/Inputs/Z/Z_macho.yaml
R llvm/unittests/ExecutionEngine/Orc/LibraryResolverTest.cpp
M llvm/utils/profcheck-xfail.txt
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma.mlir
M mlir/test/Dialect/AMDGPU/canonicalize.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
Log Message:
-----------
Merge branch 'main' into users/makslevental/fix-getOwner
Compare: https://github.com/llvm/llvm-project/compare/2cc752d1e171...6d94364c45f3
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