[all-commits] [llvm/llvm-project] 59e601: [CodeGenPrepare] Don't simplify incomplete express...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Sat Oct 25 09:49:45 PDT 2025
Branch: refs/heads/users/vitalybuka/spr/main.substringtree-add-radixtree-for-substring-matching
Home: https://github.com/llvm/llvm-project
Commit: 59e601a3d5e7669fdf809b9c6494e6f877ea5cd8
https://github.com/llvm/llvm-project/commit/59e601a3d5e7669fdf809b9c6494e6f877ea5cd8
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll
Log Message:
-----------
[CodeGenPrepare] Don't simplify incomplete expression tree in AddrModeCombine (#164628)
Since new select/phi instructions may construct loops, the expression
tree to be simplified may still be incomplete (i.e., it may contain
select with dummy values or phi without incoming values). This patch
removes the call to simplifyInstruction for now, as it doesn't break
existing tests.
Original PR: https://reviews.llvm.org/D36073
Fix the crash reported in
https://github.com/llvm/llvm-project/pull/163453#issuecomment-3429922732.
Commit: f248010a5233e726f6ab1767c09cd582057a6413
https://github.com/llvm/llvm-project/commit/f248010a5233e726f6ab1767c09cd582057a6413
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
Log Message:
-----------
[mlir][amdgpu] Update mfma assembly format with intrinsic shape (#165037)
Use the same format as introduced for wmma by
https://github.com/llvm/llvm-project/pull/164920.
Also make `blocks` default to 1.
Commit: 51fcb9d4daa73f7b62b065af4b4b23b6e8ceb090
https://github.com/llvm/llvm-project/commit/51fcb9d4daa73f7b62b065af4b4b23b6e8ceb090
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/test/CIR/CodeGen/complex.cpp
Log Message:
-----------
[CIR] Upstream CallOp with ComplexType as return type (#164980)
Upstream support calling function that returns ComplexType
Issue https://github.com/llvm/llvm-project/issues/141365
Commit: b0658b1151a7dce63e7bc29b69037462c07c355e
https://github.com/llvm/llvm-project/commit/b0658b1151a7dce63e7bc29b69037462c07c355e
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCleanup.h
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
Log Message:
-----------
[CIR][NFC] Upstream EHPersonality for function (#164883)
Upstream the EHPersonality class for a function as a prerequisite for
working with the handlers
Issue #154992
Commit: f58aa0ec8b3523f3bdaa73964b809d6d54c42768
https://github.com/llvm/llvm-project/commit/f58aa0ec8b3523f3bdaa73964b809d6d54c42768
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/lib/ExecutionEngine/Orc/Core.cpp
Log Message:
-----------
[ORC] Fix race when checking isComplete (#165063)
After #164340 there is a tsan race on `OutstandingSymbolsCount` when
decrementing it in `notifySymbolMetRequiredState` vs reading it in
`isComplete()`. Fix this by having `IL_emit` filter out non-completed
queries when it has the lock to do so, and that way we avoid needing to
call `isComplete()` later.
Commit: bbe92096bbcdfe9bdb47bf7ca42b17992ad94e74
https://github.com/llvm/llvm-project/commit/bbe92096bbcdfe9bdb47bf7ca42b17992ad94e74
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Dialect/AMDGPU/canonicalize.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
Log Message:
-----------
[mlir][amdgpu] Update scaled_mfma assembly format with intrinsic shape (#165044)
Use the same format as introduced for wmma by
https://github.com/llvm/llvm-project/pull/164920 and for mfma by
https://github.com/llvm/llvm-project/pull/165037.
Commit: 9a0a1fadef0880e19c1c278486b4e79aa04e580f
https://github.com/llvm/llvm-project/commit/9a0a1fadef0880e19c1c278486b4e79aa04e580f
Author: Luo Yuanke <lyk_03 at hotmail.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Log Message:
-----------
[ISel] Use CallBase instead of CallInst (#164769)
This is to follow the discussion in
https://github.com/llvm/llvm-project/pull/164565
CallBase can cover more call-like instructions which carry caling
convention flag.
Co-authored-by: Yuanke Luo <ykluo at birentech.com>
Commit: 1d661a97a53b8f701fec8d3056f692c39ed12f6a
https://github.com/llvm/llvm-project/commit/1d661a97a53b8f701fec8d3056f692c39ed12f6a
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
Add Codegen/Hexagon/masked_gather.ll to profcheck-xfail (#165093)
Commit: b97835d09df36e91434c82db28cad7bbdd5b37b8
https://github.com/llvm/llvm-project/commit/b97835d09df36e91434c82db28cad7bbdd5b37b8
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
Add new MemorySanitizer test cases for AArch64 (#165094)
Commit: 881b001b07cc761dd9e92c0958f0231ea56298d8
https://github.com/llvm/llvm-project/commit/881b001b07cc761dd9e92c0958f0231ea56298d8
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
M llvm/lib/CodeGen/RegisterUsageInfo.cpp
Log Message:
-----------
[ADT] Make internal methods of DenseMap/SmallDenseMap private (NFC) (#165079)
This patch moves the init, copyFrom, and grow methods in DenseMap and
SmallDenseMap from public to private to hide implementation details.
The only problem is that PhysicalRegisterUsageInfo calls
DenseMap::grow instead of DenseMap::reserve, which I don't think is
intended. This patch updates the call to reserve.
Commit: d4612449e207e7841e3fd65c21443a6e24edd4c7
https://github.com/llvm/llvm-project/commit/d4612449e207e7841e3fd65c21443a6e24edd4c7
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
M llvm/unittests/ADT/DenseMapTest.cpp
Log Message:
-----------
[ADT] Skip DenseMapBase::destroyAll on trivially destructible types (#165080)
DenseMap::destroyAll currently iterates through the entire bucket
array to call destructors keys and values. We don't need to do that
if we know that both key and value types are trivially destructible,
meaning that the destructors are no-ops.
This patch introduces "constexpr if" at the beginning of destroyAll to
skip the rest of the function if both key and value types are
trivially destructible.
Commit: 7379100be637eeb72d732d8f174a3b01d22532e3
https://github.com/llvm/llvm-project/commit/7379100be637eeb72d732d8f174a3b01d22532e3
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/Support/Recycler.h
Log Message:
-----------
[Support] Consolidate the two implementations of Recycler::clear (NFC) (#165081)
This patch consolidates the two implementations of Recycler::clear
with "if constexpr" for simplicity.
Commit: 84857775b76f7e27096d9ac311b378f99a8442c7
https://github.com/llvm/llvm-project/commit/84857775b76f7e27096d9ac311b378f99a8442c7
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
M llvm/lib/Target/AMDGPU/AMDGPUMIRFormatter.h
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.h
M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
M llvm/lib/Target/BPF/BPFTargetLoweringObjectFile.h
M llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h
M llvm/lib/Target/RISCV/RISCVConstantPoolValue.h
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
M llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
M llvm/lib/Target/SystemZ/SystemZMachineScheduler.h
M llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
M llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
M llvm/lib/Target/X86/MCA/X86CustomBehaviour.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86MachineFunctionInfo.h
Log Message:
-----------
[Target] Add "override" where appropriate (NFC) (#165083)
Note that "override" makes "virtual" redundant.
Identified with modernize-use-override.
Commit: 09eea2256e5305e7527df61b2fc35f16410b63be
https://github.com/llvm/llvm-project/commit/09eea2256e5305e7527df61b2fc35f16410b63be
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/Transforms/IPO/Attributor.cpp
A llvm/test/Transforms/Attributor/range-and-constant-fold.ll
Log Message:
-----------
[Attributor] Check range size before constant fold load (#151359)
If the range size doesn't match the type size, it might read wrong data.
Commit: 059d90d08f610d5919c42646f267bbab77f7bee4
https://github.com/llvm/llvm-project/commit/059d90d08f610d5919c42646f267bbab77f7bee4
Author: Yunqing Yu <yunqingy at nvidia.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
Log Message:
-----------
[Legalizer] Cache extracted element when lowering G_SHUFFLE_VECTOR. (#163893)
Cache extracted elements in lowerShuffleVector(). For example, when
lowering
```
%0:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
%2:_(<N x s32>) = G_SHUFFLE_VECTOR %1, shufflemask(0, 0, 0, 0 ... x N )
```
Currently, we generate `N` `G_EXTRACT_VECTOR_ELT` for each element in
shufflemask. This is undesirable and bloats the code, especially for
larger vectors.
With this change, we only generate one `G_EXTRACT_VECTOR_ELT` from `%0`
and reuse it for all four result elements.
Commit: 05c495de132f7609537686f60f312059ea70b4a6
https://github.com/llvm/llvm-project/commit/05c495de132f7609537686f60f312059ea70b4a6
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M llvm/include/llvm/Support/SpecialCaseList.h
M llvm/lib/Support/SpecialCaseList.cpp
Log Message:
-----------
[SpecialCaseList] Filtering Globs with matching prefix and suffix (#164543)
This commit enhances the `SpecialCaseList::GlobMatcher` to filter globs
more efficiently by considering both prefixes and suffixes.
Previously, the `GlobMatcher` used a `RadixTree` to store globs based
on their prefixes. This allowed for quick lookup of potential matches
by matching the query string's prefix against the stored prefixes.
However, for globs with common prefixes but different suffixes,
unnecessary glob matching attempts could still occur.
This change introduces a nested `RadixTree` structure:
`PrefixSuffixToGlob: RadixTree<Prefix, RadixTree<Suffix, Globs>>`.
Now, when a query string is matched, it first finds matching prefixes,
and then within those prefix matches, it further filters by matching
the reversed suffix of the query string against the reversed suffixes
of the globs. This significantly reduces the number of `Glob::match`
calls, especially for large special case lists with many globs sharing
common prefixes but differing in their suffixes.
According to SpecialCaseListBM:
Lookup benchmarks (significant improvements):
```
OVERALL_GEOMEAN -0.5815
```
Lookup `*suffix` and `prefix*suffix` like benchmarks (huge
improvements):
```
OVERALL_GEOMEAN -0.9316
```
https://gist.github.com/vitalybuka/e586751902760ced6beefcdf0d7b26fd
Commit: dea475645f04d92ff0bf2dad8f4d511bfc4f7767
https://github.com/llvm/llvm-project/commit/dea475645f04d92ff0bf2dad8f4d511bfc4f7767
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-10-25 (Sat, 25 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenCleanup.h
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/test/CIR/CodeGen/complex.cpp
M llvm/include/llvm/ADT/DenseMap.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/Support/Recycler.h
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/RegisterUsageInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
M llvm/lib/Target/AMDGPU/AMDGPUMIRFormatter.h
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.h
M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
M llvm/lib/Target/BPF/BPFTargetLoweringObjectFile.h
M llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h
M llvm/lib/Target/RISCV/RISCVConstantPoolValue.h
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
M llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
M llvm/lib/Target/SystemZ/SystemZMachineScheduler.h
M llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
M llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
M llvm/lib/Target/X86/MCA/X86CustomBehaviour.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86MachineFunctionInfo.h
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
A llvm/test/Transforms/Attributor/range-and-constant-fold.ll
M llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll
M llvm/unittests/ADT/DenseMapTest.cpp
M llvm/utils/profcheck-xfail.txt
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma.mlir
M mlir/test/Dialect/AMDGPU/canonicalize.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/ef2171c6c0a6...dea475645f04
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