[all-commits] [llvm/llvm-project] a7c38b: [ADT][NFC] Add missing #include <vector> (#165068)

Vitaly Buka via All-commits all-commits at lists.llvm.org
Sat Oct 25 00:31:56 PDT 2025 

  Branch: refs/heads/users/vitalybuka/spr/specialcaselist-flip-radixtree-key-order
  Home:   https://github.com/llvm/llvm-project
  Commit: a7c38b8a9c7feb94dc7f500e62c4197b8089da05
      https://github.com/llvm/llvm-project/commit/a7c38b8a9c7feb94dc7f500e62c4197b8089da05
  Author: Jordan Rupprecht <rupprecht at google.com>
  Date:   2025-10-25 (Sat, 25 Oct 2025)

  Changed paths:
    M llvm/include/llvm/ADT/RadixTree.h

  Log Message:
  -----------
  [ADT][NFC] Add missing #include <vector> (#165068)

Added in #164524. Fails when using libc++ in a mode that prunes
transitive headers.


  Commit: 30f9ce14b439ddb14a9624705ac573d7597d6ce2
      https://github.com/llvm/llvm-project/commit/30f9ce14b439ddb14a9624705ac573d7597d6ce2
  Author: Connector Switch <c8ef at outlook.com>
  Date:   2025-10-25 (Sat, 25 Oct 2025)

  Changed paths:
    M libc/include/llvm-libc-macros/gpu/signal-macros.h
    M libc/include/llvm-libc-macros/linux/signal-macros.h

  Log Message:
  -----------
  [libc] add SIG_HOLD for linux/gpu (#165007)


  Commit: 2afbd3df2ae6959b6bf5cbf22db22b57247f36ac
      https://github.com/llvm/llvm-project/commit/2afbd3df2ae6959b6bf5cbf22db22b57247f36ac
  Author: SahilPatidar <sahilpatidar60 at gmail.com>
  Date:   2025-10-25 (Sat, 25 Oct 2025)

  Changed paths:
    R llvm/include/llvm/ExecutionEngine/Orc/Shared/SymbolFilter.h
    R llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/LibraryResolver.h
    R llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/LibraryScanner.h
    M llvm/lib/ExecutionEngine/Orc/TargetProcess/CMakeLists.txt
    R llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryResolver.cpp
    R llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryScanner.cpp
    M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
    R llvm/unittests/ExecutionEngine/Orc/Inputs/A/A_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/A/A_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/B/B_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/B/B_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/C/C_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/C/C_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/D/D_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/D/D_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/Z/Z_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/Z/Z_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/LibraryResolverTest.cpp

  Log Message:
  -----------
  Revert "REAPPLY [ORC] Add automatic shared library resolver for unresolved symbols. #148410" (#165069)

Reverting llvm/llvm-project#164551 due to persistent build bot failure
caused by a path difference issue.


  Commit: 351dc85e006ffc81ea63ad19490ce9158b25d37b
      https://github.com/llvm/llvm-project/commit/351dc85e006ffc81ea63ad19490ce9158b25d37b
  Author: paperchalice <liujunchang97 at outlook.com>
  Date:   2025-10-25 (Sat, 25 Oct 2025)

  Changed paths:
    M llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
    M llvm/test/CodeGen/Mips/beqzc.ll
    M llvm/test/CodeGen/Mips/beqzc1.ll
    M llvm/test/CodeGen/Mips/brsize3.ll
    M llvm/test/CodeGen/Mips/brsize3a.ll
    M llvm/test/CodeGen/Mips/ci2.ll
    M llvm/test/CodeGen/Mips/cmplarge.ll
    M llvm/test/CodeGen/Mips/const1.ll
    M llvm/test/CodeGen/Mips/const4a.ll
    M llvm/test/CodeGen/Mips/const6.ll
    M llvm/test/CodeGen/Mips/const6a.ll
    M llvm/test/CodeGen/Mips/ctlz.ll
    M llvm/test/CodeGen/Mips/delay-slot-fill-forward.ll
    M llvm/test/CodeGen/Mips/f16abs.ll
    M llvm/test/CodeGen/Mips/fp16instrinsmc.ll
    M llvm/test/CodeGen/Mips/fpneeded.ll
    M llvm/test/CodeGen/Mips/fpnotneeded.ll
    M llvm/test/CodeGen/Mips/hf16call32.ll
    M llvm/test/CodeGen/Mips/hf16call32_body.ll
    M llvm/test/CodeGen/Mips/hfptrcall.ll
    M llvm/test/CodeGen/Mips/l3mc.ll
    M llvm/test/CodeGen/Mips/lcb2.ll
    M llvm/test/CodeGen/Mips/lcb3c.ll
    M llvm/test/CodeGen/Mips/lcb4a.ll
    M llvm/test/CodeGen/Mips/lcb5.ll
    M llvm/test/CodeGen/Mips/mbrsize4a.ll
    M llvm/test/CodeGen/Mips/micromips-attr.ll
    M llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll
    M llvm/test/CodeGen/Mips/mips16-hf-attr.ll
    M llvm/test/CodeGen/Mips/mips16_32_1.ll
    M llvm/test/CodeGen/Mips/mips16_32_10.ll
    M llvm/test/CodeGen/Mips/mips16_32_3.ll
    M llvm/test/CodeGen/Mips/mips16_32_4.ll
    M llvm/test/CodeGen/Mips/mips16_32_5.ll
    M llvm/test/CodeGen/Mips/mips16_32_6.ll
    M llvm/test/CodeGen/Mips/mips16_32_7.ll
    M llvm/test/CodeGen/Mips/mips16_32_8.ll
    M llvm/test/CodeGen/Mips/mips16_32_9.ll
    M llvm/test/CodeGen/Mips/nomips16.ll
    M llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll
    M llvm/test/CodeGen/Mips/powif64_16.ll
    M llvm/test/CodeGen/Mips/s2rem.ll
    M llvm/test/CodeGen/Mips/sel1c.ll
    M llvm/test/CodeGen/Mips/sel2c.ll
    M llvm/test/CodeGen/Mips/simplebr.ll
    M llvm/test/CodeGen/Mips/sr1.ll
    M llvm/test/CodeGen/Mips/tnaked.ll

  Log Message:
  -----------
  [test][MIPS] Remove unsafe-fp-math uses (NFC) (#164790)

Post cleanup for #164534.


  Commit: 168db5eca0da25b92a105c8df5c55ed7fd2d4cfc
      https://github.com/llvm/llvm-project/commit/168db5eca0da25b92a105c8df5c55ed7fd2d4cfc
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-10-25 (Sat, 25 Oct 2025)

  Changed paths:
    M llvm/include/llvm/Support/SpecialCaseList.h
    M llvm/lib/Support/SpecialCaseList.cpp

  Log Message:
  -----------
  [SpecialCaseList] Filtering Globs with matching prefix (#164531)

This commit optimizes `SpecialCaseList` by using a `RadixTree` to filter
glob patterns based on their prefixes. When matching a query, the
`RadixTree` quickly identifies all glob patterns whose prefixes match
the query's prefix. This significantly reduces the number of glob
patterns that need to be fully evaluated, leading to performance
improvements, especially when dealing with a large number of patterns.

According to SpecialCaseListBM:

Lookup benchmarks (significant improvements):
```
OVERALL_GEOMEAN                       -0.8177
```

Lookup like `prefix*` benchmarks (huge improvements):
```
OVERALL_GEOMEAN                       -0.9819
```

https://gist.github.com/vitalybuka/824884bcbc1713e815068c279159dafe

---------

Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>


  Commit: 44601d1a7a8a9df879998ae0a193ccab851d4131
      https://github.com/llvm/llvm-project/commit/44601d1a7a8a9df879998ae0a193ccab851d4131
  Author: Owen Pan <owenpiano at gmail.com>
  Date:   2025-10-24 (Fri, 24 Oct 2025)

  Changed paths:
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp

  Log Message:
  -----------
  Reapply "Reapply "[clang-format] Annotate ::operator and Foo::operator… (#165038)

This reverts commit bd27abcceedfc60f4598124aa022cd0b766da3d8.

See https://github.com/llvm/llvm-project/pull/164670#issuecomment-3445926724


  Commit: f7585adc94e87e0e32161be5a07d03927b6ce1a7
      https://github.com/llvm/llvm-project/commit/f7585adc94e87e0e32161be5a07d03927b6ce1a7
  Author: Tomer Shafir <tomer.shafir8 at gmail.com>
  Date:   2025-10-25 (Sat, 25 Oct 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir
    M llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll

  Log Message:
  -----------
  [AArch64] Widen GPR32 zero cycle zeroing (#164244)

Given a GPR32 zeroing instruction, if the target supports zero cycle
zeroing for GPR64 but not for GPR32, widen the instruction to 64 bit
`$xn = MOVZXi 0, 0` instead of writing to `$wn` to exploit zero cycle
zeroing.

It also aligns naming in the generic zeroing test.


  Commit: 7be3cac735b272ffa9b89e36c8c7b7a5d333cf40
      https://github.com/llvm/llvm-project/commit/7be3cac735b272ffa9b89e36c8c7b7a5d333cf40
  Author: Aiden Grossman <aidengrossman at google.com>
  Date:   2025-10-25 (Sat, 25 Oct 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/Passes.h
    M llvm/lib/Target/X86/X86.h

  Log Message:
  -----------
  [X86] Move x86 specific create*Pass Functions to X86.h

There are no other target specific passes in Passes.h and these really
belong inside x86.h to be consistent with other targets.

Reviewers: arsenm, phoebewang, RKSimon, topperc

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/165075


  Commit: f060b23b83a6a16b1d8ee3afd6d0a2310edea251
      https://github.com/llvm/llvm-project/commit/f060b23b83a6a16b1d8ee3afd6d0a2310edea251
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-10-25 (Sat, 25 Oct 2025)

  Changed paths:
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp
    M libc/include/llvm-libc-macros/gpu/signal-macros.h
    M libc/include/llvm-libc-macros/linux/signal-macros.h
    M llvm/include/llvm/ADT/RadixTree.h
    M llvm/include/llvm/CodeGen/Passes.h
    R llvm/include/llvm/ExecutionEngine/Orc/Shared/SymbolFilter.h
    R llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/LibraryResolver.h
    R llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/LibraryScanner.h
    M llvm/lib/ExecutionEngine/Orc/TargetProcess/CMakeLists.txt
    R llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryResolver.cpp
    R llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryScanner.cpp
    M llvm/lib/Support/SpecialCaseList.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/X86/X86.h
    M llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir
    M llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
    M llvm/test/CodeGen/Mips/beqzc.ll
    M llvm/test/CodeGen/Mips/beqzc1.ll
    M llvm/test/CodeGen/Mips/brsize3.ll
    M llvm/test/CodeGen/Mips/brsize3a.ll
    M llvm/test/CodeGen/Mips/ci2.ll
    M llvm/test/CodeGen/Mips/cmplarge.ll
    M llvm/test/CodeGen/Mips/const1.ll
    M llvm/test/CodeGen/Mips/const4a.ll
    M llvm/test/CodeGen/Mips/const6.ll
    M llvm/test/CodeGen/Mips/const6a.ll
    M llvm/test/CodeGen/Mips/ctlz.ll
    M llvm/test/CodeGen/Mips/delay-slot-fill-forward.ll
    M llvm/test/CodeGen/Mips/f16abs.ll
    M llvm/test/CodeGen/Mips/fp16instrinsmc.ll
    M llvm/test/CodeGen/Mips/fpneeded.ll
    M llvm/test/CodeGen/Mips/fpnotneeded.ll
    M llvm/test/CodeGen/Mips/hf16call32.ll
    M llvm/test/CodeGen/Mips/hf16call32_body.ll
    M llvm/test/CodeGen/Mips/hfptrcall.ll
    M llvm/test/CodeGen/Mips/l3mc.ll
    M llvm/test/CodeGen/Mips/lcb2.ll
    M llvm/test/CodeGen/Mips/lcb3c.ll
    M llvm/test/CodeGen/Mips/lcb4a.ll
    M llvm/test/CodeGen/Mips/lcb5.ll
    M llvm/test/CodeGen/Mips/mbrsize4a.ll
    M llvm/test/CodeGen/Mips/micromips-attr.ll
    M llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll
    M llvm/test/CodeGen/Mips/mips16-hf-attr.ll
    M llvm/test/CodeGen/Mips/mips16_32_1.ll
    M llvm/test/CodeGen/Mips/mips16_32_10.ll
    M llvm/test/CodeGen/Mips/mips16_32_3.ll
    M llvm/test/CodeGen/Mips/mips16_32_4.ll
    M llvm/test/CodeGen/Mips/mips16_32_5.ll
    M llvm/test/CodeGen/Mips/mips16_32_6.ll
    M llvm/test/CodeGen/Mips/mips16_32_7.ll
    M llvm/test/CodeGen/Mips/mips16_32_8.ll
    M llvm/test/CodeGen/Mips/mips16_32_9.ll
    M llvm/test/CodeGen/Mips/nomips16.ll
    M llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll
    M llvm/test/CodeGen/Mips/powif64_16.ll
    M llvm/test/CodeGen/Mips/s2rem.ll
    M llvm/test/CodeGen/Mips/sel1c.ll
    M llvm/test/CodeGen/Mips/sel2c.ll
    M llvm/test/CodeGen/Mips/simplebr.ll
    M llvm/test/CodeGen/Mips/sr1.ll
    M llvm/test/CodeGen/Mips/tnaked.ll
    M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
    R llvm/unittests/ExecutionEngine/Orc/Inputs/A/A_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/A/A_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/B/B_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/B/B_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/C/C_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/C/C_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/D/D_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/D/D_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/Z/Z_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/Z/Z_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/LibraryResolverTest.cpp

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]


  Commit: 277441890dfb6ff0f0ea2a925ee8ad953331ad00
      https://github.com/llvm/llvm-project/commit/277441890dfb6ff0f0ea2a925ee8ad953331ad00
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-10-25 (Sat, 25 Oct 2025)

  Changed paths:
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp
    M libc/include/llvm-libc-macros/gpu/signal-macros.h
    M libc/include/llvm-libc-macros/linux/signal-macros.h
    M llvm/include/llvm/ADT/RadixTree.h
    M llvm/include/llvm/CodeGen/Passes.h
    R llvm/include/llvm/ExecutionEngine/Orc/Shared/SymbolFilter.h
    R llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/LibraryResolver.h
    R llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/LibraryScanner.h
    M llvm/lib/ExecutionEngine/Orc/TargetProcess/CMakeLists.txt
    R llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryResolver.cpp
    R llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryScanner.cpp
    M llvm/lib/Support/SpecialCaseList.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/X86/X86.h
    M llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir
    M llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
    M llvm/test/CodeGen/Mips/beqzc.ll
    M llvm/test/CodeGen/Mips/beqzc1.ll
    M llvm/test/CodeGen/Mips/brsize3.ll
    M llvm/test/CodeGen/Mips/brsize3a.ll
    M llvm/test/CodeGen/Mips/ci2.ll
    M llvm/test/CodeGen/Mips/cmplarge.ll
    M llvm/test/CodeGen/Mips/const1.ll
    M llvm/test/CodeGen/Mips/const4a.ll
    M llvm/test/CodeGen/Mips/const6.ll
    M llvm/test/CodeGen/Mips/const6a.ll
    M llvm/test/CodeGen/Mips/ctlz.ll
    M llvm/test/CodeGen/Mips/delay-slot-fill-forward.ll
    M llvm/test/CodeGen/Mips/f16abs.ll
    M llvm/test/CodeGen/Mips/fp16instrinsmc.ll
    M llvm/test/CodeGen/Mips/fpneeded.ll
    M llvm/test/CodeGen/Mips/fpnotneeded.ll
    M llvm/test/CodeGen/Mips/hf16call32.ll
    M llvm/test/CodeGen/Mips/hf16call32_body.ll
    M llvm/test/CodeGen/Mips/hfptrcall.ll
    M llvm/test/CodeGen/Mips/l3mc.ll
    M llvm/test/CodeGen/Mips/lcb2.ll
    M llvm/test/CodeGen/Mips/lcb3c.ll
    M llvm/test/CodeGen/Mips/lcb4a.ll
    M llvm/test/CodeGen/Mips/lcb5.ll
    M llvm/test/CodeGen/Mips/mbrsize4a.ll
    M llvm/test/CodeGen/Mips/micromips-attr.ll
    M llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll
    M llvm/test/CodeGen/Mips/mips16-hf-attr.ll
    M llvm/test/CodeGen/Mips/mips16_32_1.ll
    M llvm/test/CodeGen/Mips/mips16_32_10.ll
    M llvm/test/CodeGen/Mips/mips16_32_3.ll
    M llvm/test/CodeGen/Mips/mips16_32_4.ll
    M llvm/test/CodeGen/Mips/mips16_32_5.ll
    M llvm/test/CodeGen/Mips/mips16_32_6.ll
    M llvm/test/CodeGen/Mips/mips16_32_7.ll
    M llvm/test/CodeGen/Mips/mips16_32_8.ll
    M llvm/test/CodeGen/Mips/mips16_32_9.ll
    M llvm/test/CodeGen/Mips/nomips16.ll
    M llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll
    M llvm/test/CodeGen/Mips/powif64_16.ll
    M llvm/test/CodeGen/Mips/s2rem.ll
    M llvm/test/CodeGen/Mips/sel1c.ll
    M llvm/test/CodeGen/Mips/sel2c.ll
    M llvm/test/CodeGen/Mips/simplebr.ll
    M llvm/test/CodeGen/Mips/sr1.ll
    M llvm/test/CodeGen/Mips/tnaked.ll
    M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
    R llvm/unittests/ExecutionEngine/Orc/Inputs/A/A_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/A/A_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/B/B_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/B/B_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/C/C_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/C/C_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/D/D_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/D/D_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/Z/Z_linux.yaml
    R llvm/unittests/ExecutionEngine/Orc/Inputs/Z/Z_macho.yaml
    R llvm/unittests/ExecutionEngine/Orc/LibraryResolverTest.cpp

  Log Message:
  -----------
  rebase

Created using spr 1.3.7


Compare: https://github.com/llvm/llvm-project/compare/e38e24a591b4...277441890dfb

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