[all-commits] [llvm/llvm-project] 44ed78: [DAGCombiner] Relax nsz constraint for more FP opt...

[Guy David via All-commits]

  Branch: refs/heads/users/guy-david/dag-combine-sign-insensitive
  Home:   https://github.com/llvm/llvm-project
  Commit: 44ed78de41205c4a39fd5141f99f021b473ec9cb
      https://github.com/llvm/llvm-project/commit/44ed78de41205c4a39fd5141f99f021b473ec9cb
  Author: Guy David <guyda96 at gmail.com>
  Date:   2025-10-24 (Fri, 24 Oct 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    A llvm/test/CodeGen/AArch64/nsz-bypass.ll
    M llvm/test/CodeGen/AMDGPU/swdev380865.ll

  Log Message:
  -----------
  [DAGCombiner] Relax nsz constraint for more FP optimizations

Some floating-point optimization don't trigger because they can produce
incorrect results around signed zeros, and rely on the existence of the
nsz flag which commonly appears when fast-math is enabled.
However, this flag is not a hard requirement when all of the users of
the combined value are either guranteed to overwrite the sign-bit or
simply ignore it (comparisons, etc.).

The optimizations affected:
- fadd x, -0.0 -> x
- fsub x, 0.0 -> x
- fsub -0.0, x -> fneg x
- fdiv x, sqrt(x) -> sqrt(x)
- frem lowering with power-of-2 divisors



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