[all-commits] [llvm/llvm-project] 8e5797: [flang][cuda] Make sure operand to syncthread func...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Thu Oct 23 23:16:42 PDT 2025
Branch: refs/heads/users/vitalybuka/spr/main.specialcaselist-filtering-globs-with-matching-prefix
Home: https://github.com/llvm/llvm-project
Commit: 8e5797162b5a5a1e4dc6de9c3c102919582228ea
https://github.com/llvm/llvm-project/commit/8e5797162b5a5a1e4dc6de9c3c102919582228ea
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Make sure operand to syncthread function is i32 (#164747)
Commit: 50ca1f407801cd268a1c130b9576dfb51fe7f392
https://github.com/llvm/llvm-project/commit/50ca1f407801cd268a1c130b9576dfb51fe7f392
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
Reapply "[clang-format] Annotate ::operator and Foo::operator correctly" (#164670)
This reverts commit 99abda7b02c9d6ba8b996867d2de624815ace1ce.
See https://github.com/llvm/llvm-project/pull/164670#issuecomment-3435040114
Commit: f3df058b03867e64af0195001d1e455257a81603
https://github.com/llvm/llvm-project/commit/f3df058b03867e64af0195001d1e455257a81603
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/include/llvm/CodeGen/AtomicExpand.h
M llvm/include/llvm/CodeGen/BasicBlockSectionsProfileReader.h
M llvm/include/llvm/CodeGen/CodeGenPrepare.h
M llvm/include/llvm/CodeGen/ComplexDeinterleavingPass.h
M llvm/include/llvm/CodeGen/DwarfEHPrepare.h
M llvm/include/llvm/CodeGen/ExpandFp.h
M llvm/include/llvm/CodeGen/ExpandLargeDivRem.h
M llvm/include/llvm/CodeGen/ExpandMemCmp.h
M llvm/include/llvm/CodeGen/IndirectBrExpand.h
M llvm/include/llvm/CodeGen/InterleavedAccess.h
M llvm/include/llvm/CodeGen/InterleavedLoadCombine.h
M llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h
M llvm/include/llvm/CodeGen/SafeStack.h
M llvm/include/llvm/CodeGen/SelectOptimize.h
M llvm/include/llvm/CodeGen/StackProtector.h
M llvm/include/llvm/CodeGen/TypePromotion.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/lib/CodeGen/ExpandFp.cpp
M llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
A llvm/test/tools/opt/no-target-machine.ll
Log Message:
-----------
[Passes] Report error when pass requires target machine (#142550)
Fixes #142146
Do nullptr check when pass accept `const TargetMachine &` in
constructor, but it is still not exhaustive.
Commit: d8563e51b56684e7c5491647424aff55d60017fd
https://github.com/llvm/llvm-project/commit/d8563e51b56684e7c5491647424aff55d60017fd
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Target/LLVMIR/nvvm/convert_fp4x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp6x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp8x2.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
Log Message:
-----------
[MLIR][NVVM] Add support for converting fp4/6/8 to fp16x2 (#162439)
This change adds the following NVVM dialect Ops for converting fp4/6/8
to fp16x2:
- `convert.f4x2.to.f16x2`
- `convert.f6x2.to.f16x2`
- `convert.f8x2.to.f16x2`
- `convert.f8x2.to.bf16x2`
Tests are added in `convert_fp4x2.mlir`, `convert_fp6x2.mlir`, and
`convert_fp8x2.mlir`.
PTX Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt
Commit: 5c666f559ca7c8ea0058b5b80d8b6059dc358fa7
https://github.com/llvm/llvm-project/commit/5c666f559ca7c8ea0058b5b80d8b6059dc358fa7
Author: jofrn <jofernau at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/IR/Verifier.cpp
M llvm/test/Assembler/atomic.ll
M llvm/test/Verifier/atomics.ll
Log Message:
-----------
IR/Verifier: Allow vector type in atomic load and store (#148893)
Vector types on atomics are assumed to be invalid by the verifier. However,
this type can be valid if it is lowered by codegen.
Commit: 13b5e396a007d119a65e0ba41b1f3604369376aa
https://github.com/llvm/llvm-project/commit/13b5e396a007d119a65e0ba41b1f3604369376aa
Author: Twice <twice at apache.org>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M mlir/examples/standalone/python/CMakeLists.txt
M mlir/python/CMakeLists.txt
Log Message:
-----------
[MLIR][Python] Skip stubgen while any sanitizer is enabled (#164661)
The intention of this PR is described
https://github.com/llvm/llvm-project/issues/164197#issuecomment-3432843709
(and
https://github.com/llvm/llvm-project/issues/164197#issuecomment-3432935838).
When sanitizers are enabled, some additional setup (such as preloading
certain libraries) seems to be required for the stubgen step to work
properly
(https://github.com/llvm/llvm-project/issues/164197#issuecomment-3432924034).
In this case, I chose to simply skip the stubgen process, as supporting
it would likely require some extra CMake logic, and type stubs don’t
appear to be particularly necessary in this configuration.
Commit: 407a9099e15db1aacc560f50b968f8f4f45cada7
https://github.com/llvm/llvm-project/commit/407a9099e15db1aacc560f50b968f8f4f45cada7
Author: jofrn <jofernau at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/X86/atomic-load-store.ll
Log Message:
-----------
[SelectionDAG] Legalize <1 x T> vector types for atomic load (#148894)
`load atomic <1 x T>` is not valid. This change legalizes
vector types of atomic load via scalarization in SelectionDAG
so that it can, for example, translate from `v1i32` to `i32`.
Commit: df970d5ff756e71cdb889f6253d9ef3187e9e251
https://github.com/llvm/llvm-project/commit/df970d5ff756e71cdb889f6253d9ef3187e9e251
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/test/CodeGen/MSP430/libcalls.ll
Log Message:
-----------
MSP430: Remove more default compiler-rt calls (#164752)
Commit: 7dd06b377447b2bac4a243f7db59fca59ee32e86
https://github.com/llvm/llvm-project/commit/7dd06b377447b2bac4a243f7db59fca59ee32e86
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/FoldingSet.h
Log Message:
-----------
[ADT] Simplify AddInteger overloads in FoldingSetNodeID (NFC) (#164753)
This patch simplifies the AddInteger overloads by introducing
AddIntegerImpl, a helper function to handle all cases, both 32-bit and
64-bit cases.
Commit: d548b0de1c5033f5fd396ee0afbeb244f9e025c4
https://github.com/llvm/llvm-project/commit/d548b0de1c5033f5fd396ee0afbeb244f9e025c4
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/IndexedMap.h
Log Message:
-----------
[ADT] Use default member initialization in IndexedMap (NFC) (#164754)
Commit: cae7dec112800cb6670324f52098e10a432d3306
https://github.com/llvm/llvm-project/commit/cae7dec112800cb6670324f52098e10a432d3306
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/utils/lit/lit/run.py
M llvm/utils/lit/tests/shtest-ulimit.py
Log Message:
-----------
[LIT][Cygwin] Mark `ulimit -n` unsupported for Cygwin (#164604)
Cygwin doesn't support `ulimit -n` because Windows doesn't provide such
functionality.
Commit: 542703fa68c5549292ccdd6b5c80ff8b7202a9b1
https://github.com/llvm/llvm-project/commit/542703fa68c5549292ccdd6b5c80ff8b7202a9b1
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll
M llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir
M llvm/test/CodeGen/ARM/Windows/wineh-basic.ll
M llvm/test/CodeGen/ARM/byval_load_align.ll
M llvm/test/CodeGen/ARM/cfguard-module-flag.ll
M llvm/test/CodeGen/ARM/clang-section.ll
M llvm/test/CodeGen/ARM/cmse-clear-float-bigend.mir
M llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll
M llvm/test/CodeGen/ARM/constantpool-promote-dbg.ll
M llvm/test/CodeGen/ARM/constantpool-promote.ll
M llvm/test/CodeGen/ARM/early-cfi-sections.ll
M llvm/test/CodeGen/ARM/fp16-vld.ll
M llvm/test/CodeGen/ARM/global-merge-1.ll
M llvm/test/CodeGen/ARM/isel-v8i32-crash.ll
M llvm/test/CodeGen/ARM/out-of-registers.ll
M llvm/test/CodeGen/ARM/relax-per-target-feature.ll
M llvm/test/CodeGen/ARM/softfp-constant-comparison.ll
M llvm/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll
M llvm/test/CodeGen/ARM/stack_guard_remat.ll
M llvm/test/CodeGen/ARM/struct-byval-frame-index.ll
M llvm/test/CodeGen/ARM/subtarget-align.ll
M llvm/test/CodeGen/ARM/unschedule-first-call.ll
M llvm/test/CodeGen/ARM/vector-spilling.ll
M llvm/test/CodeGen/ARM/vldm-sched-a9.ll
M llvm/test/CodeGen/Thumb/PR17309.ll
M llvm/test/CodeGen/Thumb/fastcc.ll
M llvm/test/CodeGen/Thumb/ldm-merge-call.ll
M llvm/test/CodeGen/Thumb/stack_guard_remat.ll
M llvm/test/CodeGen/Thumb/stm-merge.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-block-debug.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir
M llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll
M llvm/test/CodeGen/Thumb2/stack_guard_remat.ll
M llvm/test/CodeGen/Thumb2/t2sizereduction.mir
Log Message:
-----------
[test][ARM] Remove unsafe-fp-math-uses (NFC) (#164744)
Post cleanup for #164534.
Commit: fb4c05cf036e09ed97a48a6c515befbcc9198c61
https://github.com/llvm/llvm-project/commit/fb4c05cf036e09ed97a48a6c515befbcc9198c61
Author: Matthias Springer <me at m-sp.org>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M mlir/include/mlir/IR/Value.h
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/Shard/Transforms/Partition.cpp
Log Message:
-----------
[mlir][IR] Add implicit conversion operator to `TypedValue` (#164621)
Allow implicit conversion from `TypedValue<B>` to `TypedValue<A>` if `B`
is assignable to `A`.
Example:
```c++
TypedValue<MemRefType> val;
TypedValue<ShapedType> shapedVal = val; // this is now valid
```
Commit: a3ea51e4f161aecfe7dfe9e7c9d709b1f9cdf0ec
https://github.com/llvm/llvm-project/commit/a3ea51e4f161aecfe7dfe9e7c9d709b1f9cdf0ec
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
Log Message:
-----------
[SDAG] Introduce inbounds flag for ISD::PTRADD (#162477)
This patch introduces SDNodeFlags::InBounds, to show that an ISD::PTRADD SDNode
implements an inbounds getelementptr operation (i.e., the pointer operand is in
bounds wrt. an allocated object it is based on, and the arithmetic does not
change that). The flag is set in the DAG construction when lowering inbounds
GEPs.
Inbounds information is useful in the ISel when selecting memory instructions
that perform address computations whose intermediate steps must be in the same
memory region as the final result. Follow-up patches to propagate the flag in
DAGCombines and to use it when lowering AMDGPU's flat memory instructions,
where the immediate offset must not affect the memory aperture of the address
(similar to this GISel patch: #153001), are planned.
This mirrors #150900, which has introduced a similar flag in GlobalISel.
This patch supersedes #131862, which previously attempted to introduce an
SDNodeFlags::InBounds flag. The difference between this PR and #131862 is that
there is now an ISD::PTRADD opcode (PR #140017) and the InBounds flag is only
defined to apply to ISD::PTRADD DAG nodes. It is therefore unambiguous that
in-bounds-ness refers to a memory object into which the left operand of the
PTRADD node points (in contrast to #131862, where InBounds would have applied
to commutative ISD::ADD nodes, so that the semantics would be more difficult to
reason about).
For SWDEV-516125.
Commit: 01f29552d87ba70d876e76fdedea839a2f2b2a2a
https://github.com/llvm/llvm-project/commit/01f29552d87ba70d876e76fdedea839a2f2b2a2a
Author: Shaoce SUN <sunshaoce at outlook.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp
M llvm/lib/Target/RISCV/RISCVCombine.td
A llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll
Log Message:
-----------
[RISCV][GISel] Fold G_FCONSTANT 0.0 store into G_CONSTANT x0 (#163008)
Commit: 13a40e38924a04fd5ddf0cbfefd9861521f362ba
https://github.com/llvm/llvm-project/commit/13a40e38924a04fd5ddf0cbfefd9861521f362ba
Author: Gleb Popov <6yearold at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Analysis/InlineCost.cpp
Log Message:
-----------
[Analysis] Use the addCost() helper across InlineCost.cpp (#141901)
For the sake of consistency.
Commit: c80495c1b094dcca0a9933d8af3972393592b066
https://github.com/llvm/llvm-project/commit/c80495c1b094dcca0a9933d8af3972393592b066
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/intrinsic-select.ll
M llvm/test/Transforms/InstCombine/phi.ll
M llvm/test/Transforms/InstCombine/select_frexp.ll
M llvm/test/Transforms/PhaseOrdering/always-inline-alloca-promotion.ll
Log Message:
-----------
[InstCombine] Allow folding cross-lane operations into PHIs/selects (#164388)
Previously, cross-lane operations were disallowed here, but they are
only problematic if the `select` condition is a vector, as the input of
the operation is not simply one of the arms of the phi/select.
Commit: 4a95cd14b381b34a821ce561577d386f46e5e51c
https://github.com/llvm/llvm-project/commit/4a95cd14b381b34a821ce561577d386f46e5e51c
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/test/Bitcode/DILocation-implicit-code.ll
M llvm/test/Bitcode/drop-debug-info.3.5.ll
M llvm/test/Bitcode/upgrade-tbaa.ll
Log Message:
-----------
[test][Bitcode] Remove unsafe-fp-math uses (NFC) (#164743)
Post cleanup for #164534.
Commit: e6cd7a52bc1454c58bdb3ca51aa8780e04b3342f
https://github.com/llvm/llvm-project/commit/e6cd7a52bc1454c58bdb3ca51aa8780e04b3342f
Author: Jasmine Tang <jjasmine at igalia.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
Log Message:
-----------
[WebAssembly] [Codegen] Add pattern for relaxed min max from pmin/pmax-based patterns over v4f32 and v2f64 (#164486)
Related to https://github.com/llvm/llvm-project/issues/55932
Commit: d2889d7ce3f2eef7f38a8a429c9a23f15c6adc66
https://github.com/llvm/llvm-project/commit/d2889d7ce3f2eef7f38a8a429c9a23f15c6adc66
Author: don <122427011+donneypr at users.noreply.github.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][x86][bytecode] remove trailing returns type from interp__builtin_elementwise_int_binop callbacks (#164679)
Related to the discussion in #162346, this PR is to remove the trailing type from the 'interp__builtin_elementwise_int_binop' callbacks.
Commit: f567367c7f1d543c2825f13aed83661dd4790e66
https://github.com/llvm/llvm-project/commit/f567367c7f1d543c2825f13aed83661dd4790e66
Author: Ville-Markus Yli-Suutala <villemarkus.ylisuutala at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/math-lowering/sinh.f90
M flang/test/Lower/trigonometric-intrinsics.f90
Log Message:
-----------
[Flang] Generate math.sinh op for single and double precision sinh (#162734)
Fixes issue with double precision sinh when using OpenMP offloading with
AMD GPUs. The machinery to convert the op to a ROCDL call is already in
place.
https://github.com/llvm/llvm-project/issues/162733
Commit: 4f99111faf51a27f138f46f90bb1445a8962d13b
https://github.com/llvm/llvm-project/commit/4f99111faf51a27f138f46f90bb1445a8962d13b
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/test/CIR/CodeGen/struct-init.cpp
Log Message:
-----------
[CIR] ConstRecordBuilder check if attribute present before casting (#164575)
Fix the crash because in `ConstRecordBuilder::build` we cast to
TypedAttr then we check if it null, but in case that the result from
emitter is nullptr, that cast crash, In this PR I fixed the order to
check first if it not null, then casting to the TypedAttr
Commit: 7f66c31fab38801f9d27819ad89ee873e2fecb24
https://github.com/llvm/llvm-project/commit/7f66c31fab38801f9d27819ad89ee873e2fecb24
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCXX.cpp
M clang/test/CIR/CodeGen/global-init.cpp
Log Message:
-----------
[CIR] Implement global initializer for ComplexType (#164610)
Implement a global initializer for ComplexType
Issue https://github.com/llvm/llvm-project/issues/141365
Commit: ae6cb98b29a6e1bf8acfa0ae230493c0d16a6bbf
https://github.com/llvm/llvm-project/commit/ae6cb98b29a6e1bf8acfa0ae230493c0d16a6bbf
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M bolt/README.md
M bolt/docs/Heatmaps.md
M bolt/docs/index.rst
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/X86/nolbr.s
M bolt/test/X86/pre-aggregated-perf.test
M bolt/test/perf2bolt/perf_test.test
M clang/utils/perf-training/perf-helper.py
Log Message:
-----------
[BOLT] Add --ba flag to deprecate --nl (#164257)
The `--nl` flag, originally for Non-LBR mode, is deprecated and will be
replaced by `--basic-events` (alias `--ba`).
`--nl` remains as a deprecated alias for backward compatibility.
Commit: 0fddaf058ac0c2627553b65ed7d057719d31aa7c
https://github.com/llvm/llvm-project/commit/0fddaf058ac0c2627553b65ed7d057719d31aa7c
Author: Marco Elver <elver at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
A clang/include/clang/AST/InferAlloc.h
M clang/lib/AST/CMakeLists.txt
A clang/lib/AST/InferAlloc.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
Log Message:
-----------
[Clang] Refactor allocation type inference logic (#163636)
Refactor the logic for inferring allocated types out of `CodeGen` and
into a new reusable component in `clang/AST/InferAlloc.h`.
This is a preparatory step for implementing `__builtin_infer_alloc_token`.
By moving the type inference heuristics into a common place, it can be
shared between the existing allocation-call instrumentation and the new
builtin's implementation.
Commit: cd6e913d00cf91b7bbac205351e967a68cd14797
https://github.com/llvm/llvm-project/commit/cd6e913d00cf91b7bbac205351e967a68cd14797
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/Sema/SemaConcept.cpp
M clang/test/SemaTemplate/concepts.cpp
Log Message:
-----------
[Clang] Handle TemplateTemplateParmDecl in concept cache (#164777)
We forgot to handle those in e9972debc, hence the inconsistency across
multiple instantiations.
This is a regression on trunk, so no release note.
Fixes https://github.com/llvm/llvm-project/issues/164750
Commit: f5ac58f5b88086f6b0e6e02383bc811e343dec06
https://github.com/llvm/llvm-project/commit/f5ac58f5b88086f6b0e6e02383bc811e343dec06
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/Sema/SemaConcept.cpp
Log Message:
-----------
[Clang] Fix a use-after-move issue in SubsumptionChecker (#164781)
Spotted by Shafik.
Commit: b474be668091301d4a214da922f0cb98d416dc6b
https://github.com/llvm/llvm-project/commit/b474be668091301d4a214da922f0cb98d416dc6b
Author: Keith Thompson <Keith.S.Thompson at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/bugprone/switch-missing-default-case.rst
Log Message:
-----------
[clang-tidy][NFC] Clarify switch-missing-default-case doc (#164699) (#164709)
Falling through a defaultless switch statement has well defined
behavior. Fixes https://github.com/llvm/llvm-project/issues/164699.
Credit for noticing this problem goes to user "pozz" on comp.lang.c,
Message-ID: <10da67g$3q59f$1 at dont-email.me>
Commit: 6003a448b3998c720fe87f0f4d8f263ebe9ae2ee
https://github.com/llvm/llvm-project/commit/6003a448b3998c720fe87f0f4d8f263ebe9ae2ee
Author: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/CGData/CodeGenDataReader.cpp
Log Message:
-----------
[NFC][CGData] Use `std::move` in `lazyDeserialize` call (#164558)
Use `std::move` for shared_ptr in `lazyDeserialize` call to avoid extra
refcount ops
Commit: 710a5873fbf43d312555a1ddbafafa10f44f576e
https://github.com/llvm/llvm-project/commit/710a5873fbf43d312555a1ddbafafa10f44f576e
Author: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/CGData/StableFunctionMap.cpp
Log Message:
-----------
[NFC][CGData] Add assert to `StableFunctionMap::at` (#164564)
Add assert to `StableFunctionMap::at` to verify `FunctionHash` exists.
Commit: f801b6f67ea896d6e4d2de38bce9a79689ceb254
https://github.com/llvm/llvm-project/commit/f801b6f67ea896d6e4d2de38bce9a79689ceb254
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/test/Transforms/InstCombine/ptrtoaddr.ll
M llvm/test/Transforms/InstCombine/sub-gep.ll
Log Message:
-----------
[InstCombine] Add support for ptrtoaddr in pointer difference folds (#164428)
This adds support for folding `ptrtoaddr(p2) - ptrtoaddr(p)` pointer
subtractions. We can treat ptrtoaddr the same as ptrtoint as the
transform is truncation safe anyway (and in fact supports explicit
truncation as well).
The only interesting case is the subtraction of zext of ptrtoaddr. For
this transform it's important that the address bits are not truncated --
and if any pointer bits are truncated, that the truncation is consistent
for both operands. I've explicitly spelled out the three different cases
for this, which also fixes a miscompile in the existing ptrtoint fold.
Commit: 4f4bee428d2269808f2ef5f97f3482382d18945d
https://github.com/llvm/llvm-project/commit/4f4bee428d2269808f2ef5f97f3482382d18945d
Author: Marco Elver <elver at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/Sema/SemaChecking.cpp
A clang/test/SemaCXX/alloc-token.cpp
Log Message:
-----------
[Clang][Sema] Add __builtin_infer_alloc_token() declaration and semantic checks (#163638)
Introduce the `__builtin_infer_alloc_token()` builtin declaration and
adds the necessary semantic checks in Sema.
Commit: 902b07f711946988252f83d2fd369da89f28676d
https://github.com/llvm/llvm-project/commit/902b07f711946988252f83d2fd369da89f28676d
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-to-svbool-binops.ll
Log Message:
-----------
[LLVM][InstCombine][SVE] Improve isAllActivePredicate by looking through from.svbool. (#164446)
When a predicate is of the form "%a = sve.from.vsbool(%b)" we know all
bits in %a come from %b and thus if %b is all true then %a must also be
all true.
Commit: 6b19a546aa8d341dfdfa2a3a0a37fb90ac786f92
https://github.com/llvm/llvm-project/commit/6b19a546aa8d341dfdfa2a3a0a37fb90ac786f92
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/fully-unrolled-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/maxbandwidth-regpressure.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
A llvm/test/Transforms/LoopVectorize/WebAssembly/partial-reduce-accumulate.ll
Log Message:
-----------
[LV] Bundle partial reductions inside VPExpressionRecipe (#147302)
This PR bundles partial reductions inside the VPExpressionRecipe class.
Stacked PRs:
1. https://github.com/llvm/llvm-project/pull/147026
2. https://github.com/llvm/llvm-project/pull/147255
3. https://github.com/llvm/llvm-project/pull/156976
4. https://github.com/llvm/llvm-project/pull/160154
5. -> https://github.com/llvm/llvm-project/pull/147302
6. https://github.com/llvm/llvm-project/pull/162503
7. https://github.com/llvm/llvm-project/pull/147513
Commit: 11bbee9d9fbaa98978ed7704e799d6b56fb47295
https://github.com/llvm/llvm-project/commit/11bbee9d9fbaa98978ed7704e799d6b56fb47295
Author: ddubov100 <155631080+ddubov100 at users.noreply.github.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/test/Dialect/SCF/canonicalize.mlir
Log Message:
-----------
Adding to execute_region_op some missing support (#164159)
Adding canonicalization pattern in case execute_region op has yieldOps
which operands are from outside the execute_region, then it simplifies
the op to return just internal values. The pattern is applied only in
case all yieldOps within execute_region_op have same operands
---------
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
Commit: daf0182277831222101ee8e29f6fa3a1ac3b809d
https://github.com/llvm/llvm-project/commit/daf0182277831222101ee8e29f6fa3a1ac3b809d
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/add-nsw.ll
M llvm/test/Transforms/ConstraintElimination/gep-arithmetic-add.ll
Log Message:
-----------
[ConstraintElim] Apply add with neg constant first during decomp. (#164791)
We have dedicated decomposition logic for (add %x, -C), but if we have
(add nsw %x, -C) we will first apply the generic logic for NSWAdd, which
gives worse results for negative constants in practice.
Update the code to first apply the pattern with negative constants.
Helps to remove a number of runtime checks in practice:
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/2968
Alive2 proofs for the test changes: https://alive2.llvm.org/ce/z/JfR2Ma
PR: https://github.com/llvm/llvm-project/pull/164791
Commit: b11f0e1bcde45b2ee81d06a9c6a94da089dfd157
https://github.com/llvm/llvm-project/commit/b11f0e1bcde45b2ee81d06a9c6a94da089dfd157
Author: Vitalii Shutov <vitaly.shutov1 at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
Log Message:
-----------
[mlir][tosa] Stop folding pad into avg_pool2d (#164599)
Keep explicit padding ahead of tosa.avg_pool2d to preserve semantics.
Folding a pad into the op drops padded values from the average divisor.
Commit: 911e5aa5cceda96dfcf578baae41e5452ff2ef11
https://github.com/llvm/llvm-project/commit/911e5aa5cceda96dfcf578baae41e5452ff2ef11
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
Log Message:
-----------
[flang][NFC] fix build warning about unused argument (#164776)
Fix warning about unused arguments. Just use [[maybe_unsued]] to deal with
the fact that these arguments are not always used because of the `if constexpr`.
Commit: 0591297c8aa123d9503e4706b5c45617536ec882
https://github.com/llvm/llvm-project/commit/0591297c8aa123d9503e4706b5c45617536ec882
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/records.cpp
Log Message:
-----------
[clang][bytecode] Fix initializing primitive fields via initlist (#164789)
Fixes https://github.com/llvm/llvm-project/issues/152901
Commit: 3107c2fe94e9ec4b406eb137ca95097f57a85507
https://github.com/llvm/llvm-project/commit/3107c2fe94e9ec4b406eb137ca95097f57a85507
Author: Shawn K <kimshawn02 at icloud.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGen/builtin_prefetech.c
Log Message:
-----------
[CIR] Upstream handling for __builtin_prefetch (#164387)
Fix #163886
Commit: 249883d0c5883996bed038cd82a8999f342994c9
https://github.com/llvm/llvm-project/commit/249883d0c5883996bed038cd82a8999f342994c9
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/test/Transforms/DeadArgElim/dbginfo.ll
M llvm/test/Transforms/DeadStoreElimination/mda-with-dbg-values.ll
M llvm/test/Transforms/FunctionImport/Inputs/funcimport_debug.ll
M llvm/test/Transforms/FunctionImport/funcimport_debug.ll
M llvm/test/Transforms/GCOVProfiling/exit-block.ll
M llvm/test/Transforms/GCOVProfiling/linezero.ll
M llvm/test/Transforms/GCOVProfiling/split-indirectbr-critical-edges.ll
M llvm/test/Transforms/GVN/cond_br2.ll
M llvm/test/Transforms/GVN/pr33549.ll
M llvm/test/Transforms/GVN/pr42605.ll
M llvm/test/Transforms/GVNHoist/hoist-unsafe-pr31729.ll
M llvm/test/Transforms/GVNHoist/pr30499.ll
M llvm/test/Transforms/IndVarSimplify/X86/widen-nsw.ll
M llvm/test/Transforms/Inline/always-inline-attr.ll
M llvm/test/Transforms/Inline/debug-info-duplicate-calls.ll
M llvm/test/Transforms/Inline/inline-vla.ll
M llvm/test/Transforms/Inline/optimization-remarks-hotness-threshold.ll
M llvm/test/Transforms/Inline/optimization-remarks-passed-deleted-callee-yaml.ll
M llvm/test/Transforms/Inline/optimization-remarks-passed-yaml.ll
M llvm/test/Transforms/Inline/optimization-remarks.ll
M llvm/test/Transforms/InstCombine/bitreverse-hang.ll
M llvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll
M llvm/test/Transforms/InstCombine/select-extractelement.ll
M llvm/test/Transforms/JumpThreading/ddt-crash3.ll
M llvm/test/Transforms/LICM/volatile-alias.ll
M llvm/test/Transforms/LoopRotate/noalias.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-addressing-mode-loops.ll
M llvm/test/Transforms/LoopStrengthReduce/X86/pr17473.ll
M llvm/test/Transforms/LoopStrengthReduce/pr18165.ll
M llvm/test/Transforms/LoopStrengthReduce/two-combinations-bug.ll
M llvm/test/Transforms/LoopUnroll/runtime-epilog-debuginfo.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll
M llvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
M llvm/test/Transforms/LoopVectorize/X86/int128_no_gather.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-profitable.ll
M llvm/test/Transforms/LoopVectorize/diag-missing-instr-debug-loc.ll
M llvm/test/Transforms/LoopVectorize/diag-with-hotness-info-2.ll
M llvm/test/Transforms/LoopVectorize/diag-with-hotness-info.ll
M llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/metadata-width.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-address-space.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-readonly-address-space.ll
M llvm/test/Transforms/LoopVectorize/scev-exitlim-crash.ll
M llvm/test/Transforms/MergeICmps/X86/int64-and-ptr.ll
M llvm/test/Transforms/MergeICmps/X86/pr41917.ll
M llvm/test/Transforms/NewGVN/basic-cyclic-opt.ll
M llvm/test/Transforms/NewGVN/cond_br2-xfail.ll
M llvm/test/Transforms/NewGVN/equivalent-phi.ll
M llvm/test/Transforms/NewGVN/memory-handling.ll
M llvm/test/Transforms/NewGVN/pr31483.ll
M llvm/test/Transforms/NewGVN/pr31501.ll
M llvm/test/Transforms/NewGVN/pr33187.ll
M llvm/test/Transforms/NewGVN/pr33305.ll
M llvm/test/Transforms/NewGVN/pr34430.ll
M llvm/test/Transforms/NewGVN/pr34452.ll
M llvm/test/Transforms/OpenMP/dead_use.ll
M llvm/test/Transforms/OpenMP/icv_remarks.ll
M llvm/test/Transforms/PGOProfile/misexpect-branch-correct.ll
M llvm/test/Transforms/PGOProfile/misexpect-branch-overflow.ll
M llvm/test/Transforms/PGOProfile/misexpect-branch-stripped.ll
M llvm/test/Transforms/PGOProfile/misexpect-branch-unpredictable.ll
M llvm/test/Transforms/PGOProfile/misexpect-branch.ll
M llvm/test/Transforms/PGOProfile/misexpect-switch-default.ll
M llvm/test/Transforms/PGOProfile/misexpect-switch.ll
Log Message:
-----------
[test][Transforms] Remove unsafe-fp-math uses part 2 (NFC) (#164786)
Post cleanup for #164534.
Commit: 3f47a7be1ae689074913f5b72cfb49bedd0bad2f
https://github.com/llvm/llvm-project/commit/3f47a7be1ae689074913f5b72cfb49bedd0bad2f
Author: Nikita Kornev <nikita.kornev at intel.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll
Log Message:
-----------
[SPIRV] Upd SPV_KHR_shader_clock extension (#160147)
Add __spirv_ReadClockKHR support
Commit: a242a20f21f4f72304316573b6e08ea869b12371
https://github.com/llvm/llvm-project/commit/a242a20f21f4f72304316573b6e08ea869b12371
Author: David Green <david.green at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/test/Analysis/CostModel/ARM/fparith.ll
M llvm/test/Analysis/CostModel/ARM/fptoi_sat.ll
R llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll
A llvm/test/Analysis/CostModel/ARM/mve-intrinsic-cost-kinds.ll
A llvm/test/Analysis/CostModel/ARM/mve-target-intrinsics.ll
R llvm/test/Analysis/CostModel/ARM/target-intrinsics.ll
Log Message:
-----------
[ARM] Update more MVE costmodel tests with -cost-kind=all. NFC
Commit: 53b9441f5355fcdca07dc5b6ddc4fa5bb7ce4920
https://github.com/llvm/llvm-project/commit/53b9441f5355fcdca07dc5b6ddc4fa5bb7ce4920
Author: sstwcw <su3e8a96kzlver at posteo.net>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTestObjC.cpp
Log Message:
-----------
[clang-format] Break the line within ObjC `@selector` (#164674)
after, with style `{ColumnLimit: 60}`
```Objective-C
[objectName
respondsToSelector:
@selector(
somelonglonglonglongnameeeeeeee:
loooooooooanotherlonglonglonglongnametopush:
otherlongnameforlimit:)];
```
before
```Objective-C
[objectName
respondsToSelector:
@selector(
somelonglonglonglongnameeeeeeee:loooooooooanotherlonglonglonglongnametopush:otherlongnameforlimit:)];
```
Fixes #164574.
The stuff inside the parentheses got a new type in 2a059042882ed. I
neglected to add it to the logic for breaking lines.
Commit: ece83ed7dfe6ef65ac100efcc61f50a2a337436a
https://github.com/llvm/llvm-project/commit/ece83ed7dfe6ef65ac100efcc61f50a2a337436a
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/records.cpp
Log Message:
-----------
[clang][bytecode] Fix instance pointer in IndirectFieldDecl inits (#164751)
Points to the first chain link in this case.
Commit: 90b51c393905eb82eb882d7a1d5bb999dc67a74b
https://github.com/llvm/llvm-project/commit/90b51c393905eb82eb882d7a1d5bb999dc67a74b
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M mlir/lib/ExecutionEngine/SparseTensor/CMakeLists.txt
Log Message:
-----------
[MLIR][ExecutionEngine] don't leak -Wweak-vtables (#164498)
I'm not 100% what this is used for in this lib but the compile flag
leaks out and prevents (in certain compile scenarios) linking
`mlir_c_runner_utils`.
Commit: d43b06709c11998c63d1c7880c8670fa9a65dfca
https://github.com/llvm/llvm-project/commit/d43b06709c11998c63d1c7880c8670fa9a65dfca
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M mlir/lib/Dialect/Bufferization/Transforms/TensorCopyInsertion.cpp
Log Message:
-----------
[mlir][bufferize] Cleanup TensorCopyInsertion.cpp (NFC) (#164541)
Commit: 865cd8ea02de68b30d2ade1bae8c7527c27093c6
https://github.com/llvm/llvm-project/commit/865cd8ea02de68b30d2ade1bae8c7527c27093c6
Author: Nathan Gauër <brioche at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/include/clang/AST/Attr.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/semantics/semantic-struct-1.hlsl
A clang/test/CodeGenHLSL/semantics/semantic-struct-2.hlsl
A clang/test/CodeGenHLSL/semantics/semantic-struct-nested-inherit.hlsl
A clang/test/CodeGenHLSL/semantics/semantic-struct-nested-shadow.hlsl
A clang/test/CodeGenHLSL/semantics/semantic-struct-nested.hlsl
M clang/test/SemaHLSL/Semantics/entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/position.ps.hlsl
A clang/test/SemaHLSL/Semantics/position.ps.struct.hlsl
A clang/test/SemaHLSL/Semantics/struct_input.hlsl
M clang/utils/TableGen/ClangAttrEmitter.cpp
Log Message:
-----------
[HLSL] Allow input semantics on structs (#159047)
This PR is an incremental improvement regarding semantics I/O in HLSL.
This PR allows
system semantics to be used on struct type in addition to parameters
(state today).
This PR doesn't consider implicit indexing increment that happens when
placing a semantic on an aggregate/array as implemented system semantics
don't allow such use yet.
The next step will be to enable user semantics, which will bring the
need to properly determine semantic indices depending on context.
This PR diverge from the initial wg-hlsl proposal as all diagnostics are
done in Sema (initial proposal suggested running diags in codegen).
This is not yet a solid semantic implementation, but increases the test
coverage and improves the status from where we are now.
Commit: 2d18c498b004fe3553d444c54dfe5e2993faa7a9
https://github.com/llvm/llvm-project/commit/2d18c498b004fe3553d444c54dfe5e2993faa7a9
Author: Jorn Tuyls <jorn.tuyls at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/test/Dialect/MemRef/value-bounds-op-interface-impl.mlir
Log Message:
-----------
[MemRef] Implement value bounds interface for ExpandShapeOp (#164438)
Commit: 0ba6d6d41659fd375a43f1a646ffab7c075637f8
https://github.com/llvm/llvm-project/commit/0ba6d6d41659fd375a43f1a646ffab7c075637f8
Author: David Green <david.green at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/load-zext-bitcast.ll
Log Message:
-----------
[AArch64] Correct am_indexed used in bitcast loadext patterns. (#164588)
The i8 versions were using the wrong index modes, we didn't have enough
test cases.
Commit: 5c30a5c7b8d9cb885cf636c656d2849881a61532
https://github.com/llvm/llvm-project/commit/5c30a5c7b8d9cb885cf636c656d2849881a61532
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
Log Message:
-----------
[ExecutionEngine] Call hash_combine_range with a range (NFC) (#164755)
We can pass a range directly to hash_combine_range these days.
Commit: d7c87c71b8caae4bc6b18b909c3d0cfe83c87fce
https://github.com/llvm/llvm-project/commit/d7c87c71b8caae4bc6b18b909c3d0cfe83c87fce
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/docs/TableGen/index.rst
Log Message:
-----------
[llvm] Proofread TableGen/index.rst (#164756)
Commit: c5f1c694ac2bbb07887abd88983bf4bec00830fe
https://github.com/llvm/llvm-project/commit/c5f1c694ac2bbb07887abd88983bf4bec00830fe
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/DebugObjectManagerPlugin.h
M llvm/include/llvm/ExecutionEngine/Orc/Debugging/PerfSupportPlugin.h
M llvm/include/llvm/ExecutionEngine/Orc/EPCGenericRTDyldMemoryManager.h
M llvm/include/llvm/ExecutionEngine/Orc/IndirectionUtils.h
M llvm/include/llvm/ExecutionEngine/Orc/Layer.h
M llvm/include/llvm/ExecutionEngine/Orc/LinkGraphLinkingLayer.h
M llvm/include/llvm/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h
M llvm/include/llvm/ExecutionEngine/Orc/SimpleRemoteEPC.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/ExecutorSharedMemoryMapperService.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/SimpleExecutorDylibManager.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/SimpleExecutorMemoryManager.h
M llvm/include/llvm/ExecutionEngine/Orc/TaskDispatch.h
M llvm/lib/ExecutionEngine/JITLink/JITLinkMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
M llvm/unittests/ExecutionEngine/JITLink/JITLinkTestUtils.h
M llvm/unittests/ExecutionEngine/Orc/EPCGenericMemoryAccessTest.cpp
M llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp
M llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.h
M llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ResourceTrackerTest.cpp
Log Message:
-----------
[ExecutionEngine] Add "override" where appropriate (NFC) (#164757)
Note that "override" makes "virtual" redundant.
Identified with modernize-use-override.
Commit: 9c7b3047c428147eec84914d1bb2e103db28de98
https://github.com/llvm/llvm-project/commit/9c7b3047c428147eec84914d1bb2e103db28de98
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/test/ThinLTO/X86/devirt_external_comdat_same_guid.ll
Log Message:
-----------
[WPD] Reduce ThinLTO link time by avoiding unnecessary summary analysis (#164046)
We are scanning through every single definition of a vtable across all
translation units which is unnecessary in most cases.
If this is a local, we want to make sure there isn't another local with
the same GUID due to it having the same relative path. However, we were
always scanning through every single summary in all cases.
We can now check the new HasLocal flag added in PR164647 ahead of the
loop,
instead of checking on every iteration.
This cut down a large thin link by around 6%, which was over half the
time it spent in WPD.
Note that we previously took the last conforming vtable summary, and now
we use the first. This caused a test difference in one somewhat
contrived test for vtables in comdats.
Commit: 1c33b820719cbc506c70e100592b732a991cfd89
https://github.com/llvm/llvm-project/commit/1c33b820719cbc506c70e100592b732a991cfd89
Author: Shawn K <kimshawn02 at icloud.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/avx2intrin.h
M clang/lib/Headers/tmmintrin.h
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/ssse3-builtins.c
Log Message:
-----------
[Clang] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - allow MMX/SSE/AVX2 PSIGN intrinsics to be used in constexpr (#163685)
Fix #155812
Commit: fedbe384519115b25b193db2882b18b6bf253eaa
https://github.com/llvm/llvm-project/commit/fedbe384519115b25b193db2882b18b6bf253eaa
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/include/clang/AST/StmtOpenACC.h
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
A clang/test/CIR/CodeGenOpenACC/atomic-write.cpp
Log Message:
-----------
[OpenACC][CIR] Implement atomic-write lowering (#164627)
This is a slightly more complicated variant of this, which supports 'x =
expr', so the right hand side is an r-value. This patch implements that,
adds some tests, and does some minor refactoring to the infrastructure
added for the 'atomic read' to make it more flexible for 'write'.
This is the second of four 'atomic' kinds.
Commit: 5d7da0a5cd0031e4a3e4f685e061a0dc6d599ae9
https://github.com/llvm/llvm-project/commit/5d7da0a5cd0031e4a3e4f685e061a0dc6d599ae9
Author: Timur Golubovich <timur.golubovich at syntacore.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M lldb/source/Core/DumpDataExtractor.cpp
M lldb/test/API/commands/memory/read/TestMemoryRead.py
M lldb/test/API/commands/memory/read/main.c
Log Message:
-----------
[lldb] Added a warning in case of instruction decode failure (#164413)
While testing baremetal lldb, I came across a situation that if an
instruction could not be disassembled, lldb will print nothing as an
output which might be a bit strange. I added at least printing warning
in this case.
Commit: 45f97f71aff8c22f1880e817b6f05ae6ae3afa72
https://github.com/llvm/llvm-project/commit/45f97f71aff8c22f1880e817b6f05ae6ae3afa72
Author: A. Jiang <de34 at live.cn>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M libcxx/docs/Status/Cxx17Issues.csv
M libcxx/docs/Status/Cxx17Papers.csv
M libcxx/docs/Status/Cxx20Issues.csv
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/docs/Status/Cxx23Papers.csv
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/docs/Status/Cxx2cPapers.csv
Log Message:
-----------
[libc++][docs] Add missing column headers for GitHub issues (#164745)
We started to list GitHub issues in the status CSV tables/pages due to
e0d0b90d52f54f291c1042046ddf22e925408235. However, the changes made
existing column header insufficient. We probably need to add new column
headers for GitHub issues.
Commit: 9a5ae34eb6e90c51e2231ceb1a8cf933341f3222
https://github.com/llvm/llvm-project/commit/9a5ae34eb6e90c51e2231ceb1a8cf933341f3222
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TargetEnv.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaProfileCompliance.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/lib/Dialect/Tosa/IR/TargetEnv.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Add support for matmul_t_block_scaled (#163433)
This commit adds support for the MATMUL_T_BLOCK_SCALED operation from
the EXT_MXFP extension. This includes:
- Operation definition in TosaOps.td
- Micro-scaling supported types definition
- Shape inference and verifiers
- Validation pass checks to ensure usage is only valid when the target
environment includes ext-mxfp and at least v1.1.draft of the
specification.
As part of this commit, a notion of EXT_MXFP is also added. The
extension can be specified as part of the target environment and can
only be used if the specification version is at least 1.1.
Note: currently it excludes support for mxint8. This will be added in a
later commit.
Note: this commit adds support as defined in the spec in
https://github.com/arm/tosa-specification/commit/063846a75b9687ab01e58cb3538472bffb3a03b0.
EXT_MXFP extension is considered experimental and subject to breaking
change.
Co-authored-by: Tat Wai Chong <tatwai.chong at arm.com>
Commit: 917d1f20aecfdbdc9e5a7a0eaf947ff7be6fbe15
https://github.com/llvm/llvm-project/commit/917d1f20aecfdbdc9e5a7a0eaf947ff7be6fbe15
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
Log Message:
-----------
Silence "not all control paths return a value" warning; NFC
Commit: faf7af864f9258768133894764f1fae58d43bb09
https://github.com/llvm/llvm-project/commit/faf7af864f9258768133894764f1fae58d43bb09
Author: Chad Smith <cssmith at fb.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
R lldb/test/Shell/lldb-server/TestErrorMessages.test
A lldb/test/Shell/lldb-server/TestGdbserverErrorMessages.test
A lldb/test/Shell/lldb-server/TestPlatformErrorMessages.test
A lldb/test/Shell/lldb-server/TestPlatformHelp.test
A lldb/test/Shell/lldb-server/TestPlatformSuccessfulStartup.test
M lldb/tools/lldb-server/CMakeLists.txt
A lldb/tools/lldb-server/PlatformOptions.td
M lldb/tools/lldb-server/lldb-platform.cpp
Log Message:
-----------
[lldb] update lldb-server platform help parsing (#162730)
The lldb-server platform help text is inconsistent with lldb-server
gdbserver help text. This PR modernizes the platform server to use
LLVM's [TableGen](https://llvm.org/docs/TableGen/)-based option parsing
(matching the existing gdbserver implementation), which auto-generates
option parsing code and help text.
The changes improve documentation quality by adding comprehensive option
descriptions,, adding support for `-h`/`--help` flags, and organizing
help output with DESCRIPTION and EXAMPLES sections. Internal-only
options (`--child-platform-fd`) and unused legacy options (`--debug`,
`--verbose`) are now hidden from help while maintaining backward
compatibility. All functional behavior remains unchanged—this is purely
a documentation and code modernization improvement.
## before
```
> /opt/llvm/bin/lldb-server p -h
p: unrecognized option '-h'
Usage:
/opt/llvm/bin/lldb-server p [--log-file log-file-name] [--log-channels log-channel-list] [--port-file port-file-path] --server --listen port
```
## after
```
lldb-server p -h
OVERVIEW: lldb-server platform
USAGE: lldb-server p [options] --listen <[host]:port> [[--] program args...]
CONNECTION OPTIONS:
--gdbserver-port <port> Port to use for spawned gdbserver instances. If 0 or unspecified, a port will be chosen automatically. Short form: -P
--listen <[host]:port> Host and port to listen on. Format: [host]:port or protocol://[host]:port (e.g., tcp://localhost:1234, unix:///path/to/socket). Short form: -L
--socket-file <path> Write listening socket information (port number for TCP or path for Unix domain sockets) to the specified file. Short form: -f
GENERAL OPTIONS:
--help Display this help message and exit.
--log-channels <channel1 categories...:channel2 categories...>
Channels to log. A colon-separated list of entries. Each entry starts with a channel followed by a space-separated list of categories. Common channels: lldb, gdb-remote, platform, process. Short form: -c
--log-file <file> Destination file to log to. If empty, log to stderr. Short form: -l
--server Run in server mode, accepting multiple client connections sequentially. Without this flag, the server exits after handling the first connection.
OPTIONS:
-- program args Arguments to pass to launched gdbserver instances.
DESCRIPTION
Acts as a platform server for remote debugging. When LLDB clients connect,
the platform server handles platform operations (file transfers, process
launching) and spawns debug server instances (lldb-server gdbserver) to
handle actual debugging sessions.
By default, the server exits after handling one connection. Use --server
to keep running and accept multiple connections sequentially.
EXAMPLES
# Listen on port 1234, exit after first connection
lldb-server platform --listen tcp://0.0.0.0:1234
# Listen on port 5555, accept multiple connections
lldb-server platform --server --listen tcp://localhost:5555
# Listen on Unix domain socket
lldb-server platform --listen unix:///tmp/lldb-server.sock
```
For comparison, here is the **gdbserver** help text:
```
lldb-server g -h
OVERVIEW: lldb-server
USAGE: lldb-server g[dbserver] [options] [[host]:port] [[--] program args...]
CONNECTION:
--fd <fd> Communicate over the given file descriptor.
--named-pipe <name> Write port lldb-server will listen on to the given named pipe.
--pipe <fd> Write port lldb-server will listen on to the given file descriptor.
--reverse-connect Connect to the client instead of passively waiting for a connection. In this case [host]:port denotes the remote address to connect to.
GENERAL OPTIONS:
--help Prints out the usage information for lldb-server.
--log-channels <channel1 categories...:channel2 categories...>
Channels to log. A colon-separated list of entries. Each entry starts with a channel followed by a space-separated list of categories.
--log-file <file> Destination file to log to. If empty, log to stderr.
--setsid Run lldb-server in a new session.
TARGET SELECTION:
--attach <pid-or-name> Attach to the process given by a (numeric) process id or a name.
-- program args Launch program for debugging.
DESCRIPTION
lldb-server connects to the LLDB client, which drives the debugging session.
If no connection options are given, the [host]:port argument must be present
and will denote the address that lldb-server will listen on. [host] defaults
to "localhost" if empty. Port can be zero, in which case the port number will
be chosen dynamically and written to destinations given by --named-pipe and
--pipe arguments.
If no target is selected at startup, lldb-server can be directed by the LLDB
client to launch or attach to a process.
```
Commit: 536bd7214848a75594bb72ab01e02d13d54fb359
https://github.com/llvm/llvm-project/commit/536bd7214848a75594bb72ab01e02d13d54fb359
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/include/clang/AST/StmtOpenACC.h
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
Log Message:
-----------
[NFC] Rename 'Expr' to 'RefExpr' to fix the build warnings (#164828)
I used 'expr' since that is what it is in the standard, but that
obviously conflicts with our warnings on some build bots. This patch
fixes that by renaming it.
Commit: 0ac4a715f55ed860268740ad5f5535161b6cb552
https://github.com/llvm/llvm-project/commit/0ac4a715f55ed860268740ad5f5535161b6cb552
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[bazel][lldb] Port #162730: tablegen for lldb-server platform ops (#164832)
Commit: d130f402642fba3d065aacb506cb061c899558de
https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de
Author: Kees Cook <kees at kernel.org>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.h
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/test/CodeGen/ARM/O3-pipeline.ll
A llvm/test/CodeGen/ARM/kcfi-arm.ll
A llvm/test/CodeGen/ARM/kcfi-cbz-range.ll
A llvm/test/CodeGen/ARM/kcfi-patchable-function-prefix.ll
A llvm/test/CodeGen/ARM/kcfi-thumb.ll
A llvm/test/CodeGen/ARM/kcfi-thumb2.ll
R llvm/test/CodeGen/ARM/kcfi.ll
Log Message:
-----------
[ARM][KCFI] Add backend support for Kernel Control-Flow Integrity (#163698)
Implement KCFI (Kernel Control Flow Integrity) backend support for
ARM32, Thumb2, and Thumb1. The Linux kernel has supported ARM KCFI via
Clang's generic KCFI implementation, but this has finally started to
[cause problems](https://github.com/ClangBuiltLinux/linux/issues/2124)
so it's time to get the KCFI operand bundle lowering working on ARM.
Supports patchable-function-prefix with adjusted load offsets. Provides
an instruction size worst case estimate of how large the KCFI bundle is
so that range-limited instructions (e.g. cbz) know how big the indirect
calls can become.
ARM implementation notes:
- Four-instruction EOR sequence builds the 32-bit type ID byte-by-byte
to work within ARM's modified immediate encoding constraints.
- Scratch register selection: r12 (IP) is preferred, r3 used as fallback
when r12 holds the call target. r3 gets spilled/reloaded if it is
being used as a call argument.
- UDF trap encoding: 0x8000 | (0x1F << 5) | target_reg_index, similar
to aarch64's trap encoding.
Thumb2 implementation notes:
- Logically the same as ARM
- UDF trap encoding: 0x80 | target_reg_index
Thumb1 implementation notes:
- Due to register pressure, 2 scratch registers are needed: r3 and r2,
which get spilled/reloaded if they are being used as call args.
- Instead of EOR, add/lsl sequence to load immediate, followed by
a compare.
- No trap encoding.
Update tests to validate all three sub targets.
Commit: c6073d72ee23d8cd6aa49c08edde846359e41bde
https://github.com/llvm/llvm-project/commit/c6073d72ee23d8cd6aa49c08edde846359e41bde
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
Log Message:
-----------
[LoopCacheAnalysis] Drop incorrect nowrap flags from addrec (#164796)
This patch stops propagating nowrap flags unconditionally. In the
modified part, when we have an addrec `{%a,+,%b}` where `%b` is known to
be negative, we create a new addrec `{%a,+,(-1 * %b)}`. When creating
it, the nowrap flags are transferred from the original addrec to the new
one without any checks, which is generally incorrect. Since the nowrap
property is not essential for this analysis, it would be better to drop
it to avoid potential bugs.
Commit: 150145486e82c8da581f94cdceceb2652d644825
https://github.com/llvm/llvm-project/commit/150145486e82c8da581f94cdceceb2652d644825
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
M mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp
A mlir/test/Conversion/GPUToLLVMSPV/printf.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/gpu_printf.mlir
Log Message:
-----------
[MLIR][GPU] Generalize gpu.printf op lowering to LLVM call pattern. (#164297)
Existing pattern for lowering gpu.printf op to LLVM call uses fixed
function name and calling convention.
Those two should be exposed as pass option to allow supporting Intel
Compute Runtime for GPU.
Also adds gpu.printf op pattern to GPU to LLVMSPV pass.
It may appear out of place, but integration test is added to XeVM
integration test as that is the current best folder for testing with
Intel Compute Runtime.
Test should be moved in the future if a better test folder is added.
Commit: cf20a2685e1eb062e8c46f091797576e2a270003
https://github.com/llvm/llvm-project/commit/cf20a2685e1eb062e8c46f091797576e2a270003
Author: Andrew Ng <andrew.ng at sony.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/include/clang/Driver/CommonArgs.h
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
A clang/test/Driver/DTLTO/Inputs/dtlto-helper.py
M clang/test/Driver/DTLTO/dtlto.c
R clang/test/Driver/DTLTO/filename.py
A clang/test/Driver/DTLTO/lit.local.cfg
M clang/test/Driver/DTLTO/ps5-dtlto.c
M lld/COFF/Config.h
M lld/COFF/Driver.cpp
M lld/COFF/LTO.cpp
M lld/COFF/Options.td
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/Options.td
M lld/docs/DTLTO.rst
M llvm/include/llvm/LTO/LTO.h
M llvm/lib/LTO/LTO.cpp
M llvm/test/ThinLTO/X86/dtlto/json.ll
M llvm/tools/llvm-lto2/llvm-lto2.cpp
Log Message:
-----------
[DTLTO][Clang][LLD] Fix DTLTO for multi-call LLVM driver toolchain (#162456)
Add DTLTO linker option `--thinlto-remote-compiler-prepend-arg` to
enable support for the multi-call LLVM driver that requires an
additional option to specify the subcommand, e.g. "llvm clang ...".
Fixes https://github.com/llvm/llvm-project/issues/159125.
Commit: 6058c0cf4383149e4f0f61a6786d2a4dd6bd301a
https://github.com/llvm/llvm-project/commit/6058c0cf4383149e4f0f61a6786d2a4dd6bd301a
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.h
Log Message:
-----------
[NFC][clang][OpenMP] Cleanup leftover unused CodeGen functions (#164767)
Commit: c13ac9cadf1f9b4fa886b82d1e84a5feb0439023
https://github.com/llvm/llvm-project/commit/c13ac9cadf1f9b4fa886b82d1e84a5feb0439023
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/x86.c
Log Message:
-----------
[Compiler-rt] Fix wrong assignment in compiler_rt (#164713)
The `INTEL_CLEARWATERFOREST` belongs to `ProcessorTypes` enum, but it
was assigned to `Subtype` value, leading to cpu_specific/cpu_dispatch
not recognizing CWF. The type for `Subtype` and `Type` are changed to
respective enums to guard against these sort of errors in the future
Commit: 7ca1472df011a3a7c341f7a866e68b2308d12442
https://github.com/llvm/llvm-project/commit/7ca1472df011a3a7c341f7a866e68b2308d12442
Author: Marco Elver <elver at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticASTKinds.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/alloc-token.cpp
Log Message:
-----------
[Clang] Implement constexpr evaluation for __builtin_infer_alloc_token() (#163639)
Implement the constexpr evaluation for `__builtin_infer_alloc_token()`
in Clang's constant expression evaluators (both in ExprConstant and the
new bytecode interpreter).
The constant evaluation is only supported for stateless (hash-based)
token modes. If a stateful mode like `increment` is used, the evaluation
fails, as the token value is not deterministic at compile time.
Commit: 213b8a9f18742b2327be177b34eba42d4aedcc4c
https://github.com/llvm/llvm-project/commit/213b8a9f18742b2327be177b34eba42d4aedcc4c
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
Log Message:
-----------
[NFC][LLVM] Namespace cleanup in MergeICmps (#163761)
Commit: 71b21b5391b267f10c8222fbbe73494fbce6dd86
https://github.com/llvm/llvm-project/commit/71b21b5391b267f10c8222fbbe73494fbce6dd86
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/test/CIR/CodeGen/try-catch.cpp
Log Message:
-----------
[CIR] Move alloca from cir.try to the surrounding cir.scope (#164488)
Upstream moving the allocas from cir.try block to the surrounding
cir.scope
Issue https://github.com/llvm/llvm-project/issues/154992
Commit: 7731156f30c6e7731e08b4ff52d262be10f93b16
https://github.com/llvm/llvm-project/commit/7731156f30c6e7731e08b4ff52d262be10f93b16
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
A clang/test/SemaOpenMP/openmp-begin-declare-variant_template.cpp
Log Message:
-----------
[clang] OpenMP: fix variant template mismatch crash (#164511)
This ammends the fix commited in https://reviews.llvm.org/D109770 /
6cf6fa6ef1c28
Comparing the number of template parameter lists with the number of
template parameters is obviously wrong.
Even then, the number of parameters being the same doesn't mean the
templates are compatible.
This change compares if the template parameters are actually equivalent.
This fixes the crash, but I am not sure what is the design and intention
here, this openmp template support looks too fragile.
The added test case still doesn't work, but at least we don't crash now.
Commit: d8d80b659a2b36cda574733abe5446c9f9773524
https://github.com/llvm/llvm-project/commit/d8d80b659a2b36cda574733abe5446c9f9773524
Author: wdx727 <wudexin at kuaishou.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/docs/Extensions.rst
A llvm/include/llvm/CodeGen/MachineBlockHashInfo.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/MCContext.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CMakeLists.txt
A llvm/lib/CodeGen/MachineBlockHashInfo.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/test/CodeGen/X86/basic-block-address-map-empty-function.ll
M llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll
M llvm/test/CodeGen/X86/basic-block-address-map-pgo-features.ll
M llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-emit-bb-hash.ll
M llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll
M llvm/test/CodeGen/X86/basic-block-address-map.ll
Log Message:
-----------
Adding Matching and Inference Functionality to Propeller-PR2 (#162963)
Adding Matching and Inference Functionality to Propeller. For detailed
information, please refer to the following RFC:
https://discourse.llvm.org/t/rfc-adding-matching-and-inference-functionality-to-propeller/86238.
This is the second PR, which includes the calculation of basic block
hashes and their emission to the ELF file. It is associated with the
previous PR at https://github.com/llvm/llvm-project/pull/160706.
co-authors: lifengxiang1025
[lifengxiang at kuaishou.com](mailto:lifengxiang at kuaishou.com); zcfh
[wuminghui03 at kuaishou.com](mailto:wuminghui03 at kuaishou.com)
Co-authored-by: lifengxiang1025 <lifengxiang at kuaishou.com>
Co-authored-by: zcfh <wuminghui03 at kuaishou.com>
Co-authored-by: Rahman Lavaee <rahmanl at google.com>
Commit: 01498648143c6de409e9c3672ef373189ba97e35
https://github.com/llvm/llvm-project/commit/01498648143c6de409e9c3672ef373189ba97e35
Author: NohHyeon Kwon <96061253+swote-git at users.noreply.github.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
A clang/test/Preprocessor/cxx_oper_comma.cpp
Log Message:
-----------
[clang][test] Add test for comma operator rejection in preprocessor conditionals (#155570)
Add test coverage to ensure comma operators remain properly rejected in
`#if` directives.
Per CWG 1436, comma is not among the permitted operators in preprocessor
conditional expressions. This test prevents regressions and clarifies
the intended behavior.
Fixes #132822
Commit: 930b36cfbbc873fe6c329b95e1c56c6ae1ea1d94
https://github.com/llvm/llvm-project/commit/930b36cfbbc873fe6c329b95e1c56c6ae1ea1d94
Author: Chad Smith <cssmith at fb.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M lldb/test/Shell/lldb-server/TestPlatformErrorMessages.test
M lldb/test/Shell/lldb-server/TestPlatformHelp.test
Log Message:
-----------
[lldb] fix lldb-server test failures on windows (#164843)
Fix windows test failures from
https://github.com/llvm/llvm-project/pull/162730 by including and
optional .exe on the lldb-server name. Still passes on linux, but should
pass on windows now.
```
> bin/llvm-lit -v tools/lldb/test/Shell/lldb-server/
llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/config.py:531: note: using clang: llvm-project/build/bin/clang
llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/config.py:531: note: using ld.lld: /usr/bin/ld.lld
llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/config.py:531: note: using lld-link: /usr/bin/lld-link
llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/config.py:531: note: using ld64.lld: /usr/bin/ld64.lld
llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/config.py:531: note: using wasm-ld: /usr/bin/wasm-ld
llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/subst.py:126: note: Did not find obj2yaml in llvm-project/build/./bin:llvm-project/build/./bin
llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/subst.py:126: note: Did not find llvm-objdump in llvm-project/build/./bin:llvm-project/build/./bin
llvm-lit: llvm-project/lldb/test/Shell/lit.cfg.py:125: warning: Could not set a default per-test timeout. Requires the Python psutil module but it could not be found. Try installing it via pip or via your operating system's package manager.
-- Testing: 4 tests, 4 workers --
PASS: lldb-shell :: lldb-server/TestGdbserverErrorMessages.test (1 of 4)
PASS: lldb-shell :: lldb-server/TestPlatformHelp.test (2 of 4)
PASS: lldb-shell :: lldb-server/TestPlatformErrorMessages.test (3 of 4)
PASS: lldb-shell :: lldb-server/TestPlatformSuccessfulStartup.test (4 of 4)
Testing Time: 1.10s
Total Discovered Tests: 4
Passed: 4 (100.00%)
1 warning(s) in tests
```
Commit: 1031f1b293cad13465888722470966ea4b641386
https://github.com/llvm/llvm-project/commit/1031f1b293cad13465888722470966ea4b641386
Author: Anchu Rajendran S <asudhaku at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M flang/lib/Frontend/FrontendActions.cpp
M flang/test/CMakeLists.txt
M flang/test/Driver/lto-bc.f90
Log Message:
-----------
[Flang][Driver] Emit module summary for Full LTO (#164302)
This PR enables module summary for Full LTO. Module summaries are
enabled by default for Full LTO in clang, this change makes the flang
behaviour consistent. Reference PR: https://reviews.llvm.org/D34156
Commit: ede9dd3951e29632a29e13b2fd8c4b6b9d185643
https://github.com/llvm/llvm-project/commit/ede9dd3951e29632a29e13b2fd8c4b6b9d185643
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/test/CIR/CodeGen/dynamic-cast-exact.cpp
Log Message:
-----------
[CIR] Handle dynamic cast to null (#164732)
This adds support for handling dynamic casts that are known at compile
time to always result in a null pointer. For pointer casts, this emits a
null pointer value. For reference casts, it calls the __bad_cast
function.
Commit: 1ab6c0d60c52539b77e1cbfdc7f1ba47ad140b8d
https://github.com/llvm/llvm-project/commit/1ab6c0d60c52539b77e1cbfdc7f1ba47ad140b8d
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp
A clang/test/Modules/explicit-build-cwd.c
Log Message:
-----------
[clang] Make explicitly-built modules independent of the CWD (#164840)
PR https://github.com/llvm/llvm-project/pull/150123 changed how we
normalize the modules cache path. Unfortunately, empty path would get
normalized to the current working directory. This means that even
explicitly-built PCMs that don't rely on the CWD now embed it, leading
to surprising behavior. This PR fixes that by normalizing an empty
modules cache path to an empty string.
Commit: 38473c5d351d6b2ae21b5eb1ce66c2bcc2f7c6f7
https://github.com/llvm/llvm-project/commit/38473c5d351d6b2ae21b5eb1ce66c2bcc2f7c6f7
Author: Ian Anderson <iana at apple.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
M clang-tools-extra/clangd/index/CanonicalIncludes.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/__float_float.h
A clang/lib/Headers/__float_header_macro.h
A clang/lib/Headers/__float_infinity_nan.h
M clang/lib/Headers/float.h
M clang/lib/Headers/module.modulemap
A clang/test/Headers/floatneeds.c
M clang/test/Modules/relative-resource-dir.m
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[clang][headers] Need a way for math.h to share the definitions of INIFINITY and NAN with float.h (#164348)
In C23 mode, both float.h and math.h are required to define INIFINITY
and NAN. However, with clang modules, there needs to be a single owner
for the declarations. Let that be float.h since that's the suggested
true owner in Annex F.2.2 of ISO/IEC 9899:2024, and introduce
`__need_infinity_nan` so that math.h can pick up the compiler
definitions.
Commit: 1c53bfc635b1138a549d7ff82425af91aa9db512
https://github.com/llvm/llvm-project/commit/1c53bfc635b1138a549d7ff82425af91aa9db512
Author: Zack Johnson <zacklj89 at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
Log Message:
-----------
[compiler-rt][ASan] Define SANITIZER_INTERCEPT_WCSNLEN (#164845)
Follow up to #162028
`SANITIZER_INTERCEPT_WCSNLEN` is not defined, so `internal_wcsnlen` is
always used instead of using `REAL(wcsnlen)` if intercepted.
Commit: 2b42c6c163f8520e5a279d6b995907ab606c8600
https://github.com/llvm/llvm-project/commit/2b42c6c163f8520e5a279d6b995907ab606c8600
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/test/CodeGen/DirectX/CBufferAccess/unused.ll
Log Message:
-----------
[DirectX] Use a well-formed cbuffer in the unused cbuffer test (#164844)
CBuffers still need a layout type for now. Fix the crash when looking up
the cbuffer info.
Commit: 2b6686f2cd4424d22905a67afee7b0c514fa9042
https://github.com/llvm/llvm-project/commit/2b6686f2cd4424d22905a67afee7b0c514fa9042
Author: jofrn <jofernau at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/atomic-load-store.ll
Log Message:
-----------
[X86] Manage atomic load of fp -> int promotion in DAG (#148895)
When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.
Commit: 10bec2cd9dab796d5685fa8aadf47b912e3558fe
https://github.com/llvm/llvm-project/commit/10bec2cd9dab796d5685fa8aadf47b912e3558fe
Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/docs/CommandGuide/llvm-ir2vec.rst
M llvm/include/llvm/CodeGen/MIR2Vec.h
A llvm/test/tools/llvm-ir2vec/entities.mir
A llvm/test/tools/llvm-ir2vec/output/lit.local.cfg
A llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
A llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
A llvm/test/tools/llvm-ir2vec/triplets.mir
M llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp
Log Message:
-----------
[llvm-ir2vec][MIR2Vec] Supporting MIR mode in triplet and entity generation (#164329)
Add support for Machine IR (MIR) triplet and entity generation in llvm-ir2vec.
This change extends llvm-ir2vec to support Machine IR (MIR) in addition to LLVM IR, enabling the generation of training data for MIR2Vec embeddings. MIR2Vec provides machine-level code embeddings that capture target-specific instruction semantics, complementing the target-independent IR2Vec embeddings.
- Extended llvm-ir2vec to support triplet and entity generation for Machine IR (MIR)
- Added `--mode=mir` option to specify MIR mode (vs LLVM IR mode)
- Implemented MIR triplet generation with Next and Arg relationships
- Added entity mapping generation for MIR vocabulary
- Updated documentation to explain MIR-specific features and usage
(Partially addresses #162200 ; Tracking issue - #141817)
Commit: 83f751a001fa57dd8eaa60f08ed420e90170e11d
https://github.com/llvm/llvm-project/commit/83f751a001fa57dd8eaa60f08ed420e90170e11d
Author: Florian Mayer <fmayer at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Models/UncheckedStatusOrAccessModel.cpp
M clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp
Log Message:
-----------
[FlowSensitive] [StatusOr] [6/N] support pointer comparison (#164856)
Commit: 4d80e0c4446b3bd1c2ae2583be8dc545e5a4e0b9
https://github.com/llvm/llvm-project/commit/4d80e0c4446b3bd1c2ae2583be8dc545e5a4e0b9
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Semantics/openmp-utils.cpp
Log Message:
-----------
[flang][OpenMP] Add missing forward declarations and includes (#164860)
Add declarations/includes of Scope and Symbol to Semantics/openmp-utils.
Commit: c20835b4c978e1f20628186223e1ce27db757df2
https://github.com/llvm/llvm-project/commit/c20835b4c978e1f20628186223e1ce27db757df2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
Log Message:
-----------
[ARM] Fix a warning
This patch fixes:
llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1643:9: error: unused variable
'T2SOImmVal' [-Werror,-Wunused-variable]
Commit: b08bbe5ada92e7bebac8bf9ebe362fd1d2265ca6
https://github.com/llvm/llvm-project/commit/b08bbe5ada92e7bebac8bf9ebe362fd1d2265ca6
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
Log Message:
-----------
[ARM][KFCI] Fix unused variable for #163698 (#164857)
Commit: e665f245f501a5cb9e33e67085ddc9507959d5bb
https://github.com/llvm/llvm-project/commit/e665f245f501a5cb9e33e67085ddc9507959d5bb
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/Passes.h
M mlir/include/mlir/Dialect/Affine/Passes.td
M mlir/lib/Dialect/Affine/Transforms/LoopUnroll.cpp
M mlir/test/Dialect/Affine/unroll.mlir
M mlir/test/Transforms/scf-loop-unroll.mlir
M mlir/test/lib/Dialect/SCF/TestLoopUnrolling.cpp
Log Message:
-----------
[mlir] Delete unroll-full option for Affine/SCF unroll pass (#164658)
Make the unroll-factor take -1 as "full" and avoid potential conflict
when passing both an explicit factor and unroll-full=true.
Commit: 3f27f5723ba36c44d2cbeddf14b00eb32f6565e2
https://github.com/llvm/llvm-project/commit/3f27f5723ba36c44d2cbeddf14b00eb32f6565e2
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/SmallVector.h
M llvm/unittests/ADT/SmallVectorTest.cpp
Log Message:
-----------
[ADT] Use `adl_begin`/`end` with `to_vector` functions (#164823)
Similar to other code in ADT / STLExtras, allow `to_vector` to work with
ranges that require ADL to find the begin/end iterators.
Commit: 0198e8f068460f292477a6797de31aa4bac736f5
https://github.com/llvm/llvm-project/commit/0198e8f068460f292477a6797de31aa4bac736f5
Author: Sam Clegg <sbc at chromium.org>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
A lld/test/wasm/lto/relocation-model.ll
M lld/wasm/LTO.cpp
Log Message:
-----------
[lld][WebAssembly] Honor command line reloc model during LTO (#164838)
This code matches what the ELF linker already does. See ae4c30a4bed from
back in 2019.
Commit: 2bb4226c7c6da0edf40b4f1b87e9a625ff2a0e31
https://github.com/llvm/llvm-project/commit/2bb4226c7c6da0edf40b4f1b87e9a625ff2a0e31
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/TableGen/intrinsic-manual-name.td
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
Log Message:
-----------
[LLVM][Intrinsics] Print note if manual name matches default name (#164716)
Print a note when the manually specified name in an intrinsic matches
the default name it would have been assigned based on the record name,
in which case the manual specification is redundant and can be
eliminated.
Also remove existing redundant manual names.
Commit: b2c8b07f79cacc9d7f37e73370475e47f4121749
https://github.com/llvm/llvm-project/commit/b2c8b07f79cacc9d7f37e73370475e47f4121749
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Parser/OpenMP/declare-reduction-multi.f90
M flang/test/Parser/OpenMP/declare-reduction-operator.f90
M flang/test/Parser/OpenMP/declare-reduction-unparse.f90
M flang/test/Parser/OpenMP/metadirective-dirspec.f90
M flang/test/Parser/OpenMP/openmp6-directive-spellings.f90
Log Message:
-----------
[flang][OpenMP] Rename some AST classes to follow spec naming, NFC (#164870)
Rename OmpTypeSpecifier to OmpTypeName, since it represents a type-name
list item. Also, OpenMP 6.0 introduced type-specifier with a different
meaning.
Rename OmpReductionCombiner to OmpCombinerExpression.
Commit: f11899f6479cebe47bcdc2cf049fa8a47991ad46
https://github.com/llvm/llvm-project/commit/f11899f6479cebe47bcdc2cf049fa8a47991ad46
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
Log Message:
-----------
[ThinLTO][WPD] Simplify check for local summary for efficiency (NFCI) (#164859)
Use the new HasLocal flag to avoid looking through all summaries to see
if there is a local copy.
Commit: a909ec64dc36ba26f103b9f1bd71dd4b9c73ed5f
https://github.com/llvm/llvm-project/commit/a909ec64dc36ba26f103b9f1bd71dd4b9c73ed5f
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
Log Message:
-----------
[ThinLTO][WPD] LICM a loop invariant check (#164862)
Move a loop invariant check out of the innermost loop. I measured a
small but consistent thin link speedup from this change for a large
target (0.75%).
Commit: c745f745b11766949cfc7326e69e3cdccf9cc893
https://github.com/llvm/llvm-project/commit/c745f745b11766949cfc7326e69e3cdccf9cc893
Author: Florian Mayer <fmayer at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Models/UncheckedStatusOrAccessModel.cpp
M clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp
Log Message:
-----------
[FlowSensitive] [StatusOr] [7/N] Support StatusOr::emplace
This always makes the StatusOr OK.
Reviewers: jvoung, Xazax-hun
Reviewed By: jvoung
Pull Request: https://github.com/llvm/llvm-project/pull/163876
Commit: ad75b3be4e187e4cc634b33d8ed638c8232c33f4
https://github.com/llvm/llvm-project/commit/ad75b3be4e187e4cc634b33d8ed638c8232c33f4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
Log Message:
-----------
[RISCV] Add AltFmtType = IS_NOT_ALTFMT to SF_VFNRCLIP_X(U)_F_QF. (#164759)
These instructions are FP instructions with SEW=8. vtype.altfmt=1 should
be considered reserved for them.
Commit: d87200e8ca2a2c593baea2e113b90bf43409b534
https://github.com/llvm/llvm-project/commit/d87200e8ca2a2c593baea2e113b90bf43409b534
Author: jofrn <jofernau at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/test/CodeGen/X86/atomic-load-store.ll
Log Message:
-----------
[X86] Add atomic vector tests for unaligned >1 sizes. (#148896)
Unaligned atomic vectors with size >1 are lowered to calls.
Adding their tests separately here.
Commit: 1c30038e5af5256aeda45946ddc0b5f801749e15
https://github.com/llvm/llvm-project/commit/1c30038e5af5256aeda45946ddc0b5f801749e15
Author: Atmn Patel <atmnp at nvidia.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][mlir] add missing type conversion when lowering atomiccas (#164865)
When lowering `atomiccas`, flang does not convert the output of the
`llvm.extract_value` op to result type expected in the expression being
lowered. This results in invalid MLIR being generated such as when the
output of the atomiccas is being used for an equality check in a `do
while` loop condition, where the `arith.cmpi` would be comparing an `i64
0` with an `i1`. This change ensures that the appropriate cast is
inserted.
Reviewers: @clementval @vzakhari
Commit: f899893c1949183d35ec986090f449d82a796b2d
https://github.com/llvm/llvm-project/commit/f899893c1949183d35ec986090f449d82a796b2d
Author: LU-JOHN <John.Lu at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU][NFC] Cleanly make 32-bit abs legal (#164837)
Cleanly make 32-bit abs legal only in SIISelLowering.cpp
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: eaedab226cfcf99b92fbfc91b502096a11b45de8
https://github.com/llvm/llvm-project/commit/eaedab226cfcf99b92fbfc91b502096a11b45de8
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in Serializer.cpp (NFC)
Commit: 2b808c0e009e60460be7c91e4770225af56d5504
https://github.com/llvm/llvm-project/commit/2b808c0e009e60460be7c91e4770225af56d5504
Author: cmtice <cmtice at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
Log Message:
-----------
[CI][Github] Install Clang in Windows container (#164519)
Downloads clang-for-windows from the LLVM releases website, decompresses
and untars the images, and leave them in C:\clang\clang-msvc\...
Temporarily downloads the 'xz' utility to decompress the downloaded
clang tarball image.
Commit: 4456afcf0bcb29d3ba5670dbc583ee5ea00a01f3
https://github.com/llvm/llvm-project/commit/4456afcf0bcb29d3ba5670dbc583ee5ea00a01f3
Author: Adrian Prantl <aprantl at apple.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M lldb/test/Shell/lldb-server/TestPlatformErrorMessages.test
M lldb/test/Shell/lldb-server/TestPlatformHelp.test
Log Message:
-----------
Revert "[lldb] fix lldb-server test failures on windows (#164843)"
This reverts commit 930b36cfbbc873fe6c329b95e1c56c6ae1ea1d94.
Reverting because it depends on 5fc40a5f2bedaf6ca3f024aa2a91c5f4ce187061.
Commit: aac036a7f6730118f0d832150243d66b603c3af3
https://github.com/llvm/llvm-project/commit/aac036a7f6730118f0d832150243d66b603c3af3
Author: Adrian Prantl <aprantl at apple.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
A lldb/test/Shell/lldb-server/TestErrorMessages.test
R lldb/test/Shell/lldb-server/TestGdbserverErrorMessages.test
R lldb/test/Shell/lldb-server/TestPlatformErrorMessages.test
R lldb/test/Shell/lldb-server/TestPlatformHelp.test
R lldb/test/Shell/lldb-server/TestPlatformSuccessfulStartup.test
M lldb/tools/lldb-server/CMakeLists.txt
R lldb/tools/lldb-server/PlatformOptions.td
M lldb/tools/lldb-server/lldb-platform.cpp
Log Message:
-----------
Revert "[lldb] update lldb-server platform help parsing (#162730)"
This reverts commit faf7af864f9258768133894764f1fae58d43bb09.
This is failing on the Darwin bots.
https://green.lab.llvm.org/job/llvm.org/view/LLDB/job/lldb-cmake/16164/changes#faf7af864f9258768133894764f1fae58d43bb09
Commit: 910cf518922305ad079211184e843a4437de89ba
https://github.com/llvm/llvm-project/commit/910cf518922305ad079211184e843a4437de89ba
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
Log Message:
-----------
[gn build] Port d8d80b659a2b
Commit: c97256d540d1903d6d884f26cdfb90467ae46b59
https://github.com/llvm/llvm-project/commit/c97256d540d1903d6d884f26cdfb90467ae46b59
Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/utils/mlgo-utils/IR2Vec/generateTriplets.py
Log Message:
-----------
[MIR2Vec] Add MIR support to triplet generator script (#164332)
Add support for MIR (Machine IR) triplet generation to the triplet gen script.
Commit: d47873784174181f1d5837f1389d23afeead734c
https://github.com/llvm/llvm-project/commit/d47873784174181f1d5837f1389d23afeead734c
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M lldb/tools/debugserver/source/MacOSX/arm64/sme_thread_status.h
Log Message:
-----------
[lldb][debugserver] fix typeo in SME ZA register
chunk enumeartions. Noticed by David Spickett.
NFC--no machine with a ZA register large enough to use this exists
today.
Commit: 4ec5852c1d9f78df2d586ad4ee7af3f087a97555
https://github.com/llvm/llvm-project/commit/4ec5852c1d9f78df2d586ad4ee7af3f087a97555
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-multi-block.ll
Log Message:
-----------
[LV] Add tests for narrowing interleave groups with multiple blocks.
Add additional test coverage for narrowInterleaveGroups with loops with
multiple blocks.
Commit: 7ac29007187e43c2b5224a0334f82800f5109a34
https://github.com/llvm/llvm-project/commit/7ac29007187e43c2b5224a0334f82800f5109a34
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/test/CodeGen/arm-acle-coproc.c
A clang/test/Driver/aarch64-v97a.c
M clang/test/Driver/arm-cortex-cpus-1.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Preprocessor/arm-target-features.c
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/include/llvm/TargetParser/ARMTargetParser.def
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/ARM/ARMArchitectures.td
M llvm/lib/Target/ARM/ARMFeatures.td
M llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
M llvm/lib/TargetParser/ARMTargetParser.cpp
M llvm/lib/TargetParser/ARMTargetParserCommon.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[ARM][AArch64] Introduce the Armv9.7-A architecture version (#163154)
This introduces the Armv9.7-A architecture version, including the
relevant command-line option for -march.
More details about the Armv9.7-A architecture version can be found at:
* https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2025
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
* https://developer.arm.com/documentation/ddi0602/2025-09/
Co-authored-by: Caroline Concatto <caroline.concatto at arm.com>
Commit: f28224b78f9ef8c0017a62b9db19338fbd051394
https://github.com/llvm/llvm-project/commit/f28224b78f9ef8c0017a62b9db19338fbd051394
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/test/Driver/aarch64-v97a.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
A llvm/test/MC/AArch64/armv9.7a-memsys.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64][llvm] Armv9.7-A: Add support for FEAT_CMH and FEAT_LSCP (#163155)
Add the following instructions to support:
* `FEAT_CMH`: Contention Management Hints extension
* `SHUH` instruction
* `FEAT_LSCP`: Load-acquire and store-release pair extension
* `STLP` instruction
* `LDAP` instruction
* `LDAPP` instruction
and system registers:
- `TLBIDIDR_EL1`
- `VTLBID<n>_EL2`
- `VTLBIDOS<n>_EL2`
as documented here:
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
* https://developer.arm.com/documentation/ddi0602/2025-09/
Co-authored-by: Martin Wehking <martin.wehking at arm.com>
Commit: 66e8270e8f3cd5a291e48097095c4f547ddf417d
https://github.com/llvm/llvm-project/commit/66e8270e8f3cd5a291e48097095c4f547ddf417d
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/test/Driver/aarch64-v97a.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
A llvm/test/MC/AArch64/armv9.7a-tlbid-diagnostics.s
A llvm/test/MC/AArch64/armv9.7a-tlbid.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64][llvm] Armv9.7-A: Add support for TLBI Domains (FEAT_TLBID) (#163156)
Allow the following `TLBI` operation types to take an optional register
operand when enabled by `FEAT_TLBID`:
- ALL*
- VMALL*
- VMALLS12*
- VMALLWS2*
as documented here:
* https://developer.arm.com/documentation/ddi0602/2025-09/
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
Notes on implementation:
Currently, AArch64 `SYS` alias instructions fall into two categories:
* a register value must be present (indicated by any value except `XZR`)
* no register value must be present (this value must be `XZR`)
When +tblid is enabled, `SYS` aliases are now allowed to take an optional
register, or no register as before. We need an extra tablegen flag to
indicate if the register is optional or not (the existing "NeedsReg" flag
is binary and not suitable; the register is either present or absent,
not either for a specific TLBI operation)
Don't produce an error message if the register operand is missing or
unexpected, if it is specified as an optional register.
Commit: d30f18d2cd464383ba5777d21219026780b0b890
https://github.com/llvm/llvm-project/commit/d30f18d2cd464383ba5777d21219026780b0b890
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/test/Driver/aarch64-v97a.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/test/MC/AArch64/armv8.4a-mpam.s
A llvm/test/MC/AArch64/armv9.7a-mpamv2-diagnostics.s
A llvm/test/MC/AArch64/armv9.7a-mpamv2.s
M llvm/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64][llvm] Armv9.7-A: Add support for Memory Partitioning and Management (FEAT_MPAMv2) (#163157)
Add new instructions and system registers for `FEAT_MPAMv2`:
* MLBI ALLE1
* MLBI VMALLE1
* MLBI VPIDE1, <Xt>
* MLBI VPMGE1, <Xt>
as documented here:
* https://developer.arm.com/documentation/ddi0602/2025-09/
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
Co-authored-by: Caroline Concatto <caroline.concatto at arm.com>
Commit: ca10dacf19d52cad8cbf6c4b5eb5dad0e265a704
https://github.com/llvm/llvm-project/commit/ca10dacf19d52cad8cbf6c4b5eb5dad0e265a704
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/test/Driver/aarch64-v97a.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
A llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s
A llvm/test/MC/AArch64/armv9.7a-mtetc.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagging (FEAT_MTETC) (#163158)
Add the following instructions for `FEAT_MTETC`, which is a part of
`FEAT_VMTE` for Virtual Tagging:
* `DC ZGBVA`
* `DC GBVA`
as documented here:
* https://developer.arm.com/documentation/ddi0602/2025-09/
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
Commit: 6836261ee4acecd14c31f8d66d746f58de87a34b
https://github.com/llvm/llvm-project/commit/6836261ee4acecd14c31f8d66d746f58de87a34b
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/test/Driver/aarch64-v97a.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
A llvm/test/MC/AArch64/armv9.7a-gcie-diagnostics.s
A llvm/test/MC/AArch64/armv9.7a-gcie.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64][llvm] Armv9.7-A: Add support for GICv5 (FEAT_GCIE) (#163159)
Add new instruction and system registers that are specified in the
Generic Interrupt Controller Architecture v5 (GICv5) standard,
announced here:
* https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/introducing-gicv5
and documented here:
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
* https://developer.arm.com/documentation/ddi0602/2025-09/
Co-authored-by: Jack Styles <jack.styles at arm.com>
Commit: ef923f1b281cf25bc8fed129e0851b178a094c56
https://github.com/llvm/llvm-project/commit/ef923f1b281cf25bc8fed129e0851b178a094c56
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
Log Message:
-----------
[AMDGPU] Change patterns for v_[pk_]add_{min|max} (#164881)
The intermediate result is in fact the add with saturation
regardless of the clamp bit.
Commit: 997af95fac7b9069e8afa5bd208e02344fab8ce3
https://github.com/llvm/llvm-project/commit/997af95fac7b9069e8afa5bd208e02344fab8ce3
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx1250_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
Log Message:
-----------
[AMDGPU] Remove validation of s_set_vgpr_msb range (#164888)
We will need the full 16-bit range of the operand to record
previous mode.
Commit: cab4c68a669df7856c9b0babf05709e10f89c7e2
https://github.com/llvm/llvm-project/commit/cab4c68a669df7856c9b0babf05709e10f89c7e2
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/test/Driver/aarch64-v97a.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/MC/AArch64/SVE2p3/arithmetic-diagnostics.s
A llvm/test/MC/AArch64/SVE2p3/arithmetic.s
A llvm/test/MC/AArch64/SVE2p3/directive-arch-negative.s
A llvm/test/MC/AArch64/SVE2p3/directive-arch_extension-negative.s
A llvm/test/MC/AArch64/SVE2p3/directive-cpu-negative.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64][llvm] Armv9.7-A: Add support for SVE2p3 arithmetic operations (#163160)
Add instructions for SVE2p3 arithmetic operations:
- `ADDQP` (add pairwise within quadword vector segments)
- `ADDSUBP` (add subtract pairwise)
- `SABAL` (two-way signed absolute difference sum and accumulate long)
- `SUBP` (subtract pairwise)
- `UABAL` (two-way unsigned absolute difference sum and accumulate long)
as documented here:
* https://developer.arm.com/documentation/ddi0602/2025-09/
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
Commit: bfae15a1257a63f205db12308ca4b131f3b3f3b3
https://github.com/llvm/llvm-project/commit/bfae15a1257a63f205db12308ca4b131f3b3f3b3
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/test/Driver/aarch64-v97a.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/MC/AArch64/SVE/bfmmla-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/sdot-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/udot-diagnostics.s
A llvm/test/MC/AArch64/SVE2p2/fmmla-diagnostics.s
A llvm/test/MC/AArch64/SVE2p2/fmmla.s
A llvm/test/MC/AArch64/SVE2p3/bfmmla-diagnostics.s
A llvm/test/MC/AArch64/SVE2p3/bfmmla.s
A llvm/test/MC/AArch64/SVE2p3/dot-diagnostics.s
A llvm/test/MC/AArch64/SVE2p3/dot.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64][llvm] Armv9.7-A: Add support for SVE2p3 DOT and MLA operations (#163161)
Add instructions for SVE2p3 DOT and MLA operations:
- BFMMLA (non-widening)
- FMMLA (non-widening)
- SDOT (2-way, vectors)
- SDOT (2-way, indexed)
- UDOT (2-way, vectors)
- UDOT (2-way, indexed)
as documented here:
* https://developer.arm.com/documentation/ddi0602/2025-09/
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
Commit: 29969c988bb9004d201e7e6280e193cbcf7aacc8
https://github.com/llvm/llvm-project/commit/29969c988bb9004d201e7e6280e193cbcf7aacc8
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/MC/AArch64/SVE2p3/cvt-diagnostics.s
A llvm/test/MC/AArch64/SVE2p3/cvt.s
Log Message:
-----------
[AArch64][llvm] Armv9.7-A: Add support for SVE2p3 CVT operations (#163162)
Add instructions for SVE2p3 CVT operations:
- FCVTZSN
- FCVTZUN
- SCVTF
- SCVTFLT
- UCVTF
- UCVTFLT
as documented here:
* https://developer.arm.com/documentation/ddi0602/2025-09/
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
Commit: 301fa24671256734df6b7ee65f23ad885400108e
https://github.com/llvm/llvm-project/commit/301fa24671256734df6b7ee65f23ad885400108e
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-multi-block.ll
Log Message:
-----------
[VPlan] Limit narrowInterleaveGroups to single block regions for now.
Currently only regions with a single block are supported by the legality
checks.
Commit: 9470c2e152c6917b8950d2d506b0a4505723011a
https://github.com/llvm/llvm-project/commit/9470c2e152c6917b8950d2d506b0a4505723011a
Author: Oliver Hunt <oliver at apple.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M clang/lib/AST/ASTContext.cpp
A clang/test/SemaCXX/ptrauth-nested-incomplete-types.cpp
Log Message:
-----------
[PAC][clang] Correct handling of ptrauth queries of incomplete types (#164528)
In normal circumstances we can never get to this point as earlier Sema
checks will have already have prevented us from making these queries.
However in some cases, for example a sufficiently large number of
errors, clang can start allowing incomplete types in records.
This means a number of the internal interfaces can end up perform type
trait queries that require querying the pointer authentication
properties of types that contain incomplete types. While the trait
queries attempt to guard against incomplete types, those tests fail in
this case as the incomplete types are actually nested in the seemingly
complete parent type.
Commit: d12ab4434cd84667a25cee6e7eddedc0ac7e4371
https://github.com/llvm/llvm-project/commit/d12ab4434cd84667a25cee6e7eddedc0ac7e4371
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s
A llvm/test/MC/AArch64/SVE2p3/qshrn.s
Log Message:
-----------
[AArch64][llvm] Armv9.7-A: Add support for SVE2p3 shift operations (#163163)
Add instructions for SVE2p3 shift operations:
- SQRSHRN
- SQRSHRUN
- SQSHRN
- SQSHRUN
- UQRSHRN
- UQSHRN
as documented here:
* https://developer.arm.com/documentation/ddi0602/2025-09/
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
Commit: 475a1c5882305357ec432c93c496fed7c8e1fcdf
https://github.com/llvm/llvm-project/commit/475a1c5882305357ec432c93c496fed7c8e1fcdf
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s
A llvm/test/MC/AArch64/SME2p3/luti6.s
A llvm/test/MC/AArch64/SVE2p3/luti6-diagnostics.s
A llvm/test/MC/AArch64/SVE2p3/luti6.s
Log Message:
-----------
[AArch64][llvm] Armv9.7-A: Add support for SVE2p3 LUTI6 operations (#163164)
Add instructions for SVE2p3 LUTI6 operations:
- LUTI6 (16-bit)
- LUTI6 (8-bit)
- LUTI6 (vector, 16-bit)
- LUTI6 (table, four registers, 8-bit)
- LUTI6 (table, single, 8-bit)
as documented here:
* https://developer.arm.com/documentation/ddi0602/2025-09/
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
Co-authored-by: Virginia Cangelosi <virginia.cangelosi at arm.com>
Commit: 09cf301384ce29312347c608db4871f21af753fc
https://github.com/llvm/llvm-project/commit/09cf301384ce29312347c608db4871f21af753fc
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-aarch64.c
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s
A llvm/test/MC/AArch64/neon-fdot-diagnostics.s
A llvm/test/MC/AArch64/neon-fdot.s
A llvm/test/MC/AArch64/neon-fmmla-HtoS-diagnostics.s
A llvm/test/MC/AArch64/neon-fmmla-HtoS.s
A llvm/test/MC/AArch64/neon-fmmla-diagnostics.s
A llvm/test/MC/AArch64/neon-fmmla.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64][llvm] Armv9.7-A: Add support for new Advanced SIMD (Neon) instructions (#163165)
Add support for new Advanced SIMD (Neon) instructions:
- FDOT (half-precision to single-precision, by element)
- FDOT (half-precision to single-precision, vector)
- FMMLA (half-precision, non-widening)
- FMMLA (widening, half-precision to single-precision)
as documented here:
* https://developer.arm.com/documentation/ddi0602/2025-09/
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
Co-authored-by: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Co-authored-by: Caroline Concatto <caroline.concatto at arm.com>
Co-authored-by: Virginia Cangelosi <virginia.cangelosi at arm.com>
Commit: 6dd78f6aefdb76ce7c82ea69813f8e92481737cd
https://github.com/llvm/llvm-project/commit/6dd78f6aefdb76ce7c82ea69813f8e92481737cd
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/test/MC/AArch64/armv8.4a-mpam.s
M llvm/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt
Log Message:
-----------
[AArch64][llvm] Remove FeatureMPAM guards for parity with gcc (#163166)
Remove `AArch64::FeatureMPAM` guards from some MPAM system registers,
since these system registers are not any under feature guard for gcc.
Commit: 7d0ce4840c1f2850de905b06d957a6dcd99c2825
https://github.com/llvm/llvm-project/commit/7d0ce4840c1f2850de905b06d957a6dcd99c2825
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
Log Message:
-----------
[AArch64] (NFC) Tidy up alignment/formatting in AArch64/AArch64InstrInfo.td (#163645)
It was noted in a code-review for earlier changes in this stack
that some of the new 9.7 entries were mis-aligned. But actually,
many of the entries were, so I've tidied them all up.
Commit: 0e8781100357b46c9ec6cd2e31a635ad2b2b3211
https://github.com/llvm/llvm-project/commit/0e8781100357b46c9ec6cd2e31a635ad2b2b3211
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M clang/test/Driver/aarch64-v96a.c
M clang/test/Driver/aarch64-v97a.c
M llvm/lib/Target/AArch64/AArch64Features.td
Log Message:
-----------
[AArch64][llvm] Relax mandatory features for Armv9.6-A (#163973)
`FEAT_FPRCVT` is moved from being mandatory in Armv9.6-A to Armv9.7-A
`FEAT_SVE2p2` is removed from being mandatory in Armv9.6-A
Commit: cea8ffa5f3412a58adc5c9c4b0ad0e31869f6e3d
https://github.com/llvm/llvm-project/commit/cea8ffa5f3412a58adc5c9c4b0ad0e31869f6e3d
Author: Thurston Dang <thurston at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M compiler-rt/lib/asan/asan_interceptors.cpp
Log Message:
-----------
[asan] Avoid -Wpointer-bool-conversion warning by comparing to nullptr (#164906)
The current code may trigger a compiler warning:
```
address of function 'wcsnlen' will always evaluate to 'true' [-Wpointer-bool-conversion]
```
Fix this by comparing to nullptr. The same fix is applied to strnlen for
future-proofing.
Commit: 169626f11ab19a0b33fba2ca84cf4d9ec2b76fb1
https://github.com/llvm/llvm-project/commit/169626f11ab19a0b33fba2ca84cf4d9ec2b76fb1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Log Message:
-----------
[RISCV] Rename RISCVISD::ABSW->NEGW_MAX. NFC (#164909)
This matches what it expands to. The P extension adds a proper ABSW
instruction so being precise is important to avoid confusion.
Commit: 6ed814a823258fa357c25bd71e76eb688fbbff79
https://github.com/llvm/llvm-project/commit/6ed814a823258fa357c25bd71e76eb688fbbff79
Author: Andrew Savonichev <andrew.savonichev at gmail.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M llvm/lib/IR/Module.cpp
M llvm/unittests/IR/ModuleTest.cpp
Log Message:
-----------
[IR] Fix Module::setModuleFlag for uniqued metadata (#164580)
`Module::setModuleFlag` is supposed to change a single module. However,
when an `MDNode` has the same value in more than one module in the same
`LLVMContext`, such `MDNode` is shared (uniqued) across all of them.
Therefore `MDNode::replaceOperandWith` changes all modules that share
the same `MDNode`.
This used to cause problems for #86212, where a module is marked as
"upgraded" via a module flag. When this flag is shared across multiple
modules, all of them are marked, yet some may not have been processed at
all.
After the patch we now construct a new `MDNode` and replace the old one.
Commit: 4a84f10554a78486e69384590582117c09154ce3
https://github.com/llvm/llvm-project/commit/4a84f10554a78486e69384590582117c09154ce3
Author: Carl Peto <carl.peto at me.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/AVR/AVRRegisterInfo.td
M llvm/test/CodeGen/AVR/dynalloca.ll
A llvm/test/CodeGen/AVR/issue-163015.ll
Log Message:
-----------
[AVR] Fix occasional corruption in stack passed params
Corruption can occur with passing parameters on the stack when under register pressure.
Fixes #163015 .
Commit: 6a0f392bb50d890f13cb961a911be28f965ed4f2
https://github.com/llvm/llvm-project/commit/6a0f392bb50d890f13cb961a911be28f965ed4f2
Author: Thurston Dang <thurston at google.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M compiler-rt/lib/asan/asan_interceptors.cpp
Log Message:
-----------
[asan] Avoid -Wtautological-pointer-compare (#164918)
https://github.com/llvm/llvm-project/pull/164906 converted a
-Wpointer-bool-conversion warning into a -Wtautological-pointer-compare
warning. Avoid both by using the bool cast.
Commit: bcee0ee68dbdcdd5e07e16303b6a5805814d1dfd
https://github.com/llvm/llvm-project/commit/bcee0ee68dbdcdd5e07e16303b6a5805814d1dfd
Author: Serge Pavlov <sepavloff at gmail.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
Log Message:
-----------
[SDAG] Fix deferring constrained function calls (#153029)
Selection DAG has a more sophisticated execution order representation
than the simple sequence used in IR, so building the DAG can take into
account specific properties of the nodes to better express possible
parallelism. The existing implementation does this for constrained
function calls, some of them are considered as independent, which can
potentially improve the generated code. However this mechanism
incorrectly implies that the calls with exception behavior 'ebIgnore'
cannot raise floating-point exception. The purpose of this change is to
fix the implementation.
In the current implementation, constrained function calls don't
immediately update the DAG root. Instead, the DAG builder collects their
output chains and flushes them when the root is required. Constrained
function calls cannot be moved across calls of external functions and
intrinsics that access floating-point environment, they work as
barriers. Between the barriers, constrained function calls can be
reordered, they may be considered independent from viewpoint of raising
exceptions. For strictfp functions this is possible only if
floating-point trapping is disabled.
This change introduces a new restriction - the calls with default
exception handling cannot not be moved between strictfp function calls.
Otherwise the exceptions raised by such call can disturb the expected
exception sequence. It means that constrained function calls with strict
exception behavior act as barriers for the calls with non-strict
behavior and vice versa. Effectively it means that the entire sequence
of constrained calls in IR is split into "strict" and "non-strict"
regions, in which restrictions on the order of constrained calls are
relaxed, but move from one region to another is not allowed. It agrees
with the representation of strictfp code in high-level languages. For
example, C/C++ strictfp code correspond to blocks where pragma `STDC
FENV_ACCESS ON` is in effect, this restriction should help preserving
the intended semantics.
When floating-point exception trapping is enabled, constrained
intrinsics with 'ebStrict' cannot be reordered, their sequence must be
identical to the original source order. The current implementation does
not distinguish between strictfp modes with trapping and without it.
This change make assumption that the trapping is disabled. It is not
correct in the general case, but is compatible with the existing
implementation.
Commit: 0341fb63f2abe2ce98434c45fef8826718f9198c
https://github.com/llvm/llvm-project/commit/0341fb63f2abe2ce98434c45fef8826718f9198c
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/include/llvm/LTO/LTO.h
M llvm/lib/LTO/LTO.cpp
Log Message:
-----------
[ThinLTO] Avoid creating map entries on lookup (NFCI) (#164873)
We could inadvertently create new entries in the PrevailingModuleForGUID
map during lookup, which was always using operator[]. In most cases we
will have one for external symbols, but not in cases where the
prevailing copy is in a native object. Or if this happened to be looked
up for a local.
Make the map private and create and use accessors.
Commit: 750a58337ee8594f5253733786e066f7941d617d
https://github.com/llvm/llvm-project/commit/750a58337ee8594f5253733786e066f7941d617d
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/LTO/LTO.cpp
Log Message:
-----------
[ThinLTO] Simplify checking for single external copy (NFCI) (#164861)
Replace a loop over all summary copies with a simple check for a single
externally available copy of a symbol. The usage of this result has
changed since it was added and we now only need to know if there is a
single one.
Commit: e4c308424f9fbde2b9429f5f977e92e289e10991
https://github.com/llvm/llvm-project/commit/e4c308424f9fbde2b9429f5f977e92e289e10991
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/unittests/Analysis/MemoryProfileInfoTest.cpp
Log Message:
-----------
[MemProf] Fix the propagation of context/size info after inlining (#164872)
In certain cases the context/size info we use for reporting of hinted
bytes in the LTO link was being dropped when we re-constructed context
tries and memprof metadata after inlining. This only affected cases
where we were using the -memprof-min-percent-max-cold-size option to
only keep that information for the largest cold contexts, and where the
pre-LTO compile did *not* specify -memprof-report-hinted-sizes.
The issue is that we don't have a MaxSize, which is only available
during the profile matching step. Use an existing bool indicating that
we are redoing this from existing metadata to always propagate any
context size metadata in that case.
Commit: 93bb5c699f9fc2e6ee26fc8f86f8bca038f58409
https://github.com/llvm/llvm-project/commit/93bb5c699f9fc2e6ee26fc8f86f8bca038f58409
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/arrays.cpp
Log Message:
-----------
[clang][bytecode] Fix CXXConstructExpr for multidim arrays (#164760)
This is a thing apparently.
Fixes https://github.com/llvm/llvm-project/issues/153803
Commit: 57ccb4624f7a8329567ec5a02962815f5617e3f1
https://github.com/llvm/llvm-project/commit/57ccb4624f7a8329567ec5a02962815f5617e3f1
Author: David Green <david.green at arm.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M llvm/test/Analysis/CostModel/ARM/add-cast-vect.ll
M llvm/test/Analysis/CostModel/ARM/cast_ldst.ll
M llvm/test/Analysis/CostModel/ARM/freeshift.ll
M llvm/test/Analysis/CostModel/ARM/gep.ll
M llvm/test/Analysis/CostModel/ARM/immediates.ll
M llvm/test/Analysis/CostModel/ARM/insertelement.ll
M llvm/test/Analysis/CostModel/ARM/load-to-trunc.ll
M llvm/test/Analysis/CostModel/ARM/load_store.ll
M llvm/test/Analysis/CostModel/ARM/logicalop.ll
M llvm/test/Analysis/CostModel/ARM/mul-cast-vect.ll
M llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll
M llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll
M llvm/test/Analysis/CostModel/ARM/select.ll
M llvm/test/Analysis/CostModel/ARM/shl-cast-vect.ll
M llvm/test/Analysis/CostModel/ARM/shuffle.ll
M llvm/test/Analysis/CostModel/ARM/sub-cast-vect.ll
Log Message:
-----------
[ARM] Update remaining cost tests with -cost-kind=all. NFC
Commit: 7c441b21b7fac52a8c28eaa4a4b829c0e5ce6d7b
https://github.com/llvm/llvm-project/commit/7c441b21b7fac52a8c28eaa4a4b829c0e5ce6d7b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Opcodes.td
M clang/test/AST/ByteCode/placement-new.cpp
Log Message:
-----------
[clang][bytecode] Catch placement-new into invalid destination (#164804)
We failed to check for null and non-block pointers.
Fixes https://github.com/llvm/llvm-project/issues/152952
Commit: 43a7c4c0abe72405fcd19d5e32eee94564cc31d1
https://github.com/llvm/llvm-project/commit/43a7c4c0abe72405fcd19d5e32eee94564cc31d1
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M bolt/README.md
M bolt/docs/Heatmaps.md
M bolt/docs/index.rst
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/X86/nolbr.s
M bolt/test/X86/pre-aggregated-perf.test
M bolt/test/perf2bolt/perf_test.test
M clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp
M clang-tools-extra/clangd/index/CanonicalIncludes.cpp
M clang-tools-extra/docs/clang-tidy/checks/bugprone/switch-missing-default-case.rst
M clang/include/clang/AST/Attr.h
A clang/include/clang/AST/InferAlloc.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/DiagnosticASTKinds.td
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Driver/CommonArgs.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/CMakeLists.txt
M clang/lib/AST/ExprConstant.cpp
A clang/lib/AST/InferAlloc.cpp
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/Analysis/FlowSensitive/Models/UncheckedStatusOrAccessModel.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.h
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/__float_float.h
A clang/lib/Headers/__float_header_macro.h
A clang/lib/Headers/__float_infinity_nan.h
M clang/lib/Headers/avx2intrin.h
M clang/lib/Headers/float.h
M clang/lib/Headers/module.modulemap
M clang/lib/Headers/tmmintrin.h
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp
M clang/test/AST/ByteCode/arrays.cpp
M clang/test/AST/ByteCode/placement-new.cpp
M clang/test/AST/ByteCode/records.cpp
A clang/test/CIR/CodeGen/builtin_prefetech.c
M clang/test/CIR/CodeGen/dynamic-cast-exact.cpp
M clang/test/CIR/CodeGen/global-init.cpp
M clang/test/CIR/CodeGen/struct-init.cpp
M clang/test/CIR/CodeGen/try-catch.cpp
A clang/test/CIR/CodeGenOpenACC/atomic-write.cpp
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/ssse3-builtins.c
M clang/test/CodeGen/arm-acle-coproc.c
A clang/test/CodeGenHLSL/semantics/semantic-struct-1.hlsl
A clang/test/CodeGenHLSL/semantics/semantic-struct-2.hlsl
A clang/test/CodeGenHLSL/semantics/semantic-struct-nested-inherit.hlsl
A clang/test/CodeGenHLSL/semantics/semantic-struct-nested-shadow.hlsl
A clang/test/CodeGenHLSL/semantics/semantic-struct-nested.hlsl
A clang/test/Driver/DTLTO/Inputs/dtlto-helper.py
M clang/test/Driver/DTLTO/dtlto.c
R clang/test/Driver/DTLTO/filename.py
A clang/test/Driver/DTLTO/lit.local.cfg
M clang/test/Driver/DTLTO/ps5-dtlto.c
M clang/test/Driver/aarch64-v96a.c
A clang/test/Driver/aarch64-v97a.c
M clang/test/Driver/arm-cortex-cpus-1.c
M clang/test/Driver/print-supported-extensions-aarch64.c
A clang/test/Headers/floatneeds.c
A clang/test/Modules/explicit-build-cwd.c
M clang/test/Modules/relative-resource-dir.m
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Preprocessor/arm-target-features.c
A clang/test/Preprocessor/cxx_oper_comma.cpp
A clang/test/SemaCXX/alloc-token.cpp
A clang/test/SemaCXX/ptrauth-nested-incomplete-types.cpp
M clang/test/SemaHLSL/Semantics/entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/position.ps.hlsl
A clang/test/SemaHLSL/Semantics/position.ps.struct.hlsl
A clang/test/SemaHLSL/Semantics/struct_input.hlsl
A clang/test/SemaOpenMP/openmp-begin-declare-variant_template.cpp
M clang/test/SemaTemplate/concepts.cpp
M clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp
M clang/unittests/Format/FormatTestObjC.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/perf-training/perf-helper.py
M compiler-rt/lib/asan/asan_interceptors.cpp
M compiler-rt/lib/builtins/cpu_model/x86.c
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/openmp-utils.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/CMakeLists.txt
M flang/test/Driver/lto-bc.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
M flang/test/Lower/math-lowering/sinh.f90
M flang/test/Lower/trigonometric-intrinsics.f90
M flang/test/Parser/OpenMP/declare-reduction-multi.f90
M flang/test/Parser/OpenMP/declare-reduction-operator.f90
M flang/test/Parser/OpenMP/declare-reduction-unparse.f90
M flang/test/Parser/OpenMP/metadirective-dirspec.f90
M flang/test/Parser/OpenMP/openmp6-directive-spellings.f90
M libcxx/docs/Status/Cxx17Issues.csv
M libcxx/docs/Status/Cxx17Papers.csv
M libcxx/docs/Status/Cxx20Issues.csv
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/docs/Status/Cxx23Papers.csv
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/docs/Status/Cxx2cPapers.csv
M lld/COFF/Config.h
M lld/COFF/Driver.cpp
M lld/COFF/LTO.cpp
M lld/COFF/Options.td
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/Options.td
M lld/docs/DTLTO.rst
A lld/test/wasm/lto/relocation-model.ll
M lld/wasm/LTO.cpp
M lldb/source/Core/DumpDataExtractor.cpp
M lldb/test/API/commands/memory/read/TestMemoryRead.py
M lldb/test/API/commands/memory/read/main.c
M lldb/tools/debugserver/source/MacOSX/arm64/sme_thread_status.h
M llvm/docs/CommandGuide/llvm-ir2vec.rst
M llvm/docs/Extensions.rst
M llvm/docs/LangRef.rst
M llvm/docs/ProgrammersManual.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/TableGen/index.rst
M llvm/include/llvm/ADT/FoldingSet.h
M llvm/include/llvm/ADT/IndexedMap.h
M llvm/include/llvm/ADT/RadixTree.h
M llvm/include/llvm/ADT/SmallVector.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/CodeGen/AtomicExpand.h
M llvm/include/llvm/CodeGen/BasicBlockSectionsProfileReader.h
M llvm/include/llvm/CodeGen/CodeGenPrepare.h
M llvm/include/llvm/CodeGen/ComplexDeinterleavingPass.h
M llvm/include/llvm/CodeGen/DwarfEHPrepare.h
M llvm/include/llvm/CodeGen/ExpandFp.h
M llvm/include/llvm/CodeGen/ExpandLargeDivRem.h
M llvm/include/llvm/CodeGen/ExpandMemCmp.h
M llvm/include/llvm/CodeGen/IndirectBrExpand.h
M llvm/include/llvm/CodeGen/InterleavedAccess.h
M llvm/include/llvm/CodeGen/InterleavedLoadCombine.h
M llvm/include/llvm/CodeGen/MIR2Vec.h
A llvm/include/llvm/CodeGen/MachineBlockHashInfo.h
M llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/CodeGen/SafeStack.h
M llvm/include/llvm/CodeGen/SelectOptimize.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/StackProtector.h
M llvm/include/llvm/CodeGen/TypePromotion.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/DebugObjectManagerPlugin.h
M llvm/include/llvm/ExecutionEngine/Orc/Debugging/PerfSupportPlugin.h
M llvm/include/llvm/ExecutionEngine/Orc/EPCGenericRTDyldMemoryManager.h
M llvm/include/llvm/ExecutionEngine/Orc/IndirectionUtils.h
M llvm/include/llvm/ExecutionEngine/Orc/Layer.h
M llvm/include/llvm/ExecutionEngine/Orc/LinkGraphLinkingLayer.h
M llvm/include/llvm/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h
M llvm/include/llvm/ExecutionEngine/Orc/SimpleRemoteEPC.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/ExecutorSharedMemoryMapperService.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/SimpleExecutorDylibManager.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/SimpleExecutorMemoryManager.h
M llvm/include/llvm/ExecutionEngine/Orc/TaskDispatch.h
M llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LTO/LTO.h
M llvm/include/llvm/MC/MCContext.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/include/llvm/TargetParser/ARMTargetParser.def
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/Analysis/InlineCost.cpp
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CGData/CodeGenDataReader.cpp
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/ExpandFp.cpp
A llvm/lib/CodeGen/MachineBlockHashInfo.cpp
M llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/ExecutionEngine/JITLink/JITLinkMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
M llvm/lib/IR/Module.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMArchitectures.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.h
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMFeatures.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/AVR/AVRRegisterInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/ARMTargetParser.cpp
M llvm/lib/TargetParser/ARMTargetParserCommon.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Analysis/CostModel/ARM/add-cast-vect.ll
M llvm/test/Analysis/CostModel/ARM/cast_ldst.ll
M llvm/test/Analysis/CostModel/ARM/fparith.ll
M llvm/test/Analysis/CostModel/ARM/fptoi_sat.ll
M llvm/test/Analysis/CostModel/ARM/freeshift.ll
M llvm/test/Analysis/CostModel/ARM/gep.ll
M llvm/test/Analysis/CostModel/ARM/immediates.ll
M llvm/test/Analysis/CostModel/ARM/insertelement.ll
R llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll
M llvm/test/Analysis/CostModel/ARM/load-to-trunc.ll
M llvm/test/Analysis/CostModel/ARM/load_store.ll
M llvm/test/Analysis/CostModel/ARM/logicalop.ll
M llvm/test/Analysis/CostModel/ARM/mul-cast-vect.ll
M llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll
M llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll
A llvm/test/Analysis/CostModel/ARM/mve-intrinsic-cost-kinds.ll
A llvm/test/Analysis/CostModel/ARM/mve-target-intrinsics.ll
M llvm/test/Analysis/CostModel/ARM/select.ll
M llvm/test/Analysis/CostModel/ARM/shl-cast-vect.ll
M llvm/test/Analysis/CostModel/ARM/shuffle.ll
M llvm/test/Analysis/CostModel/ARM/sub-cast-vect.ll
R llvm/test/Analysis/CostModel/ARM/target-intrinsics.ll
M llvm/test/Assembler/atomic.ll
M llvm/test/Bitcode/DILocation-implicit-code.ll
M llvm/test/Bitcode/drop-debug-info.3.5.ll
M llvm/test/Bitcode/upgrade-tbaa.ll
M llvm/test/CodeGen/AArch64/load-zext-bitcast.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll
M llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir
M llvm/test/CodeGen/ARM/O3-pipeline.ll
M llvm/test/CodeGen/ARM/Windows/wineh-basic.ll
M llvm/test/CodeGen/ARM/byval_load_align.ll
M llvm/test/CodeGen/ARM/cfguard-module-flag.ll
M llvm/test/CodeGen/ARM/clang-section.ll
M llvm/test/CodeGen/ARM/cmse-clear-float-bigend.mir
M llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll
M llvm/test/CodeGen/ARM/constantpool-promote-dbg.ll
M llvm/test/CodeGen/ARM/constantpool-promote.ll
M llvm/test/CodeGen/ARM/early-cfi-sections.ll
M llvm/test/CodeGen/ARM/fp16-vld.ll
M llvm/test/CodeGen/ARM/global-merge-1.ll
M llvm/test/CodeGen/ARM/isel-v8i32-crash.ll
A llvm/test/CodeGen/ARM/kcfi-arm.ll
A llvm/test/CodeGen/ARM/kcfi-cbz-range.ll
A llvm/test/CodeGen/ARM/kcfi-patchable-function-prefix.ll
A llvm/test/CodeGen/ARM/kcfi-thumb.ll
A llvm/test/CodeGen/ARM/kcfi-thumb2.ll
R llvm/test/CodeGen/ARM/kcfi.ll
M llvm/test/CodeGen/ARM/out-of-registers.ll
M llvm/test/CodeGen/ARM/relax-per-target-feature.ll
M llvm/test/CodeGen/ARM/softfp-constant-comparison.ll
M llvm/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll
M llvm/test/CodeGen/ARM/stack_guard_remat.ll
M llvm/test/CodeGen/ARM/struct-byval-frame-index.ll
M llvm/test/CodeGen/ARM/subtarget-align.ll
M llvm/test/CodeGen/ARM/unschedule-first-call.ll
M llvm/test/CodeGen/ARM/vector-spilling.ll
M llvm/test/CodeGen/ARM/vldm-sched-a9.ll
M llvm/test/CodeGen/AVR/dynalloca.ll
A llvm/test/CodeGen/AVR/issue-163015.ll
M llvm/test/CodeGen/DirectX/CBufferAccess/unused.ll
M llvm/test/CodeGen/MSP430/libcalls.ll
A llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll
M llvm/test/CodeGen/Thumb/PR17309.ll
M llvm/test/CodeGen/Thumb/fastcc.ll
M llvm/test/CodeGen/Thumb/ldm-merge-call.ll
M llvm/test/CodeGen/Thumb/stack_guard_remat.ll
M llvm/test/CodeGen/Thumb/stm-merge.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-block-debug.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir
M llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll
M llvm/test/CodeGen/Thumb2/stack_guard_remat.ll
M llvm/test/CodeGen/Thumb2/t2sizereduction.mir
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
M llvm/test/CodeGen/X86/atomic-load-store.ll
M llvm/test/CodeGen/X86/basic-block-address-map-empty-function.ll
M llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll
M llvm/test/CodeGen/X86/basic-block-address-map-pgo-features.ll
M llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-emit-bb-hash.ll
M llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll
M llvm/test/CodeGen/X86/basic-block-address-map.ll
M llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
M llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s
A llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s
A llvm/test/MC/AArch64/SME2p3/luti6.s
M llvm/test/MC/AArch64/SVE/bfmmla-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/sdot-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/udot-diagnostics.s
A llvm/test/MC/AArch64/SVE2p2/fmmla-diagnostics.s
A llvm/test/MC/AArch64/SVE2p2/fmmla.s
A llvm/test/MC/AArch64/SVE2p3/arithmetic-diagnostics.s
A llvm/test/MC/AArch64/SVE2p3/arithmetic.s
A llvm/test/MC/AArch64/SVE2p3/bfmmla-diagnostics.s
A llvm/test/MC/AArch64/SVE2p3/bfmmla.s
A llvm/test/MC/AArch64/SVE2p3/cvt-diagnostics.s
A llvm/test/MC/AArch64/SVE2p3/cvt.s
A llvm/test/MC/AArch64/SVE2p3/directive-arch-negative.s
A llvm/test/MC/AArch64/SVE2p3/directive-arch_extension-negative.s
A llvm/test/MC/AArch64/SVE2p3/directive-cpu-negative.s
A llvm/test/MC/AArch64/SVE2p3/dot-diagnostics.s
A llvm/test/MC/AArch64/SVE2p3/dot.s
A llvm/test/MC/AArch64/SVE2p3/luti6-diagnostics.s
A llvm/test/MC/AArch64/SVE2p3/luti6.s
A llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s
A llvm/test/MC/AArch64/SVE2p3/qshrn.s
M llvm/test/MC/AArch64/armv8.4a-mpam.s
A llvm/test/MC/AArch64/armv9.7a-gcie-diagnostics.s
A llvm/test/MC/AArch64/armv9.7a-gcie.s
A llvm/test/MC/AArch64/armv9.7a-memsys.s
A llvm/test/MC/AArch64/armv9.7a-mpamv2-diagnostics.s
A llvm/test/MC/AArch64/armv9.7a-mpamv2.s
A llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s
A llvm/test/MC/AArch64/armv9.7a-mtetc.s
A llvm/test/MC/AArch64/armv9.7a-tlbid-diagnostics.s
A llvm/test/MC/AArch64/armv9.7a-tlbid.s
A llvm/test/MC/AArch64/neon-fdot-diagnostics.s
A llvm/test/MC/AArch64/neon-fdot.s
A llvm/test/MC/AArch64/neon-fmmla-HtoS-diagnostics.s
A llvm/test/MC/AArch64/neon-fmmla-HtoS.s
A llvm/test/MC/AArch64/neon-fmmla-diagnostics.s
A llvm/test/MC/AArch64/neon-fmmla.s
M llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx1250_err.s
M llvm/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
A llvm/test/TableGen/intrinsic-manual-name.td
M llvm/test/ThinLTO/X86/devirt_external_comdat_same_guid.ll
M llvm/test/ThinLTO/X86/dtlto/json.ll
M llvm/test/Transforms/ConstraintElimination/add-nsw.ll
M llvm/test/Transforms/ConstraintElimination/gep-arithmetic-add.ll
M llvm/test/Transforms/DeadArgElim/dbginfo.ll
M llvm/test/Transforms/DeadStoreElimination/mda-with-dbg-values.ll
M llvm/test/Transforms/FunctionImport/Inputs/funcimport_debug.ll
M llvm/test/Transforms/FunctionImport/funcimport_debug.ll
M llvm/test/Transforms/GCOVProfiling/exit-block.ll
M llvm/test/Transforms/GCOVProfiling/linezero.ll
M llvm/test/Transforms/GCOVProfiling/split-indirectbr-critical-edges.ll
M llvm/test/Transforms/GVN/cond_br2.ll
M llvm/test/Transforms/GVN/pr33549.ll
M llvm/test/Transforms/GVN/pr42605.ll
M llvm/test/Transforms/GVNHoist/hoist-unsafe-pr31729.ll
M llvm/test/Transforms/GVNHoist/pr30499.ll
M llvm/test/Transforms/IndVarSimplify/X86/widen-nsw.ll
M llvm/test/Transforms/Inline/always-inline-attr.ll
M llvm/test/Transforms/Inline/debug-info-duplicate-calls.ll
M llvm/test/Transforms/Inline/inline-vla.ll
M llvm/test/Transforms/Inline/optimization-remarks-hotness-threshold.ll
M llvm/test/Transforms/Inline/optimization-remarks-passed-deleted-callee-yaml.ll
M llvm/test/Transforms/Inline/optimization-remarks-passed-yaml.ll
M llvm/test/Transforms/Inline/optimization-remarks.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-to-svbool-binops.ll
M llvm/test/Transforms/InstCombine/bitreverse-hang.ll
M llvm/test/Transforms/InstCombine/intrinsic-select.ll
M llvm/test/Transforms/InstCombine/phi.ll
M llvm/test/Transforms/InstCombine/ptrtoaddr.ll
M llvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll
M llvm/test/Transforms/InstCombine/select-extractelement.ll
M llvm/test/Transforms/InstCombine/select_frexp.ll
M llvm/test/Transforms/InstCombine/sub-gep.ll
M llvm/test/Transforms/JumpThreading/ddt-crash3.ll
M llvm/test/Transforms/LICM/volatile-alias.ll
M llvm/test/Transforms/LoopRotate/noalias.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-addressing-mode-loops.ll
M llvm/test/Transforms/LoopStrengthReduce/X86/pr17473.ll
M llvm/test/Transforms/LoopStrengthReduce/pr18165.ll
M llvm/test/Transforms/LoopStrengthReduce/two-combinations-bug.ll
M llvm/test/Transforms/LoopUnroll/runtime-epilog-debuginfo.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fully-unrolled-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/maxbandwidth-regpressure.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
A llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-multi-block.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
A llvm/test/Transforms/LoopVectorize/WebAssembly/partial-reduce-accumulate.ll
M llvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
M llvm/test/Transforms/LoopVectorize/X86/int128_no_gather.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-profitable.ll
M llvm/test/Transforms/LoopVectorize/diag-missing-instr-debug-loc.ll
M llvm/test/Transforms/LoopVectorize/diag-with-hotness-info-2.ll
M llvm/test/Transforms/LoopVectorize/diag-with-hotness-info.ll
M llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/metadata-width.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-address-space.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-readonly-address-space.ll
M llvm/test/Transforms/LoopVectorize/scev-exitlim-crash.ll
M llvm/test/Transforms/MergeICmps/X86/int64-and-ptr.ll
M llvm/test/Transforms/MergeICmps/X86/pr41917.ll
M llvm/test/Transforms/NewGVN/basic-cyclic-opt.ll
M llvm/test/Transforms/NewGVN/cond_br2-xfail.ll
M llvm/test/Transforms/NewGVN/equivalent-phi.ll
M llvm/test/Transforms/NewGVN/memory-handling.ll
M llvm/test/Transforms/NewGVN/pr31483.ll
M llvm/test/Transforms/NewGVN/pr31501.ll
M llvm/test/Transforms/NewGVN/pr33187.ll
M llvm/test/Transforms/NewGVN/pr33305.ll
M llvm/test/Transforms/NewGVN/pr34430.ll
M llvm/test/Transforms/NewGVN/pr34452.ll
M llvm/test/Transforms/OpenMP/dead_use.ll
M llvm/test/Transforms/OpenMP/icv_remarks.ll
M llvm/test/Transforms/PGOProfile/misexpect-branch-correct.ll
M llvm/test/Transforms/PGOProfile/misexpect-branch-overflow.ll
M llvm/test/Transforms/PGOProfile/misexpect-branch-stripped.ll
M llvm/test/Transforms/PGOProfile/misexpect-branch-unpredictable.ll
M llvm/test/Transforms/PGOProfile/misexpect-branch.ll
M llvm/test/Transforms/PGOProfile/misexpect-switch-default.ll
M llvm/test/Transforms/PGOProfile/misexpect-switch.ll
M llvm/test/Transforms/PhaseOrdering/always-inline-alloca-promotion.ll
M llvm/test/Verifier/atomics.ll
A llvm/test/tools/llvm-ir2vec/entities.mir
A llvm/test/tools/llvm-ir2vec/output/lit.local.cfg
A llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
A llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
A llvm/test/tools/llvm-ir2vec/triplets.mir
A llvm/test/tools/opt/no-target-machine.ll
M llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp
M llvm/tools/llvm-lto2/llvm-lto2.cpp
M llvm/unittests/ADT/RadixTreeTest.cpp
M llvm/unittests/ADT/SmallVectorTest.cpp
M llvm/unittests/Analysis/MemoryProfileInfoTest.cpp
M llvm/unittests/ExecutionEngine/JITLink/JITLinkTestUtils.h
M llvm/unittests/ExecutionEngine/Orc/EPCGenericMemoryAccessTest.cpp
M llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp
M llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.h
M llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ResourceTrackerTest.cpp
M llvm/unittests/IR/ModuleTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
M llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/lit/lit/run.py
M llvm/utils/lit/tests/shtest-ulimit.py
M llvm/utils/mlgo-utils/IR2Vec/generateTriplets.py
M mlir/examples/standalone/python/CMakeLists.txt
M mlir/include/mlir/Dialect/Affine/Passes.h
M mlir/include/mlir/Dialect/Affine/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TargetEnv.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaProfileCompliance.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/include/mlir/IR/Value.h
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
M mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopUnroll.cpp
M mlir/lib/Dialect/Bufferization/Transforms/TensorCopyInsertion.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/Shard/Transforms/Partition.cpp
M mlir/lib/Dialect/Tosa/IR/TargetEnv.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/ExecutionEngine/SparseTensor/CMakeLists.txt
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/python/CMakeLists.txt
A mlir/test/Conversion/GPUToLLVMSPV/printf.mlir
M mlir/test/Dialect/Affine/unroll.mlir
M mlir/test/Dialect/MemRef/value-bounds-op-interface-impl.mlir
M mlir/test/Dialect/SCF/canonicalize.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/gpu_printf.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp4x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp6x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp8x2.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
M mlir/test/Transforms/scf-loop-unroll.mlir
M mlir/test/lib/Dialect/SCF/TestLoopUnrolling.cpp
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/a3e5a1347f1e...43a7c4c0abe7
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