[all-commits] [llvm/llvm-project] 66e827: [AArch64][llvm] Armv9.7-A: Add support for TLBI Do...

[Jonathan Thackray via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 66e8270e8f3cd5a291e48097095c4f547ddf417d
      https://github.com/llvm/llvm-project/commit/66e8270e8f3cd5a291e48097095c4f547ddf417d
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2025-10-23 (Thu, 23 Oct 2025)

  Changed paths:
    M clang/test/Driver/aarch64-v97a.c
    M clang/test/Driver/print-supported-extensions-aarch64.c
    M llvm/lib/Target/AArch64/AArch64Features.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SystemOperands.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
    M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
    A llvm/test/MC/AArch64/armv9.7a-tlbid-diagnostics.s
    A llvm/test/MC/AArch64/armv9.7a-tlbid.s
    M llvm/unittests/TargetParser/TargetParserTest.cpp

  Log Message:
  -----------
  [AArch64][llvm] Armv9.7-A: Add support for TLBI Domains (FEAT_TLBID) (#163156)

Allow the following `TLBI` operation types to take an optional register
operand when enabled by `FEAT_TLBID`:
  - ALL*
  - VMALL*
  - VMALLS12*
  - VMALLWS2*

as documented here:

  * https://developer.arm.com/documentation/ddi0602/2025-09/
  * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions

Notes on implementation:

Currently, AArch64 `SYS` alias instructions fall into two categories:
  * a register value must be present (indicated by any value except `XZR`)
  * no register value must be present (this value must be `XZR`)

When +tblid is enabled, `SYS` aliases are now allowed to take an optional
register, or no register as before. We need an extra tablegen flag to
indicate if the register is optional or not (the existing "NeedsReg" flag
is binary and not suitable; the register is either present or absent,
not either for a specific TLBI operation)

Don't produce an error message if the register operand is missing or
unexpected, if it is specified as an optional register.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications