[all-commits] [llvm/llvm-project] 104b78: [AArch64] Extend bitcast(extload) tests. NFC
Marco Elver via All-commits
all-commits at lists.llvm.org
Wed Oct 22 06:04:25 PDT 2025
Branch: refs/heads/users/melver/spr/clangsema-add-__builtin_infer_alloc_token-declaration-and-semantic-checks
Home: https://github.com/llvm/llvm-project
Commit: 104b78330662ec13fcdd472582589b2aee8428b9
https://github.com/llvm/llvm-project/commit/104b78330662ec13fcdd472582589b2aee8428b9
Author: David Green <david.green at arm.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/load-zext-bitcast.ll
Log Message:
-----------
[AArch64] Extend bitcast(extload) tests. NFC
Commit: c9fb37c75f741f1179f2d2c661d27d36645b0310
https://github.com/llvm/llvm-project/commit/c9fb37c75f741f1179f2d2c661d27d36645b0310
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp
A flang/test/Fir/assumed-size-ops-codegen.fir
A flang/test/Fir/assumed-size-ops-folding.fir
A flang/test/Fir/assumed-size-ops-roundtrip.fir
M flang/test/HLFIR/assumed-type-actual-args.f90
M flang/test/Lower/HLFIR/assumed-rank-iface.f90
M flang/test/Lower/HLFIR/select-rank.f90
M flang/test/Lower/Intrinsics/lbound.f90
M flang/test/Lower/Intrinsics/ubound.f90
M flang/test/Lower/array-expression-assumed-size.f90
M flang/test/Lower/entry-statement.f90
Log Message:
-----------
[flang][FIR] add fir.assumed_size_extent to abstract assumed-size extent encoding (#164452)
The purpose of this patch is to allow converting FIR array representation to
memref when possible without hitting memref verifier issue.
The issue was that FIR arrays may be assumed size, in which case the
last dimension will not be known at runtime. Flang uses -1 to encode
this to fulfill Fortran 2023 standard requirements in 18.5.3 point 5
about CFI_desc_t.
When arrays are converted to memeref, if this `-1` reaches memeref
operations, it triggers verifier errors (even if the conversion happened
in code that guards the code to be entered at runtime if the array is
assumed-size because folders/verifiers do not take into account
reachability).
This follows-up on discussions in #163505 merge requests
Commit: e83eee335c477ab80612b09bf840700d6982c3ef
https://github.com/llvm/llvm-project/commit/e83eee335c477ab80612b09bf840700d6982c3ef
Author: kper <kevin.per at protonmail.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[DAG] Create SDPatternMatch method `m_SelectLike` to match `ISD::Select` and `ISD::VSelect` (#164069)
Fixes #150019
Commit: 1fbfac30f107cbf63f91101fa5b34dee397089af
https://github.com/llvm/llvm-project/commit/1fbfac30f107cbf63f91101fa5b34dee397089af
Author: Jasmine Tang <jjasmine at igalia.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
A llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
A llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
Log Message:
-----------
[WebAssembly] [Codegen] Add pattern for relaxed min max from fminimum/fmaximum over v4f32 and v2f64 (#162948)
Related to #55932
Commit: 0d20f3fa1fee43bc50883fbc988171cc0eb5a8e3
https://github.com/llvm/llvm-project/commit/0d20f3fa1fee43bc50883fbc988171cc0eb5a8e3
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M lldb/unittests/Target/MemoryTest.cpp
Log Message:
-----------
[lldb][test] Fix address type in ReadMemoryRanges test
Tests added by #163651.
Use lldb::addr_t (which is always 64-bit) for all addresses
so that we don't calculate an invalid address on 32-bit
and segfault.
As happened on Linaro's Arm 32-bit buildbot.
Commit: 4f020c4fb3b014e00caeee14a48f1063390977f8
https://github.com/llvm/llvm-project/commit/4f020c4fb3b014e00caeee14a48f1063390977f8
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/docs/CommandGuide/llc.rst
M llvm/docs/CommandGuide/lli.rst
M llvm/docs/SourceLevelDebugging.rst
Log Message:
-----------
[doc] Remove unsafe-fp-math references (#164579)
Stop mentioning `unsafe-fp-math` related things in documents.
Commit: b7a93b1f7ffc7591d25984f9a940edf1289b971c
https://github.com/llvm/llvm-project/commit/b7a93b1f7ffc7591d25984f9a940edf1289b971c
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/test/MC/AMDGPU/literals.s
M llvm/utils/update_mc_test_checks.py
Log Message:
-----------
[Utils][update_mc_test_checks] Generate check lines in alphabetical order. (#164424)
Currently, check lines are generated beginning from those with
the most used prefixes, and then if two or more prefixes cover
the same number of RUN lines, they would come in the order of
those RUN lines.
This means adding RUN lines may change the order of check lines,
even if the set of check prefixes remained the same, which is not
ideal.
Commit: 20340accf235579d64faf322abc428bc5ddd7f91
https://github.com/llvm/llvm-project/commit/20340accf235579d64faf322abc428bc5ddd7f91
Author: Sam Parker <sam.parker at arm.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/test/CodeGen/WebAssembly/memory-interleave.ll
M llvm/test/CodeGen/WebAssembly/simd-vector-trunc.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/memory-interleave.ll
Log Message:
-----------
[NFC][WebAssembly] FP conversion interleave tests (#164576)
Commit: 12bf1836dec8d5f47339b485727603568fa9e819
https://github.com/llvm/llvm-project/commit/12bf1836dec8d5f47339b485727603568fa9e819
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/lib/IR/AutoUpgrade.cpp
A llvm/test/Assembler/autoupgrade-invalid-masked-align.ll
Log Message:
-----------
[AutoUpgrade] Gracefully handle invalid alignment on masked intrinsics
Generate a usage error instead of asserting.
Commit: cde445716907ccf1003f2d7a95c1a672178d6e8e
https://github.com/llvm/llvm-project/commit/cde445716907ccf1003f2d7a95c1a672178d6e8e
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/shrink-wrap-const-pool-access.mir
Log Message:
-----------
[ShrinkWrap][NFC] Test with load from constant pool preventing shrink (#162476)
wrapping
Shrink wrapping treats a load from constant pool as a stack access. This
is not correct. Constants are basically stored in read only section
AFAIU. This prevents shrink wrapping from kicking in.
(Related to PR #160257. PR #160257 will be closed.)
Commit: 10d3c6bc11ca919563036aa590440c38502bcd2f
https://github.com/llvm/llvm-project/commit/10d3c6bc11ca919563036aa590440c38502bcd2f
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/test/CodeGen/AArch64/shrink-wrap-const-pool-access.mir
M llvm/test/CodeGen/X86/fp128-select.ll
Log Message:
-----------
[ShrinkWrap] Consider constant pool access as non-stack access (#164393)
As far as I understand, constant pool access does not access stack and
accesses read-only memory.
This patch considers constant pool access as non-stack access allowing
shrink wrapping to happen in the concerned test.
We should be seeing perf improvement with povray benchmark from
SPEC17(around 12% with -flto -Ofast) after this patch.
An NFC PR #162476 already exists to upload the test before the patch but
approval has got delayed. So, as @davemgreen suggested in that PR, I
have uploaded the test and patch in this single PR to show how test
looks like.
Commit: 15d11ebc84886e06127750ef5bea60ba1d36798a
https://github.com/llvm/llvm-project/commit/15d11ebc84886e06127750ef5bea60ba1d36798a
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
Log Message:
-----------
[NFC] "unsafe-fp-math" post cleanup (code comments part) (#164582)
Commit: ec546ce5745b195655cbdf645322d5dda91374e0
https://github.com/llvm/llvm-project/commit/ec546ce5745b195655cbdf645322d5dda91374e0
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M lld/test/COFF/Inputs/undefined-symbol-lto-a.ll
M lld/test/COFF/Inputs/undefined-symbol-lto-b.ll
M lld/test/COFF/Inputs/undefined-symbol-multi-lto.ll
M lld/test/MachO/lto-mattrs.ll
M lld/test/wasm/Inputs/debuginfo1.ll
M lld/test/wasm/Inputs/debuginfo2.ll
M lld/test/wasm/debug-removed-fn.ll
Log Message:
-----------
[lld][test] Remove unsafe-fp-math uses (NFC) (#164598)
Commit: 8b2aba2e20c3cfb9d2e9337fdc38c889b0ff8ae2
https://github.com/llvm/llvm-project/commit/8b2aba2e20c3cfb9d2e9337fdc38c889b0ff8ae2
Author: Hassnaa Hamdi <hassnaa.hamdi at arm.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
A llvm/test/Transforms/WholeProgramDevirt/speculative-devirt-single-impl.ll
M llvm/test/Transforms/WholeProgramDevirt/virtual-const-prop-check.ll
Log Message:
-----------
[WPD]: Enable speculative devirtualizatoin. (#159048)
This patch implements the speculative devirtualization feature in the
LLVM backend.
It handles the case of single implementation devirtualization where
there is a single possible callee of a virtual function.
- Add cl::opt 'devirtualize-speculatively' to enable it.
- Flag is disabled by default.
- It works regardless of the visibility of the object.
- Not enabled for LTO for now.
Commit: a4dbd111c285012d744fa0f86e710e4b3032d826
https://github.com/llvm/llvm-project/commit/a4dbd111c285012d744fa0f86e710e4b3032d826
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/test/CodeGen/AArch64/arm64-ld1.ll
Log Message:
-----------
[LLVM][CodeGen][AArch64] Fix global-isel for LD1R. (#164418)
LD1Rv8b only supports a base register but the DAG is matched using
am_indexed8 with the offset it finds silently dropped.
I've also fixed a couple of immediate operands types inconsistencies
that don't manifest as bugs because their incorrect scaling is overriden
by the complex pattern and MachineInstr that are correct and thus
there's nothing to test.
Commit: 128eacfaba78162c944c073270db02e237b7b851
https://github.com/llvm/llvm-project/commit/128eacfaba78162c944c073270db02e237b7b851
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
Log Message:
-----------
[LLVM][CodeGen][SVE] Fix typo in PPR_p8to15's DecoderMethod. (#164429)
Commit: b8062f85dd3612f2b5c0c5cfc14bdc5c0eae641f
https://github.com/llvm/llvm-project/commit/b8062f85dd3612f2b5c0c5cfc14bdc5c0eae641f
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M lldb/tools/lldb-dap/Handler/ExceptionInfoRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/unittests/DAP/CMakeLists.txt
A lldb/unittests/DAP/ProtocolRequestsTest.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
M lldb/unittests/TestingSupport/TestUtilities.cpp
M lldb/unittests/TestingSupport/TestUtilities.h
Log Message:
-----------
[lldb-dap] Use protocol types for exceptioninfo (#164318)
It also separates the `ProtocolRequestsTests` from `ProtocolTypesTests`
as I did not want to increase the work in
https://github.com/llvm/llvm-project/pull/144595
Commit: 37fcaf5c3441564ab5051d8088f5a29701026acb
https://github.com/llvm/llvm-project/commit/37fcaf5c3441564ab5051d8088f5a29701026acb
Author: NexusXe <andastrike at gmail.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vpclmulqdqvl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-bmi1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-cmpxchg.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-pclmul.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-sse42.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-x86_64.s
Log Message:
-----------
[X86] Fix some values for Znver4 model (#161405)
This PR fixes a handful of latency and uop changes between Znver3 and
Znver4 that were otherwise copied from Znver3.
Latency and uop values listed that matched Zen3 on uops.info were
updated to those for Zen4.
Includes: BSF/BSR, DIV, TZCNT, CLMUL, PCMPISTRM, VALIGN, VPERM
Commit: becf84790126ce83ba36eaddc06a0a0a46005048
https://github.com/llvm/llvm-project/commit/becf84790126ce83ba36eaddc06a0a0a46005048
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
M llvm/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll
M llvm/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
M llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
M llvm/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
M llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
M llvm/test/CodeGen/AArch64/arm64-detect-vec-redux.ll
M llvm/test/CodeGen/AArch64/arm64-fma-combine-with-fpfusion.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
M llvm/test/CodeGen/AArch64/arm64-rounding.ll
M llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll
M llvm/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll
M llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll
M llvm/test/CodeGen/AArch64/consthoist-gep.ll
M llvm/test/CodeGen/AArch64/dag-combine-invaraints.ll
M llvm/test/CodeGen/AArch64/partial-pipeline-execution.ll
M llvm/test/CodeGen/AArch64/recp-fastmath.ll
M llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll
M llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
M llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll
M llvm/test/CodeGen/AArch64/stack_guard_remat.ll
M llvm/test/CodeGen/AArch64/vector_merge_dep_check.ll
M llvm/test/CodeGen/AArch64/wineh-frame5.mir
M llvm/test/CodeGen/AArch64/wineh-frame6.mir
M llvm/test/CodeGen/AArch64/wineh-frame7.mir
M llvm/test/CodeGen/AArch64/wineh-frame8.mir
M llvm/test/CodeGen/AArch64/wineh5.mir
M llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
Log Message:
-----------
[AArch64][test] Remove unsafe-fp-math uses (NFC) (#164606)
Post cleanup for #164534
Commit: 57412c3485c5614348015f37ce69be0f378fcad9
https://github.com/llvm/llvm-project/commit/57412c3485c5614348015f37ce69be0f378fcad9
Author: David Green <david.green at arm.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/docs/GlobalISel/GenericOpcode.rst
Log Message:
-----------
[GlobalISel] Update the documentation of abd. (#164594)
The abd nodes do not perform the same as abs(x-y), although they are
often mistaken to do so. They extend into a larger bit size before
performing the sub / abs and so produce different results. Update the
description of the instruction to avoid misunderstandings.
Commit: c636a39e33594f493e3a4e831ddee952cd9b5cb6
https://github.com/llvm/llvm-project/commit/c636a39e33594f493e3a4e831ddee952cd9b5cb6
Author: Nathan Corbyn <n_corbyn at apple.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
A llvm/test/Analysis/BasicAA/matrix-intrinsics.ll
A llvm/test/Transforms/DeadStoreElimination/matrix-intrinsics.ll
A llvm/test/Transforms/GVN/matrix-intrinsics.ll
Log Message:
-----------
[Matrix] Add tests identifying GVN and DSE opportunities for matrix store / load intrinsics (#163573)
This patch adds several tests identifying potential opportunities for
eliminating dead stores and redundant loads when using the
`llvm.matrix.column.major.store.*` and `llvm.matrix.column.major.load.*`
intrinsics.
PR: https://github.com/llvm/llvm-project/pull/163573
Commit: f7fb52aea0b90a2fa76f162e8cbd481c5e1bd91b
https://github.com/llvm/llvm-project/commit/f7fb52aea0b90a2fa76f162e8cbd481c5e1bd91b
Author: Marco Elver <elver at google.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M clang/docs/AllocToken.rst
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/test/Driver/fsanitize-alloc-token.c
Log Message:
-----------
[Clang] Move AllocToken frontend options to LangOptions (#163635)
Move the `AllocTokenMax` from `CodeGenOptions` and introduces a new
`AllocTokenMode` to `LangOptions`. Note, `-falloc-token-mode=`
deliberately remains an internal experimental option.
This refactoring is necessary because these options influence frontend
behavior, specifically constexpr evaluation of `__builtin_infer_alloc_token`.
Placing them in `LangOptions` makes them accessible during semantic analysis,
which occurs before codegen.
Commit: 50acc09c1d6074ae7d1ed4e258cb1d82492f7c1a
https://github.com/llvm/llvm-project/commit/50acc09c1d6074ae7d1ed4e258cb1d82492f7c1a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
R clang/tools/clang-fuzzer/Dockerfile
M clang/tools/clang-fuzzer/README.txt
Log Message:
-----------
[clang-fuzzer] Remove Dockerfile (#162555)
Was going through Dockerfiles to see where we are missing FROM lines
with fully qualified names and came across this one. I think it is safe
to say it has not been used in a very long time or maintained at all
since then since it still tries to download the source tree using svn.
Given that, delete it to lower support surface slightly.
Commit: 6e0553f545df37a31b096f462f5319312728daca
https://github.com/llvm/llvm-project/commit/6e0553f545df37a31b096f462f5319312728daca
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M polly/docs/ReleaseNotes.rst
M polly/include/polly/LinkAllPasses.h
A polly/include/polly/ScopInliner.h
M polly/lib/Support/PollyPasses.def
M polly/lib/Support/RegisterPasses.cpp
M polly/lib/Transform/ScopInliner.cpp
M polly/test/ScopInliner/ignore-declares.ll
M polly/test/ScopInliner/invariant-load-func.ll
M polly/test/ScopInliner/simple-inline-loop.ll
Log Message:
-----------
Reapply "[Polly] Update ScopInliner for NPM (#125427)" (#164601)
An assertion failed when Polly was registering for the pass manager
which assumed that there would be only Polly passes. Since this does not
need to be the case, re-apply with the assert removed.
Includes a non-Polly change to trigger the premerge CI to trigger
check-llvm which failed for 0b9a7b80c0674c5c6f746139912111bea7eae63b,
but pre-merge did not catch.
Commit: 02eda67d85fa0275b74cd4058ba0cecf7c900a22
https://github.com/llvm/llvm-project/commit/02eda67d85fa0275b74cd4058ba0cecf7c900a22
Author: Marco Elver <elver at google.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
R clang/tools/clang-fuzzer/Dockerfile
M clang/tools/clang-fuzzer/README.txt
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp
A flang/test/Fir/assumed-size-ops-codegen.fir
A flang/test/Fir/assumed-size-ops-folding.fir
A flang/test/Fir/assumed-size-ops-roundtrip.fir
M flang/test/HLFIR/assumed-type-actual-args.f90
M flang/test/Lower/HLFIR/assumed-rank-iface.f90
M flang/test/Lower/HLFIR/select-rank.f90
M flang/test/Lower/Intrinsics/lbound.f90
M flang/test/Lower/Intrinsics/ubound.f90
M flang/test/Lower/array-expression-assumed-size.f90
M flang/test/Lower/entry-statement.f90
M lld/test/COFF/Inputs/undefined-symbol-lto-a.ll
M lld/test/COFF/Inputs/undefined-symbol-lto-b.ll
M lld/test/COFF/Inputs/undefined-symbol-multi-lto.ll
M lld/test/MachO/lto-mattrs.ll
M lld/test/wasm/Inputs/debuginfo1.ll
M lld/test/wasm/Inputs/debuginfo2.ll
M lld/test/wasm/debug-removed-fn.ll
M lldb/tools/lldb-dap/Handler/ExceptionInfoRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/unittests/DAP/CMakeLists.txt
A lldb/unittests/DAP/ProtocolRequestsTest.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
M lldb/unittests/Target/MemoryTest.cpp
M lldb/unittests/TestingSupport/TestUtilities.cpp
M lldb/unittests/TestingSupport/TestUtilities.h
M llvm/docs/CommandGuide/llc.rst
M llvm/docs/CommandGuide/lli.rst
M llvm/docs/GlobalISel/GenericOpcode.rst
M llvm/docs/SourceLevelDebugging.rst
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
A llvm/test/Analysis/BasicAA/matrix-intrinsics.ll
A llvm/test/Assembler/autoupgrade-invalid-masked-align.ll
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
M llvm/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll
M llvm/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
M llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
M llvm/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
M llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
M llvm/test/CodeGen/AArch64/arm64-detect-vec-redux.ll
M llvm/test/CodeGen/AArch64/arm64-fma-combine-with-fpfusion.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll
M llvm/test/CodeGen/AArch64/arm64-ld1.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
M llvm/test/CodeGen/AArch64/arm64-rounding.ll
M llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll
M llvm/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll
M llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll
M llvm/test/CodeGen/AArch64/consthoist-gep.ll
M llvm/test/CodeGen/AArch64/dag-combine-invaraints.ll
M llvm/test/CodeGen/AArch64/load-zext-bitcast.ll
M llvm/test/CodeGen/AArch64/partial-pipeline-execution.ll
M llvm/test/CodeGen/AArch64/recp-fastmath.ll
A llvm/test/CodeGen/AArch64/shrink-wrap-const-pool-access.mir
M llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll
M llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
M llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll
M llvm/test/CodeGen/AArch64/stack_guard_remat.ll
M llvm/test/CodeGen/AArch64/vector_merge_dep_check.ll
M llvm/test/CodeGen/AArch64/wineh-frame5.mir
M llvm/test/CodeGen/AArch64/wineh-frame6.mir
M llvm/test/CodeGen/AArch64/wineh-frame7.mir
M llvm/test/CodeGen/AArch64/wineh-frame8.mir
M llvm/test/CodeGen/AArch64/wineh5.mir
M llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
M llvm/test/CodeGen/WebAssembly/memory-interleave.ll
A llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
A llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
M llvm/test/CodeGen/WebAssembly/simd-vector-trunc.ll
M llvm/test/CodeGen/X86/fp128-select.ll
M llvm/test/MC/AMDGPU/literals.s
A llvm/test/Transforms/DeadStoreElimination/matrix-intrinsics.ll
A llvm/test/Transforms/GVN/matrix-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/memory-interleave.ll
A llvm/test/Transforms/WholeProgramDevirt/speculative-devirt-single-impl.ll
M llvm/test/Transforms/WholeProgramDevirt/virtual-const-prop-check.ll
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vpclmulqdqvl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-bmi1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-cmpxchg.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-pclmul.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-sse42.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-x86_64.s
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/utils/update_mc_test_checks.py
M polly/docs/ReleaseNotes.rst
M polly/include/polly/LinkAllPasses.h
A polly/include/polly/ScopInliner.h
M polly/lib/Support/PollyPasses.def
M polly/lib/Support/RegisterPasses.cpp
M polly/lib/Transform/ScopInliner.cpp
M polly/test/ScopInliner/ignore-declares.ll
M polly/test/ScopInliner/invariant-load-func.ll
M polly/test/ScopInliner/simple-inline-loop.ll
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.8-beta.1
[skip ci]
Commit: 66b3bc719de75a3fcbcd7802f345a8452c3611c2
https://github.com/llvm/llvm-project/commit/66b3bc719de75a3fcbcd7802f345a8452c3611c2
Author: Marco Elver <elver at google.com>
Date: 2025-10-22 (Wed, 22 Oct 2025)
Changed paths:
R clang/tools/clang-fuzzer/Dockerfile
M clang/tools/clang-fuzzer/README.txt
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp
A flang/test/Fir/assumed-size-ops-codegen.fir
A flang/test/Fir/assumed-size-ops-folding.fir
A flang/test/Fir/assumed-size-ops-roundtrip.fir
M flang/test/HLFIR/assumed-type-actual-args.f90
M flang/test/Lower/HLFIR/assumed-rank-iface.f90
M flang/test/Lower/HLFIR/select-rank.f90
M flang/test/Lower/Intrinsics/lbound.f90
M flang/test/Lower/Intrinsics/ubound.f90
M flang/test/Lower/array-expression-assumed-size.f90
M flang/test/Lower/entry-statement.f90
M lld/test/COFF/Inputs/undefined-symbol-lto-a.ll
M lld/test/COFF/Inputs/undefined-symbol-lto-b.ll
M lld/test/COFF/Inputs/undefined-symbol-multi-lto.ll
M lld/test/MachO/lto-mattrs.ll
M lld/test/wasm/Inputs/debuginfo1.ll
M lld/test/wasm/Inputs/debuginfo2.ll
M lld/test/wasm/debug-removed-fn.ll
M lldb/tools/lldb-dap/Handler/ExceptionInfoRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/unittests/DAP/CMakeLists.txt
A lldb/unittests/DAP/ProtocolRequestsTest.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
M lldb/unittests/Target/MemoryTest.cpp
M lldb/unittests/TestingSupport/TestUtilities.cpp
M lldb/unittests/TestingSupport/TestUtilities.h
M llvm/docs/CommandGuide/llc.rst
M llvm/docs/CommandGuide/lli.rst
M llvm/docs/GlobalISel/GenericOpcode.rst
M llvm/docs/SourceLevelDebugging.rst
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
A llvm/test/Analysis/BasicAA/matrix-intrinsics.ll
A llvm/test/Assembler/autoupgrade-invalid-masked-align.ll
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
M llvm/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll
M llvm/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
M llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
M llvm/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
M llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
M llvm/test/CodeGen/AArch64/arm64-detect-vec-redux.ll
M llvm/test/CodeGen/AArch64/arm64-fma-combine-with-fpfusion.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll
M llvm/test/CodeGen/AArch64/arm64-ld1.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
M llvm/test/CodeGen/AArch64/arm64-rounding.ll
M llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll
M llvm/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll
M llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll
M llvm/test/CodeGen/AArch64/consthoist-gep.ll
M llvm/test/CodeGen/AArch64/dag-combine-invaraints.ll
M llvm/test/CodeGen/AArch64/load-zext-bitcast.ll
M llvm/test/CodeGen/AArch64/partial-pipeline-execution.ll
M llvm/test/CodeGen/AArch64/recp-fastmath.ll
A llvm/test/CodeGen/AArch64/shrink-wrap-const-pool-access.mir
M llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll
M llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
M llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll
M llvm/test/CodeGen/AArch64/stack_guard_remat.ll
M llvm/test/CodeGen/AArch64/vector_merge_dep_check.ll
M llvm/test/CodeGen/AArch64/wineh-frame5.mir
M llvm/test/CodeGen/AArch64/wineh-frame6.mir
M llvm/test/CodeGen/AArch64/wineh-frame7.mir
M llvm/test/CodeGen/AArch64/wineh-frame8.mir
M llvm/test/CodeGen/AArch64/wineh5.mir
M llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
M llvm/test/CodeGen/WebAssembly/memory-interleave.ll
A llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
A llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
M llvm/test/CodeGen/WebAssembly/simd-vector-trunc.ll
M llvm/test/CodeGen/X86/fp128-select.ll
M llvm/test/MC/AMDGPU/literals.s
A llvm/test/Transforms/DeadStoreElimination/matrix-intrinsics.ll
A llvm/test/Transforms/GVN/matrix-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/memory-interleave.ll
A llvm/test/Transforms/WholeProgramDevirt/speculative-devirt-single-impl.ll
M llvm/test/Transforms/WholeProgramDevirt/virtual-const-prop-check.ll
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vpclmulqdqvl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-bmi1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-cmpxchg.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-pclmul.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-sse42.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-x86_64.s
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/utils/update_mc_test_checks.py
M polly/docs/ReleaseNotes.rst
M polly/include/polly/LinkAllPasses.h
A polly/include/polly/ScopInliner.h
M polly/lib/Support/PollyPasses.def
M polly/lib/Support/RegisterPasses.cpp
M polly/lib/Transform/ScopInliner.cpp
M polly/test/ScopInliner/ignore-declares.ll
M polly/test/ScopInliner/invariant-load-func.ll
M polly/test/ScopInliner/simple-inline-loop.ll
Log Message:
-----------
rebase
Created using spr 1.3.8-beta.1
Compare: https://github.com/llvm/llvm-project/compare/f88af9515e82...66b3bc719de7
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