[all-commits] [llvm/llvm-project] 7d356e: [AArch64] Convert `CSEL(X, 1)` into `CSINC(X, XZR)...

[Csanád Hajdú via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7d356e901b85b9cc0998690ec01f8f3c005329d8
      https://github.com/llvm/llvm-project/commit/7d356e901b85b9cc0998690ec01f8f3c005329d8
  Author: Csanád Hajdú <csanad.hajdu at arm.com>
  Date:   2025-10-20 (Mon, 20 Oct 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/test/CodeGen/AArch64/arm64-early-ifcvt.ll
    M llvm/test/CodeGen/AArch64/peephole-csel.ll

  Log Message:
  -----------
  [AArch64] Convert `CSEL(X, 1)` into `CSINC(X, XZR)` in early-ifcvt (#162993)

Early if conversion can create instruction sequences such as
```
mov  x1, #1
csel x0, x1, x2, eq
```
which could be simplified into the following instead
```
csinc x0, x2, xzr, ne
```

One notable example that generates code like this is `cmpxchg weak`.

This is fixed by handling an immediate value of 1 as `add(wzr, 1)` so
that the addition can be folded into CSEL by using CSINC instead.



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