[all-commits] [llvm/llvm-project] 22a2a8: [X86] Add support for Nova Lake (#163552)
Krzysztof Parzyszek via All-commits
all-commits at lists.llvm.org
Thu Oct 16 10:03:16 PDT 2025
Branch: refs/heads/users/kparzysz/q05-more-requires-clauses
Home: https://github.com/llvm/llvm-project
Commit: 22a2a820543739497f7b954a77897ae41f809b4c
https://github.com/llvm/llvm-project/commit/22a2a820543739497f7b954a77897ae41f809b4c
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Basic/Targets/X86.cpp
M clang/test/CodeGen/attr-target-mv.c
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/Driver/x86-march.c
M clang/test/Misc/target-invalid-cpu-note/x86.c
M clang/test/Preprocessor/predefined-arch-macros.c
M clang/test/Sema/attr-cpuspecific-cpus.c
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/lib/Target/X86/X86.td
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/test/CodeGen/X86/cpus-intel.ll
Log Message:
-----------
[X86] Add support for Nova Lake (#163552)
Add support for Nova Lake, per Intel Architecture Instruction Set
Extensions Programming Reference rev. 59
(https://cdrdv2.intel.com/v1/dl/getContent/671368)
Commit: 1d5bd289062748c89bb9f3f88d0f804972185e93
https://github.com/llvm/llvm-project/commit/1d5bd289062748c89bb9f3f88d0f804972185e93
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/Basic/LangOptions.def
M clang/lib/AST/ASTContext.cpp
M clang/lib/Basic/LangOptions.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaType.cpp
M clang/test/SemaCXX/matrix-type.cpp
M clang/test/SemaHLSL/BuiltIns/matrix-basic_types-errors.hlsl
M clang/unittests/Frontend/CompilerInvocationTest.cpp
Log Message:
-----------
[Matrix][Clang][HLSL] Move MaxMatrixDimension to a LangOpt (#163307)
fixes #160190
fixes #116710
This change just makes MaxMatrixDimension configurable by language mode.
It was previously introduced in
https://github.com/llvm/llvm-project/commit/94b43118e2203fed8ca0377ae762c08189aa6f3d
when there was not a need to make dimensions configurable.
Current testing to this effect exists in:
- clang/test/Sema/matrix-type-builtins.c
- clang/test/SemaCXX/matrix-type-builtins.cpp
- clang/test/SemaHLSL/BuiltIns/matrix-basic_types-errors.hlsl
New Tests to confirm configurability by language mode:
- clang/unittests/Frontend/CompilerInvocationTest.cpp
I considered adding a driver flag to
`clang/include/clang/Driver/Options.td` but HLSL matrix max dim is
always 4 so we don't need this configurable beyond that size for our use
case.
Commit: fc08613145a2e85c671da4aa7eaae33e8ba4e6e0
https://github.com/llvm/llvm-project/commit/fc08613145a2e85c671da4aa7eaae33e8ba4e6e0
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
Log Message:
-----------
[CGBuiltin] Use helper methods for creating masked intrinsics (NFC)
Use the CreateMaskedLoad etc helper methods instead of manually
creating the intrinsics.
Commit: d13bcb6abcf78ddd49102cb1de93385770bfde33
https://github.com/llvm/llvm-project/commit/d13bcb6abcf78ddd49102cb1de93385770bfde33
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/test/Transforms/GVN/PRE/pre-load.ll
Log Message:
-----------
[GVN] Additional test coverage for `findLoadToHoistIntoPred` (NFC)
Add coverage exercizing `isNonLocal` when hoisting identical
loads in `findLoadToHoistIntoPred`, previously lacking.
Commit: ffca377c666f8da9fd80ac6fca4afb7baebf6d34
https://github.com/llvm/llvm-project/commit/ffca377c666f8da9fd80ac6fca4afb7baebf6d34
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M lld/ELF/Symbols.cpp
M lld/MachO/Driver.cpp
Log Message:
-----------
[lld] Replace LLVM_ATTRIBUTE_UNUSED with [[maybe_unused]] (NFC) (#163701)
This patch replaces LLVM_ATTRIBUTE_UNUSED with [[maybe_unused]],
introduced as part of C++17.
Commit: 96cf20658db8edc5ddd64a4ce8f7fda2c1b002a9
https://github.com/llvm/llvm-project/commit/96cf20658db8edc5ddd64a4ce8f7fda2c1b002a9
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Support/Windows/Signals.inc
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
Log Message:
-----------
[llvm] Replace LLVM_ATTRIBUTE_UNUSED with [[maybe_unused]] (NFC) (#163702)
This patch replaces LLVM_ATTRIBUTE_UNUSED with [[maybe_unused]],
introduced as part of C++17.
Commit: 6870f689786273840d567eac95afac5e8af86278
https://github.com/llvm/llvm-project/commit/6870f689786273840d567eac95afac5e8af86278
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/LoopUtils.h
M mlir/lib/Analysis/FlatLinearValueConstraints.cpp
M mlir/lib/Analysis/Presburger/Simplex.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/lib/Dialect/SparseTensor/IR/Detail/Var.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/Transform/IR/TransformTypes.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/Tools/PDLL/CodeGen/CPPGen.cpp
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.cpp
M mlir/test/mlir-pdll/CodeGen/CPP/general.pdll
M mlir/tools/mlir-tblgen/LLVMIRConversionGen.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
M mlir/unittests/Dialect/SparseTensor/MergerTest.cpp
Log Message:
-----------
[mlir] Replace LLVM_ATTRIBUTE_UNUSED with [[maybe_unused]] (NFC) (#163703)
This patch replaces LLVM_ATTRIBUTE_UNUSED with [[maybe_unused]],
introduced as part of C++17.
Commit: 5614d366e4d546c7e738f502e0aba3247640bb02
https://github.com/llvm/llvm-project/commit/5614d366e4d546c7e738f502e0aba3247640bb02
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/docs/HowToReleaseLLVM.rst
Log Message:
-----------
[llvm] Proofread HowToReleaseLLVM.rst (#163704)
Commit: b71515cc7673e1fbc412b61e1d92ea63c36d0ddf
https://github.com/llvm/llvm-project/commit/b71515cc7673e1fbc412b61e1d92ea63c36d0ddf
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/assume.ll
M llvm/test/Transforms/LoopVectorize/operand-bundles.ll
M llvm/test/Transforms/LoopVectorize/scalable-assume.ll
Log Message:
-----------
[VPlan] Extend licm to hoist assumes (#162636)
Assumes are safe to hoist if they're guaranteed to execute, since they
don't alias, and don't throw. This mirrors what the IR-LICM does.
Commit: fbdd98f74f0d9afd1b5e958e5e05022c46b11076
https://github.com/llvm/llvm-project/commit/fbdd98f74f0d9afd1b5e958e5e05022c46b11076
Author: Asher Mancinelli <ashermancinelli at gmail.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M mlir/python/mlir/dialects/gpu/__init__.py
M mlir/test/python/dialects/gpu/dialect.py
Log Message:
-----------
[mlir][python] Add pythonic interface for GPUFuncOp (#163596)
The func dialect provides a more pythonic interface for constructing
operations, but the gpu dialect does not; this is the first PR to
provide the same conveniences for the gpu dialect, starting with the
gpu.func op.
Commit: 6311e1610918576ac25cbb37fe85e36181ba85d4
https://github.com/llvm/llvm-project/commit/6311e1610918576ac25cbb37fe85e36181ba85d4
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
[AMDGPU][NFC] Remove a duplicate isInlinableLiteralBF16() declaration.
Commit: d55de66c1da53754ee9c5162594267a5c6367363
https://github.com/llvm/llvm-project/commit/d55de66c1da53754ee9c5162594267a5c6367363
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
Log Message:
-----------
[X86] min-legal-vector-width.ll - fix AVX512 skylake check prefix clashes (#163783)
Fix check prefix clash warnings in update_llc_test_checks.py by adding an additional prefix for skylake targets with/without vbmi support
Commit: e5825c455ea40760d48be18491d383172dce4928
https://github.com/llvm/llvm-project/commit/e5825c455ea40760d48be18491d383172dce4928
Author: Asher Mancinelli <ashermancinelli at gmail.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M mlir/python/CMakeLists.txt
A mlir/python/mlir/dialects/OpenACCOps.td
A mlir/python/mlir/dialects/openacc.py
A mlir/test/python/dialects/openacc.py
Log Message:
-----------
[mlir][python] Add bindings for OpenACC dialect (#163620)
Adds initial support for Python bindings to the OpenACC dialect.
* The bindings do not provide any niceties yet, just the barebones
exposure of the dialect to Python. Construction of OpenACC ops is
therefore verbose and somewhat inconvenient, as evidenced by the test.
* The test only constructs one module, but I attempted to use enough
operations to be meaningful. It does not test all the ops exposed, but
does contain a realistic example of a memcpy idiom.
Commit: 919395bf463c251f595a728bde1cccfc79c5a28a
https://github.com/llvm/llvm-project/commit/919395bf463c251f595a728bde1cccfc79c5a28a
Author: Endre Fülöp <endre.fulop at sigmatechnology.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
Log Message:
-----------
[NFC][analyzer] Remove empty alpha.security.cert checker category (#163606)
Commit: 5a6756d2a0450cca1efd6688ea4d7e1bad1a32c9
https://github.com/llvm/llvm-project/commit/5a6756d2a0450cca1efd6688ea4d7e1bad1a32c9
Author: Muzammil <55665739+Muzammiluddin-Syed-ECE at users.noreply.github.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
Log Message:
-----------
[mlir][AMGPU] Replace use of SmallVector with ArrayRef, NFC (#163770)
Improving choice of class used, from SmallVector to ArrayRef
(https://llvm.org/docs/ProgrammersManual.html#llvm-adt-arrayref-h). Also infer template types when possible.
Leftover from https://github.com/llvm/llvm-project/pull/155951.
---------
Signed-off-by: Muzammiluddin Syed <muzasyed at amd.com>
Commit: 9c3da74846ee87cc0c62174850f2841f9f82cb27
https://github.com/llvm/llvm-project/commit/9c3da74846ee87cc0c62174850f2841f9f82cb27
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
M llvm/test/CodeGen/X86/isel-fpclass.ll
Log Message:
-----------
Revert "[X86][GlobalIsel] Support G_IS_FPCLASS" (#163792)
Reverts #162232 due to failures on EXPENSIVE_CHECKS enabled targets
Commit: a885961216ac72d08b98bd0110860e5b6e51d5c9
https://github.com/llvm/llvm-project/commit/a885961216ac72d08b98bd0110860e5b6e51d5c9
Author: Asher Mancinelli <ashermancinelli at gmail.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M mlir/test/python/dialects/openacc.py
Log Message:
-----------
[mlir][python] Fix lit run line for openacc test (#163797)
This test passed locally because I had a python environment with the
`python` command available, but I should have used the `%PYTHON` lit
command substitution instead. Fixes buildbot failures from #163620.
Commit: 56503d85dc007d8db40039c113e3ab148ba6c8b9
https://github.com/llvm/llvm-project/commit/56503d85dc007d8db40039c113e3ab148ba6c8b9
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
R llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov-fpr.ll
R llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov-gpr.ll
A llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll
A llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll
Log Message:
-----------
[AArch64][NFC] Align ZCM test names to MOVE not MOV (#163069)
Commit: 05cbcf13c880a45baf84b0e732fc4792c1e09892
https://github.com/llvm/llvm-project/commit/05cbcf13c880a45baf84b0e732fc4792c1e09892
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M clang/test/CodeGen/arm-mve-intrinsics/load-store.c
Log Message:
-----------
[Clang] Regenerate test checks (NFC)
Commit: 893b1d4187e435a1fe12902a3aad0f6cdc7123be
https://github.com/llvm/llvm-project/commit/893b1d4187e435a1fe12902a3aad0f6cdc7123be
Author: Jasmine Tang <jjasmine at igalia.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
A llvm/test/CodeGen/WebAssembly/simd-relaxed-dot.ll
Log Message:
-----------
[WebAssembly] [Codegen] Add patterns for relaxed dot (#163266)
The pattern I added for `relaxed dot` similar to normal dot @
https://github.com/llvm/llvm-project/pull/151775.
For `relaxed dot add`, i noticed that in the proposal the portion of dot
implementation is similar to `relaxed dot`, so I think we can add a
pattern where after we do relaxed dot and do extadd pairwise, we can do
`relaxed dot add`.
One current obstacles is I don't think there is any pattern to singly
create a extadd pairwise from other instructions so the `relaxed dot
add` pattern would not cover a wide range of instructions.
related to https://github.com/llvm/llvm-project/issues/55932
Commit: 5fd59466f2bdd5338453826d46cc813b949c9ad5
https://github.com/llvm/llvm-project/commit/5fd59466f2bdd5338453826d46cc813b949c9ad5
Author: Rajveer Singh Bharadwaj <rajveer.developer at icloud.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
Log Message:
-----------
[AArch64][SVE] Allow factors other than 2/4 for load+deinterleave3+store patterns for codegen (#162475)
Resolves #159801 and #162068
Commit: 0935e1510da9435c6a7c43fd383caf8b91971d4b
https://github.com/llvm/llvm-project/commit/0935e1510da9435c6a7c43fd383caf8b91971d4b
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
A llvm/test/DebugInfo/AArch64/callsite.mir
Log Message:
-----------
Return nullopt if Reg is undef. (#155893)
In describeORRLoadedValue in AArch64InstrInfo.cpp, we try to check if an
instruction is a copy like instruction, the isCopyLikeInstr function
returns a pair of destination and source registers. If any of them are
undef, we should just return a nullopt to avoid any crashes later in the
code when trying to get the SubReg for one of those registers.
rdar://158581204
Commit: 581b654f4005a5fd1389dc93fd97be03a5329edf
https://github.com/llvm/llvm-project/commit/581b654f4005a5fd1389dc93fd97be03a5329edf
Author: Krish Gupta <krishom70 at gmail.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
A flang/test/Semantics/OpenMP/omp-common-fp-lp.f90
Log Message:
-----------
[flang][OpenMP] Add semantics test: named COMMON + member with firstprivate+lastprivate is valid (#162234)
This adds a positive semantics test showing that:
- A named COMMON block in a clause is equivalent to listing all explicit
members.
- The same list item may appear in both firstprivate and lastprivate on
the same construct.
The reporter example in #162033 therefore conforms to OpenMP and Flang
is correct to accept it. This test documents and locks in that behavior
to avoid regressions.
<img width="1606" height="350" alt="image"
src="https://github.com/user-attachments/assets/0b464c58-b9cc-43e0-8d1f-1c5a5b993bf6"
/>
Co-authored-by: Krish Gupta <krishgupta at Krishs-MacBook-Air.local>
Commit: 1499880a5a0295bccf8c6dc47950cb0c02a0e54f
https://github.com/llvm/llvm-project/commit/1499880a5a0295bccf8c6dc47950cb0c02a0e54f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/idiv_large.ll
Log Message:
-----------
[RISCV] Expand divisions larger than 64 bits on RV32. (#163688)
The __(u)divti3, __(u)modti3 functions don't exist in libgcc for RV32.
Commit: a7cda50cbc80d43e6c5c4e3dc8f030dea54a8a43
https://github.com/llvm/llvm-project/commit/a7cda50cbc80d43e6c5c4e3dc8f030dea54a8a43
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M .ci/monolithic-linux.sh
M .ci/monolithic-windows.sh
M .ci/utils.sh
Log Message:
-----------
[CI] Save All .ninja_log Files (#163485)
We currently only save the .ninja_log from the last ninja invocation
because ninja overwrites any existing .ninja_log file. This prevents us
from easily doing performance introspection of earlier ninja invocations
(which take the bulk of the time) using the .ninja_log file.
Commit: d4b1ab77c16491d423d5bbf19db4f00d214178fa
https://github.com/llvm/llvm-project/commit/d4b1ab77c16491d423d5bbf19db4f00d214178fa
Author: Austin Kerbow <Austin.Kerbow at amd.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
A llvm/test/CodeGen/AMDGPU/schedule-pending-queue.mir
Log Message:
-----------
[AMDGPU] Examine instructions in pending queues during scheduling (#147653)
Examine instructions in the pending queue when scheduling. This makes
instructions visible to scheduling heuristics even when they aren't
immediately issuable due to hardware resource constraints.
The scheduler has two hardware resource modeling modes: an in-order mode
where instructions must be ready to issue before scheduling, and
out-of-order models where instructions are always visible to heuristics.
Special handling exists for unbuffered processor resources in
out-of-order models. These resources can cause pipeline stalls when used
back-to-back, so they're typically avoided. However, for AMDGPU targets,
managing register pressure and reducing spilling is critical enough to
justify exceptions to this approach.
This change enables examination of instructions that can't be
immediately issued because they use an already occupied unbuffered
resource. By making these instructions visible to scheduling heuristics
anyway, we gain more flexibility in scheduling decisions, potentially
allowing better register pressure and hardware resource management.
Commit: 733fe4266ce26fa47ce02e3a62b7a104ef791ff3
https://github.com/llvm/llvm-project/commit/733fe4266ce26fa47ce02e3a62b7a104ef791ff3
Author: Austin Kerbow <Austin.Kerbow at amd.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
Log Message:
-----------
[AMDGPU][NFC] Fix out-of-line definition sanitizer error after 05851eb3
NDEBUG check was removed from definition but not function declaration.
Commit: 7fe069121b57a187e2072f01ecc84523948d9f04
https://github.com/llvm/llvm-project/commit/7fe069121b57a187e2072f01ecc84523948d9f04
Author: Ahmed Nour <ahmednour.mohamed2012 at gmail.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M clang/lib/Headers/avx512dqintrin.h
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avx512vldqintrin.h
M clang/lib/Headers/avx512vlintrin.h
M clang/test/CodeGen/X86/avx512dq-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/X86/avx512vldq-builtins.c
Log Message:
-----------
[Headers][X86] Allow AVX512 masked shuffles to be used in constexpr (#162301)
This PR makes AVX512 masked shuffle and broadcast intrinsics usable in constexpr
Fixes #162074
Commit: 39b0cbe69ca8704dbc5846a91d136f0ed6101782
https://github.com/llvm/llvm-project/commit/39b0cbe69ca8704dbc5846a91d136f0ed6101782
Author: Florian Mayer <fmayer at google.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
M llvm/test/Transforms/IndVarSimplify/X86/overflow-intrinsics.ll
A llvm/test/Transforms/IndVarSimplify/unreachable-exit.ll
Log Message:
-----------
[IndVarSimplify] Allow predicateLoopExit on some loops with thread-local writes (#155901)
This is important to optimize patterns that frequently appear with
bounds checks:
```
for (int i = 0; i < N; ++i) {
bar[i] = foo[i] + 123;
}
```
which gets roughly turned into
```
for (int i = 0; i < N; ++i) {
if (i >= size of foo)
ubsan.trap();
if (i >= size of bar)
ubsan.trap();
bar[i] = foo[i] + 123;
}
```
Motivating example:
https://github.com/google/boringssl/blob/main/crypto/fipsmodule/hmac/hmac.cc.inc#L138
I hand-verified the assembly and confirmed that this optimization
removes the check in the loop.
This also allowed the loop to be vectorized.
Alive2: https://alive2.llvm.org/ce/z/3qMdLF
I did a `stage2-check-all` for both normal and
`-DBOOTSTRAP_CMAKE_C[XX]_FLAGS="-fsanitize=array-bounds
-fsanitize-trap=all"`.
I also ran some Google-internal tests with `fsanitize=array-bounds`.
Everything passes.
Commit: 8fa4a1029cbad3c788a90152cf978f8233a6f87f
https://github.com/llvm/llvm-project/commit/8fa4a1029cbad3c788a90152cf978f8233a6f87f
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/multiple-result-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-struct-return.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-fold-uniform-memops.ll
M llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
Log Message:
-----------
[LoopVectorize] Regenerate test checks (NFC)
Commit: be3aa41ecc9b6cc68248e660a30829a16eda26b3
https://github.com/llvm/llvm-project/commit/be3aa41ecc9b6cc68248e660a30829a16eda26b3
Author: Patrick Simmons <psimmons at pensando.io>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M flang-rt/cmake/modules/AddFlangRT.cmake
Log Message:
-----------
[Flang-RT] Fix GCC 15.1 Fortran Runtime libstdc++ Undefined Symbols (#157385)
Define the _GLIBCXX_THROW_OR_ABORT macro to not use its _EXC argument. _EXC may contain an expression constructing an std::exception object which is non-inline and therefore require a link dependency on the libstdc++ runtime. In -fno-exceptions builds it is typically optimized away when appearing in unreachable code, but is still present when compiling with -O0 when compiling with Clang.
---------
Co-authored-by: Michael Kruse <github at meinersbur.de>
Commit: 32cb4b2c6d136ad098de1690ea3312095d5742a2
https://github.com/llvm/llvm-project/commit/32cb4b2c6d136ad098de1690ea3312095d5742a2
Author: foxfromabyss <22933823+foxfromabyss at users.noreply.github.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M clang-tools-extra/test/clang-tidy/checkers/misc/misplaced-const-cxx17.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/Analysis/zero-size-non-pod-array.cpp
M clang/test/CXX/dcl.decl/dcl.decomp/p2.cpp
M clang/test/CXX/dcl.decl/dcl.decomp/p3.cpp
M clang/test/CXX/dcl.decl/dcl.decomp/p4.cpp
M clang/test/CXX/drs/cwg22xx.cpp
M clang/test/CXX/drs/cwg23xx.cpp
M clang/test/CXX/drs/cwg26xx.cpp
M clang/test/CXX/stmt.stmt/stmt.iter/stmt.ranged/p1.cpp
M clang/test/CXX/temp/temp.res/temp.local/p6.cpp
M clang/test/FixIt/fixit-constrained-structured-binding.cpp
M clang/test/PCH/cxx1z-decomposition.cpp
M clang/test/Parser/cxx1z-class-template-argument-deduction.cpp
M clang/test/Parser/cxx1z-decomposition.cpp
M clang/test/Parser/cxx2c-binding-pack.cpp
M clang/test/SemaCXX/builtin-structured-binding-size.cpp
M clang/test/SemaCXX/cxx17-compat.cpp
M clang/test/SemaCXX/cxx1z-decomposition.cpp
M clang/test/SemaCXX/cxx2c-binding-pack-nontemplate.cpp
M clang/test/SemaCXX/cxx2c-binding-pack.cpp
M clang/test/SemaCXX/sizeless-1.cpp
M clang/test/SemaCXX/warn-shadow-in-lambdas.cpp
M clang/test/SemaTemplate/cxx1z-decomposition.cpp
Log Message:
-----------
[Clang][Diagnostics] Use "structured binding" instead of "decomposition" (#163101)
[P0615R0](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2017/p0615r0.html)
changed the term "decomposition" to "structured binding". Some
diagnostic messages were created before this paper. These messages
should be updated using "structured binding" to avoid making users
confused.
Closes #157880
---------
Co-authored-by: foxfromabyss <foxfromabyss at foxfromabyss.com>
Co-authored-by: Sirraide <aeternalmail at gmail.com>
Commit: 401c05ab1b2535286c49f29ac92fa93bf4331363
https://github.com/llvm/llvm-project/commit/401c05ab1b2535286c49f29ac92fa93bf4331363
Author: Grigory Pastukhov <99913765+grigorypas at users.noreply.github.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroAnnotationElide.cpp
Log Message:
-----------
[Coroutines] Fix assertion failure in CoroAnnotationElide pass (#163609)
Replace BranchProbability::getBranchProbability(BlockFreq, EntryFreq)
with
direct frequency comparison to avoid assertion failure when BlockFreq >
EntryFreq
(e.g., call site in hot loop). Semantics unchanged.
Commit: ccf5b3ed62ac70ccaf4648f06c89d98b3d2a800b
https://github.com/llvm/llvm-project/commit/ccf5b3ed62ac70ccaf4648f06c89d98b3d2a800b
Author: vangthao95 <vang.thao at amd.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_READSTEADYCOUNTER (#163661)
Commit: e6afe2a85471ee0b2463428ee3fc0411e25237cc
https://github.com/llvm/llvm-project/commit/e6afe2a85471ee0b2463428ee3fc0411e25237cc
Author: lntue <lntue at google.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M libc/src/__support/FPUtil/double_double.h
Log Message:
-----------
[libc] Fix temporary types for fputil::split template. (#163813)
Fix #163711.
Commit: 0ca14470fc9fc6f8d8afd355daee590be9ea98b8
https://github.com/llvm/llvm-project/commit/0ca14470fc9fc6f8d8afd355daee590be9ea98b8
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M flang/include/flang/Lower/OpenMP/Clauses.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Parser/OpenMP/requires.f90
M flang/test/Semantics/OpenMP/requires-modfile.f90
A flang/test/Semantics/OpenMP/requires10.f90
M llvm/include/llvm/Frontend/OpenMP/ClauseT.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[flang][OpenMP] Add optional argument to requirement clauses (#163557)
OpenMP 6.0 added an optional logical parameter to the requirement
clauses (except ATOMIC_DEFAULT_MEM_ORDER) to indicate whether the clause
should take effect or not. The parameter defaults to true if not
specified.
The parameter value is a compile-time constant expression, but it may
require folding to get the final value. Since name resolution happens
before folding, the argument expression needs to be analyzed by hand.
The determination of the value needs to happen during name resolution
because the requirement directives need to be available through module
files (and the module reader doesn't to semantic checks beyond name
resolution).
Commit: 467487f2a15d9b62c6999184daddbe9b51864e3b
https://github.com/llvm/llvm-project/commit/467487f2a15d9b62c6999184daddbe9b51864e3b
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Parser/OpenMP/allocate-align-tree.f90
M flang/test/Semantics/OpenMP/allocate-align01.f90
Log Message:
-----------
[flang][OpenMP] Reuse semantic check for "constantness" of alignment (#163624)
Use ScalarIntConstantExpr in the parse tree instead of ScalarIntExpr.
This will still parse a general expression, but the semantic checker for
expressions will automatically perfom a test for whether the value is
constant or not.
Use that instead of manual checks, it will make diagnostics more
uniform. There is no functional change other than that.
Commit: 543932f034a15a8a1f6fda545432f87d26949667
https://github.com/llvm/llvm-project/commit/543932f034a15a8a1f6fda545432f87d26949667
Author: Petr Hosek <phosek at google.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/baremetal/config.json
Log Message:
-----------
[libc] Make LIBC_MATH_NO_ERRNO imply `-fno-math-errno` (#125794)
This partially reverts #124200. Rather than using a CMake option to
control whether to enable `-fno-math-errno`, use LIBC_MATH_NO_ERRNO
configuration option. While there might be other cases when we want to
set `-fno-math-errno`, having LIBC_MATH_NO_ERRNO imply it should be
always safe and represents a reasonable starting point.
Commit: 8b06ef3191093d60317fec430847cf92dfbce0f9
https://github.com/llvm/llvm-project/commit/8b06ef3191093d60317fec430847cf92dfbce0f9
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M flang/test/Lower/CUDA/cuda-managed.cuf
Log Message:
-----------
[flang][cuda] Move function result assignment to managed variable on host (#163705)
- Update data transfer detection to let an assignment with a host rhs
and managed lhs to be performed on the host. This helps if the rhs is a
function result.
- Fix test `cuda-maanaged-cuf` introduces on eef4b5a. The test was not
checking for the implicit transfer but the explicit transfer that was
part of the first loop.
Commit: 165783082a45f23e90dcd6dfc922ca5459c6b9f5
https://github.com/llvm/llvm-project/commit/165783082a45f23e90dcd6dfc922ca5459c6b9f5
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M .ci/monolithic-linux.sh
M .ci/monolithic-windows.sh
M .ci/utils.sh
M clang-tools-extra/test/clang-tidy/checkers/misc/misplaced-const-cxx17.cpp
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/Basic/LangOptions.cpp
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/avx512dqintrin.h
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avx512vldqintrin.h
M clang/lib/Headers/avx512vlintrin.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaType.cpp
M clang/test/Analysis/zero-size-non-pod-array.cpp
M clang/test/CXX/dcl.decl/dcl.decomp/p2.cpp
M clang/test/CXX/dcl.decl/dcl.decomp/p3.cpp
M clang/test/CXX/dcl.decl/dcl.decomp/p4.cpp
M clang/test/CXX/drs/cwg22xx.cpp
M clang/test/CXX/drs/cwg23xx.cpp
M clang/test/CXX/drs/cwg26xx.cpp
M clang/test/CXX/stmt.stmt/stmt.iter/stmt.ranged/p1.cpp
M clang/test/CXX/temp/temp.res/temp.local/p6.cpp
M clang/test/CodeGen/X86/avx512dq-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/X86/avx512vldq-builtins.c
M clang/test/CodeGen/arm-mve-intrinsics/load-store.c
M clang/test/CodeGen/attr-target-mv.c
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/Driver/x86-march.c
M clang/test/FixIt/fixit-constrained-structured-binding.cpp
M clang/test/Misc/target-invalid-cpu-note/x86.c
M clang/test/PCH/cxx1z-decomposition.cpp
M clang/test/Parser/cxx1z-class-template-argument-deduction.cpp
M clang/test/Parser/cxx1z-decomposition.cpp
M clang/test/Parser/cxx2c-binding-pack.cpp
M clang/test/Preprocessor/predefined-arch-macros.c
M clang/test/Sema/attr-cpuspecific-cpus.c
M clang/test/SemaCXX/builtin-structured-binding-size.cpp
M clang/test/SemaCXX/cxx17-compat.cpp
M clang/test/SemaCXX/cxx1z-decomposition.cpp
M clang/test/SemaCXX/cxx2c-binding-pack-nontemplate.cpp
M clang/test/SemaCXX/cxx2c-binding-pack.cpp
M clang/test/SemaCXX/matrix-type.cpp
M clang/test/SemaCXX/sizeless-1.cpp
M clang/test/SemaCXX/warn-shadow-in-lambdas.cpp
M clang/test/SemaHLSL/BuiltIns/matrix-basic_types-errors.hlsl
M clang/test/SemaTemplate/cxx1z-decomposition.cpp
M clang/unittests/Frontend/CompilerInvocationTest.cpp
M compiler-rt/lib/builtins/cpu_model/x86.c
M flang-rt/cmake/modules/AddFlangRT.cmake
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M flang/test/Lower/CUDA/cuda-managed.cuf
M flang/test/Parser/OpenMP/allocate-align-tree.f90
M flang/test/Semantics/OpenMP/allocate-align01.f90
A flang/test/Semantics/OpenMP/omp-common-fp-lp.f90
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/baremetal/config.json
M libc/src/__support/FPUtil/double_double.h
M lld/ELF/Symbols.cpp
M lld/MachO/Driver.cpp
M llvm/docs/HowToReleaseLLVM.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/lib/Support/Windows/Signals.inc
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/Coroutines/CoroAnnotationElide.cpp
M llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
R llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov-fpr.ll
R llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov-gpr.ll
A llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll
A llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
A llvm/test/CodeGen/AMDGPU/schedule-pending-queue.mir
M llvm/test/CodeGen/RISCV/idiv_large.ll
A llvm/test/CodeGen/WebAssembly/simd-relaxed-dot.ll
M llvm/test/CodeGen/X86/cpus-intel.ll
M llvm/test/CodeGen/X86/isel-fpclass.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
A llvm/test/DebugInfo/AArch64/callsite.mir
M llvm/test/Transforms/GVN/PRE/pre-load.ll
M llvm/test/Transforms/IndVarSimplify/X86/overflow-intrinsics.ll
A llvm/test/Transforms/IndVarSimplify/unreachable-exit.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/multiple-result-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-struct-return.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-fold-uniform-memops.ll
M llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/assume.ll
M llvm/test/Transforms/LoopVectorize/operand-bundles.ll
M llvm/test/Transforms/LoopVectorize/scalable-assume.ll
M mlir/include/mlir/Dialect/Affine/LoopUtils.h
M mlir/lib/Analysis/FlatLinearValueConstraints.cpp
M mlir/lib/Analysis/Presburger/Simplex.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/lib/Dialect/SparseTensor/IR/Detail/Var.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/Transform/IR/TransformTypes.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/Tools/PDLL/CodeGen/CPPGen.cpp
M mlir/python/CMakeLists.txt
A mlir/python/mlir/dialects/OpenACCOps.td
M mlir/python/mlir/dialects/gpu/__init__.py
A mlir/python/mlir/dialects/openacc.py
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.cpp
M mlir/test/mlir-pdll/CodeGen/CPP/general.pdll
M mlir/test/python/dialects/gpu/dialect.py
A mlir/test/python/dialects/openacc.py
M mlir/tools/mlir-tblgen/LLVMIRConversionGen.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
M mlir/unittests/Dialect/SparseTensor/MergerTest.cpp
Log Message:
-----------
Merge branch 'main' into users/kparzysz/q05-more-requires-clauses
Compare: https://github.com/llvm/llvm-project/compare/9279568db4c2...165783082a45
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