[all-commits] [llvm/llvm-project] e3f9b4: [X86] Relax vector element width constraint on SSE...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e3f9b4ce25fa59c714120d9cdcecbba94a4c9f04
      https://github.com/llvm/llvm-project/commit/e3f9b4ce25fa59c714120d9cdcecbba94a4c9f04
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-10-16 (Thu, 16 Oct 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86MCInstLower.cpp
    M llvm/test/CodeGen/X86/combine-udiv.ll
    M llvm/test/CodeGen/X86/madd.ll
    M llvm/test/CodeGen/X86/vector-fshr-128.ll
    M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
    M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll

  Log Message:
  -----------
  [X86] Relax vector element width constraint on SSE pmul/madd asm comments (#163590)

As noticed on #163567 - if the constant pool data wasn't the expected element size for the instruction, we weren't adding the asm comment at all



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